system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matrix
* tpd and thetas : a M * K matrix
*
* numElements = (num documents in one batch)
*
* p: K * numDocumentsInOneBatch
*/
extern "C"
__global__ void drawLatentVariables(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* wpt, int* wt, int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int V, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0 || c_word >= V){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
atomicAdd(&wpt[j + (c_word * K)], 1);
atomicAdd(&wt[j], 1);
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
extern "C"
__global__ void drawLatentVariablesForTestingQuick(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
extern __shared__ float p[];
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* Use this to infer topics for testing;
* phis are fixed and not updated
*
*/
extern "C"
__global__ void drawLatentVariablesForTesting(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
curandState s;
// reset a random number generator
curand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = curand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* K = 30
* V = 120000
*
* numElements = K * V
*
* wpt and phis : a K * V matrix
*
* wpt[k][v] : words per topic
* wt[k] : total words per topic
*
*/
extern "C"
__global__ void computePhis(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, float beta, float betaV, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + beta) / (wt[k] + betaV);
}
}
extern "C"
__global__ void computePhisExact(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + 0.0) / wt[k];
}
}
/**
* M = 90000
* K = 30
*
* numElements = M * K
*
* thetas : a M * K matrix
*
* tpd[m][k] : topics per document
* td[m] : total topics per document
*/
extern "C"
__global__ void computeThetas(const int* __restrict__ tpd, const int* __restrict__ td, float* thetas,
float alpha, float alphaK, int M, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int m = i % M;
thetas[i] = (tpd[i] + alpha) / (td[m] + alphaK);
}
} | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matrix
* tpd and thetas : a M * K matrix
*
* numElements = (num documents in one batch)
*
* p: K * numDocumentsInOneBatch
*/
extern "C"
__global__ void drawLatentVariables(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* wpt, int* wt, int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int V, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0 || c_word >= V){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
atomicAdd(&wpt[j + (c_word * K)], 1);
atomicAdd(&wt[j], 1);
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
extern "C"
__global__ void drawLatentVariablesForTestingQuick(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
extern __shared__ float p[];
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* Use this to infer topics for testing;
* phis are fixed and not updated
*
*/
extern "C"
__global__ void drawLatentVariablesForTesting(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* K = 30
* V = 120000
*
* numElements = K * V
*
* wpt and phis : a K * V matrix
*
* wpt[k][v] : words per topic
* wt[k] : total words per topic
*
*/
extern "C"
__global__ void computePhis(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, float beta, float betaV, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + beta) / (wt[k] + betaV);
}
}
extern "C"
__global__ void computePhisExact(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + 0.0) / wt[k];
}
}
/**
* M = 90000
* K = 30
*
* numElements = M * K
*
* thetas : a M * K matrix
*
* tpd[m][k] : topics per document
* td[m] : total topics per document
*/
extern "C"
__global__ void computeThetas(const int* __restrict__ tpd, const int* __restrict__ td, float* thetas,
float alpha, float alphaK, int M, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int m = i % M;
thetas[i] = (tpd[i] + alpha) / (td[m] + alphaK);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matrix
* tpd and thetas : a M * K matrix
*
* numElements = (num documents in one batch)
*
* p: K * numDocumentsInOneBatch
*/
extern "C"
__global__ void drawLatentVariables(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* wpt, int* wt, int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int V, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0 || c_word >= V){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
atomicAdd(&wpt[j + (c_word * K)], 1);
atomicAdd(&wt[j], 1);
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
extern "C"
__global__ void drawLatentVariablesForTestingQuick(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
extern __shared__ float p[];
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* Use this to infer topics for testing;
* phis are fixed and not updated
*
*/
extern "C"
__global__ void drawLatentVariablesForTesting(
const int* __restrict__ docsWordCounts, const int* __restrict__ docsWordOffsets, const int* __restrict__ docsWordIndices,
int* tpd, int* td, const float* __restrict__ phis, const float* __restrict__ thetas,
float* p,
int docOffset, int K, int M, int numDocumentsInOneBatch) {
/**
* with size numDocumentsInOneBatch * K
*/
int m = blockDim.x * blockIdx.x + threadIdx.x;
if (m < numDocumentsInOneBatch) {
int Nm = docsWordCounts[m];
int docIndex = docOffset + m;
int docWordOffset = docsWordOffsets[m];
hiprandState s;
// reset a random number generator
hiprand_init(docIndex, 0, 0, &s);
int pOffset = m * K;
for (int i = 0; i < Nm; i++) {
float sum = 0;
int c_word = docsWordIndices[docWordOffset + i];
if (c_word < 0){
continue;
}
int j;
for (j = 0; j < K; j++) {
sum += phis[j + (c_word * K)] * thetas[docIndex + (j * M)];
p[j + pOffset] = sum;
}
float stop = hiprand_uniform(&s) * sum;
for (j = 0; j < K; j++) {
if (stop < p[j + pOffset]) {
break;
}
}
if (j == K){
j--;
}
tpd[docIndex + (j * M)]++;
}
td[docIndex] += Nm;
}
}
/**
* K = 30
* V = 120000
*
* numElements = K * V
*
* wpt and phis : a K * V matrix
*
* wpt[k][v] : words per topic
* wt[k] : total words per topic
*
*/
extern "C"
__global__ void computePhis(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, float beta, float betaV, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + beta) / (wt[k] + betaV);
}
}
extern "C"
__global__ void computePhisExact(const int* __restrict__ wpt, const int* __restrict__ wt, float* phis, int K, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int k = i % K;
phis[i] = (wpt[i] + 0.0) / wt[k];
}
}
/**
* M = 90000
* K = 30
*
* numElements = M * K
*
* thetas : a M * K matrix
*
* tpd[m][k] : topics per document
* td[m] : total topics per document
*/
extern "C"
__global__ void computeThetas(const int* __restrict__ tpd, const int* __restrict__ td, float* thetas,
float alpha, float alphaK, int M, int numElements)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < numElements) {
int m = i % M;
thetas[i] = (tpd[i] + alpha) / (td[m] + alphaK);
}
} | .text
.file "CudaLDAFunctions.hip"
.globl __device_stub__drawLatentVariables # -- Begin function __device_stub__drawLatentVariables
.p2align 4, 0x90
.type __device_stub__drawLatentVariables,@function
__device_stub__drawLatentVariables: # @__device_stub__drawLatentVariables
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariables, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size __device_stub__drawLatentVariables, .Lfunc_end0-__device_stub__drawLatentVariables
.cfi_endproc
# -- End function
.globl __device_stub__drawLatentVariablesForTestingQuick # -- Begin function __device_stub__drawLatentVariablesForTestingQuick
.p2align 4, 0x90
.type __device_stub__drawLatentVariablesForTestingQuick,@function
__device_stub__drawLatentVariablesForTestingQuick: # @__device_stub__drawLatentVariablesForTestingQuick
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariablesForTestingQuick, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size __device_stub__drawLatentVariablesForTestingQuick, .Lfunc_end1-__device_stub__drawLatentVariablesForTestingQuick
.cfi_endproc
# -- End function
.globl __device_stub__drawLatentVariablesForTesting # -- Begin function __device_stub__drawLatentVariablesForTesting
.p2align 4, 0x90
.type __device_stub__drawLatentVariablesForTesting,@function
__device_stub__drawLatentVariablesForTesting: # @__device_stub__drawLatentVariablesForTesting
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariablesForTesting, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size __device_stub__drawLatentVariablesForTesting, .Lfunc_end2-__device_stub__drawLatentVariablesForTesting
.cfi_endproc
# -- End function
.globl __device_stub__computePhis # -- Begin function __device_stub__computePhis
.p2align 4, 0x90
.type __device_stub__computePhis,@function
__device_stub__computePhis: # @__device_stub__computePhis
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $computePhis, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size __device_stub__computePhis, .Lfunc_end3-__device_stub__computePhis
.cfi_endproc
# -- End function
.globl __device_stub__computePhisExact # -- Begin function __device_stub__computePhisExact
.p2align 4, 0x90
.type __device_stub__computePhisExact,@function
__device_stub__computePhisExact: # @__device_stub__computePhisExact
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $computePhisExact, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size __device_stub__computePhisExact, .Lfunc_end4-__device_stub__computePhisExact
.cfi_endproc
# -- End function
.globl __device_stub__computeThetas # -- Begin function __device_stub__computeThetas
.p2align 4, 0x90
.type __device_stub__computeThetas,@function
__device_stub__computeThetas: # @__device_stub__computeThetas
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $computeThetas, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size __device_stub__computeThetas, .Lfunc_end5-__device_stub__computeThetas
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariables, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariablesForTestingQuick, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariablesForTesting, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computePhis, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computePhisExact, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computeThetas, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type drawLatentVariables,@object # @drawLatentVariables
.section .rodata,"a",@progbits
.globl drawLatentVariables
.p2align 3, 0x0
drawLatentVariables:
.quad __device_stub__drawLatentVariables
.size drawLatentVariables, 8
.type drawLatentVariablesForTestingQuick,@object # @drawLatentVariablesForTestingQuick
.globl drawLatentVariablesForTestingQuick
.p2align 3, 0x0
drawLatentVariablesForTestingQuick:
.quad __device_stub__drawLatentVariablesForTestingQuick
.size drawLatentVariablesForTestingQuick, 8
.type drawLatentVariablesForTesting,@object # @drawLatentVariablesForTesting
.globl drawLatentVariablesForTesting
.p2align 3, 0x0
drawLatentVariablesForTesting:
.quad __device_stub__drawLatentVariablesForTesting
.size drawLatentVariablesForTesting, 8
.type computePhis,@object # @computePhis
.globl computePhis
.p2align 3, 0x0
computePhis:
.quad __device_stub__computePhis
.size computePhis, 8
.type computePhisExact,@object # @computePhisExact
.globl computePhisExact
.p2align 3, 0x0
computePhisExact:
.quad __device_stub__computePhisExact
.size computePhisExact, 8
.type computeThetas,@object # @computeThetas
.globl computeThetas
.p2align 3, 0x0
computeThetas:
.quad __device_stub__computeThetas
.size computeThetas, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "drawLatentVariables"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "drawLatentVariablesForTestingQuick"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "drawLatentVariablesForTesting"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "computePhis"
.size .L__unnamed_4, 12
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "computePhisExact"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "computeThetas"
.size .L__unnamed_6, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__drawLatentVariables
.addrsig_sym __device_stub__drawLatentVariablesForTestingQuick
.addrsig_sym __device_stub__drawLatentVariablesForTesting
.addrsig_sym __device_stub__computePhis
.addrsig_sym __device_stub__computePhisExact
.addrsig_sym __device_stub__computeThetas
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym drawLatentVariables
.addrsig_sym drawLatentVariablesForTestingQuick
.addrsig_sym drawLatentVariablesForTesting
.addrsig_sym computePhis
.addrsig_sym computePhisExact
.addrsig_sym computeThetas
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5749_00000000-6_CudaLDAFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2243:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
.type _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii, @function
_Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii:
.LFB2265:
.cfi_startproc
endbr64
subq $296, %rsp
.cfi_def_cfa_offset 304
movq %rcx, 40(%rsp)
movq %r8, 32(%rsp)
movq %r9, 24(%rsp)
movq 304(%rsp), %rax
movq %rax, 16(%rsp)
movq 328(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 280(%rsp)
xorl %eax, %eax
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 168(%rsp)
movq %rdx, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
movq 312(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
movq 320(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 224(%rsp)
leaq 8(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 360(%rsp), %rax
movq %rax, 264(%rsp)
leaq 368(%rsp), %rax
movq %rax, 272(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 280(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $296, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 312
pushq 104(%rsp)
.cfi_def_cfa_offset 320
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq drawLatentVariables(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 304
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2265:
.size _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii, .-_Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
.globl drawLatentVariables
.type drawLatentVariables, @function
drawLatentVariables:
.LFB2266:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 88(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
pushq 88(%rsp)
.cfi_def_cfa_offset 72
pushq 88(%rsp)
.cfi_def_cfa_offset 80
pushq 88(%rsp)
.cfi_def_cfa_offset 88
pushq 88(%rsp)
.cfi_def_cfa_offset 96
call _Z70__device_stub__Z19drawLatentVariablesPKiS0_S0_PiS1_S1_S1_PKfS3_PfiiiiiPKiS0_S0_PiS1_S1_S1_PKfS3_Pfiiiii
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2266:
.size drawLatentVariables, .-drawLatentVariables
.globl _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
.type _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii, @function
_Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii:
.LFB2267:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movq %r9, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
movq 240(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 264(%rsp), %rax
movq %rax, 200(%rsp)
leaq 272(%rsp), %rax
movq %rax, 208(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq drawLatentVariablesForTestingQuick(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2267:
.size _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii, .-_Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
.globl drawLatentVariablesForTestingQuick
.type drawLatentVariablesForTestingQuick, @function
drawLatentVariablesForTestingQuick:
.LFB2268:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z76__device_stub__Z34drawLatentVariablesForTestingQuickPKiS0_S0_PiS1_PKfS3_iiiiPKiS0_S0_PiS1_PKfS3_iiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2268:
.size drawLatentVariablesForTestingQuick, .-drawLatentVariablesForTestingQuick
.globl _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
.type _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii, @function
_Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii:
.LFB2269:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq 280(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
movq %rdi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsi, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
movq %rdx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
movq %r9, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
movq 272(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
leaq 304(%rsp), %rax
movq %rax, 224(%rsp)
leaq 312(%rsp), %rax
movq %rax, 232(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 280
pushq 88(%rsp)
.cfi_def_cfa_offset 288
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq drawLatentVariablesForTesting(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2269:
.size _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii, .-_Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
.globl drawLatentVariablesForTesting
.type drawLatentVariablesForTesting, @function
drawLatentVariablesForTesting:
.LFB2270:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z73__device_stub__Z29drawLatentVariablesForTestingPKiS0_S0_PiS1_PKfS3_PfiiiiPKiS0_S0_PiS1_PKfS3_Pfiiii
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2270:
.size drawLatentVariablesForTesting, .-drawLatentVariablesForTesting
.globl _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
.type _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii, @function
_Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii:
.LFB2271:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq computePhis(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii, .-_Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
.globl computePhis
.type computePhis, @function
computePhis:
.LFB2272:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11computePhisPKiS0_PfffiiPKiS0_Pfffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2272:
.size computePhis, .-computePhis
.globl _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
.type _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii, @function
_Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii:
.LFB2273:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq computePhisExact(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2273:
.size _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii, .-_Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
.globl computePhisExact
.type computePhisExact, @function
computePhisExact:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z16computePhisExactPKiS0_PfiiPKiS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size computePhisExact, .-computePhisExact
.globl _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
.type _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii, @function
_Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii:
.LFB2275:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq computeThetas(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2275:
.size _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii, .-_Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
.globl computeThetas
.type computeThetas, @function
computeThetas:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z13computeThetasPKiS0_PfffiiPKiS0_Pfffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size computeThetas, .-computeThetas
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "computeThetas"
.LC1:
.string "computePhisExact"
.LC2:
.string "computePhis"
.LC3:
.string "drawLatentVariablesForTesting"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "drawLatentVariablesForTestingQuick"
.section .rodata.str1.1
.LC5:
.string "drawLatentVariables"
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2278:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq computeThetas(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq computePhisExact(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq computePhis(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariablesForTesting(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariablesForTestingQuick(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq drawLatentVariables(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2278:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CudaLDAFunctions.hip"
.globl __device_stub__drawLatentVariables # -- Begin function __device_stub__drawLatentVariables
.p2align 4, 0x90
.type __device_stub__drawLatentVariables,@function
__device_stub__drawLatentVariables: # @__device_stub__drawLatentVariables
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 232(%rsp), %rax
movq %rax, 152(%rsp)
leaq 240(%rsp), %rax
movq %rax, 160(%rsp)
leaq 248(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariables, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size __device_stub__drawLatentVariables, .Lfunc_end0-__device_stub__drawLatentVariables
.cfi_endproc
# -- End function
.globl __device_stub__drawLatentVariablesForTestingQuick # -- Begin function __device_stub__drawLatentVariablesForTestingQuick
.p2align 4, 0x90
.type __device_stub__drawLatentVariablesForTestingQuick,@function
__device_stub__drawLatentVariablesForTestingQuick: # @__device_stub__drawLatentVariablesForTestingQuick
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariablesForTestingQuick, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size __device_stub__drawLatentVariablesForTestingQuick, .Lfunc_end1-__device_stub__drawLatentVariablesForTestingQuick
.cfi_endproc
# -- End function
.globl __device_stub__drawLatentVariablesForTesting # -- Begin function __device_stub__drawLatentVariablesForTesting
.p2align 4, 0x90
.type __device_stub__drawLatentVariablesForTesting,@function
__device_stub__drawLatentVariablesForTesting: # @__device_stub__drawLatentVariablesForTesting
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $drawLatentVariablesForTesting, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end2:
.size __device_stub__drawLatentVariablesForTesting, .Lfunc_end2-__device_stub__drawLatentVariablesForTesting
.cfi_endproc
# -- End function
.globl __device_stub__computePhis # -- Begin function __device_stub__computePhis
.p2align 4, 0x90
.type __device_stub__computePhis,@function
__device_stub__computePhis: # @__device_stub__computePhis
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $computePhis, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size __device_stub__computePhis, .Lfunc_end3-__device_stub__computePhis
.cfi_endproc
# -- End function
.globl __device_stub__computePhisExact # -- Begin function __device_stub__computePhisExact
.p2align 4, 0x90
.type __device_stub__computePhisExact,@function
__device_stub__computePhisExact: # @__device_stub__computePhisExact
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $computePhisExact, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size __device_stub__computePhisExact, .Lfunc_end4-__device_stub__computePhisExact
.cfi_endproc
# -- End function
.globl __device_stub__computeThetas # -- Begin function __device_stub__computeThetas
.p2align 4, 0x90
.type __device_stub__computeThetas,@function
__device_stub__computeThetas: # @__device_stub__computeThetas
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $computeThetas, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size __device_stub__computeThetas, .Lfunc_end5-__device_stub__computeThetas
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariables, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariablesForTestingQuick, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $drawLatentVariablesForTesting, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computePhis, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computePhisExact, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $computeThetas, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type drawLatentVariables,@object # @drawLatentVariables
.section .rodata,"a",@progbits
.globl drawLatentVariables
.p2align 3, 0x0
drawLatentVariables:
.quad __device_stub__drawLatentVariables
.size drawLatentVariables, 8
.type drawLatentVariablesForTestingQuick,@object # @drawLatentVariablesForTestingQuick
.globl drawLatentVariablesForTestingQuick
.p2align 3, 0x0
drawLatentVariablesForTestingQuick:
.quad __device_stub__drawLatentVariablesForTestingQuick
.size drawLatentVariablesForTestingQuick, 8
.type drawLatentVariablesForTesting,@object # @drawLatentVariablesForTesting
.globl drawLatentVariablesForTesting
.p2align 3, 0x0
drawLatentVariablesForTesting:
.quad __device_stub__drawLatentVariablesForTesting
.size drawLatentVariablesForTesting, 8
.type computePhis,@object # @computePhis
.globl computePhis
.p2align 3, 0x0
computePhis:
.quad __device_stub__computePhis
.size computePhis, 8
.type computePhisExact,@object # @computePhisExact
.globl computePhisExact
.p2align 3, 0x0
computePhisExact:
.quad __device_stub__computePhisExact
.size computePhisExact, 8
.type computeThetas,@object # @computeThetas
.globl computeThetas
.p2align 3, 0x0
computeThetas:
.quad __device_stub__computeThetas
.size computeThetas, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "drawLatentVariables"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "drawLatentVariablesForTestingQuick"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "drawLatentVariablesForTesting"
.size .L__unnamed_3, 30
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "computePhis"
.size .L__unnamed_4, 12
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "computePhisExact"
.size .L__unnamed_5, 17
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "computeThetas"
.size .L__unnamed_6, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__drawLatentVariables
.addrsig_sym __device_stub__drawLatentVariablesForTestingQuick
.addrsig_sym __device_stub__drawLatentVariablesForTesting
.addrsig_sym __device_stub__computePhis
.addrsig_sym __device_stub__computePhisExact
.addrsig_sym __device_stub__computeThetas
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym drawLatentVariables
.addrsig_sym drawLatentVariablesForTestingQuick
.addrsig_sym drawLatentVariablesForTesting
.addrsig_sym computePhis
.addrsig_sym computePhisExact
.addrsig_sym computeThetas
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
cudaStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
cudaMallocHost((void**)&h_a, nsize * sizeof(float));
cudaMallocHost((void**)&h_b, nsize * sizeof(float));
cudaMallocHost((void**)&h_c, nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
cudaDeviceSynchronize();
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
cudaStreamDestroy(streams[i]);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R0, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04007820 */
/* 0x004fca0000400000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*00f0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*0100*/ MUFU.EX2 R8, R0 ; /* 0x0000000000087308 */
/* 0x000e240000000800 */
/*0110*/ @!P0 FMUL R8, R8, R8 ; /* 0x0000000808088220 */
/* 0x001fc80000400000 */
/*0120*/ FMUL R9, R8, R3 ; /* 0x0000000308097220 */
/* 0x008fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
cudaStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
cudaMallocHost((void**)&h_a, nsize * sizeof(float));
cudaMallocHost((void**)&h_b, nsize * sizeof(float));
cudaMallocHost((void**)&h_c, nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
cudaDeviceSynchronize();
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
cudaStreamDestroy(streams[i]);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .file "tmpxft_001b1d6d_00000000-6_Exercise_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13initArrayDataPffi
.type _Z13initArrayDataPffi, @function
_Z13initArrayDataPffi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 12(%rsp), %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13initArrayDataPffi, .-_Z13initArrayDataPffi
.globl _Z12getChunkInfoiPiS_S_S_iiii
.type _Z12getChunkInfoiPiS_S_S_iiii, @function
_Z12getChunkInfoiPiS_S_S_iiii:
.LFB2059:
.cfi_startproc
endbr64
movq %rsi, %r10
movq %rdx, %rsi
movq %rcx, %r11
movl 8(%rsp), %ecx
movl %r9d, %eax
cltd
idivl %ecx
movl %edx, %r9d
movl %ecx, %eax
imull %edi, %eax
movl %eax, (%r11)
movl %edi, %eax
cltd
idivl 24(%rsp)
movl %edx, (%r8)
movl %ecx, (%rsi)
imull (%r8), %ecx
movl %ecx, (%r10)
testl %r9d, %r9d
je .L8
movl 16(%rsp), %eax
subl $1, %eax
cmpl %edi, %eax
je .L10
.L8:
ret
.L10:
movl %r9d, (%rsi)
ret
.cfi_endproc
.LFE2059:
.size _Z12getChunkInfoiPiS_S_S_iiii, .-_Z12getChunkInfoiPiS_S_S_iiii
.globl _Z12arrayFuncCPUPKfS0_Pfi
.type _Z12arrayFuncCPUPKfS0_Pfi, @function
_Z12arrayFuncCPUPKfS0_Pfi:
.LFB2060:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L16
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r12
movl $0, %ebx
.L13:
movl 0(%r13,%rbx), %ebp
movss (%r14,%rbx), %xmm0
call expf@PLT
movd %ebp, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z12arrayFuncCPUPKfS0_Pfi, .-_Z12arrayFuncCPUPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.LC2:
.string "Number of streams: %d\n"
.LC3:
.string "Number of chunks: %d\n"
.LC6:
.string "\nGPU computation ... "
.LC7:
.string "ok\n"
.LC8:
.string "Elapsed time on GPU: %.2f ms\n"
.LC9:
.string "\nCPU computation ... "
.LC10:
.string "Elapsed time on CPU: %.2f ms\n"
.LC11:
.string "\nSpeed UP CPU/GPU %.1fx\n"
.LC12:
.string "\nCheck results:\n"
.LC13:
.string "h_c[0] = %f\n"
.LC14:
.string "cpuResult[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $2097152, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $8, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
movl $2097152, %esi
movss .LC4(%rip), %xmm0
movq 16(%rsp), %rdi
call _Z13initArrayDataPffi
movl $2097152, %esi
movss .LC5(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z13initArrayDataPffi
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, %eax
.L20:
subl $1, %eax
jne .L20
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2097152, %ecx
movq 56(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z12arrayFuncCPUPKfS0_Pfi
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 128(%rsp), %rbp
.L21:
movq (%rbx), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L21
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9arrayFuncPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.type _Z9arrayFuncPfS_S_i, @function
_Z9arrayFuncPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9arrayFuncPfS_S_i, .-_Z9arrayFuncPfS_S_i
.section .rodata.str1.1
.LC15:
.string "_Z9arrayFuncPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayFuncPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
cudaStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
cudaMallocHost((void**)&h_a, nsize * sizeof(float));
cudaMallocHost((void**)&h_b, nsize * sizeof(float));
cudaMallocHost((void**)&h_c, nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
cudaDeviceSynchronize();
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
cudaStreamDestroy(streams[i]);
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
cudaFreeHost(h_a);
cudaFreeHost(h_b);
cudaFreeHost(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
hipStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
hipHostMalloc((void**)&h_a, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_b, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_c, nsize * sizeof(float), hipHostMallocDefault);
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
hipDeviceSynchronize();
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
hipStreamDestroy(streams[i]);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
hipStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
hipHostMalloc((void**)&h_a, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_b, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_c, nsize * sizeof(float), hipHostMallocDefault);
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
hipDeviceSynchronize();
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
hipStreamDestroy(streams[i]);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayFuncPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayFuncPfS_S_i, .Lfunc_end0-_Z9arrayFuncPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayFuncPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayFuncPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams);
#define NSIZE 2097152
#define CHUNKSIZEMAX 65536
#define NUMSTREAMS 8
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
int chunk_size_max = CHUNKSIZEMAX;
int num_streams = NUMSTREAMS;
int num_chunk;
int i;
int h_offset, d_offset;
int chunk_size, chunk_stream;
hipStream_t streams[NUMSTREAMS];
// chunk number calculation
num_chunk = (nsize-1) / chunk_size_max + 1;
printf("Number of elements: %d\n", nsize);
printf("Number of streams: %d\n", num_streams);
printf("Number of chunks: %d\n", num_chunk);
// allocation and initialization of host buffers
hipHostMalloc((void**)&h_a, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_b, nsize * sizeof(float), hipHostMallocDefault);
hipHostMalloc((void**)&h_c, nsize * sizeof(float), hipHostMallocDefault);
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDA code ----------------
// device buffers allocation
// streams creation
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
for (i = 0; i < num_chunk; i++) {
// please see getChunkInfo function description
getChunkInfo(i, &d_offset, &chunk_size, &h_offset, &chunk_stream, nsize, chunk_size_max, num_chunk, num_streams);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
// block number calculation
nBlocks = (chunk_size-1) / nThreads + 1;
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
}
hipDeviceSynchronize();
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
for (i = 0; i< num_streams; i++)
hipStreamDestroy(streams[i]);
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
hipHostFree(h_a);
hipHostFree(h_b);
hipHostFree(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
// getChunkInfo is used to compute some useful information starting
// from the i-th chunk, the total number of used chunks,
// the maximum chunk size and the array size to process
// getChunkInfo returns:
// * chunk_size: the number of elements to use in current chunk
// * chunk_stream: the stream to use to process i-th chunk
// * the X_offsets to use for accessing the correct elements of host
// and device arrays in data movements and kernel launch
//
void getChunkInfo(int i, int *d_offset, int *chunk_size, int *h_offset, int *chunk_stream, int nSize, int chunk_size_max, int num_chunk, int num_streams){
int Reminder = nSize%chunk_size_max;
*h_offset = i*chunk_size_max;
*chunk_stream = i%num_streams;
*chunk_size = chunk_size_max;
*d_offset = *chunk_stream * chunk_size_max;
if (Reminder && (i == num_chunk-1)) *chunk_size = Reminder;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .text
.file "Exercise_2.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9arrayFuncPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayFuncPfS_S_i, .Lfunc_end0-_Z24__device_stub__arrayFuncPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $2097152, %esi # imm = 0x200000
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $32, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
movq 32(%rsp), %r14
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
cmpq $2097152, %rbx # imm = 0x200000
jne .LBB1_1
# %bb.2: # %_Z13initArrayDataPffi.exit
movq 24(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $2097152, %r14 # imm = 0x200000
jne .LBB1_3
# %bb.4: # %_Z13initArrayDataPffi.exit33
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
xorl %ebx, %ebx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %r14
movq 24(%rsp), %r15
movq 48(%rsp), %r12
.p2align 4, 0x90
.LBB1_5: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp) # 4-byte Spill
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 44(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq $2097152, %rbx # imm = 0x200000
jne .LBB1_5
# %bb.6: # %_Z12arrayFuncCPUPKfS0_Pfi.exit
movq (%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 20(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 56(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 64(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $8, %rbx
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
callq hipFree
callq hipFree
callq hipFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 56(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13initArrayDataPffi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13initArrayDataPffi
.p2align 4, 0x90
.type _Z13initArrayDataPffi,@function
_Z13initArrayDataPffi: # @_Z13initArrayDataPffi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
mulss .LCPI2_0(%rip), %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13initArrayDataPffi, .Lfunc_end2-_Z13initArrayDataPffi
.cfi_endproc
# -- End function
.globl _Z12getChunkInfoiPiS_S_S_iiii # -- Begin function _Z12getChunkInfoiPiS_S_S_iiii
.p2align 4, 0x90
.type _Z12getChunkInfoiPiS_S_S_iiii,@function
_Z12getChunkInfoiPiS_S_S_iiii: # @_Z12getChunkInfoiPiS_S_S_iiii
.cfi_startproc
# %bb.0:
movl %r9d, %eax
movq %rdx, %r10
movl %edi, %r9d
movl 8(%rsp), %r11d
cltd
idivl %r11d
movl %edx, %edi
movl %r11d, %eax
imull %r9d, %eax
movl %eax, (%rcx)
movl %r9d, %eax
cltd
idivl 24(%rsp)
movl %edx, (%r8)
movl %r11d, (%r10)
imull (%r8), %r11d
movl %r11d, (%rsi)
testl %edi, %edi
je .LBB3_3
# %bb.1:
movl 16(%rsp), %eax
decl %eax
cmpl %r9d, %eax
jne .LBB3_3
# %bb.2:
movl %edi, (%r10)
.LBB3_3:
retq
.Lfunc_end3:
.size _Z12getChunkInfoiPiS_S_S_iiii, .Lfunc_end3-_Z12getChunkInfoiPiS_S_S_iiii
.cfi_endproc
# -- End function
.globl _Z12arrayFuncCPUPKfS0_Pfi # -- Begin function _Z12arrayFuncCPUPKfS0_Pfi
.p2align 4, 0x90
.type _Z12arrayFuncCPUPKfS0_Pfi,@function
_Z12arrayFuncCPUPKfS0_Pfi: # @_Z12arrayFuncCPUPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_4
# %bb.1: # %.critedge.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB4_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12arrayFuncCPUPKfS0_Pfi, .Lfunc_end4-_Z12arrayFuncCPUPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayFuncPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayFuncPfS_S_i,@object # @_Z9arrayFuncPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9arrayFuncPfS_S_i
.p2align 3, 0x0
_Z9arrayFuncPfS_S_i:
.quad _Z24__device_stub__arrayFuncPfS_S_i
.size _Z9arrayFuncPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of streams: %d\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of chunks: %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nGPU computation ... "
.size .L.str.3, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Elapsed time on GPU: %.2f ms\n"
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nCPU computation ... "
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Elapsed time on CPU: %.2f ms\n"
.size .L.str.7, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nSpeed UP CPU/GPU %.1fx\n"
.size .L.str.8, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "h_c[0] = %f\n"
.size .L.str.10, 19
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cpuResult[0] = %f\n"
.size .L.str.11, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9arrayFuncPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "ok"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nCheck results:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayFuncPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayFuncPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R0, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04007820 */
/* 0x004fca0000400000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*00f0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*0100*/ MUFU.EX2 R8, R0 ; /* 0x0000000000087308 */
/* 0x000e240000000800 */
/*0110*/ @!P0 FMUL R8, R8, R8 ; /* 0x0000000808088220 */
/* 0x001fc80000400000 */
/*0120*/ FMUL R9, R8, R3 ; /* 0x0000000308097220 */
/* 0x008fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayFuncPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayFuncPfS_S_i, .Lfunc_end0-_Z9arrayFuncPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayFuncPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayFuncPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b1d6d_00000000-6_Exercise_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13initArrayDataPffi
.type _Z13initArrayDataPffi, @function
_Z13initArrayDataPffi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 12(%rsp), %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13initArrayDataPffi, .-_Z13initArrayDataPffi
.globl _Z12getChunkInfoiPiS_S_S_iiii
.type _Z12getChunkInfoiPiS_S_S_iiii, @function
_Z12getChunkInfoiPiS_S_S_iiii:
.LFB2059:
.cfi_startproc
endbr64
movq %rsi, %r10
movq %rdx, %rsi
movq %rcx, %r11
movl 8(%rsp), %ecx
movl %r9d, %eax
cltd
idivl %ecx
movl %edx, %r9d
movl %ecx, %eax
imull %edi, %eax
movl %eax, (%r11)
movl %edi, %eax
cltd
idivl 24(%rsp)
movl %edx, (%r8)
movl %ecx, (%rsi)
imull (%r8), %ecx
movl %ecx, (%r10)
testl %r9d, %r9d
je .L8
movl 16(%rsp), %eax
subl $1, %eax
cmpl %edi, %eax
je .L10
.L8:
ret
.L10:
movl %r9d, (%rsi)
ret
.cfi_endproc
.LFE2059:
.size _Z12getChunkInfoiPiS_S_S_iiii, .-_Z12getChunkInfoiPiS_S_S_iiii
.globl _Z12arrayFuncCPUPKfS0_Pfi
.type _Z12arrayFuncCPUPKfS0_Pfi, @function
_Z12arrayFuncCPUPKfS0_Pfi:
.LFB2060:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L16
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r12
movl $0, %ebx
.L13:
movl 0(%r13,%rbx), %ebp
movss (%r14,%rbx), %xmm0
call expf@PLT
movd %ebp, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2060:
.size _Z12arrayFuncCPUPKfS0_Pfi, .-_Z12arrayFuncCPUPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.LC2:
.string "Number of streams: %d\n"
.LC3:
.string "Number of chunks: %d\n"
.LC6:
.string "\nGPU computation ... "
.LC7:
.string "ok\n"
.LC8:
.string "Elapsed time on GPU: %.2f ms\n"
.LC9:
.string "\nCPU computation ... "
.LC10:
.string "Elapsed time on CPU: %.2f ms\n"
.LC11:
.string "\nSpeed UP CPU/GPU %.1fx\n"
.LC12:
.string "\nCheck results:\n"
.LC13:
.string "h_c[0] = %f\n"
.LC14:
.string "cpuResult[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $152, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movl $2097152, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $8, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
movl $2097152, %esi
movss .LC4(%rip), %xmm0
movq 16(%rsp), %rdi
call _Z13initArrayDataPffi
movl $2097152, %esi
movss .LC5(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z13initArrayDataPffi
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $32, %eax
.L20:
subl $1, %eax
jne .L20
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 56(%rsp), %rdi
movl $8388608, %esi
call cudaMallocHost@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2097152, %ecx
movq 56(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z12arrayFuncCPUPKfS0_Pfi
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 64(%rsp), %rbx
leaq 128(%rsp), %rbp
.L21:
movq (%rbx), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L21
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9arrayFuncPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.type _Z9arrayFuncPfS_S_i, @function
_Z9arrayFuncPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9arrayFuncPfS_S_i, .-_Z9arrayFuncPfS_S_i
.section .rodata.str1.1
.LC15:
.string "_Z9arrayFuncPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayFuncPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Exercise_2.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9arrayFuncPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayFuncPfS_S_i, .Lfunc_end0-_Z24__device_stub__arrayFuncPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $2097152, %esi # imm = 0x200000
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $8, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $32, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
leaq 24(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
leaq 56(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
movq 32(%rsp), %r14
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
cmpq $2097152, %rbx # imm = 0x200000
jne .LBB1_1
# %bb.2: # %_Z13initArrayDataPffi.exit
movq 24(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i29
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $2097152, %r14 # imm = 0x200000
jne .LBB1_3
# %bb.4: # %_Z13initArrayDataPffi.exit33
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
xorl %ebx, %ebx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 20(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
xorl %edx, %edx
callq hipHostMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %r14
movq 24(%rsp), %r15
movq 48(%rsp), %r12
.p2align 4, 0x90
.LBB1_5: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp) # 4-byte Spill
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 44(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r12,%rbx,4)
incq %rbx
cmpq $2097152, %rbx # imm = 0x200000
jne .LBB1_5
# %bb.6: # %_Z12arrayFuncCPUPKfS0_Pfi.exit
movq (%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 20(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movq 56(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq 64(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $8, %rbx
jne .LBB1_7
# %bb.8:
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
callq hipFree
callq hipFree
callq hipFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 24(%rsp), %rdi
callq hipHostFree
movq 56(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13initArrayDataPffi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13initArrayDataPffi
.p2align 4, 0x90
.type _Z13initArrayDataPffi,@function
_Z13initArrayDataPffi: # @_Z13initArrayDataPffi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
mulss .LCPI2_0(%rip), %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13initArrayDataPffi, .Lfunc_end2-_Z13initArrayDataPffi
.cfi_endproc
# -- End function
.globl _Z12getChunkInfoiPiS_S_S_iiii # -- Begin function _Z12getChunkInfoiPiS_S_S_iiii
.p2align 4, 0x90
.type _Z12getChunkInfoiPiS_S_S_iiii,@function
_Z12getChunkInfoiPiS_S_S_iiii: # @_Z12getChunkInfoiPiS_S_S_iiii
.cfi_startproc
# %bb.0:
movl %r9d, %eax
movq %rdx, %r10
movl %edi, %r9d
movl 8(%rsp), %r11d
cltd
idivl %r11d
movl %edx, %edi
movl %r11d, %eax
imull %r9d, %eax
movl %eax, (%rcx)
movl %r9d, %eax
cltd
idivl 24(%rsp)
movl %edx, (%r8)
movl %r11d, (%r10)
imull (%r8), %r11d
movl %r11d, (%rsi)
testl %edi, %edi
je .LBB3_3
# %bb.1:
movl 16(%rsp), %eax
decl %eax
cmpl %r9d, %eax
jne .LBB3_3
# %bb.2:
movl %edi, (%r10)
.LBB3_3:
retq
.Lfunc_end3:
.size _Z12getChunkInfoiPiS_S_S_iiii, .Lfunc_end3-_Z12getChunkInfoiPiS_S_S_iiii
.cfi_endproc
# -- End function
.globl _Z12arrayFuncCPUPKfS0_Pfi # -- Begin function _Z12arrayFuncCPUPKfS0_Pfi
.p2align 4, 0x90
.type _Z12arrayFuncCPUPKfS0_Pfi,@function
_Z12arrayFuncCPUPKfS0_Pfi: # @_Z12arrayFuncCPUPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB4_4
# %bb.1: # %.critedge.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB4_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB4_4: # %._crit_edge
retq
.Lfunc_end4:
.size _Z12arrayFuncCPUPKfS0_Pfi, .Lfunc_end4-_Z12arrayFuncCPUPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayFuncPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayFuncPfS_S_i,@object # @_Z9arrayFuncPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9arrayFuncPfS_S_i
.p2align 3, 0x0
_Z9arrayFuncPfS_S_i:
.quad _Z24__device_stub__arrayFuncPfS_S_i
.size _Z9arrayFuncPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Number of streams: %d\n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Number of chunks: %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nGPU computation ... "
.size .L.str.3, 22
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Elapsed time on GPU: %.2f ms\n"
.size .L.str.5, 30
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nCPU computation ... "
.size .L.str.6, 22
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Elapsed time on CPU: %.2f ms\n"
.size .L.str.7, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nSpeed UP CPU/GPU %.1fx\n"
.size .L.str.8, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "h_c[0] = %f\n"
.size .L.str.10, 19
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cpuResult[0] = %f\n"
.size .L.str.11, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9arrayFuncPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "ok"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nCheck results:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayFuncPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayFuncPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) - 1) / 2)
__global__ void nlmSimple(int N, double const *input_grid, double *output_grid, float filtSigma)
{
__shared__ double temp_grid[BLOCK_SIZE * FILTER_SIZE];
// Define global and local indices of current pixel
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + FILTER_RADIUS * blockDim.x;
int pix_ix, pix_iy, pix_jx, pix_jy;
double neighbor_j,
neighbor_i,
output = 0,
sum_weights = 0;
// Read input elements into shared memory
for (int i = -FILTER_RADIUS; i <= FILTER_RADIUS; i++)
{
if ((int)blockIdx.x + i >= 0 && (int)blockIdx.x + i < N)
{
temp_grid[lindex + i * (int)blockDim.x] = input_grid[gindex + i * (int)blockDim.x];
}
}
// Synchronize (ensure all the data is available)
__syncthreads();
pix_iy = lindex % N;
pix_ix = (lindex - pix_iy) / N;
if (pix_ix < FILTER_SIZE && pix_iy < N)
{
int window_radius = (WINDOW_SIZE - 1) / 2;
int neighbor_radius = (NEIGHBOR_SIZE - 1) / 2;
// Iterate through window
for (int k = -window_radius; k <= window_radius; k++)
for (int l = -window_radius; l <= window_radius; l++)
{
double weight = 0;
double distance = 0;
pix_jx = pix_ix + k;
pix_jy = pix_iy + l;
if (pix_jx < 0 || pix_jx >= FILTER_SIZE ||
pix_jy < 0 || pix_jy >= N)
continue;
// Iterate through every pix_j neighbors
for (int p = -neighbor_radius; p <= neighbor_radius; p++)
for (int q = -neighbor_radius; q <= neighbor_radius; q++)
{
if (pix_jx + p < 0 || pix_jx + p >= FILTER_SIZE ||
pix_jy + q < 0 || pix_jy + q >= N ||
pix_ix + p < 0 || pix_ix + p >= FILTER_SIZE ||
pix_iy + q < 0 || pix_iy + q >= N)
continue;
neighbor_j = TEMP(pix_jx + p, pix_jy + q);
neighbor_i = TEMP(pix_ix + p, pix_iy + q);
distance += (neighbor_i - neighbor_j) * (neighbor_i - neighbor_j);
}
// Derive weight for pixels i and j
weight = __expf(-(distance / filtSigma +
(k*k + l*l) * (1.0f)/(float)(WINDOW_SIZE* WINDOW_SIZE)));
sum_weights += weight;
// Sum for every pixel in the window
output += TEMP(pix_jx, pix_jy) * weight;
}
// Normalize
sum_weights = (double)(1 / sum_weights);
output *= sum_weights;
// Write output to global memory
output_grid[gindex] = output;
}
} | .file "tmpxft_001638b3_00000000-6_nlmSharedKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
.type _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf, @function
_Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9nlmSimpleiPKdPdf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf, .-_Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
.globl _Z9nlmSimpleiPKdPdf
.type _Z9nlmSimpleiPKdPdf, @function
_Z9nlmSimpleiPKdPdf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z9nlmSimpleiPKdPdf, .-_Z9nlmSimpleiPKdPdf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9nlmSimpleiPKdPdf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9nlmSimpleiPKdPdf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) - 1) / 2)
__global__ void nlmSimple(int N, double const *input_grid, double *output_grid, float filtSigma)
{
__shared__ double temp_grid[BLOCK_SIZE * FILTER_SIZE];
// Define global and local indices of current pixel
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + FILTER_RADIUS * blockDim.x;
int pix_ix, pix_iy, pix_jx, pix_jy;
double neighbor_j,
neighbor_i,
output = 0,
sum_weights = 0;
// Read input elements into shared memory
for (int i = -FILTER_RADIUS; i <= FILTER_RADIUS; i++)
{
if ((int)blockIdx.x + i >= 0 && (int)blockIdx.x + i < N)
{
temp_grid[lindex + i * (int)blockDim.x] = input_grid[gindex + i * (int)blockDim.x];
}
}
// Synchronize (ensure all the data is available)
__syncthreads();
pix_iy = lindex % N;
pix_ix = (lindex - pix_iy) / N;
if (pix_ix < FILTER_SIZE && pix_iy < N)
{
int window_radius = (WINDOW_SIZE - 1) / 2;
int neighbor_radius = (NEIGHBOR_SIZE - 1) / 2;
// Iterate through window
for (int k = -window_radius; k <= window_radius; k++)
for (int l = -window_radius; l <= window_radius; l++)
{
double weight = 0;
double distance = 0;
pix_jx = pix_ix + k;
pix_jy = pix_iy + l;
if (pix_jx < 0 || pix_jx >= FILTER_SIZE ||
pix_jy < 0 || pix_jy >= N)
continue;
// Iterate through every pix_j neighbors
for (int p = -neighbor_radius; p <= neighbor_radius; p++)
for (int q = -neighbor_radius; q <= neighbor_radius; q++)
{
if (pix_jx + p < 0 || pix_jx + p >= FILTER_SIZE ||
pix_jy + q < 0 || pix_jy + q >= N ||
pix_ix + p < 0 || pix_ix + p >= FILTER_SIZE ||
pix_iy + q < 0 || pix_iy + q >= N)
continue;
neighbor_j = TEMP(pix_jx + p, pix_jy + q);
neighbor_i = TEMP(pix_ix + p, pix_iy + q);
distance += (neighbor_i - neighbor_j) * (neighbor_i - neighbor_j);
}
// Derive weight for pixels i and j
weight = __expf(-(distance / filtSigma +
(k*k + l*l) * (1.0f)/(float)(WINDOW_SIZE* WINDOW_SIZE)));
sum_weights += weight;
// Sum for every pixel in the window
output += TEMP(pix_jx, pix_jy) * weight;
}
// Normalize
sum_weights = (double)(1 / sum_weights);
output *= sum_weights;
// Write output to global memory
output_grid[gindex] = output;
}
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) - 1) / 2)
__global__ void nlmSimple(int N, double const *input_grid, double *output_grid, float filtSigma)
{
__shared__ double temp_grid[BLOCK_SIZE * FILTER_SIZE];
// Define global and local indices of current pixel
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + FILTER_RADIUS * blockDim.x;
int pix_ix, pix_iy, pix_jx, pix_jy;
double neighbor_j,
neighbor_i,
output = 0,
sum_weights = 0;
// Read input elements into shared memory
for (int i = -FILTER_RADIUS; i <= FILTER_RADIUS; i++)
{
if ((int)blockIdx.x + i >= 0 && (int)blockIdx.x + i < N)
{
temp_grid[lindex + i * (int)blockDim.x] = input_grid[gindex + i * (int)blockDim.x];
}
}
// Synchronize (ensure all the data is available)
__syncthreads();
pix_iy = lindex % N;
pix_ix = (lindex - pix_iy) / N;
if (pix_ix < FILTER_SIZE && pix_iy < N)
{
int window_radius = (WINDOW_SIZE - 1) / 2;
int neighbor_radius = (NEIGHBOR_SIZE - 1) / 2;
// Iterate through window
for (int k = -window_radius; k <= window_radius; k++)
for (int l = -window_radius; l <= window_radius; l++)
{
double weight = 0;
double distance = 0;
pix_jx = pix_ix + k;
pix_jy = pix_iy + l;
if (pix_jx < 0 || pix_jx >= FILTER_SIZE ||
pix_jy < 0 || pix_jy >= N)
continue;
// Iterate through every pix_j neighbors
for (int p = -neighbor_radius; p <= neighbor_radius; p++)
for (int q = -neighbor_radius; q <= neighbor_radius; q++)
{
if (pix_jx + p < 0 || pix_jx + p >= FILTER_SIZE ||
pix_jy + q < 0 || pix_jy + q >= N ||
pix_ix + p < 0 || pix_ix + p >= FILTER_SIZE ||
pix_iy + q < 0 || pix_iy + q >= N)
continue;
neighbor_j = TEMP(pix_jx + p, pix_jy + q);
neighbor_i = TEMP(pix_ix + p, pix_iy + q);
distance += (neighbor_i - neighbor_j) * (neighbor_i - neighbor_j);
}
// Derive weight for pixels i and j
weight = __expf(-(distance / filtSigma +
(k*k + l*l) * (1.0f)/(float)(WINDOW_SIZE* WINDOW_SIZE)));
sum_weights += weight;
// Sum for every pixel in the window
output += TEMP(pix_jx, pix_jy) * weight;
}
// Normalize
sum_weights = (double)(1 / sum_weights);
output *= sum_weights;
// Write output to global memory
output_grid[gindex] = output;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) - 1) / 2)
__global__ void nlmSimple(int N, double const *input_grid, double *output_grid, float filtSigma)
{
__shared__ double temp_grid[BLOCK_SIZE * FILTER_SIZE];
// Define global and local indices of current pixel
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + FILTER_RADIUS * blockDim.x;
int pix_ix, pix_iy, pix_jx, pix_jy;
double neighbor_j,
neighbor_i,
output = 0,
sum_weights = 0;
// Read input elements into shared memory
for (int i = -FILTER_RADIUS; i <= FILTER_RADIUS; i++)
{
if ((int)blockIdx.x + i >= 0 && (int)blockIdx.x + i < N)
{
temp_grid[lindex + i * (int)blockDim.x] = input_grid[gindex + i * (int)blockDim.x];
}
}
// Synchronize (ensure all the data is available)
__syncthreads();
pix_iy = lindex % N;
pix_ix = (lindex - pix_iy) / N;
if (pix_ix < FILTER_SIZE && pix_iy < N)
{
int window_radius = (WINDOW_SIZE - 1) / 2;
int neighbor_radius = (NEIGHBOR_SIZE - 1) / 2;
// Iterate through window
for (int k = -window_radius; k <= window_radius; k++)
for (int l = -window_radius; l <= window_radius; l++)
{
double weight = 0;
double distance = 0;
pix_jx = pix_ix + k;
pix_jy = pix_iy + l;
if (pix_jx < 0 || pix_jx >= FILTER_SIZE ||
pix_jy < 0 || pix_jy >= N)
continue;
// Iterate through every pix_j neighbors
for (int p = -neighbor_radius; p <= neighbor_radius; p++)
for (int q = -neighbor_radius; q <= neighbor_radius; q++)
{
if (pix_jx + p < 0 || pix_jx + p >= FILTER_SIZE ||
pix_jy + q < 0 || pix_jy + q >= N ||
pix_ix + p < 0 || pix_ix + p >= FILTER_SIZE ||
pix_iy + q < 0 || pix_iy + q >= N)
continue;
neighbor_j = TEMP(pix_jx + p, pix_jy + q);
neighbor_i = TEMP(pix_ix + p, pix_iy + q);
distance += (neighbor_i - neighbor_j) * (neighbor_i - neighbor_j);
}
// Derive weight for pixels i and j
weight = __expf(-(distance / filtSigma +
(k*k + l*l) * (1.0f)/(float)(WINDOW_SIZE* WINDOW_SIZE)));
sum_weights += weight;
// Sum for every pixel in the window
output += TEMP(pix_jx, pix_jy) * weight;
}
// Normalize
sum_weights = (double)(1 / sum_weights);
output *= sum_weights;
// Write output to global memory
output_grid[gindex] = output;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9nlmSimpleiPKdPdf
.globl _Z9nlmSimpleiPKdPdf
.p2align 8
.type _Z9nlmSimpleiPKdPdf,@function
_Z9nlmSimpleiPKdPdf:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s5, -4
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_add_i32 s4, s15, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s6, v[0:1]
s_lshl_b32 s4, s6, 3
s_branch .LBB0_2
.p2align 6
.LBB0_1:
v_add_nc_u32_e32 v3, s4, v3
v_add_nc_u32_e32 v1, s6, v1
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 5
s_cbranch_scc1 .LBB0_4
.LBB0_2:
s_add_i32 s8, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lt_i32 s8, 0
s_cselect_b32 s9, -1, 0
s_cmp_ge_i32 s8, s7
s_cselect_b32 s8, -1, 0
s_or_b32 s8, s9, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[1:2]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
ds_store_b64 v3, v[4:5]
s_branch .LBB0_1
.LBB0_4:
s_ashr_i32 s2, s7, 31
v_lshl_add_u32 v5, s6, 2, v0
s_add_i32 s3, s7, s2
s_waitcnt lgkmcnt(0)
s_xor_b32 s3, s3, s2
s_barrier
v_cvt_f32_u32_e32 v1, s3
v_ashrrev_i32_e32 v3, 31, v5
s_sub_i32 s4, 0, s3
s_cmp_gt_i32 s7, -1
buffer_gl0_inv
v_rcp_iflag_f32_e32 v1, v1
v_add_nc_u32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s2, v3
s_cselect_b32 s2, -1, 0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s3
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v1, v1, v4 :: v_dual_cndmask_b32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v1
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_xor_b32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v1, v3
v_cmp_gt_i32_e32 vcc_lo, 9, v9
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_22
s_load_b32 s2, s[0:1], 0x18
v_lshlrev_b32_e32 v1, 3, v5
v_mul_lo_u32 v6, v9, s7
s_lshl_b32 s8, s7, 3
s_mov_b32 s9, -3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v7, s8, v1
v_sub_nc_u32_e32 v10, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v11, -8, v7
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[3:4], s2
s_lshl_b32 s2, s7, 5
v_subrev_nc_u32_e32 v8, s2, v1
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v12, 32, v8
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v1
s_branch .LBB0_7
.LBB0_6:
v_add_nc_u32_e32 v12, s8, v12
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, 4
s_cbranch_scc1 .LBB0_21
.LBB0_7:
v_add_nc_u32_e32 v13, s9, v9
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v15, v12
s_mul_i32 s10, s9, s9
s_mov_b32 s11, -4
s_mov_b32 s12, -3
v_mul_lo_u32 v14, v13, s7
v_cmp_gt_u32_e64 s2, 9, v13
s_branch .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_div_scale_f64 v[17:18], null, v[3:4], v[3:4], v[7:8]
v_div_scale_f64 v[23:24], vcc_lo, v[7:8], v[3:4], v[7:8]
s_mul_i32 s3, s12, s12
v_add_lshl_u32 v16, v16, v14, 3
s_add_i32 s3, s3, s10
v_rcp_f64_e32 v[19:20], v[17:18]
s_waitcnt_depctr 0xfff
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_fma_f64 v[21:22], -v[17:18], v[19:20], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[19:20], v[19:20], v[21:22], v[19:20]
v_mul_f64 v[21:22], v[23:24], v[19:20]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[17:18], v[21:22], v[23:24]
v_cvt_f32_i32_e32 v23, s3
v_div_scale_f32 v24, null, 0x42440000, 0x42440000, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v25, v24
s_waitcnt_depctr 0xfff
v_fma_f32 v26, -v24, v25, 1.0
v_fmac_f32_e32 v25, v26, v25
v_div_fmas_f64 v[17:18], v[17:18], v[19:20], v[21:22]
v_div_scale_f32 v19, vcc_lo, v23, 0x42440000, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v20, v19, v25
v_fma_f32 v21, -v24, v20, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v20, v21, v25
v_fma_f32 v19, -v24, v20, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v19, v19, v25, v20
v_div_fixup_f32 v19, v19, 0x42440000, v23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[19:20], v19
v_div_fixup_f64 v[7:8], v[17:18], v[3:4], v[7:8]
ds_load_b64 v[16:17], v16
v_add_f64 v[7:8], v[7:8], v[19:20]
v_cvt_f32_f64_e32 v7, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0xbfb8aa3b, v7
v_exp_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_cvt_f64_f32_e32 v[7:8], v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_waitcnt lgkmcnt(0)
v_fma_f64 v[1:2], v[16:17], v[7:8], v[1:2]
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v15, 8, v15
s_add_i32 s12, s12, 1
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s12, 4
s_cbranch_scc1 .LBB0_6
.LBB0_10:
v_add_nc_u32_e32 v16, s12, v10
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v16
v_cmp_gt_i32_e64 s3, s7, v16
s_and_b32 s4, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v18, v11
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v17, v15
s_mov_b32 s14, -1
s_branch .LBB0_13
.LBB0_12:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v18, s8, v18
v_add_nc_u32_e32 v17, s8, v17
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s14, 2
s_cbranch_scc1 .LBB0_8
.LBB0_13:
v_add_nc_u32_e32 v19, s14, v13
v_add_nc_u32_e32 v20, s14, v9
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, 9, v19
v_mov_b32_e32 v19, v10
v_cmp_lt_u32_e64 s3, 8, v20
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_17
.p2align 6
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s18
.LBB0_16:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v19, 1, v19
s_add_i32 s16, s16, 8
s_cmp_eq_u32 s16, 24
s_cbranch_scc1 .LBB0_12
.LBB0_17:
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_16
v_add_nc_u32_e32 v20, s11, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s4, 0, v20
v_cmp_le_i32_e64 s5, s7, v20
s_or_b32 s4, s4, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s4, s3
s_xor_b32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s18, s4
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v20, -1, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s4, -1, v20
v_cmp_gt_i32_e64 s5, s7, v20
s_and_b32 s5, s4, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s5
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v20, s16, v17
v_add_nc_u32_e32 v22, s16, v18
ds_load_b64 v[20:21], v20
ds_load_b64 v[22:23], v22
s_waitcnt lgkmcnt(0)
v_add_f64 v[20:21], v[22:23], -v[20:21]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[7:8], v[20:21], v[20:21], v[7:8]
s_branch .LBB0_14
.LBB0_21:
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_scale_f64 v[3:4], null, v[5:6], v[5:6], 1.0
s_load_b64 s[0:1], s[0:1], 0x10
v_rcp_f64_e32 v[7:8], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
v_div_scale_f64 v[9:10], vcc_lo, 1.0, v[5:6], 1.0
v_mul_f64 v[11:12], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], -v[3:4], v[11:12], v[9:10]
v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[3:4], v[5:6], 1.0
v_mul_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9nlmSimpleiPKdPdf
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9nlmSimpleiPKdPdf, .Lfunc_end0-_Z9nlmSimpleiPKdPdf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9nlmSimpleiPKdPdf
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z9nlmSimpleiPKdPdf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) - 1) / 2)
__global__ void nlmSimple(int N, double const *input_grid, double *output_grid, float filtSigma)
{
__shared__ double temp_grid[BLOCK_SIZE * FILTER_SIZE];
// Define global and local indices of current pixel
int gindex = threadIdx.x + blockIdx.x * blockDim.x;
int lindex = threadIdx.x + FILTER_RADIUS * blockDim.x;
int pix_ix, pix_iy, pix_jx, pix_jy;
double neighbor_j,
neighbor_i,
output = 0,
sum_weights = 0;
// Read input elements into shared memory
for (int i = -FILTER_RADIUS; i <= FILTER_RADIUS; i++)
{
if ((int)blockIdx.x + i >= 0 && (int)blockIdx.x + i < N)
{
temp_grid[lindex + i * (int)blockDim.x] = input_grid[gindex + i * (int)blockDim.x];
}
}
// Synchronize (ensure all the data is available)
__syncthreads();
pix_iy = lindex % N;
pix_ix = (lindex - pix_iy) / N;
if (pix_ix < FILTER_SIZE && pix_iy < N)
{
int window_radius = (WINDOW_SIZE - 1) / 2;
int neighbor_radius = (NEIGHBOR_SIZE - 1) / 2;
// Iterate through window
for (int k = -window_radius; k <= window_radius; k++)
for (int l = -window_radius; l <= window_radius; l++)
{
double weight = 0;
double distance = 0;
pix_jx = pix_ix + k;
pix_jy = pix_iy + l;
if (pix_jx < 0 || pix_jx >= FILTER_SIZE ||
pix_jy < 0 || pix_jy >= N)
continue;
// Iterate through every pix_j neighbors
for (int p = -neighbor_radius; p <= neighbor_radius; p++)
for (int q = -neighbor_radius; q <= neighbor_radius; q++)
{
if (pix_jx + p < 0 || pix_jx + p >= FILTER_SIZE ||
pix_jy + q < 0 || pix_jy + q >= N ||
pix_ix + p < 0 || pix_ix + p >= FILTER_SIZE ||
pix_iy + q < 0 || pix_iy + q >= N)
continue;
neighbor_j = TEMP(pix_jx + p, pix_jy + q);
neighbor_i = TEMP(pix_ix + p, pix_iy + q);
distance += (neighbor_i - neighbor_j) * (neighbor_i - neighbor_j);
}
// Derive weight for pixels i and j
weight = __expf(-(distance / filtSigma +
(k*k + l*l) * (1.0f)/(float)(WINDOW_SIZE* WINDOW_SIZE)));
sum_weights += weight;
// Sum for every pixel in the window
output += TEMP(pix_jx, pix_jy) * weight;
}
// Normalize
sum_weights = (double)(1 / sum_weights);
output *= sum_weights;
// Write output to global memory
output_grid[gindex] = output;
}
} | .text
.file "nlmSharedKernel.hip"
.globl _Z24__device_stub__nlmSimpleiPKdPdf # -- Begin function _Z24__device_stub__nlmSimpleiPKdPdf
.p2align 4, 0x90
.type _Z24__device_stub__nlmSimpleiPKdPdf,@function
_Z24__device_stub__nlmSimpleiPKdPdf: # @_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movss %xmm0, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9nlmSimpleiPKdPdf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__nlmSimpleiPKdPdf, .Lfunc_end0-_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9nlmSimpleiPKdPdf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9nlmSimpleiPKdPdf,@object # @_Z9nlmSimpleiPKdPdf
.section .rodata,"a",@progbits
.globl _Z9nlmSimpleiPKdPdf
.p2align 3, 0x0
_Z9nlmSimpleiPKdPdf:
.quad _Z24__device_stub__nlmSimpleiPKdPdf
.size _Z9nlmSimpleiPKdPdf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9nlmSimpleiPKdPdf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__nlmSimpleiPKdPdf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9nlmSimpleiPKdPdf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001638b3_00000000-6_nlmSharedKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
.type _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf, @function
_Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9nlmSimpleiPKdPdf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf, .-_Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
.globl _Z9nlmSimpleiPKdPdf
.type _Z9nlmSimpleiPKdPdf, @function
_Z9nlmSimpleiPKdPdf:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9nlmSimpleiPKdPdfiPKdPdf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z9nlmSimpleiPKdPdf, .-_Z9nlmSimpleiPKdPdf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9nlmSimpleiPKdPdf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9nlmSimpleiPKdPdf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nlmSharedKernel.hip"
.globl _Z24__device_stub__nlmSimpleiPKdPdf # -- Begin function _Z24__device_stub__nlmSimpleiPKdPdf
.p2align 4, 0x90
.type _Z24__device_stub__nlmSimpleiPKdPdf,@function
_Z24__device_stub__nlmSimpleiPKdPdf: # @_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movss %xmm0, 8(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9nlmSimpleiPKdPdf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__nlmSimpleiPKdPdf, .Lfunc_end0-_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9nlmSimpleiPKdPdf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9nlmSimpleiPKdPdf,@object # @_Z9nlmSimpleiPKdPdf
.section .rodata,"a",@progbits
.globl _Z9nlmSimpleiPKdPdf
.p2align 3, 0x0
_Z9nlmSimpleiPKdPdf:
.quad _Z24__device_stub__nlmSimpleiPKdPdf
.size _Z9nlmSimpleiPKdPdf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9nlmSimpleiPKdPdf"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__nlmSimpleiPKdPdf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9nlmSimpleiPKdPdf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} | .file "tmpxft_001205af_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.globl _Z6matmulPdS_S_i
.type _Z6matmulPdS_S_i, @function
_Z6matmulPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matmulPdS_S_i, .-_Z6matmulPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matmulPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPdS_S_i, .Lfunc_end0-_Z6matmulPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
} | .text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPdS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPdS_S_i,@object # @_Z6matmulPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPdS_S_i
.p2align 3, 0x0
_Z6matmulPdS_S_i:
.quad _Z21__device_stub__matmulPdS_S_i
.size _Z6matmulPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matmulPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPdS_S_i, .Lfunc_end0-_Z6matmulPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001205af_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.globl _Z6matmulPdS_S_i
.type _Z6matmulPdS_S_i, @function
_Z6matmulPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6matmulPdS_S_i, .-_Z6matmulPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6matmulPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPdS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPdS_S_i,@object # @_Z6matmulPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPdS_S_i
.p2align 3, 0x0
_Z6matmulPdS_S_i:
.quad _Z21__device_stub__matmulPdS_S_i
.size _Z6matmulPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6matmulPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | code for sm_80
Function : _Z25BaseNeuronSetFloatPtArrayPfPiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R4, R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a24 */
/* 0x004fc800078e02ff */
/*00c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .file "tmpxft_00191108_00000000-6_BaseNeuronSetFloatPtArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
.type _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif, @function
_Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25BaseNeuronSetFloatPtArrayPfPiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif, .-_Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif, @function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, .-_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25BaseNeuronSetFloatPtArrayPfPiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25BaseNeuronSetFloatPtArrayPfPiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25BaseNeuronSetFloatPtArrayPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 8
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_mov_b32_e32 v2, s1
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, s0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25BaseNeuronSetFloatPtArrayPfPiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, .Lfunc_end0-_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25BaseNeuronSetFloatPtArrayPfPiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25BaseNeuronSetFloatPtArrayPfPiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .text
.file "BaseNeuronSetFloatPtArray.hip"
.globl _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif # -- Begin function _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.p2align 4, 0x90
.type _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif: # @_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25BaseNeuronSetFloatPtArrayPfPiiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif, .Lfunc_end0-_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25BaseNeuronSetFloatPtArrayPfPiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@object # @_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .rodata,"a",@progbits
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 3, 0x0
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
.quad _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25BaseNeuronSetFloatPtArrayPfPiiif"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25BaseNeuronSetFloatPtArrayPfPiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25BaseNeuronSetFloatPtArrayPfPiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R4, R2, c[0x0][0x174], RZ ; /* 0x00005d0002047a24 */
/* 0x004fc800078e02ff */
/*00c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25BaseNeuronSetFloatPtArrayPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 8
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_mov_b32_e32 v2, s1
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v0, s0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25BaseNeuronSetFloatPtArrayPfPiiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, .Lfunc_end0-_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25BaseNeuronSetFloatPtArrayPfPiiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25BaseNeuronSetFloatPtArrayPfPiiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00191108_00000000-6_BaseNeuronSetFloatPtArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
.type _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif, @function
_Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25BaseNeuronSetFloatPtArrayPfPiiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif, .-_Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif, @function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25BaseNeuronSetFloatPtArrayPfPiiifPfPiiif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, .-_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25BaseNeuronSetFloatPtArrayPfPiiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25BaseNeuronSetFloatPtArrayPfPiiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BaseNeuronSetFloatPtArray.hip"
.globl _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif # -- Begin function _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.p2align 4, 0x90
.type _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif: # @_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25BaseNeuronSetFloatPtArrayPfPiiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif, .Lfunc_end0-_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25BaseNeuronSetFloatPtArrayPfPiiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@object # @_Z25BaseNeuronSetFloatPtArrayPfPiiif
.section .rodata,"a",@progbits
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 3, 0x0
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
.quad _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.size _Z25BaseNeuronSetFloatPtArrayPfPiiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25BaseNeuronSetFloatPtArrayPfPiiif"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25BaseNeuronSetFloatPtArrayPfPiiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*******************************************************************************
*
******************************************************************************/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
*
******************************************************************************/ | .file "tmpxft_000f63fd_00000000-6_CuMain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
*
******************************************************************************/ | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ | .text
.file "CuMain.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f63fd_00000000-6_CuMain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CuMain.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start, 0);
cudaEventCreate(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
cudaMalloc((void **)&dev_data, sizeof(int) * SIZE);
cudaMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
cudaEventRecord(start, 0);
cudaMemcpy(dev_data, data, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
cudaMemcpy(count, dev_c, sizeof(int) * numOfBlocks, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
cudaFree(dev_data);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z14countOddKernelPilS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ LOP3.LUT R0, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102007812 */
/* 0x004fc800078ec0ff */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00f0*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff008424 */
/* 0x000fca00078e00ff */
/*0100*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0110*/ @P0 STS [R7.X4], RZ ; /* 0x000000ff07000388 */
/* 0x0001e40000004800 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0160*/ ISETP.NE.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003f05270 */
/*0170*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fc800078e00ff */
/*0180*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0190*/ @!P1 BRA 0x270 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*01c0*/ @!P1 IMAD R2, R3.reuse, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x040fe200078e0200 */
/*01d0*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe80000004800 */
/*01e0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0210*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0220*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0250*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0260*/ @P1 BRA 0x1b0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start, 0);
cudaEventCreate(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
cudaMalloc((void **)&dev_data, sizeof(int) * SIZE);
cudaMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
cudaEventRecord(start, 0);
cudaMemcpy(dev_data, data, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
cudaMemcpy(count, dev_c, sizeof(int) * numOfBlocks, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
cudaFree(dev_data);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_00111175_00000000-6_oddInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14countOddKernelPilS_PilS_
.type _Z37__device_stub__Z14countOddKernelPilS_PilS_, @function
_Z37__device_stub__Z14countOddKernelPilS_PilS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14countOddKernelPilS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z14countOddKernelPilS_PilS_, .-_Z37__device_stub__Z14countOddKernelPilS_PilS_
.globl _Z14countOddKernelPilS_
.type _Z14countOddKernelPilS_, @function
_Z14countOddKernelPilS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14countOddKernelPilS_PilS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14countOddKernelPilS_, .-_Z14countOddKernelPilS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time : %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaEventCreateWithFlags@PLT
leaq 24(%rsp), %rdi
movl $0, %esi
call cudaEventCreateWithFlags@PLT
movl $8000000, %edi
call malloc@PLT
movq %rax, %r12
movl $2000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $8000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 8000000(%r12), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $8000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $500000, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2000000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $500000, %eax
.L14:
subl $1, %eax
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $2000000, %esi
movq (%rsp), %rdi
call _Z37__device_stub__Z14countOddKernelPilS_PilS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14countOddKernelPilS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14countOddKernelPilS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<cuda.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start, 0);
cudaEventCreate(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
cudaMalloc((void **)&dev_data, sizeof(int) * SIZE);
cudaMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
cudaEventRecord(start, 0);
cudaMemcpy(dev_data, data, sizeof(int) * SIZE, cudaMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
cudaMemcpy(count, dev_c, sizeof(int) * numOfBlocks, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
cudaFree(dev_data);
cudaFree(dev_c);
return 0;
} | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
hipEvent_t start, stop;
hipEventCreateWithFlags(&start, 0);
hipEventCreateWithFlags(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
hipMalloc((void **)&dev_data, sizeof(int) * SIZE);
hipMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
hipEventRecord(start, 0);
hipMemcpy(dev_data, data, sizeof(int) * SIZE, hipMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
hipMemcpy(count, dev_c, sizeof(int) * numOfBlocks, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
hipFree(dev_data);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
hipEvent_t start, stop;
hipEventCreateWithFlags(&start, 0);
hipEventCreateWithFlags(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
hipMalloc((void **)&dev_data, sizeof(int) * SIZE);
hipMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
hipEventRecord(start, 0);
hipMemcpy(dev_data, data, sizeof(int) * SIZE, hipMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
hipMemcpy(count, dev_c, sizeof(int) * numOfBlocks, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
hipFree(dev_data);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countOddKernelPilS_
.globl _Z14countOddKernelPilS_
.p2align 8
.type _Z14countOddKernelPilS_,@function
_Z14countOddKernelPilS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 1, v1
ds_store_b32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v1, 2, v0
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countOddKernelPilS_
.amdhsa_group_segment_fixed_size 20
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14countOddKernelPilS_, .Lfunc_end0-_Z14countOddKernelPilS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countOddKernelPilS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countOddKernelPilS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each block is passed back to the CPU, where all of them are added to get the final count.
* Implemented in CUDA
*
*
*
* coded by Anand Goyal. Dated: 12/13/2014
*/
#include<stdio.h>
#include<hip/hip_runtime.h>
#include<time.h>
#include<sys/time.h>
#define SIZE 2000000
#define THREAD_NUM 4
__global__ void countOddKernel(int *inData, long size, int *count)
{
__shared__ int temp[THREAD_NUM + 1];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
if(tid < size) {
if(inData[tid] % 2 != 0)
temp[threadIdx.x] = 1;
else
temp[threadIdx.x] = 0;
}
__syncthreads();
int i = blockDim.x/2;
while(i != 0) {
if(threadIdx.x < i)
temp[threadIdx.x] += temp[threadIdx.x + i];
__syncthreads();
i /= 2;
}
if(threadIdx.x == 0)
count[blockIdx.x] = temp[0];
}
int main()
{
int *data, *dev_data, *count, *dev_c;
int i, total_count = 0;
int numOfBlocks = (SIZE + THREAD_NUM - 1)/THREAD_NUM;
float elapsedTime;
hipEvent_t start, stop;
hipEventCreateWithFlags(&start, 0);
hipEventCreateWithFlags(&stop, 0);
data = (int *)malloc(sizeof(int) * SIZE);
count = (int *)malloc(sizeof(int) * numOfBlocks );
hipMalloc((void **)&dev_data, sizeof(int) * SIZE);
hipMalloc((void **)&dev_c, sizeof(int) * numOfBlocks);
srand(time(NULL));
for(i = 0; i < SIZE; i++) {
data[i] = rand()%100 + 1;
}
/* for(i = 0; i < SIZE; i++)
printf("%d\n", data[i]);
printf("*************************\n");
*/
hipEventRecord(start, 0);
hipMemcpy(dev_data, data, sizeof(int) * SIZE, hipMemcpyHostToDevice);
countOddKernel<<<numOfBlocks, THREAD_NUM>>>(dev_data, SIZE, dev_c);
hipMemcpy(count, dev_c, sizeof(int) * numOfBlocks, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
for(i = 0; i < numOfBlocks; i++) {
total_count += count[i];
}
// printf("Number of Odd numbers = %d\n", total_count);
printf("Time : %3.1f ms \n", elapsedTime);
free(data);
free(count);
hipFree(dev_data);
hipFree(dev_c);
return 0;
} | .text
.file "oddInt.hip"
.globl _Z29__device_stub__countOddKernelPilS_ # -- Begin function _Z29__device_stub__countOddKernelPilS_
.p2align 4, 0x90
.type _Z29__device_stub__countOddKernelPilS_,@function
_Z29__device_stub__countOddKernelPilS_: # @_Z29__device_stub__countOddKernelPilS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14countOddKernelPilS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__countOddKernelPilS_, .Lfunc_end0-_Z29__device_stub__countOddKernelPilS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventCreateWithFlags
movq %rsp, %rdi
xorl %esi, %esi
callq hipEventCreateWithFlags
movl $8000000, %edi # imm = 0x7A1200
callq malloc
movq %rax, %rbx
movl $2000000, %edi # imm = 0x1E8480
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $2000000, %r15 # imm = 0x1E8480
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movl $8000000, %edx # imm = 0x7A1200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 499996(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq $2000000, 112(%rsp) # imm = 0x1E8480
movq %rcx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14countOddKernelPilS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14countOddKernelPilS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14countOddKernelPilS_,@object # @_Z14countOddKernelPilS_
.section .rodata,"a",@progbits
.globl _Z14countOddKernelPilS_
.p2align 3, 0x0
_Z14countOddKernelPilS_:
.quad _Z29__device_stub__countOddKernelPilS_
.size _Z14countOddKernelPilS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %3.1f ms \n"
.size .L.str, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14countOddKernelPilS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__countOddKernelPilS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14countOddKernelPilS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14countOddKernelPilS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x130 ; /* 0x000000f000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 BRA 0x120 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00a0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ LOP3.LUT R0, R2, 0x1, RZ, 0xc0, !PT ; /* 0x0000000102007812 */
/* 0x004fc800078ec0ff */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05070 */
/*00f0*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff008424 */
/* 0x000fca00078e00ff */
/*0100*/ @!P0 STS [R7.X4], R0 ; /* 0x0000000007008388 */
/* 0x0001e80000004800 */
/*0110*/ @P0 STS [R7.X4], RZ ; /* 0x000000ff07000388 */
/* 0x0001e40000004800 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0160*/ ISETP.NE.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720c */
/* 0x040fe20003f05270 */
/*0170*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fc800078e00ff */
/*0180*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*0190*/ @!P1 BRA 0x270 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*01c0*/ @!P1 IMAD R2, R3.reuse, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x040fe200078e0200 */
/*01d0*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe80000004800 */
/*01e0*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 IMAD.IADD R4, R4, 0x1, R5 ; /* 0x0000000104049824 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0210*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0220*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0250*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0260*/ @P1 BRA 0x1b0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*0270*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0280*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02a0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*02b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countOddKernelPilS_
.globl _Z14countOddKernelPilS_
.p2align 8
.type _Z14countOddKernelPilS_,@function
_Z14countOddKernelPilS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 1, v1
ds_store_b32 v2, v1
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_lshlrev_b32_e32 v1, 2, v0
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_4
.LBB0_7:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14countOddKernelPilS_
.amdhsa_group_segment_fixed_size 20
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14countOddKernelPilS_, .Lfunc_end0-_Z14countOddKernelPilS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 20
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14countOddKernelPilS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14countOddKernelPilS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111175_00000000-6_oddInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14countOddKernelPilS_PilS_
.type _Z37__device_stub__Z14countOddKernelPilS_PilS_, @function
_Z37__device_stub__Z14countOddKernelPilS_PilS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14countOddKernelPilS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z14countOddKernelPilS_PilS_, .-_Z37__device_stub__Z14countOddKernelPilS_PilS_
.globl _Z14countOddKernelPilS_
.type _Z14countOddKernelPilS_, @function
_Z14countOddKernelPilS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14countOddKernelPilS_PilS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14countOddKernelPilS_, .-_Z14countOddKernelPilS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time : %3.1f ms \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %esi
call cudaEventCreateWithFlags@PLT
leaq 24(%rsp), %rdi
movl $0, %esi
call cudaEventCreateWithFlags@PLT
movl $8000000, %edi
call malloc@PLT
movq %rax, %r12
movl $2000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $8000000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $2000000, %esi
call cudaMalloc@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 8000000(%r12), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $8000000, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $500000, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $2000000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $500000, %eax
.L14:
subl $1, %eax
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $2000000, %esi
movq (%rsp), %rdi
call _Z37__device_stub__Z14countOddKernelPilS_PilS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14countOddKernelPilS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14countOddKernelPilS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "oddInt.hip"
.globl _Z29__device_stub__countOddKernelPilS_ # -- Begin function _Z29__device_stub__countOddKernelPilS_
.p2align 4, 0x90
.type _Z29__device_stub__countOddKernelPilS_,@function
_Z29__device_stub__countOddKernelPilS_: # @_Z29__device_stub__countOddKernelPilS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14countOddKernelPilS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__countOddKernelPilS_, .Lfunc_end0-_Z29__device_stub__countOddKernelPilS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventCreateWithFlags
movq %rsp, %rdi
xorl %esi, %esi
callq hipEventCreateWithFlags
movl $8000000, %edi # imm = 0x7A1200
callq malloc
movq %rax, %rbx
movl $2000000, %edi # imm = 0x1E8480
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $8000000, %esi # imm = 0x7A1200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2000000, %esi # imm = 0x1E8480
callq hipMalloc
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq $2000000, %r15 # imm = 0x1E8480
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
movl $8000000, %edx # imm = 0x7A1200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 499996(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 120(%rsp)
movq $2000000, 112(%rsp) # imm = 0x1E8480
movq %rcx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z14countOddKernelPilS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $2000000, %edx # imm = 0x1E8480
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14countOddKernelPilS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14countOddKernelPilS_,@object # @_Z14countOddKernelPilS_
.section .rodata,"a",@progbits
.globl _Z14countOddKernelPilS_
.p2align 3, 0x0
_Z14countOddKernelPilS_:
.quad _Z29__device_stub__countOddKernelPilS_
.size _Z14countOddKernelPilS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %3.1f ms \n"
.size .L.str, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14countOddKernelPilS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__countOddKernelPilS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14countOddKernelPilS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel(int n, int c, int* NNZ, int* preSum, int* colIndex,int* randoms, int* colors){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x*gridDim.x;
if (index < n){
for (int i = index; i < n; i += stride){
bool f = true;
if ((colors[i] != -1 )){
continue;
}
int ir = randoms[i];
for (int k = preSum[i]; k < preSum[i + 1]; k++){
int j = colIndex[k];
int jc = colors[j];
if (((jc != -1) && (jc != c)) || (i == j)){
continue;
}
int jr = randoms[j];
if (ir <= jr){
f = false;
}
}
if (f){
colors[i] = c;
}
}
}
}
//jones plassmann luby algorithm for graphcoloring
void colorJPL(int n, int* NNZ, int* preSum, int* colIndex, int* colors){
int* randoms;
cudaMallocManaged(&randoms, sizeof(int)* n);
for (int i = 0; i < n; i++){
randoms[i] = rand();
}
thrust::fill(colors, colors+n, -1);
for(int c = 1; c< n+1; c++){
int nt = 256;
int nb = min((n + nt -1)/nt, MAXBLOCKS);
colorJPLKernel<<<nb,nt>>>(n,c,NNZ,preSum,colIndex, randoms,colors);
cudaDeviceSynchronize();
int left = (int)thrust::count(colors, colors+n, -1);
if (left ==0){
break;
}
}
printf("\n");
for(int i = 0; i < n; i++){
printf("%d ", colors[i]);
}
printf("\n");
cudaFree(randoms);
}
// Counts the number of unique colors in a solution
int CountColors(int V, int* color)
{
int num_colors = 0;
set<int> seen_colors;
for (int i = 0; i < V; i++) {
if (seen_colors.find(color[i]) == seen_colors.end()) {
seen_colors.insert(color[i]);
num_colors++;
}
}
return num_colors;
}
// Returns true if the color assignment is valid for the graph
bool IsValidColoring(bool* graph, int V, int* color)
{
for (int i = 0; i < V; i++) {
for (int j = 0; j < V; j++) {
if (graph[i * V + j]) {
if (i != j && color[i] == color[j]) {
printf("Vertex %d and Vertex %d are connected and have the same color %d\n", i, j, color[i]);
return false;
}
if (color[i] < 1) {
printf("Vertex %d has invalid color %d\n", i, color[i]);
return false;
}
}
}
}
return true;
}
// Read DIMACS graphs
// Assumes input nodes are numbered starting from 1
void ReadColFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
int num_rows, num_edges;
while (getline(infile, line)) {
istringstream iss(line);
string s;
int node1, node2;
iss >> s;
if (s == "p") {
iss >> s; // read string "edge"
iss >> num_rows;
iss >> num_edges;
*V = num_rows;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
continue;
} else if (s != "e")
continue;
iss >> node1 >> node2;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
// Read MatrixMarket graphs
// Assumes input nodes are numbered starting from 1
void ReadMMFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
// Reading comments
while (getline(infile, line)) {
istringstream iss(line);
if (line.find("%") == string::npos)
break;
}
// Reading metadata
istringstream iss(line);
int num_rows, num_cols, num_edges;
iss >> num_rows >> num_cols >> num_edges;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
*V = num_rows;
// Reading nodes
while (getline(infile, line)) {
istringstream iss(line);
int node1, node2, weight;
iss >> node1 >> node2 >> weight;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
//store sparse graph in compressed sparse row format
void CSRConvert(bool** graph, int rows, int** NNZ, int* preSum, int** colIndex, int* counter){
//assume square matrix
int cols = rows;
*counter = 0;
int rowElem[rows];
for (int i = 0; i < rows; i++){
rowElem[i] = 0;
}
//initialize preSum
preSum[0] = 0;
for (int i = 0; i < rows; i++){
for (int j = 0; j < cols; j++){
if ((*graph)[i*rows + j] == false){
continue;
}
else{
//reallocate size of NNZ and colIndex
*NNZ = (int*)realloc(*NNZ, sizeof(int)*(*counter + 1));
(*NNZ)[*counter] = 1;
*colIndex = (int*)realloc(*colIndex, sizeof(int) * (*counter +1));
(*colIndex)[*counter] = j;
//preSum[counter + 1] = preSum[counter] + prevRowCount;
rowElem[i]++;
*counter += 1;
}
}
}
for (int i = 0; i < rows +1; i++){
preSum[i+1] = preSum[i] + rowElem[i];
}
}
void GraphColoringGPU(const char filename[], int** color){
bool* graph;
int V;
if (string(filename).find(".col") != string::npos)
ReadColFile(filename, &graph, &V);
else{
ReadMMFile(filename, &graph, &V);
}
//convert the sparse array into compact sparse row format
int *NNZ = (int*)malloc(sizeof(int));
int *preSum = (int*)malloc(sizeof(int) * (V + 1));
int *colIndex= (int*)malloc(sizeof(int));
int counter = 0;
CSRConvert(&graph, V, &NNZ, preSum, &colIndex, &counter);
//migrate values to GPU
int* Ao;
int* Av;
int* Ac;
int* colors;
cudaMallocManaged(&Ao, sizeof(int)*(V+1));
cudaMallocManaged(&Av, sizeof(int)*counter);
cudaMallocManaged(&Ac, sizeof(int)*counter);
cudaMallocManaged(&colors, sizeof(int)* V);
for(int i = 0; i < counter; i++){
Av[i] = NNZ[i];
Ac[i] = colIndex[i];
}
//printf("offset values : ");
for (int i = 0; i < V + 1; i++){
Ao[i] = preSum[i];
}
colorJPL(V, Av, Ao, Ac,colors);
printf("JPL coloring found solution with %d colors\n", CountColors(V, colors));
printf("Valid coloring: %d\n", IsValidColoring(graph, V, colors));
free(NNZ);
free(preSum);
free(colIndex);
cudaFree(Ao);
cudaFree(Av);
cudaFree(Ac);
}
int main(int argc, char* argv[]){
const char fileName[] = "/home/zwharris/EEC289Q/Hw3/planar16.col";
int* color;
GraphColoringGPU(fileName, &color);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14colorJPLKerneliiPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R10, R9, c[0x0][0x188] ; /* 0x000062000a027625 */
/* 0x000fca00078e0209 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B1, 0x9b0 ; /* 0x0000090000017945 */
/* 0x000fe20003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x004fda0003f05270 */
/*00c0*/ @P0 BRA 0x9a0 ; /* 0x000008d000000947 */
/* 0x020fea0003800000 */
/*00d0*/ IMAD.SHL.U32 R6, R10, 0x4, RZ ; /* 0x000000040a067824 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fc8000001140a */
/*00f0*/ SHF.L.U64.HI R0, R10, 0x2, R5 ; /* 0x000000020a007819 */
/* 0x000fe40000010205 */
/*0100*/ IADD3 R4, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fca00007fe4ff */
/*0120*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R6, P1, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fe20007f3e0ff */
/*0150*/ BSSY B0, 0x970 ; /* 0x0000081000007945 */
/* 0x000fe20003800000 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0170*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610000077a10 */
/* 0x000fe40000ffe4ff */
/*0180*/ ISETP.GE.AND P0, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x004fda0003f06270 */
/*0190*/ @P0 BRA 0x960 ; /* 0x000007c000000947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000162000c1e1900 */
/*01b0*/ IADD3 R0, R12, 0x1, RZ ; /* 0x000000010c007810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ BSSY B2, 0x650 ; /* 0x0000048000027945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*01e0*/ IMNMX R5, R13, R0, !PT ; /* 0x000000000d057217 */
/* 0x000fe40007800200 */
/*01f0*/ LOP3.LUT R0, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff007212 */
/* 0x000fc600078e33ff */
/*0200*/ IMAD.IADD R13, R5.reuse, 0x1, -R12 ; /* 0x00000001050d7824 */
/* 0x040fe400078e0a0c */
/*0210*/ IMAD.IADD R5, R5, 0x1, R0 ; /* 0x0000000105057824 */
/* 0x000fc600078e0200 */
/*0220*/ LOP3.LUT R0, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d007812 */
/* 0x000fe400078ec0ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0240*/ ISETP.NE.AND P4, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f85270 */
/*0250*/ @!P0 BRA 0x640 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.WIDE R4, R12, R9, c[0x0][0x178] ; /* 0x00005e000c047625 */
/* 0x001fc800078e0209 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.IADD R13, R13, 0x1, -R0 ; /* 0x000000010d0d7824 */
/* 0x000fe400078e0a00 */
/*0290*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0404107981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.WIDE R22, R21, R9, c[0x0][0x188] ; /* 0x0000620015167625 */
/* 0x004fcc00078e0209 */
/*02f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.WIDE R6, R20, R9, c[0x0][0x188] ; /* 0x0000620014067625 */
/* 0x008fc800078e0209 */
/*0310*/ IMAD.WIDE R14, R17, R9.reuse, c[0x0][0x188] ; /* 0x00006200110e7625 */
/* 0x090fe400078e0209 */
/*0320*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000e8000c1e1900 */
/*0330*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1900 */
/*0340*/ IMAD.WIDE R18, R16, R9, c[0x0][0x188] ; /* 0x0000620010127625 */
/* 0x000fcc00078e0209 */
/*0350*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*0360*/ SHF.R.S32.HI R7, RZ, 0x1f, R20 ; /* 0x0000001fff077819 */
/* 0x001fe40000011414 */
/*0370*/ ISETP.NE.AND P0, PT, R22, -0x1, PT ; /* 0xffffffff1600780c */
/* 0x004fc80003f05270 */
/*0380*/ ISETP.NE.AND P0, PT, R22, c[0x0][0x164], P0 ; /* 0x0000590016007a0c */
/* 0x000fe40000705270 */
/*0390*/ ISETP.NE.AND P1, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fe40003f25270 */
/*03a0*/ ISETP.EQ.OR P0, PT, R10, R21, P0 ; /* 0x000000150a00720c */
/* 0x000fe40000702670 */
/*03b0*/ ISETP.NE.AND P1, PT, R6, c[0x0][0x164], P1 ; /* 0x0000590006007a0c */
/* 0x000fe40000f25270 */
/*03c0*/ ISETP.NE.AND P2, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x010fe40003f45270 */
/*03d0*/ ISETP.EQ.OR P1, PT, R10, R20, P1 ; /* 0x000000140a00720c */
/* 0x000fc40000f22670 */
/*03e0*/ ISETP.NE.AND P2, PT, R14, c[0x0][0x164], P2 ; /* 0x000059000e007a0c */
/* 0x000fe40001745270 */
/*03f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R21 ; /* 0x0000001fff067819 */
/* 0x000fe40000011415 */
/*0400*/ ISETP.EQ.OR P2, PT, R10, R17, P2 ; /* 0x000000110a00720c */
/* 0x000fe40001742670 */
/*0410*/ @!P0 LEA R14, P5, R21.reuse, c[0x0][0x180], 0x2 ; /* 0x00006000150e8a11 */
/* 0x040fe400078a10ff */
/*0420*/ ISETP.NE.AND P3, PT, R18, -0x1, PT ; /* 0xffffffff1200780c */
/* 0x000fe40003f65270 */
/*0430*/ @!P0 LEA.HI.X R15, R21, c[0x0][0x184], R6, 0x2, P5 ; /* 0x00006100150f8a11 */
/* 0x000fc400028f1406 */
/*0440*/ @!P1 LEA R6, P5, R20, c[0x0][0x180], 0x2 ; /* 0x0000600014069a11 */
/* 0x000fe400078a10ff */
/*0450*/ ISETP.NE.AND P3, PT, R18, c[0x0][0x164], P3 ; /* 0x0000590012007a0c */
/* 0x000fe40001f65270 */
/*0460*/ @!P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f8981 */
/* 0x000ea2000c1e1900 */
/*0470*/ @!P1 LEA.HI.X R7, R20, c[0x0][0x184], R7, 0x2, P5 ; /* 0x0000610014079a11 */
/* 0x000fe400028f1407 */
/*0480*/ SHF.R.S32.HI R20, RZ, 0x1f, R17 ; /* 0x0000001fff147819 */
/* 0x000fe40000011411 */
/*0490*/ @!P2 LEA R18, P5, R17, c[0x0][0x180], 0x2 ; /* 0x000060001112aa11 */
/* 0x000fe400078a10ff */
/*04a0*/ @!P1 LDG.E R7, [R6.64] ; /* 0x0000000406079981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ ISETP.EQ.OR P3, PT, R10, R16, P3 ; /* 0x000000100a00720c */
/* 0x000fc40001f62670 */
/*04c0*/ @!P2 LEA.HI.X R19, R17, c[0x0][0x184], R20, 0x2, P5 ; /* 0x000061001113aa11 */
/* 0x000fcc00028f1414 */
/*04d0*/ @!P2 LDG.E R19, [R18.64] ; /* 0x000000041213a981 */
/* 0x000f22000c1e1900 */
/*04e0*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fc80000011410 */
/*04f0*/ @!P3 LEA R20, P5, R16, c[0x0][0x180], 0x2 ; /* 0x000060001014ba11 */
/* 0x000fc800078a10ff */
/*0500*/ @!P3 LEA.HI.X R21, R16, c[0x0][0x184], R17, 0x2, P5 ; /* 0x000061001015ba11 */
/* 0x000fcc00028f1411 */
/*0510*/ @!P3 LDG.E R21, [R20.64] ; /* 0x000000041415b981 */
/* 0x000f22000c1e1900 */
/*0520*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0540*/ @!P0 ISETP.GT.AND P5, PT, R8, R15, PT ; /* 0x0000000f0800820c */
/* 0x024fc80003fa4270 */
/*0550*/ @!P0 SEL R14, R11, RZ, P5 ; /* 0x000000ff0b0e8207 */
/* 0x000fc80002800000 */
/*0560*/ @!P0 PRMT R11, R14, 0x7610, R11 ; /* 0x000076100e0b8816 */
/* 0x000fe4000000000b */
/*0570*/ @!P1 ISETP.GT.AND P0, PT, R8, R7, PT ; /* 0x000000070800920c */
/* 0x008fc80003f04270 */
/*0580*/ @!P1 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b069207 */
/* 0x000fe40000000000 */
/*0590*/ @!P2 ISETP.GT.AND P0, PT, R8, R19, PT ; /* 0x000000130800a20c */
/* 0x010fe40003f04270 */
/*05a0*/ @!P1 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060b9816 */
/* 0x000fc8000000000b */
/*05b0*/ @!P2 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b06a207 */
/* 0x000fc80000000000 */
/*05c0*/ @!P2 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060ba816 */
/* 0x000fe4000000000b */
/*05d0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*05e0*/ @!P3 ISETP.GT.AND P0, PT, R8, R21, PT ; /* 0x000000150800b20c */
/* 0x000fe40003f04270 */
/*05f0*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f3e0ff */
/*0600*/ @!P3 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b06b207 */
/* 0x000fc60000000000 */
/*0610*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0620*/ @!P3 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060bb816 */
/* 0x000fc6000000000b */
/*0630*/ @P2 BRA 0x290 ; /* 0xfffffc5000002947 */
/* 0x000fea000383ffff */
/*0640*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0650*/ @!P4 BRA 0x960 ; /* 0x000003000000c947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R12, R12, R9, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fca00078e0209 */
/*0670*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea4000c1e1900 */
/*0680*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x004fcc00078e0209 */
/*0690*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ BSSY B2, 0x770 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*06b0*/ ISETP.NE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f25270 */
/*06c0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*06d0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*06e0*/ ISETP.EQ.OR P0, PT, R10, R6, P0 ; /* 0x000000060a00720c */
/* 0x000fda0000702670 */
/*06f0*/ @P0 BRA 0x760 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0700*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0710*/ LEA R4, P0, R6, c[0x0][0x180], 0x2 ; /* 0x0000600006047a11 */
/* 0x000fc800078010ff */
/*0720*/ LEA.HI.X R5, R6, c[0x0][0x184], R5, 0x2, P0 ; /* 0x0000610006057a11 */
/* 0x000fcc00000f1405 */
/*0730*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0740*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0750*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0760*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0770*/ @!P1 BRA 0x960 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea4000c1e1900 */
/*0790*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x004fcc00078e0209 */
/*07a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ BSSY B2, 0x880 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*07c0*/ ISETP.NE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f25270 */
/*07d0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*07e0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*07f0*/ ISETP.EQ.OR P0, PT, R10, R6, P0 ; /* 0x000000060a00720c */
/* 0x000fda0000702670 */
/*0800*/ @P0 BRA 0x870 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0810*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0820*/ LEA R4, P0, R6, c[0x0][0x180], 0x2 ; /* 0x0000600006047a11 */
/* 0x000fc800078010ff */
/*0830*/ LEA.HI.X R5, R6, c[0x0][0x184], R5, 0x2, P0 ; /* 0x0000610006057a11 */
/* 0x000fcc00000f1405 */
/*0840*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0850*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0860*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0870*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0880*/ @!P1 BRA 0x960 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0890*/ LDG.E R12, [R12.64+0x8] ; /* 0x000008040c0c7981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD.WIDE R4, R12, R9, c[0x0][0x188] ; /* 0x000062000c047625 */
/* 0x004fcc00078e0209 */
/*08b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*08c0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*08d0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*08e0*/ ISETP.EQ.OR P0, PT, R10, R12, P0 ; /* 0x0000000c0a00720c */
/* 0x000fda0000702670 */
/*08f0*/ @P0 BRA 0x960 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0900*/ SHF.R.S32.HI R5, RZ, 0x1f, R12 ; /* 0x0000001fff057819 */
/* 0x000fe4000001140c */
/*0910*/ LEA R4, P0, R12, c[0x0][0x180], 0x2 ; /* 0x000060000c047a11 */
/* 0x000fc800078010ff */
/*0920*/ LEA.HI.X R5, R12, c[0x0][0x184], R5, 0x2, P0 ; /* 0x000061000c057a11 */
/* 0x000fcc00000f1405 */
/*0930*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0940*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0950*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT P0, RZ, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0bff7812 */
/* 0x000fda000780c0ff */
/*0980*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff050624 */
/* 0x000fca00078e00ff */
/*0990*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e4000c101904 */
/*09a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*09c0*/ IMAD R10, R3, c[0x0][0xc], R10 ; /* 0x00000300030a7a24 */
/* 0x000fca00078e020a */
/*09d0*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*09e0*/ @!P0 BRA 0x70 ; /* 0xfffff68000008947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel(int n, int c, int* NNZ, int* preSum, int* colIndex,int* randoms, int* colors){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x*gridDim.x;
if (index < n){
for (int i = index; i < n; i += stride){
bool f = true;
if ((colors[i] != -1 )){
continue;
}
int ir = randoms[i];
for (int k = preSum[i]; k < preSum[i + 1]; k++){
int j = colIndex[k];
int jc = colors[j];
if (((jc != -1) && (jc != c)) || (i == j)){
continue;
}
int jr = randoms[j];
if (ir <= jr){
f = false;
}
}
if (f){
colors[i] = c;
}
}
}
}
//jones plassmann luby algorithm for graphcoloring
void colorJPL(int n, int* NNZ, int* preSum, int* colIndex, int* colors){
int* randoms;
cudaMallocManaged(&randoms, sizeof(int)* n);
for (int i = 0; i < n; i++){
randoms[i] = rand();
}
thrust::fill(colors, colors+n, -1);
for(int c = 1; c< n+1; c++){
int nt = 256;
int nb = min((n + nt -1)/nt, MAXBLOCKS);
colorJPLKernel<<<nb,nt>>>(n,c,NNZ,preSum,colIndex, randoms,colors);
cudaDeviceSynchronize();
int left = (int)thrust::count(colors, colors+n, -1);
if (left ==0){
break;
}
}
printf("\n");
for(int i = 0; i < n; i++){
printf("%d ", colors[i]);
}
printf("\n");
cudaFree(randoms);
}
// Counts the number of unique colors in a solution
int CountColors(int V, int* color)
{
int num_colors = 0;
set<int> seen_colors;
for (int i = 0; i < V; i++) {
if (seen_colors.find(color[i]) == seen_colors.end()) {
seen_colors.insert(color[i]);
num_colors++;
}
}
return num_colors;
}
// Returns true if the color assignment is valid for the graph
bool IsValidColoring(bool* graph, int V, int* color)
{
for (int i = 0; i < V; i++) {
for (int j = 0; j < V; j++) {
if (graph[i * V + j]) {
if (i != j && color[i] == color[j]) {
printf("Vertex %d and Vertex %d are connected and have the same color %d\n", i, j, color[i]);
return false;
}
if (color[i] < 1) {
printf("Vertex %d has invalid color %d\n", i, color[i]);
return false;
}
}
}
}
return true;
}
// Read DIMACS graphs
// Assumes input nodes are numbered starting from 1
void ReadColFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
int num_rows, num_edges;
while (getline(infile, line)) {
istringstream iss(line);
string s;
int node1, node2;
iss >> s;
if (s == "p") {
iss >> s; // read string "edge"
iss >> num_rows;
iss >> num_edges;
*V = num_rows;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
continue;
} else if (s != "e")
continue;
iss >> node1 >> node2;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
// Read MatrixMarket graphs
// Assumes input nodes are numbered starting from 1
void ReadMMFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
// Reading comments
while (getline(infile, line)) {
istringstream iss(line);
if (line.find("%") == string::npos)
break;
}
// Reading metadata
istringstream iss(line);
int num_rows, num_cols, num_edges;
iss >> num_rows >> num_cols >> num_edges;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
*V = num_rows;
// Reading nodes
while (getline(infile, line)) {
istringstream iss(line);
int node1, node2, weight;
iss >> node1 >> node2 >> weight;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
//store sparse graph in compressed sparse row format
void CSRConvert(bool** graph, int rows, int** NNZ, int* preSum, int** colIndex, int* counter){
//assume square matrix
int cols = rows;
*counter = 0;
int rowElem[rows];
for (int i = 0; i < rows; i++){
rowElem[i] = 0;
}
//initialize preSum
preSum[0] = 0;
for (int i = 0; i < rows; i++){
for (int j = 0; j < cols; j++){
if ((*graph)[i*rows + j] == false){
continue;
}
else{
//reallocate size of NNZ and colIndex
*NNZ = (int*)realloc(*NNZ, sizeof(int)*(*counter + 1));
(*NNZ)[*counter] = 1;
*colIndex = (int*)realloc(*colIndex, sizeof(int) * (*counter +1));
(*colIndex)[*counter] = j;
//preSum[counter + 1] = preSum[counter] + prevRowCount;
rowElem[i]++;
*counter += 1;
}
}
}
for (int i = 0; i < rows +1; i++){
preSum[i+1] = preSum[i] + rowElem[i];
}
}
void GraphColoringGPU(const char filename[], int** color){
bool* graph;
int V;
if (string(filename).find(".col") != string::npos)
ReadColFile(filename, &graph, &V);
else{
ReadMMFile(filename, &graph, &V);
}
//convert the sparse array into compact sparse row format
int *NNZ = (int*)malloc(sizeof(int));
int *preSum = (int*)malloc(sizeof(int) * (V + 1));
int *colIndex= (int*)malloc(sizeof(int));
int counter = 0;
CSRConvert(&graph, V, &NNZ, preSum, &colIndex, &counter);
//migrate values to GPU
int* Ao;
int* Av;
int* Ac;
int* colors;
cudaMallocManaged(&Ao, sizeof(int)*(V+1));
cudaMallocManaged(&Av, sizeof(int)*counter);
cudaMallocManaged(&Ac, sizeof(int)*counter);
cudaMallocManaged(&colors, sizeof(int)* V);
for(int i = 0; i < counter; i++){
Av[i] = NNZ[i];
Ac[i] = colIndex[i];
}
//printf("offset values : ");
for (int i = 0; i < V + 1; i++){
Ao[i] = preSum[i];
}
colorJPL(V, Av, Ao, Ac,colors);
printf("JPL coloring found solution with %d colors\n", CountColors(V, colors));
printf("Valid coloring: %d\n", IsValidColoring(graph, V, colors));
free(NNZ);
free(preSum);
free(colIndex);
cudaFree(Ao);
cudaFree(Av);
cudaFree(Ac);
}
int main(int argc, char* argv[]){
const char fileName[] = "/home/zwharris/EEC289Q/Hw3/planar16.col";
int* color;
GraphColoringGPU(fileName, &color);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel(int n, int c, int* NNZ, int* preSum, int* colIndex,int* randoms, int* colors){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x*gridDim.x;
if (index < n){
for (int i = index; i < n; i += stride){
bool f = true;
if ((colors[i] != -1 )){
continue;
}
int ir = randoms[i];
for (int k = preSum[i]; k < preSum[i + 1]; k++){
int j = colIndex[k];
int jc = colors[j];
if (((jc != -1) && (jc != c)) || (i == j)){
continue;
}
int jr = randoms[j];
if (ir <= jr){
f = false;
}
}
if (f){
colors[i] = c;
}
}
}
}
//jones plassmann luby algorithm for graphcoloring
void colorJPL(int n, int* NNZ, int* preSum, int* colIndex, int* colors){
int* randoms;
hipMallocManaged(&randoms, sizeof(int)* n);
for (int i = 0; i < n; i++){
randoms[i] = rand();
}
thrust::fill(colors, colors+n, -1);
for(int c = 1; c< n+1; c++){
int nt = 256;
int nb = min((n + nt -1)/nt, MAXBLOCKS);
colorJPLKernel<<<nb,nt>>>(n,c,NNZ,preSum,colIndex, randoms,colors);
hipDeviceSynchronize();
int left = (int)thrust::count(colors, colors+n, -1);
if (left ==0){
break;
}
}
printf("\n");
for(int i = 0; i < n; i++){
printf("%d ", colors[i]);
}
printf("\n");
hipFree(randoms);
}
// Counts the number of unique colors in a solution
int CountColors(int V, int* color)
{
int num_colors = 0;
set<int> seen_colors;
for (int i = 0; i < V; i++) {
if (seen_colors.find(color[i]) == seen_colors.end()) {
seen_colors.insert(color[i]);
num_colors++;
}
}
return num_colors;
}
// Returns true if the color assignment is valid for the graph
bool IsValidColoring(bool* graph, int V, int* color)
{
for (int i = 0; i < V; i++) {
for (int j = 0; j < V; j++) {
if (graph[i * V + j]) {
if (i != j && color[i] == color[j]) {
printf("Vertex %d and Vertex %d are connected and have the same color %d\n", i, j, color[i]);
return false;
}
if (color[i] < 1) {
printf("Vertex %d has invalid color %d\n", i, color[i]);
return false;
}
}
}
}
return true;
}
// Read DIMACS graphs
// Assumes input nodes are numbered starting from 1
void ReadColFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
int num_rows, num_edges;
while (getline(infile, line)) {
istringstream iss(line);
string s;
int node1, node2;
iss >> s;
if (s == "p") {
iss >> s; // read string "edge"
iss >> num_rows;
iss >> num_edges;
*V = num_rows;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
continue;
} else if (s != "e")
continue;
iss >> node1 >> node2;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
// Read MatrixMarket graphs
// Assumes input nodes are numbered starting from 1
void ReadMMFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
// Reading comments
while (getline(infile, line)) {
istringstream iss(line);
if (line.find("%") == string::npos)
break;
}
// Reading metadata
istringstream iss(line);
int num_rows, num_cols, num_edges;
iss >> num_rows >> num_cols >> num_edges;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
*V = num_rows;
// Reading nodes
while (getline(infile, line)) {
istringstream iss(line);
int node1, node2, weight;
iss >> node1 >> node2 >> weight;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
//store sparse graph in compressed sparse row format
void CSRConvert(bool** graph, int rows, int** NNZ, int* preSum, int** colIndex, int* counter){
//assume square matrix
int cols = rows;
*counter = 0;
int rowElem[rows];
for (int i = 0; i < rows; i++){
rowElem[i] = 0;
}
//initialize preSum
preSum[0] = 0;
for (int i = 0; i < rows; i++){
for (int j = 0; j < cols; j++){
if ((*graph)[i*rows + j] == false){
continue;
}
else{
//reallocate size of NNZ and colIndex
*NNZ = (int*)realloc(*NNZ, sizeof(int)*(*counter + 1));
(*NNZ)[*counter] = 1;
*colIndex = (int*)realloc(*colIndex, sizeof(int) * (*counter +1));
(*colIndex)[*counter] = j;
//preSum[counter + 1] = preSum[counter] + prevRowCount;
rowElem[i]++;
*counter += 1;
}
}
}
for (int i = 0; i < rows +1; i++){
preSum[i+1] = preSum[i] + rowElem[i];
}
}
void GraphColoringGPU(const char filename[], int** color){
bool* graph;
int V;
if (string(filename).find(".col") != string::npos)
ReadColFile(filename, &graph, &V);
else{
ReadMMFile(filename, &graph, &V);
}
//convert the sparse array into compact sparse row format
int *NNZ = (int*)malloc(sizeof(int));
int *preSum = (int*)malloc(sizeof(int) * (V + 1));
int *colIndex= (int*)malloc(sizeof(int));
int counter = 0;
CSRConvert(&graph, V, &NNZ, preSum, &colIndex, &counter);
//migrate values to GPU
int* Ao;
int* Av;
int* Ac;
int* colors;
hipMallocManaged(&Ao, sizeof(int)*(V+1));
hipMallocManaged(&Av, sizeof(int)*counter);
hipMallocManaged(&Ac, sizeof(int)*counter);
hipMallocManaged(&colors, sizeof(int)* V);
for(int i = 0; i < counter; i++){
Av[i] = NNZ[i];
Ac[i] = colIndex[i];
}
//printf("offset values : ");
for (int i = 0; i < V + 1; i++){
Ao[i] = preSum[i];
}
colorJPL(V, Av, Ao, Ac,colors);
printf("JPL coloring found solution with %d colors\n", CountColors(V, colors));
printf("Valid coloring: %d\n", IsValidColoring(graph, V, colors));
free(NNZ);
free(preSum);
free(colIndex);
hipFree(Ao);
hipFree(Av);
hipFree(Ac);
}
int main(int argc, char* argv[]){
const char fileName[] = "/home/zwharris/EEC289Q/Hw3/planar16.col";
int* color;
GraphColoringGPU(fileName, &color);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel(int n, int c, int* NNZ, int* preSum, int* colIndex,int* randoms, int* colors){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x*gridDim.x;
if (index < n){
for (int i = index; i < n; i += stride){
bool f = true;
if ((colors[i] != -1 )){
continue;
}
int ir = randoms[i];
for (int k = preSum[i]; k < preSum[i + 1]; k++){
int j = colIndex[k];
int jc = colors[j];
if (((jc != -1) && (jc != c)) || (i == j)){
continue;
}
int jr = randoms[j];
if (ir <= jr){
f = false;
}
}
if (f){
colors[i] = c;
}
}
}
}
//jones plassmann luby algorithm for graphcoloring
void colorJPL(int n, int* NNZ, int* preSum, int* colIndex, int* colors){
int* randoms;
hipMallocManaged(&randoms, sizeof(int)* n);
for (int i = 0; i < n; i++){
randoms[i] = rand();
}
thrust::fill(colors, colors+n, -1);
for(int c = 1; c< n+1; c++){
int nt = 256;
int nb = min((n + nt -1)/nt, MAXBLOCKS);
colorJPLKernel<<<nb,nt>>>(n,c,NNZ,preSum,colIndex, randoms,colors);
hipDeviceSynchronize();
int left = (int)thrust::count(colors, colors+n, -1);
if (left ==0){
break;
}
}
printf("\n");
for(int i = 0; i < n; i++){
printf("%d ", colors[i]);
}
printf("\n");
hipFree(randoms);
}
// Counts the number of unique colors in a solution
int CountColors(int V, int* color)
{
int num_colors = 0;
set<int> seen_colors;
for (int i = 0; i < V; i++) {
if (seen_colors.find(color[i]) == seen_colors.end()) {
seen_colors.insert(color[i]);
num_colors++;
}
}
return num_colors;
}
// Returns true if the color assignment is valid for the graph
bool IsValidColoring(bool* graph, int V, int* color)
{
for (int i = 0; i < V; i++) {
for (int j = 0; j < V; j++) {
if (graph[i * V + j]) {
if (i != j && color[i] == color[j]) {
printf("Vertex %d and Vertex %d are connected and have the same color %d\n", i, j, color[i]);
return false;
}
if (color[i] < 1) {
printf("Vertex %d has invalid color %d\n", i, color[i]);
return false;
}
}
}
}
return true;
}
// Read DIMACS graphs
// Assumes input nodes are numbered starting from 1
void ReadColFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
int num_rows, num_edges;
while (getline(infile, line)) {
istringstream iss(line);
string s;
int node1, node2;
iss >> s;
if (s == "p") {
iss >> s; // read string "edge"
iss >> num_rows;
iss >> num_edges;
*V = num_rows;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
continue;
} else if (s != "e")
continue;
iss >> node1 >> node2;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
// Read MatrixMarket graphs
// Assumes input nodes are numbered starting from 1
void ReadMMFile(const char filename[], bool** graph, int* V)
{
string line;
ifstream infile(filename);
if (infile.fail()) {
printf("Failed to open %s\n", filename);
return;
}
// Reading comments
while (getline(infile, line)) {
istringstream iss(line);
if (line.find("%") == string::npos)
break;
}
// Reading metadata
istringstream iss(line);
int num_rows, num_cols, num_edges;
iss >> num_rows >> num_cols >> num_edges;
*graph = new bool[num_rows * num_rows];
memset(*graph, 0, num_rows * num_rows * sizeof(bool));
*V = num_rows;
// Reading nodes
while (getline(infile, line)) {
istringstream iss(line);
int node1, node2, weight;
iss >> node1 >> node2 >> weight;
// Assume node numbering starts at 1
(*graph)[(node1 - 1) * num_rows + (node2 - 1)] = true;
(*graph)[(node2 - 1) * num_rows + (node1 - 1)] = true;
}
infile.close();
}
//store sparse graph in compressed sparse row format
void CSRConvert(bool** graph, int rows, int** NNZ, int* preSum, int** colIndex, int* counter){
//assume square matrix
int cols = rows;
*counter = 0;
int rowElem[rows];
for (int i = 0; i < rows; i++){
rowElem[i] = 0;
}
//initialize preSum
preSum[0] = 0;
for (int i = 0; i < rows; i++){
for (int j = 0; j < cols; j++){
if ((*graph)[i*rows + j] == false){
continue;
}
else{
//reallocate size of NNZ and colIndex
*NNZ = (int*)realloc(*NNZ, sizeof(int)*(*counter + 1));
(*NNZ)[*counter] = 1;
*colIndex = (int*)realloc(*colIndex, sizeof(int) * (*counter +1));
(*colIndex)[*counter] = j;
//preSum[counter + 1] = preSum[counter] + prevRowCount;
rowElem[i]++;
*counter += 1;
}
}
}
for (int i = 0; i < rows +1; i++){
preSum[i+1] = preSum[i] + rowElem[i];
}
}
void GraphColoringGPU(const char filename[], int** color){
bool* graph;
int V;
if (string(filename).find(".col") != string::npos)
ReadColFile(filename, &graph, &V);
else{
ReadMMFile(filename, &graph, &V);
}
//convert the sparse array into compact sparse row format
int *NNZ = (int*)malloc(sizeof(int));
int *preSum = (int*)malloc(sizeof(int) * (V + 1));
int *colIndex= (int*)malloc(sizeof(int));
int counter = 0;
CSRConvert(&graph, V, &NNZ, preSum, &colIndex, &counter);
//migrate values to GPU
int* Ao;
int* Av;
int* Ac;
int* colors;
hipMallocManaged(&Ao, sizeof(int)*(V+1));
hipMallocManaged(&Av, sizeof(int)*counter);
hipMallocManaged(&Ac, sizeof(int)*counter);
hipMallocManaged(&colors, sizeof(int)* V);
for(int i = 0; i < counter; i++){
Av[i] = NNZ[i];
Ac[i] = colIndex[i];
}
//printf("offset values : ");
for (int i = 0; i < V + 1; i++){
Ao[i] = preSum[i];
}
colorJPL(V, Av, Ao, Ac,colors);
printf("JPL coloring found solution with %d colors\n", CountColors(V, colors));
printf("Valid coloring: %d\n", IsValidColoring(graph, V, colors));
free(NNZ);
free(preSum);
free(colIndex);
hipFree(Ao);
hipFree(Av);
hipFree(Ac);
}
int main(int argc, char* argv[]){
const char fileName[] = "/home/zwharris/EEC289Q/Hw3/planar16.col";
int* color;
GraphColoringGPU(fileName, &color);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14colorJPLKerneliiPiS_S_S_S_
.globl _Z14colorJPLKerneliiPiS_S_S_S_
.p2align 8
.type _Z14colorJPLKerneliiPiS_S_S_S_,@function
_Z14colorJPLKerneliiPiS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_12
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b256 s[4:11], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s13
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_12
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
s_mov_b32 s0, -1
s_mov_b32 s15, exec_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_10
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s18, -1
s_mov_b32 s16, 0
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v7, 31, v4
v_mov_b32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 1, v4
v_add_co_u32 v6, s0, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 s0, s17, exec_lo
s_and_b32 s1, s19, exec_lo
s_and_not1_b32 s18, s18, exec_lo
s_or_b32 s17, s0, s1
s_or_b32 s18, s18, s1
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_9
.LBB0_7:
global_load_b32 v10, v[6:7], off
s_and_not1_b32 s19, s19, exec_lo
s_and_b32 s20, s18, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 s19, s19, s20
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v11, 31, v10
v_cmp_ne_u32_e64 s1, v1, v10
v_lshlrev_b64 v[8:9], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v9, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v11
v_cmp_eq_u32_e64 s0, s2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_6
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v0, v8
s_and_b32 s1, vcc_lo, s18
s_and_not1_b32 s18, s19, exec_lo
s_and_b32 s1, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s19, s18, s1
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, s17, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, s2
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14colorJPLKerneliiPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14colorJPLKerneliiPiS_S_S_S_, .Lfunc_end0-_Z14colorJPLKerneliiPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14colorJPLKerneliiPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z14colorJPLKerneliiPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14colorJPLKerneliiPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0080*/ IMAD.WIDE R2, R10, R9, c[0x0][0x188] ; /* 0x000062000a027625 */
/* 0x000fca00078e0209 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B1, 0x9b0 ; /* 0x0000090000017945 */
/* 0x000fe20003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, -0x1, PT ; /* 0xffffffff0000780c */
/* 0x004fda0003f05270 */
/*00c0*/ @P0 BRA 0x9a0 ; /* 0x000008d000000947 */
/* 0x020fea0003800000 */
/*00d0*/ IMAD.SHL.U32 R6, R10, 0x4, RZ ; /* 0x000000040a067824 */
/* 0x000fe200078e00ff */
/*00e0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fc8000001140a */
/*00f0*/ SHF.L.U64.HI R0, R10, 0x2, R5 ; /* 0x000000020a007819 */
/* 0x000fe40000010205 */
/*0100*/ IADD3 R4, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000057a10 */
/* 0x000fca00007fe4ff */
/*0120*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R4.64+0x4] ; /* 0x00000404040d7981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R6, P1, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fe20007f3e0ff */
/*0150*/ BSSY B0, 0x970 ; /* 0x0000081000007945 */
/* 0x000fe20003800000 */
/*0160*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0170*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610000077a10 */
/* 0x000fe40000ffe4ff */
/*0180*/ ISETP.GE.AND P0, PT, R12, R13, PT ; /* 0x0000000d0c00720c */
/* 0x004fda0003f06270 */
/*0190*/ @P0 BRA 0x960 ; /* 0x000007c000000947 */
/* 0x000fea0003800000 */
/*01a0*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000162000c1e1900 */
/*01b0*/ IADD3 R0, R12, 0x1, RZ ; /* 0x000000010c007810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ BSSY B2, 0x650 ; /* 0x0000048000027945 */
/* 0x000fe20003800000 */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*01e0*/ IMNMX R5, R13, R0, !PT ; /* 0x000000000d057217 */
/* 0x000fe40007800200 */
/*01f0*/ LOP3.LUT R0, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff007212 */
/* 0x000fc600078e33ff */
/*0200*/ IMAD.IADD R13, R5.reuse, 0x1, -R12 ; /* 0x00000001050d7824 */
/* 0x040fe400078e0a0c */
/*0210*/ IMAD.IADD R5, R5, 0x1, R0 ; /* 0x0000000105057824 */
/* 0x000fc600078e0200 */
/*0220*/ LOP3.LUT R0, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d007812 */
/* 0x000fe400078ec0ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*0240*/ ISETP.NE.AND P4, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fd60003f85270 */
/*0250*/ @!P0 BRA 0x640 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.WIDE R4, R12, R9, c[0x0][0x178] ; /* 0x00005e000c047625 */
/* 0x001fc800078e0209 */
/*0270*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.IADD R13, R13, 0x1, -R0 ; /* 0x000000010d0d7824 */
/* 0x000fe400078e0a00 */
/*0290*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R20, [R4.64+0x4] ; /* 0x0000040404147981 */
/* 0x000ee8000c1e1900 */
/*02b0*/ LDG.E R17, [R4.64+0x8] ; /* 0x0000080404117981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R16, [R4.64+0xc] ; /* 0x00000c0404107981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*02e0*/ IMAD.WIDE R22, R21, R9, c[0x0][0x188] ; /* 0x0000620015167625 */
/* 0x004fcc00078e0209 */
/*02f0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000ea2000c1e1900 */
/*0300*/ IMAD.WIDE R6, R20, R9, c[0x0][0x188] ; /* 0x0000620014067625 */
/* 0x008fc800078e0209 */
/*0310*/ IMAD.WIDE R14, R17, R9.reuse, c[0x0][0x188] ; /* 0x00006200110e7625 */
/* 0x090fe400078e0209 */
/*0320*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0000e8000c1e1900 */
/*0330*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1900 */
/*0340*/ IMAD.WIDE R18, R16, R9, c[0x0][0x188] ; /* 0x0000620010127625 */
/* 0x000fcc00078e0209 */
/*0350*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*0360*/ SHF.R.S32.HI R7, RZ, 0x1f, R20 ; /* 0x0000001fff077819 */
/* 0x001fe40000011414 */
/*0370*/ ISETP.NE.AND P0, PT, R22, -0x1, PT ; /* 0xffffffff1600780c */
/* 0x004fc80003f05270 */
/*0380*/ ISETP.NE.AND P0, PT, R22, c[0x0][0x164], P0 ; /* 0x0000590016007a0c */
/* 0x000fe40000705270 */
/*0390*/ ISETP.NE.AND P1, PT, R6, -0x1, PT ; /* 0xffffffff0600780c */
/* 0x008fe40003f25270 */
/*03a0*/ ISETP.EQ.OR P0, PT, R10, R21, P0 ; /* 0x000000150a00720c */
/* 0x000fe40000702670 */
/*03b0*/ ISETP.NE.AND P1, PT, R6, c[0x0][0x164], P1 ; /* 0x0000590006007a0c */
/* 0x000fe40000f25270 */
/*03c0*/ ISETP.NE.AND P2, PT, R14, -0x1, PT ; /* 0xffffffff0e00780c */
/* 0x010fe40003f45270 */
/*03d0*/ ISETP.EQ.OR P1, PT, R10, R20, P1 ; /* 0x000000140a00720c */
/* 0x000fc40000f22670 */
/*03e0*/ ISETP.NE.AND P2, PT, R14, c[0x0][0x164], P2 ; /* 0x000059000e007a0c */
/* 0x000fe40001745270 */
/*03f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R21 ; /* 0x0000001fff067819 */
/* 0x000fe40000011415 */
/*0400*/ ISETP.EQ.OR P2, PT, R10, R17, P2 ; /* 0x000000110a00720c */
/* 0x000fe40001742670 */
/*0410*/ @!P0 LEA R14, P5, R21.reuse, c[0x0][0x180], 0x2 ; /* 0x00006000150e8a11 */
/* 0x040fe400078a10ff */
/*0420*/ ISETP.NE.AND P3, PT, R18, -0x1, PT ; /* 0xffffffff1200780c */
/* 0x000fe40003f65270 */
/*0430*/ @!P0 LEA.HI.X R15, R21, c[0x0][0x184], R6, 0x2, P5 ; /* 0x00006100150f8a11 */
/* 0x000fc400028f1406 */
/*0440*/ @!P1 LEA R6, P5, R20, c[0x0][0x180], 0x2 ; /* 0x0000600014069a11 */
/* 0x000fe400078a10ff */
/*0450*/ ISETP.NE.AND P3, PT, R18, c[0x0][0x164], P3 ; /* 0x0000590012007a0c */
/* 0x000fe40001f65270 */
/*0460*/ @!P0 LDG.E R15, [R14.64] ; /* 0x000000040e0f8981 */
/* 0x000ea2000c1e1900 */
/*0470*/ @!P1 LEA.HI.X R7, R20, c[0x0][0x184], R7, 0x2, P5 ; /* 0x0000610014079a11 */
/* 0x000fe400028f1407 */
/*0480*/ SHF.R.S32.HI R20, RZ, 0x1f, R17 ; /* 0x0000001fff147819 */
/* 0x000fe40000011411 */
/*0490*/ @!P2 LEA R18, P5, R17, c[0x0][0x180], 0x2 ; /* 0x000060001112aa11 */
/* 0x000fe400078a10ff */
/*04a0*/ @!P1 LDG.E R7, [R6.64] ; /* 0x0000000406079981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ ISETP.EQ.OR P3, PT, R10, R16, P3 ; /* 0x000000100a00720c */
/* 0x000fc40001f62670 */
/*04c0*/ @!P2 LEA.HI.X R19, R17, c[0x0][0x184], R20, 0x2, P5 ; /* 0x000061001113aa11 */
/* 0x000fcc00028f1414 */
/*04d0*/ @!P2 LDG.E R19, [R18.64] ; /* 0x000000041213a981 */
/* 0x000f22000c1e1900 */
/*04e0*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fc80000011410 */
/*04f0*/ @!P3 LEA R20, P5, R16, c[0x0][0x180], 0x2 ; /* 0x000060001014ba11 */
/* 0x000fc800078a10ff */
/*0500*/ @!P3 LEA.HI.X R21, R16, c[0x0][0x184], R17, 0x2, P5 ; /* 0x000061001015ba11 */
/* 0x000fcc00028f1411 */
/*0510*/ @!P3 LDG.E R21, [R20.64] ; /* 0x000000041415b981 */
/* 0x000f22000c1e1900 */
/*0520*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R12, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe40007ffe0ff */
/*0540*/ @!P0 ISETP.GT.AND P5, PT, R8, R15, PT ; /* 0x0000000f0800820c */
/* 0x024fc80003fa4270 */
/*0550*/ @!P0 SEL R14, R11, RZ, P5 ; /* 0x000000ff0b0e8207 */
/* 0x000fc80002800000 */
/*0560*/ @!P0 PRMT R11, R14, 0x7610, R11 ; /* 0x000076100e0b8816 */
/* 0x000fe4000000000b */
/*0570*/ @!P1 ISETP.GT.AND P0, PT, R8, R7, PT ; /* 0x000000070800920c */
/* 0x008fc80003f04270 */
/*0580*/ @!P1 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b069207 */
/* 0x000fe40000000000 */
/*0590*/ @!P2 ISETP.GT.AND P0, PT, R8, R19, PT ; /* 0x000000130800a20c */
/* 0x010fe40003f04270 */
/*05a0*/ @!P1 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060b9816 */
/* 0x000fc8000000000b */
/*05b0*/ @!P2 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b06a207 */
/* 0x000fc80000000000 */
/*05c0*/ @!P2 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060ba816 */
/* 0x000fe4000000000b */
/*05d0*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f45270 */
/*05e0*/ @!P3 ISETP.GT.AND P0, PT, R8, R21, PT ; /* 0x000000150800b20c */
/* 0x000fe40003f04270 */
/*05f0*/ IADD3 R4, P1, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe40007f3e0ff */
/*0600*/ @!P3 SEL R6, R11, RZ, P0 ; /* 0x000000ff0b06b207 */
/* 0x000fc60000000000 */
/*0610*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0620*/ @!P3 PRMT R11, R6, 0x7610, R11 ; /* 0x00007610060bb816 */
/* 0x000fc6000000000b */
/*0630*/ @P2 BRA 0x290 ; /* 0xfffffc5000002947 */
/* 0x000fea000383ffff */
/*0640*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x001fea0003800000 */
/*0650*/ @!P4 BRA 0x960 ; /* 0x000003000000c947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R12, R12, R9, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fca00078e0209 */
/*0670*/ LDG.E R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea4000c1e1900 */
/*0680*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x004fcc00078e0209 */
/*0690*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ BSSY B2, 0x770 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*06b0*/ ISETP.NE.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f25270 */
/*06c0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*06d0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*06e0*/ ISETP.EQ.OR P0, PT, R10, R6, P0 ; /* 0x000000060a00720c */
/* 0x000fda0000702670 */
/*06f0*/ @P0 BRA 0x760 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0700*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0710*/ LEA R4, P0, R6, c[0x0][0x180], 0x2 ; /* 0x0000600006047a11 */
/* 0x000fc800078010ff */
/*0720*/ LEA.HI.X R5, R6, c[0x0][0x184], R5, 0x2, P0 ; /* 0x0000610006057a11 */
/* 0x000fcc00000f1405 */
/*0730*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0740*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0750*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0760*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0770*/ @!P1 BRA 0x960 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea4000c1e1900 */
/*0790*/ IMAD.WIDE R4, R6, R9, c[0x0][0x188] ; /* 0x0000620006047625 */
/* 0x004fcc00078e0209 */
/*07a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*07b0*/ BSSY B2, 0x880 ; /* 0x000000c000027945 */
/* 0x000fe20003800000 */
/*07c0*/ ISETP.NE.AND P1, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f25270 */
/*07d0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*07e0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*07f0*/ ISETP.EQ.OR P0, PT, R10, R6, P0 ; /* 0x000000060a00720c */
/* 0x000fda0000702670 */
/*0800*/ @P0 BRA 0x870 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0810*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0820*/ LEA R4, P0, R6, c[0x0][0x180], 0x2 ; /* 0x0000600006047a11 */
/* 0x000fc800078010ff */
/*0830*/ LEA.HI.X R5, R6, c[0x0][0x184], R5, 0x2, P0 ; /* 0x0000610006057a11 */
/* 0x000fcc00000f1405 */
/*0840*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0850*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0860*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0870*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0880*/ @!P1 BRA 0x960 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0890*/ LDG.E R12, [R12.64+0x8] ; /* 0x000008040c0c7981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IMAD.WIDE R4, R12, R9, c[0x0][0x188] ; /* 0x000062000c047625 */
/* 0x004fcc00078e0209 */
/*08b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*08c0*/ ISETP.NE.AND P0, PT, R4, -0x1, PT ; /* 0xffffffff0400780c */
/* 0x004fc80003f05270 */
/*08d0*/ ISETP.NE.AND P0, PT, R4, c[0x0][0x164], P0 ; /* 0x0000590004007a0c */
/* 0x000fc80000705270 */
/*08e0*/ ISETP.EQ.OR P0, PT, R10, R12, P0 ; /* 0x0000000c0a00720c */
/* 0x000fda0000702670 */
/*08f0*/ @P0 BRA 0x960 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0900*/ SHF.R.S32.HI R5, RZ, 0x1f, R12 ; /* 0x0000001fff057819 */
/* 0x000fe4000001140c */
/*0910*/ LEA R4, P0, R12, c[0x0][0x180], 0x2 ; /* 0x000060000c047a11 */
/* 0x000fc800078010ff */
/*0920*/ LEA.HI.X R5, R12, c[0x0][0x184], R5, 0x2, P0 ; /* 0x000061000c057a11 */
/* 0x000fcc00000f1405 */
/*0930*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0940*/ ISETP.GT.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x024fc80003f04270 */
/*0950*/ SEL R11, R11, RZ, P0 ; /* 0x000000ff0b0b7207 */
/* 0x000fc80000000000 */
/*0960*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT P0, RZ, R11, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0bff7812 */
/* 0x000fda000780c0ff */
/*0980*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff050624 */
/* 0x000fca00078e00ff */
/*0990*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x0001e4000c101904 */
/*09a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*09c0*/ IMAD R10, R3, c[0x0][0xc], R10 ; /* 0x00000300030a7a24 */
/* 0x000fca00078e020a */
/*09d0*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*09e0*/ @!P0 BRA 0x70 ; /* 0xfffff68000008947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14colorJPLKerneliiPiS_S_S_S_
.globl _Z14colorJPLKerneliiPiS_S_S_S_
.p2align 8
.type _Z14colorJPLKerneliiPiS_S_S_S_,@function
_Z14colorJPLKerneliiPiS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s13, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_12
s_load_b32 s3, s[2:3], 0x0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4
s_load_b256 s[4:11], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s13
s_mov_b32 s13, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_12
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v7, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 -1, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v4, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
s_mov_b32 s0, -1
s_mov_b32 s15, exec_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v4, v5
s_cbranch_execz .LBB0_10
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_mov_b32 s18, -1
s_mov_b32 s16, 0
global_load_b32 v0, v[6:7], off
v_ashrrev_i32_e32 v7, 31, v4
v_mov_b32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v4, 1, v4
v_add_co_u32 v6, s0, v6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v7, s0, 0, v7, s0
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 s0, s17, exec_lo
s_and_b32 s1, s19, exec_lo
s_and_not1_b32 s18, s18, exec_lo
s_or_b32 s17, s0, s1
s_or_b32 s18, s18, s1
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB0_9
.LBB0_7:
global_load_b32 v10, v[6:7], off
s_and_not1_b32 s19, s19, exec_lo
s_and_b32 s20, s18, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 s19, s19, s20
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v11, 31, v10
v_cmp_ne_u32_e64 s1, v1, v10
v_lshlrev_b64 v[8:9], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v9, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v11
v_cmp_eq_u32_e64 s0, s2, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 s1, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_6
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v0, v8
s_and_b32 s1, vcc_lo, s18
s_and_not1_b32 s18, s19, exec_lo
s_and_b32 s1, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s19, s18, s1
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, s17, exec_lo
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v0, s2
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14colorJPLKerneliiPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14colorJPLKerneliiPiS_S_S_S_, .Lfunc_end0-_Z14colorJPLKerneliiPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14colorJPLKerneliiPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z14colorJPLKerneliiPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
inline __device__ float sigmoidGPU(const float& x) { return 1.0f / (1.0f + __expf(-x)); }
__global__ void gpuYoloLayerV3(float* input, const uint gridSize, const uint numOutputClasses,
const uint numBBoxes)
{
uint x_id = blockIdx.x * blockDim.x + threadIdx.x;
uint y_id = blockIdx.y * blockDim.y + threadIdx.y;
uint z_id = blockIdx.z * blockDim.z + threadIdx.z;
if ((x_id >= gridSize) || (y_id >= gridSize) || (z_id >= numBBoxes))
{
return;
}
const int numGridCells = gridSize * gridSize;
const int bbindex = y_id * gridSize + x_id;
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]);
for (uint i = 0; i < numOutputClasses; ++i)
{
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]);
}
}
cudaError_t cudaYoloLayerV3(void* input, const uint& batchSize, const uint& gridSize,
const uint& numOutputClasses, const uint& numBBoxes,
uint64_t outputSize, cudaStream_t stream)
{
dim3 threads_per_block(16, 16, 4);
dim3 number_of_blocks((gridSize / threads_per_block.x) + 1,
(gridSize / threads_per_block.y) + 1,
(numBBoxes / threads_per_block.z) + 1);
for (int batch = 0; batch < batchSize; ++batch)
{
gpuYoloLayerV3<<<number_of_blocks, threads_per_block, 0, stream>>>(
reinterpret_cast<float*>(input) + (batch * outputSize), gridSize, numOutputClasses,
numBBoxes);
}
return cudaGetLastError();
} | .file "tmpxft_0007ed2c_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
.type _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj, @function
_Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14gpuYoloLayerV3Pfjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj, .-_Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
.globl _Z14gpuYoloLayerV3Pfjjj
.type _Z14gpuYoloLayerV3Pfjjj, @function
_Z14gpuYoloLayerV3Pfjjj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14gpuYoloLayerV3Pfjjj, .-_Z14gpuYoloLayerV3Pfjjj
.globl _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st
.type _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st, @function
_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdx, %r14
movq %rcx, 8(%rsp)
movl (%r8), %edx
shrl $2, %edx
addl $1, %edx
movl (%r14), %eax
shrl $4, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %eax, 40(%rsp)
movl %edx, 44(%rsp)
cmpl $0, (%rsi)
je .L12
movq %rdi, %rbp
movq %rsi, %r13
movq %r8, %r15
leaq 0(,%r9,4), %r12
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
addq %r12, %rbp
cmpl 0(%r13), %ebx
jnb .L12
.L14:
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movq 112(%rsp), %r9
movl $0, %r8d
movq 24(%rsp), %rdx
movl $4, %ecx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl (%r15), %ecx
movq 8(%rsp), %rax
movl (%rax), %edx
movl (%r14), %esi
movq %rbp, %rdi
call _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
jmp .L13
.L12:
call cudaGetLastError@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st, .-_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14gpuYoloLayerV3Pfjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gpuYoloLayerV3Pfjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*
*/
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
inline __device__ float sigmoidGPU(const float& x) { return 1.0f / (1.0f + __expf(-x)); }
__global__ void gpuYoloLayerV3(float* input, const uint gridSize, const uint numOutputClasses,
const uint numBBoxes)
{
uint x_id = blockIdx.x * blockDim.x + threadIdx.x;
uint y_id = blockIdx.y * blockDim.y + threadIdx.y;
uint z_id = blockIdx.z * blockDim.z + threadIdx.z;
if ((x_id >= gridSize) || (y_id >= gridSize) || (z_id >= numBBoxes))
{
return;
}
const int numGridCells = gridSize * gridSize;
const int bbindex = y_id * gridSize + x_id;
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]);
for (uint i = 0; i < numOutputClasses; ++i)
{
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]);
}
}
cudaError_t cudaYoloLayerV3(void* input, const uint& batchSize, const uint& gridSize,
const uint& numOutputClasses, const uint& numBBoxes,
uint64_t outputSize, cudaStream_t stream)
{
dim3 threads_per_block(16, 16, 4);
dim3 number_of_blocks((gridSize / threads_per_block.x) + 1,
(gridSize / threads_per_block.y) + 1,
(numBBoxes / threads_per_block.z) + 1);
for (int batch = 0; batch < batchSize; ++batch)
{
gpuYoloLayerV3<<<number_of_blocks, threads_per_block, 0, stream>>>(
reinterpret_cast<float*>(input) + (batch * outputSize), gridSize, numOutputClasses,
numBBoxes);
}
return cudaGetLastError();
} | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
inline __device__ float sigmoidGPU(const float& x) { return 1.0f / (1.0f + __expf(-x)); }
__global__ void gpuYoloLayerV3(float* input, const uint gridSize, const uint numOutputClasses,
const uint numBBoxes)
{
uint x_id = blockIdx.x * blockDim.x + threadIdx.x;
uint y_id = blockIdx.y * blockDim.y + threadIdx.y;
uint z_id = blockIdx.z * blockDim.z + threadIdx.z;
if ((x_id >= gridSize) || (y_id >= gridSize) || (z_id >= numBBoxes))
{
return;
}
const int numGridCells = gridSize * gridSize;
const int bbindex = y_id * gridSize + x_id;
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]);
for (uint i = 0; i < numOutputClasses; ++i)
{
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]);
}
}
hipError_t cudaYoloLayerV3(void* input, const uint& batchSize, const uint& gridSize,
const uint& numOutputClasses, const uint& numBBoxes,
uint64_t outputSize, hipStream_t stream)
{
dim3 threads_per_block(16, 16, 4);
dim3 number_of_blocks((gridSize / threads_per_block.x) + 1,
(gridSize / threads_per_block.y) + 1,
(numBBoxes / threads_per_block.z) + 1);
for (int batch = 0; batch < batchSize; ++batch)
{
gpuYoloLayerV3<<<number_of_blocks, threads_per_block, 0, stream>>>(
reinterpret_cast<float*>(input) + (batch * outputSize), gridSize, numOutputClasses,
numBBoxes);
}
return hipGetLastError();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
inline __device__ float sigmoidGPU(const float& x) { return 1.0f / (1.0f + __expf(-x)); }
__global__ void gpuYoloLayerV3(float* input, const uint gridSize, const uint numOutputClasses,
const uint numBBoxes)
{
uint x_id = blockIdx.x * blockDim.x + threadIdx.x;
uint y_id = blockIdx.y * blockDim.y + threadIdx.y;
uint z_id = blockIdx.z * blockDim.z + threadIdx.z;
if ((x_id >= gridSize) || (y_id >= gridSize) || (z_id >= numBBoxes))
{
return;
}
const int numGridCells = gridSize * gridSize;
const int bbindex = y_id * gridSize + x_id;
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]);
for (uint i = 0; i < numOutputClasses; ++i)
{
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]);
}
}
hipError_t cudaYoloLayerV3(void* input, const uint& batchSize, const uint& gridSize,
const uint& numOutputClasses, const uint& numBBoxes,
uint64_t outputSize, hipStream_t stream)
{
dim3 threads_per_block(16, 16, 4);
dim3 number_of_blocks((gridSize / threads_per_block.x) + 1,
(gridSize / threads_per_block.y) + 1,
(numBBoxes / threads_per_block.z) + 1);
for (int batch = 0; batch < batchSize; ++batch)
{
gpuYoloLayerV3<<<number_of_blocks, threads_per_block, 0, stream>>>(
reinterpret_cast<float*>(input) + (batch * outputSize), gridSize, numOutputClasses,
numBBoxes);
}
return hipGetLastError();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14gpuYoloLayerV3Pfjjj
.globl _Z14gpuYoloLayerV3Pfjjj
.p2align 8
.type _Z14gpuYoloLayerV3Pfjjj,@function
_Z14gpuYoloLayerV3Pfjjj:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
v_bfe_u32 v6, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s13, s13, s6
s_mul_i32 s14, s14, s2
v_add_nc_u32_e32 v0, s13, v3
v_add_nc_u32_e32 v5, s14, v4
s_and_b32 s2, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[6:7]
v_max_u32_e32 v2, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_u32_e32 vcc_lo, s4, v2
v_cmp_gt_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0xc
v_mad_u64_u32 v[6:7], null, v5, s4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s2, 5
s_cmp_eq_u32 s2, 0
v_mul_lo_u32 v0, v1, s3
s_mul_i32 s3, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, v0, s3, v[6:7]
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v14, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0xbfb8aa3b, v5
v_add_nc_u32_e32 v1, s3, v1
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_add_f32_e32 v5, 1.0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v9, null, v5, v5, 1.0
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v12, vcc_lo, 1.0, v5, 1.0
v_mul_f32_e32 v11, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v9, v11, v12
v_fmac_f32_e32 v11, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v11, v12
v_div_fmas_f32 v11, v9, v10, v11
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v11, v5, 1.0
v_add_co_u32 v9, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
global_store_b32 v[7:8], v1, off
global_load_b32 v1, v[9:10], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, 0xbfb8aa3b, v1
v_exp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_add_f32_e32 v1, 1.0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v1, v1, 1.0
v_div_scale_f32 v12, vcc_lo, 1.0, v1, 1.0
v_rcp_f32_e32 v11, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v11, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v7, v11
v_mul_f32_e32 v13, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v5, v13, v12
v_fmac_f32_e32 v13, v7, v11
v_mad_u64_u32 v[7:8], null, v14, s3, v[6:7]
v_mov_b32_e32 v8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v5, v13, v12
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v5, v5, v11, v13
v_add_co_u32 v7, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_div_fixup_f32 v1, v5, v1, 1.0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
v_add_nc_u32_e32 v5, 3, v0
global_store_b32 v[9:10], v1, off
global_load_b32 v1, v[7:8], off
v_mad_u64_u32 v[9:10], null, v5, s3, v[6:7]
v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v5, 4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v9, vcc_lo, s0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, 0x3fb8aa3b, v1
v_exp_f32_e32 v1, v1
global_store_b32 v[7:8], v1, off
global_load_b32 v1, v[9:10], off
v_mad_u64_u32 v[7:8], null, v5, s3, v[6:7]
s_waitcnt vmcnt(0)
v_dual_mov_b32 v8, v2 :: v_dual_mul_f32 v5, 0x3fb8aa3b, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[7:8]
v_exp_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[9:10], v5, off
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v5, 0xbfb8aa3b, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_add_f32_e32 v5, 1.0, v5
v_div_scale_f32 v6, null, v5, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v7
v_fma_f32 v10, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v7
v_fma_f32 v6, -v6, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v7, v9
v_div_fixup_f32 v5, v6, v5, 1.0
global_store_b32 v[1:2], v5, off
s_cbranch_scc1 .LBB0_4
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, 5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s4, v0
v_add3_u32 v0, v4, v0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, s4, v0
v_add3_u32 v0, v3, v0, s13
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_nc_u32_e32 v0, s3, v0
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0xbfb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_add_f32_e32 v4, 1.0, v4
v_div_scale_f32 v5, null, v4, v4, 1.0
v_div_scale_f32 v8, vcc_lo, 1.0, v4, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
v_fmac_f32_e32 v6, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v8, v6
v_fma_f32 v9, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v9, v6
v_fma_f32 v5, -v5, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v7
v_div_fixup_f32 v4, v5, v4, 1.0
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14gpuYoloLayerV3Pfjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14gpuYoloLayerV3Pfjjj, .Lfunc_end0-_Z14gpuYoloLayerV3Pfjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14gpuYoloLayerV3Pfjjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14gpuYoloLayerV3Pfjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
inline __device__ float sigmoidGPU(const float& x) { return 1.0f / (1.0f + __expf(-x)); }
__global__ void gpuYoloLayerV3(float* input, const uint gridSize, const uint numOutputClasses,
const uint numBBoxes)
{
uint x_id = blockIdx.x * blockDim.x + threadIdx.x;
uint y_id = blockIdx.y * blockDim.y + threadIdx.y;
uint z_id = blockIdx.z * blockDim.z + threadIdx.z;
if ((x_id >= gridSize) || (y_id >= gridSize) || (z_id >= numBBoxes))
{
return;
}
const int numGridCells = gridSize * gridSize;
const int bbindex = y_id * gridSize + x_id;
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 0)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 1)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 2)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]
= __expf(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 3)]);
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + 4)]);
for (uint i = 0; i < numOutputClasses; ++i)
{
input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]
= sigmoidGPU(input[bbindex + numGridCells * (z_id * (5 + numOutputClasses) + (5 + i))]);
}
}
hipError_t cudaYoloLayerV3(void* input, const uint& batchSize, const uint& gridSize,
const uint& numOutputClasses, const uint& numBBoxes,
uint64_t outputSize, hipStream_t stream)
{
dim3 threads_per_block(16, 16, 4);
dim3 number_of_blocks((gridSize / threads_per_block.x) + 1,
(gridSize / threads_per_block.y) + 1,
(numBBoxes / threads_per_block.z) + 1);
for (int batch = 0; batch < batchSize; ++batch)
{
gpuYoloLayerV3<<<number_of_blocks, threads_per_block, 0, stream>>>(
reinterpret_cast<float*>(input) + (batch * outputSize), gridSize, numOutputClasses,
numBBoxes);
}
return hipGetLastError();
} | .text
.file "kernels.hip"
.globl _Z29__device_stub__gpuYoloLayerV3Pfjjj # -- Begin function _Z29__device_stub__gpuYoloLayerV3Pfjjj
.p2align 4, 0x90
.type _Z29__device_stub__gpuYoloLayerV3Pfjjj,@function
_Z29__device_stub__gpuYoloLayerV3Pfjjj: # @_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14gpuYoloLayerV3Pfjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__gpuYoloLayerV3Pfjjj, .Lfunc_end0-_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_endproc
# -- End function
.globl _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t # -- Begin function _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.p2align 4, 0x90
.type _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t,@function
_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t: # @_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 24(%rsp) # 8-byte Spill
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
cmpl $0, (%rsi)
je .LBB1_5
# %bb.1: # %.lr.ph
movq %r9, %rbx
movq %rsi, %r13
movq %rdi, %rbp
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
shrl $4, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movq 24(%rsp), %rax # 8-byte Reload
movl (%rax), %r14d
shrl $2, %r14d
incl %r14d
movabsq $4294967297, %r12 # imm = 0x100000001
addq %rcx, %r12
shlq $2, %rbx
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incq %r15
movl (%r13), %eax
addq %rbx, %rbp
cmpq %rax, %r15
jae .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl %r14d, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $4, %ecx
xorl %r8d, %r8d
movq 192(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
movq 32(%rsp), %rcx # 8-byte Reload
movl (%rcx), %ecx
movq 24(%rsp), %rdx # 8-byte Reload
movl (%rdx), %edx
movq %rbp, 88(%rsp)
movl %eax, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14gpuYoloLayerV3Pfjjj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.LBB1_5: # %._crit_edge
callq hipGetLastError
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t, .Lfunc_end1-_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpuYoloLayerV3Pfjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14gpuYoloLayerV3Pfjjj,@object # @_Z14gpuYoloLayerV3Pfjjj
.section .rodata,"a",@progbits
.globl _Z14gpuYoloLayerV3Pfjjj
.p2align 3, 0x0
_Z14gpuYoloLayerV3Pfjjj:
.quad _Z29__device_stub__gpuYoloLayerV3Pfjjj
.size _Z14gpuYoloLayerV3Pfjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14gpuYoloLayerV3Pfjjj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__gpuYoloLayerV3Pfjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14gpuYoloLayerV3Pfjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007ed2c_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
.type _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj, @function
_Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14gpuYoloLayerV3Pfjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj, .-_Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
.globl _Z14gpuYoloLayerV3Pfjjj
.type _Z14gpuYoloLayerV3Pfjjj, @function
_Z14gpuYoloLayerV3Pfjjj:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14gpuYoloLayerV3Pfjjj, .-_Z14gpuYoloLayerV3Pfjjj
.globl _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st
.type _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st, @function
_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdx, %r14
movq %rcx, 8(%rsp)
movl (%r8), %edx
shrl $2, %edx
addl $1, %edx
movl (%r14), %eax
shrl $4, %eax
addl $1, %eax
movl %eax, 36(%rsp)
movl %eax, 40(%rsp)
movl %edx, 44(%rsp)
cmpl $0, (%rsi)
je .L12
movq %rdi, %rbp
movq %rsi, %r13
movq %r8, %r15
leaq 0(,%r9,4), %r12
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
addq %r12, %rbp
cmpl 0(%r13), %ebx
jnb .L12
.L14:
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movq 112(%rsp), %r9
movl $0, %r8d
movq 24(%rsp), %rdx
movl $4, %ecx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl (%r15), %ecx
movq 8(%rsp), %rax
movl (%rax), %edx
movl (%r14), %esi
movq %rbp, %rdi
call _Z37__device_stub__Z14gpuYoloLayerV3PfjjjPfjjj
jmp .L13
.L12:
call cudaGetLastError@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st, .-_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP11CUstream_st
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14gpuYoloLayerV3Pfjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gpuYoloLayerV3Pfjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels.hip"
.globl _Z29__device_stub__gpuYoloLayerV3Pfjjj # -- Begin function _Z29__device_stub__gpuYoloLayerV3Pfjjj
.p2align 4, 0x90
.type _Z29__device_stub__gpuYoloLayerV3Pfjjj,@function
_Z29__device_stub__gpuYoloLayerV3Pfjjj: # @_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14gpuYoloLayerV3Pfjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__gpuYoloLayerV3Pfjjj, .Lfunc_end0-_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_endproc
# -- End function
.globl _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t # -- Begin function _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.p2align 4, 0x90
.type _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t,@function
_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t: # @_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, 24(%rsp) # 8-byte Spill
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
cmpl $0, (%rsi)
je .LBB1_5
# %bb.1: # %.lr.ph
movq %r9, %rbx
movq %rsi, %r13
movq %rdi, %rbp
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
shrl $4, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movq 24(%rsp), %rax # 8-byte Reload
movl (%rax), %r14d
shrl $2, %r14d
incl %r14d
movabsq $4294967297, %r12 # imm = 0x100000001
addq %rcx, %r12
shlq $2, %rbx
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
incq %r15
movl (%r13), %eax
addq %rbx, %rbp
cmpq %rax, %r15
jae .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl %r14d, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $4, %ecx
xorl %r8d, %r8d
movq 192(%rsp), %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
movq 32(%rsp), %rcx # 8-byte Reload
movl (%rcx), %ecx
movq 24(%rsp), %rdx # 8-byte Reload
movl (%rdx), %edx
movq %rbp, 88(%rsp)
movl %eax, 12(%rsp)
movl %ecx, 8(%rsp)
movl %edx, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z14gpuYoloLayerV3Pfjjj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.LBB1_5: # %._crit_edge
callq hipGetLastError
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t, .Lfunc_end1-_Z15cudaYoloLayerV3PvRKjS1_S1_S1_mP12ihipStream_t
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14gpuYoloLayerV3Pfjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14gpuYoloLayerV3Pfjjj,@object # @_Z14gpuYoloLayerV3Pfjjj
.section .rodata,"a",@progbits
.globl _Z14gpuYoloLayerV3Pfjjj
.p2align 3, 0x0
_Z14gpuYoloLayerV3Pfjjj:
.quad _Z29__device_stub__gpuYoloLayerV3Pfjjj
.size _Z14gpuYoloLayerV3Pfjjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14gpuYoloLayerV3Pfjjj"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__gpuYoloLayerV3Pfjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14gpuYoloLayerV3Pfjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
cudaMalloc((void**)&x_gpu, sizeof(float) * 50);
cudaMalloc((void**)&mask, sizeof(int) * 8);
cudaMemcpy(x_gpu,x,sizeof(float) * 20, cudaMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
cudaMemcpy(x, x_gpu, sizeof(float) * 28, cudaMemcpyDeviceToHost);
cudaMemcpy(mask_cpu, mask, sizeof(int) * 8, cudaMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
cudaMalloc((void**)&x_gpu, sizeof(float) * 50);
cudaMalloc((void**)&mask, sizeof(int) * 8);
cudaMemcpy(x_gpu,x,sizeof(float) * 20, cudaMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
cudaMemcpy(x, x_gpu, sizeof(float) * 28, cudaMemcpyDeviceToHost);
cudaMemcpy(mask_cpu, mask, sizeof(int) * 8, cudaMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} | .file "tmpxft_0007272d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movl $0, %edx
.L4:
movslq %edx, %rax
imulq $954437177, %rax, %rax
sarq $33, %rax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
leal (%rax,%rax,8), %esi
movl %edx, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx)
addl $50, %edx
addq $4, %rcx
cmpl $2500, %edx
jne .L4
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
leaq 80(%rdi), %rsi
pushq 16(%rsp)
.cfi_def_cfa_offset 88
pushq $2
.cfi_def_cfa_offset 96
pushq $2
.cfi_def_cfa_offset 104
pushq $2
.cfi_def_cfa_offset 112
movl $2, %r9d
movl $4, %r8d
movl $10, %ecx
movl $2, %edx
call max_stride@PLT
addq $32, %rsp
.cfi_def_cfa_offset 80
movl $2, %ecx
movl $112, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 80(%rbx), %r14
movq %rbx, %r12
leaq .LC0(%rip), %r13
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r14, %r12
jne .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %r12
addq $112, %rbx
leaq .LC0(%rip), %r13
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %rbx, %r12
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $16, %rbp
leaq .LC2(%rip), %r12
.L7:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
cudaMalloc((void**)&x_gpu, sizeof(float) * 50);
cudaMalloc((void**)&mask, sizeof(int) * 8);
cudaMemcpy(x_gpu,x,sizeof(float) * 20, cudaMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
cudaMemcpy(x, x_gpu, sizeof(float) * 28, cudaMemcpyDeviceToHost);
cudaMemcpy(mask_cpu, mask, sizeof(int) * 8, cudaMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
hipMalloc((void**)&x_gpu, sizeof(float) * 50);
hipMalloc((void**)&mask, sizeof(int) * 8);
hipMemcpy(x_gpu,x,sizeof(float) * 20, hipMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
hipMemcpy(x, x_gpu, sizeof(float) * 28, hipMemcpyDeviceToHost);
hipMemcpy(mask_cpu, mask, sizeof(int) * 8, hipMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
hipMalloc((void**)&x_gpu, sizeof(float) * 50);
hipMalloc((void**)&mask, sizeof(int) * 8);
hipMemcpy(x_gpu,x,sizeof(float) * 20, hipMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
hipMemcpy(x, x_gpu, sizeof(float) * 28, hipMemcpyDeviceToHost);
hipMemcpy(mask_cpu, mask, sizeof(int) * 8, hipMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)malloc(sizeof(float) * 50);
mask_cpu = (int *)malloc(sizeof(int) * 8);
for (i=0;i<50;i++)
x[i] = (i*50) % 9;
hipMalloc((void**)&x_gpu, sizeof(float) * 50);
hipMalloc((void**)&mask, sizeof(int) * 8);
hipMemcpy(x_gpu,x,sizeof(float) * 20, hipMemcpyHostToDevice);
max_stride(x_gpu,x_gpu+20,2,10,4,2,2,2,2,mask);
hipMemcpy(x, x_gpu, sizeof(float) * 28, hipMemcpyDeviceToHost);
hipMemcpy(mask_cpu, mask, sizeof(int) * 8, hipMemcpyDeviceToHost);
for (i=0; i<20;i++)
printf("%f ",x[i]);
printf("\n");
for (i=20; i<28;i++)
printf("%f ",x[i]);
printf("\n");
for (i = 0; i < 4; i++)
printf("%d ",mask_cpu[i]);
return 0;
} | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %r14
movl $32, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq $954437177, %rdx, %rdx # imm = 0x38E38E39
shrq $33, %rdx
leal (%rdx,%rdx,8), %edx
movl %eax, %esi
subl %edx, %esi
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
addl $50, %eax
cmpq $50, %rcx
jne .LBB0_1
# %bb.2:
movq %rsp, %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 80(%rdi), %rsi
movl $2, %edx
movl $10, %ecx
movl $4, %r8d
movl $2, %r9d
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
callq max_stride
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq (%rsp), %rsi
movl $112, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $20, %r15
jne .LBB0_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss 80(%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $8, %r15
jne .LBB0_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB0_7
# %bb.8:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007272d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.LC2:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movl $0, %edx
.L4:
movslq %edx, %rax
imulq $954437177, %rax, %rax
sarq $33, %rax
movl %edx, %esi
sarl $31, %esi
subl %esi, %eax
leal (%rax,%rax,8), %esi
movl %edx, %eax
subl %esi, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx)
addl $50, %edx
addq $4, %rcx
cmpl $2500, %edx
jne .L4
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
leaq 80(%rdi), %rsi
pushq 16(%rsp)
.cfi_def_cfa_offset 88
pushq $2
.cfi_def_cfa_offset 96
pushq $2
.cfi_def_cfa_offset 104
pushq $2
.cfi_def_cfa_offset 112
movl $2, %r9d
movl $4, %r8d
movl $10, %ecx
movl $2, %edx
call max_stride@PLT
addq $32, %rsp
.cfi_def_cfa_offset 80
movl $2, %ecx
movl $112, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 80(%rbx), %r14
movq %rbx, %r12
leaq .LC0(%rip), %r13
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %r14, %r12
jne .L5
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rbx), %r12
addq $112, %rbx
leaq .LC0(%rip), %r13
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq %rbx, %r12
jne .L6
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $16, %rbp
leaq .LC2(%rip), %r12
.L7:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L7
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %r14
movl $32, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, %edx
imulq $954437177, %rdx, %rdx # imm = 0x38E38E39
shrq $33, %rdx
leal (%rdx,%rdx,8), %edx
movl %eax, %esi
subl %edx, %esi
xorps %xmm0, %xmm0
cvtsi2ss %esi, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
addl $50, %eax
cmpq $50, %rcx
jne .LBB0_1
# %bb.2:
movq %rsp, %rdi
movl $200, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
leaq 80(%rdi), %rsi
movl $2, %edx
movl $10, %ecx
movl $4, %r8d
movl $2, %r9d
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
pushq $2
.cfi_adjust_cfa_offset 8
callq max_stride
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq (%rsp), %rsi
movl $112, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $20, %r15
jne .LBB0_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movss 80(%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $8, %r15
jne .LBB0_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB0_7
# %bb.8:
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} | code for sm_80
Function : _Z8matrix_tPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R18, SR_CTAID.Y ; /* 0x0000000000127919 */
/* 0x000e280000002600 */
/*0070*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R8, R18, R4, 0x5 ; /* 0x0000000412087211 */
/* 0x001fe200078e28ff */
/*00b0*/ IMAD R7, R0, 0x20, R5 ; /* 0x0000002000077824 */
/* 0x002fc800078e0205 */
/*00c0*/ IMAD R7, R8, R9, R7 ; /* 0x0000000908077224 */
/* 0x004fe200078e0207 */
/*00d0*/ SHF.L.U32 R9, R9, 0x3, RZ ; /* 0x0000000309097819 */
/* 0x000fc600000006ff */
/*00e0*/ IMAD.WIDE R10, R7, R6, c[0x0][0x160] ; /* 0x00005800070a7625 */
/* 0x000fcc00078e0206 */
/*00f0*/ IMAD.WIDE R12, R9.reuse, 0x4, R10 ; /* 0x00000004090c7825 */
/* 0x040fe400078e020a */
/*0100*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*0110*/ IMAD.WIDE R14, R9.reuse, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x040fe400078e020c */
/*0120*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ IMAD.WIDE R16, R9, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x000fc400078e020e */
/*0140*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1900 */
/*0160*/ IMAD R19, R5, 0x20, R4 ; /* 0x0000002005137824 */
/* 0x000fe200078e0204 */
/*0170*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fc600078e00ff */
/*0190*/ STS [R19.X4], R11 ; /* 0x0000000b13007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R19.X4+0x20], R12 ; /* 0x0000200c13007388 */
/* 0x0081e80000004800 */
/*01b0*/ STS [R19.X4+0x40], R14 ; /* 0x0000400e13007388 */
/* 0x0101e80000004800 */
/*01c0*/ STS [R19.X4+0x60], R16 ; /* 0x0000601013007388 */
/* 0x0201e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ LEA R7, R18, R5, 0x5 ; /* 0x0000000512077211 */
/* 0x000fe200078e28ff */
/*0200*/ BSSY B0, 0x2e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0210*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x004fda0003f06270 */
/*0220*/ @P0 BRA 0x2d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ea2000c1e1900 */
/*0240*/ IMAD R11, R0, 0x20, R4 ; /* 0x00000020000b7824 */
/* 0x000fca00078e0204 */
/*0250*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0260*/ @P0 BRA 0x2d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0270*/ LEA R15, R4, R5, 0x5 ; /* 0x00000005040f7211 */
/* 0x000fe200078e28ff */
/*0280*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0290*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe200078e0206 */
/*02a0*/ LDS R15, [R15.X4] ; /* 0x000000000f0f7984 */
/* 0x000e280000004800 */
/*02b0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*02c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02e0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fe20003f06270 */
/*02f0*/ BSSY B0, 0x4c0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0300*/ @P0 BRA 0x4b0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R11, R0, 0x20, R4 ; /* 0x00000020000b7824 */
/* 0x000fe200078e0204 */
/*0330*/ BSSY B1, 0x3e0 ; /* 0x000000a000017945 */
/* 0x000fe80003800000 */
/*0340*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0360*/ @P0 BRA 0x3d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0370*/ LEA R15, R4, R5, 0x5 ; /* 0x00000005040f7211 */
/* 0x000fe200078e28ff */
/*0380*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0390*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe200078e0206 */
/*03a0*/ LDS R15, [R15.X4+0x400] ; /* 0x000400000f0f7984 */
/* 0x000e280000004800 */
/*03b0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*03c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fda0003f06270 */
/*03f0*/ @P0 BRA 0x4b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ea2000c1e1900 */
/*0410*/ LEA R11, R0, R4, 0x5 ; /* 0x00000004000b7211 */
/* 0x000fc800078e28ff */
/*0420*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0440*/ @P0 BRA 0x4b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R15, R4, 0x20, R5 ; /* 0x00000020040f7824 */
/* 0x000fe400078e0205 */
/*0460*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0470*/ LDS R15, [R15.X4+0x800] ; /* 0x000800000f0f7984 */
/* 0x000e220000004800 */
/*0480*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fca00078e0206 */
/*0490*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*04a0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fda0003f06270 */
/*04d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ LEA R0, R0, R4, 0x5 ; /* 0x0000000400007211 */
/* 0x000fc800078e28ff */
/*0500*/ IADD3 R0, R0, 0x18, RZ ; /* 0x0000001800007810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06270 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ LEA R3, R4, R5, 0x5 ; /* 0x0000000504037211 */
/* 0x000fe200078e28ff */
/*0540*/ IMAD R7, R0, R10, R7 ; /* 0x0000000a00077224 */
/* 0x000fc800078e0207 */
/*0550*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0206 */
/*0560*/ LDS R3, [R3.X4+0xc00] ; /* 0x000c000003037984 */
/* 0x000e680000004800 */
/*0570*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x002fe2000c101904 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} | .file "tmpxft_0005acf0_00000000-6_matrix_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
.type _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_, @function
_Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8matrix_tPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_, .-_Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.type _Z8matrix_tPiS_S_S_, @function
_Z8matrix_tPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8matrix_tPiS_S_S_, .-_Z8matrix_tPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matrix_tPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matrix_tPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matrix_tPiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.p2align 8
.type _Z8matrix_tPiS_S_S_,@function
_Z8matrix_tPiS_S_S_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s7, s14, 5
s_mov_b32 s9, -8
v_add_nc_u32_e32 v1, s6, v2
v_lshlrev_b32_e32 v0, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v3, 7, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s8, v1
s_lshl_b32 s8, s8, 3
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s7
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s9, s9, 8
s_cmp_gt_u32 s9, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s8, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 32, v4
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 2, v3
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, s6, v3
v_add_nc_u32_e32 v1, s7, v2
s_mov_b32 s6, -8
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v2, v2, 7, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, 0x400, v2
s_add_i32 s6, s6, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s6, 23
s_cbranch_scc1 .LBB0_7
.LBB0_4:
global_load_b32 v4, v3, s[2:3]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v4
s_cbranch_execz .LBB0_3
global_load_b32 v6, v3, s[4:5]
v_add3_u32 v5, v1, s6, 8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[6:7], null, v4, v5, v[0:1]
ds_load_b32 v8, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[4:5], v8, off
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8matrix_tPiS_S_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8matrix_tPiS_S_S_, .Lfunc_end0-_Z8matrix_tPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8matrix_tPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8matrix_tPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
chunk[threadIdx.x][threadIdx.y+i] = data[(y + i) * *cols + x];
}
__syncthreads();
x = blockIdx.y * CHUNK_SIZE + threadIdx.x;
y = blockIdx.x * CHUNK_SIZE + threadIdx.y;
for (int i=0; i<CHUNK_SIZE; i+= CHUNK_ROWS) {
if (x < *rows && y+i < *cols) {
out[(y + i) * *rows + x] = chunk[threadIdx.y + i][threadIdx.x];
// out[(y + i) * *rows + x] = 1;
}
}
} | .text
.file "matrix_t.hip"
.globl _Z23__device_stub__matrix_tPiS_S_S_ # -- Begin function _Z23__device_stub__matrix_tPiS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__matrix_tPiS_S_S_,@function
_Z23__device_stub__matrix_tPiS_S_S_: # @_Z23__device_stub__matrix_tPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8matrix_tPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__matrix_tPiS_S_S_, .Lfunc_end0-_Z23__device_stub__matrix_tPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matrix_tPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matrix_tPiS_S_S_,@object # @_Z8matrix_tPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z8matrix_tPiS_S_S_
.p2align 3, 0x0
_Z8matrix_tPiS_S_S_:
.quad _Z23__device_stub__matrix_tPiS_S_S_
.size _Z8matrix_tPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matrix_tPiS_S_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matrix_tPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matrix_tPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8matrix_tPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R18, SR_CTAID.Y ; /* 0x0000000000127919 */
/* 0x000e280000002600 */
/*0070*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e280000002200 */
/*0080*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0090*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*00a0*/ LEA R8, R18, R4, 0x5 ; /* 0x0000000412087211 */
/* 0x001fe200078e28ff */
/*00b0*/ IMAD R7, R0, 0x20, R5 ; /* 0x0000002000077824 */
/* 0x002fc800078e0205 */
/*00c0*/ IMAD R7, R8, R9, R7 ; /* 0x0000000908077224 */
/* 0x004fe200078e0207 */
/*00d0*/ SHF.L.U32 R9, R9, 0x3, RZ ; /* 0x0000000309097819 */
/* 0x000fc600000006ff */
/*00e0*/ IMAD.WIDE R10, R7, R6, c[0x0][0x160] ; /* 0x00005800070a7625 */
/* 0x000fcc00078e0206 */
/*00f0*/ IMAD.WIDE R12, R9.reuse, 0x4, R10 ; /* 0x00000004090c7825 */
/* 0x040fe400078e020a */
/*0100*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea8000c1e1900 */
/*0110*/ IMAD.WIDE R14, R9.reuse, 0x4, R12 ; /* 0x00000004090e7825 */
/* 0x040fe400078e020c */
/*0120*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ IMAD.WIDE R16, R9, 0x4, R14 ; /* 0x0000000409107825 */
/* 0x000fc400078e020e */
/*0140*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f62000c1e1900 */
/*0160*/ IMAD R19, R5, 0x20, R4 ; /* 0x0000002005137824 */
/* 0x000fe200078e0204 */
/*0170*/ MOV R8, c[0x0][0x170] ; /* 0x00005c0000087a02 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff097624 */
/* 0x000fc600078e00ff */
/*0190*/ STS [R19.X4], R11 ; /* 0x0000000b13007388 */
/* 0x0041e80000004800 */
/*01a0*/ STS [R19.X4+0x20], R12 ; /* 0x0000200c13007388 */
/* 0x0081e80000004800 */
/*01b0*/ STS [R19.X4+0x40], R14 ; /* 0x0000400e13007388 */
/* 0x0101e80000004800 */
/*01c0*/ STS [R19.X4+0x60], R16 ; /* 0x0000601013007388 */
/* 0x0201e80000004800 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01e0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ LEA R7, R18, R5, 0x5 ; /* 0x0000000512077211 */
/* 0x000fe200078e28ff */
/*0200*/ BSSY B0, 0x2e0 ; /* 0x000000d000007945 */
/* 0x000fe60003800000 */
/*0210*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x004fda0003f06270 */
/*0220*/ @P0 BRA 0x2d0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ea2000c1e1900 */
/*0240*/ IMAD R11, R0, 0x20, R4 ; /* 0x00000020000b7824 */
/* 0x000fca00078e0204 */
/*0250*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0260*/ @P0 BRA 0x2d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0270*/ LEA R15, R4, R5, 0x5 ; /* 0x00000005040f7211 */
/* 0x000fe200078e28ff */
/*0280*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0290*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe200078e0206 */
/*02a0*/ LDS R15, [R15.X4] ; /* 0x000000000f0f7984 */
/* 0x000e280000004800 */
/*02b0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*02c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02e0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fe20003f06270 */
/*02f0*/ BSSY B0, 0x4c0 ; /* 0x000001c000007945 */
/* 0x000fd80003800000 */
/*0300*/ @P0 BRA 0x4b0 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R11, R0, 0x20, R4 ; /* 0x00000020000b7824 */
/* 0x000fe200078e0204 */
/*0330*/ BSSY B1, 0x3e0 ; /* 0x000000a000017945 */
/* 0x000fe80003800000 */
/*0340*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0360*/ @P0 BRA 0x3d0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0370*/ LEA R15, R4, R5, 0x5 ; /* 0x00000005040f7211 */
/* 0x000fe200078e28ff */
/*0380*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0390*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fe200078e0206 */
/*03a0*/ LDS R15, [R15.X4+0x400] ; /* 0x000400000f0f7984 */
/* 0x000e280000004800 */
/*03b0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*03c0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fda0003f06270 */
/*03f0*/ @P0 BRA 0x4b0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0400*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x001ea2000c1e1900 */
/*0410*/ LEA R11, R0, R4, 0x5 ; /* 0x00000004000b7211 */
/* 0x000fc800078e28ff */
/*0420*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GE.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x004fda0003f06270 */
/*0440*/ @P0 BRA 0x4b0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R15, R4, 0x20, R5 ; /* 0x00000020040f7824 */
/* 0x000fe400078e0205 */
/*0460*/ IMAD R13, R10, R11, R7 ; /* 0x0000000b0a0d7224 */
/* 0x000fc800078e0207 */
/*0470*/ LDS R15, [R15.X4+0x800] ; /* 0x000800000f0f7984 */
/* 0x000e220000004800 */
/*0480*/ IMAD.WIDE R12, R13, R6, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fca00078e0206 */
/*0490*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0011e8000c101904 */
/*04a0*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x000164000c1e1900 */
/*04b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.GE.AND P0, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x020fda0003f06270 */
/*04d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ LEA R0, R0, R4, 0x5 ; /* 0x0000000400007211 */
/* 0x000fc800078e28ff */
/*0500*/ IADD3 R0, R0, 0x18, RZ ; /* 0x0000001800007810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06270 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ LEA R3, R4, R5, 0x5 ; /* 0x0000000504037211 */
/* 0x000fe200078e28ff */
/*0540*/ IMAD R7, R0, R10, R7 ; /* 0x0000000a00077224 */
/* 0x000fc800078e0207 */
/*0550*/ IMAD.WIDE R6, R7, R6, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fe200078e0206 */
/*0560*/ LDS R3, [R3.X4+0xc00] ; /* 0x000c000003037984 */
/* 0x000e680000004800 */
/*0570*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x002fe2000c101904 */
/*0580*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0590*/ BRA 0x590; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matrix_tPiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.p2align 8
.type _Z8matrix_tPiS_S_S_,@function
_Z8matrix_tPiS_S_S_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s7, s14, 5
s_mov_b32 s9, -8
v_add_nc_u32_e32 v1, s6, v2
v_lshlrev_b32_e32 v0, 2, v2
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v4, v3, 7, v0
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, s8, v1
s_lshl_b32 s8, s8, 3
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v0, v3, v1, s7
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s9, s9, 8
s_cmp_gt_u32 s9, 23
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_add_nc_u32_e32 v0, s8, v0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
v_add_nc_u32_e32 v4, 32, v4
s_cbranch_scc0 .LBB0_1
s_load_b128 s[0:3], s[0:1], 0x8
v_lshlrev_b32_e32 v4, 2, v3
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v0, s6, v3
v_add_nc_u32_e32 v1, s7, v2
s_mov_b32 s6, -8
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v2, v2, 7, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, 0x400, v2
s_add_i32 s6, s6, 8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s6, 23
s_cbranch_scc1 .LBB0_7
.LBB0_4:
global_load_b32 v4, v3, s[2:3]
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v4
s_cbranch_execz .LBB0_3
global_load_b32 v6, v3, s[4:5]
v_add3_u32 v5, v1, s6, 8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v5, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[6:7], null, v4, v5, v[0:1]
ds_load_b32 v8, v2
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[6:7]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[4:5], v8, off
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8matrix_tPiS_S_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8matrix_tPiS_S_S_, .Lfunc_end0-_Z8matrix_tPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8matrix_tPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8matrix_tPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005acf0_00000000-6_matrix_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
.type _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_, @function
_Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8matrix_tPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_, .-_Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.type _Z8matrix_tPiS_S_S_, @function
_Z8matrix_tPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z8matrix_tPiS_S_S_PiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8matrix_tPiS_S_S_, .-_Z8matrix_tPiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8matrix_tPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matrix_tPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_t.hip"
.globl _Z23__device_stub__matrix_tPiS_S_S_ # -- Begin function _Z23__device_stub__matrix_tPiS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__matrix_tPiS_S_S_,@function
_Z23__device_stub__matrix_tPiS_S_S_: # @_Z23__device_stub__matrix_tPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8matrix_tPiS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__matrix_tPiS_S_S_, .Lfunc_end0-_Z23__device_stub__matrix_tPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matrix_tPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8matrix_tPiS_S_S_,@object # @_Z8matrix_tPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z8matrix_tPiS_S_S_
.p2align 3, 0x0
_Z8matrix_tPiS_S_S_:
.quad _Z23__device_stub__matrix_tPiS_S_S_
.size _Z8matrix_tPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8matrix_tPiS_S_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__matrix_tPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8matrix_tPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
cudaMallocManaged(&x, n*sizeof(Real));
cudaMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
cudaDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
} | code for sm_80
Function : _Z3addiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a2000c1e1b00 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02d0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004e0e000000000a */
/*02e0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e4000c101b04 */
/*02f0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x002fc800078e00ff */
/*0340*/ IMAD.WIDE R6, R3, R4, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0204 */
/*0350*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fe200078e0204 */
/*0360*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0380*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0206 */
/*0390*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004046000000000a */
/*03a0*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x001fc800078e0204 */
/*03b0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0021e8000c101b04 */
/*03c0*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R18, R0, 0x8, R12 ; /* 0x0000000800127825 */
/* 0x000fe200078e020c */
/*03f0*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x0042860000000010 */
/*0400*/ IMAD.WIDE R16, R0, 0x8, R10 ; /* 0x0000000800107825 */
/* 0x002fc800078e020a */
/*0410*/ STG.E.64 [R12.64], R14 ; /* 0x0000000e0c007986 */
/* 0x0043e8000c101b04 */
/*0420*/ LDG.E.64 R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R6, R0, 0x8, R18 ; /* 0x0000000800067825 */
/* 0x001fe200078e0212 */
/*0450*/ DADD R4, R4, R20 ; /* 0x0000000004047229 */
/* 0x0040860000000014 */
/*0460*/ IMAD.WIDE R20, R0, 0x8, R16 ; /* 0x0000000800147825 */
/* 0x001fc800078e0210 */
/*0470*/ STG.E.64 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x0043e8000c101b04 */
/*0480*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ DADD R8, R8, R20 ; /* 0x0000000008087229 */
/* 0x004e0e0000000014 */
/*04e0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0013ea000c101b04 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
cudaMallocManaged(&x, n*sizeof(Real));
cudaMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
cudaDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
} | .file "tmpxft_0010de61_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4206:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4206:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPdS_iPdS_
.type _Z25__device_stub__Z3addiPdS_iPdS_, @function
_Z25__device_stub__Z3addiPdS_iPdS_:
.LFB4228:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4228:
.size _Z25__device_stub__Z3addiPdS_iPdS_, .-_Z25__device_stub__Z3addiPdS_iPdS_
.globl _Z3addiPdS_
.type _Z3addiPdS_, @function
_Z3addiPdS_:
.LFB4229:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4229:
.size _Z3addiPdS_, .-_Z3addiPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max Error: "
.text
.globl main
.type main, @function
main:
.LFB4203:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq _ZSt4cout(%rip), %rdx
movq _ZSt4cout(%rip), %rcx
movq %rdx, %rsi
addq -24(%rcx), %rsi
movl 24(%rsi), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rsi)
movq -24(%rcx), %rax
movq $20, 8(%rdx,%rax)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm1
movsd .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movsd %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq $8388608, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
leaq 8388608(%rax), %rdx
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm2
movq .LC4(%rip), %xmm1
.L16:
movsd (%rax), %xmm0
subsd %xmm2, %xmm0
andpd %xmm1, %xmm0
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rax, %rdx
jne .L16
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPdS_iPdS_
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4203:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4231:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4231:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1074266112
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
cudaMallocManaged(&x, n*sizeof(Real));
cudaMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
cudaDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
cudaFree(x);
cudaFree(y);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
hipMallocManaged(&x, n*sizeof(Real));
hipMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
hipDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
hipMallocManaged(&x, n*sizeof(Real));
hipMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
hipDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdS_
.globl _Z3addiPdS_
.p2align 8
.type _Z3addiPdS_,@function
_Z3addiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[6:7], off
v_add_co_u32 v2, s0, v2, s8
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[8:9]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPdS_, .Lfunc_end0-_Z3addiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::fixed << std::setprecision(20);
int n = 1<<20;
Real *x, *y;
hipMallocManaged(&x, n*sizeof(Real));
hipMallocManaged(&y, n*sizeof(Real));
for(int i=0; i<n; i++){
x[i] = static_cast<Real>(1);
y[i] = static_cast<Real>(2);
}
int blocksize = 32*8;
int numBlock = (n + blocksize - 1) / blocksize;
add<<<numBlock, blocksize>>>(n, x, y);
hipDeviceSynchronize();
Real maxError = static_cast<Real>(0);
for(int i=0; i<n; ++i){
maxError = std::max(maxError, std::fabs(y[i] - static_cast<Real>(3)));
}
std::cout << "Max Error: " << maxError << std::endl;
hipFree(x);
hipFree(y);
} | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPdS_ # -- Begin function _Z18__device_stub__addiPdS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPdS_,@function
_Z18__device_stub__addiPdS_: # @_Z18__device_stub__addiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPdS_, .Lfunc_end0-_Z18__device_stub__addiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xc008000000000000 # double -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $20, _ZSt4cout+8(%rax)
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
movabsq $4607182418800017408, %rsi # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rdi # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rsi, (%rax,%rcx,8)
movq %rdi, (%rdx,%rcx,8)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPdS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorpd %xmm3, %xmm3
xorl %eax, %eax
movq 8(%rsp), %rcx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movapd %xmm3, %xmm2
movsd (%rcx,%rax,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
maxsd %xmm2, %xmm3
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movapd %xmm3, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movaps 128(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPdS_,@object # @_Z3addiPdS_
.section .rodata,"a",@progbits
.globl _Z3addiPdS_
.p2align 3, 0x0
_Z3addiPdS_:
.quad _Z18__device_stub__addiPdS_
.size _Z3addiPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max Error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPdS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x310 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0206 */
/*0270*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0280*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a2000c1e1b00 */
/*0290*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02a0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02b0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02c0*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*02d0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004e0e000000000a */
/*02e0*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0011e4000c101b04 */
/*02f0*/ IMAD.WIDE R4, R0, 0x8, R4 ; /* 0x0000000800047825 */
/* 0x001fe400078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x002fc800078e00ff */
/*0340*/ IMAD.WIDE R6, R3, R4, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0204 */
/*0350*/ IMAD.WIDE R4, R3, R4, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fe200078e0204 */
/*0360*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0370*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea2000c1e1b00 */
/*0380*/ IMAD.WIDE R12, R0, 0x8, R6 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0206 */
/*0390*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004046000000000a */
/*03a0*/ IMAD.WIDE R10, R0, 0x8, R4 ; /* 0x00000008000a7825 */
/* 0x001fc800078e0204 */
/*03b0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0021e8000c101b04 */
/*03c0*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1b00 */
/*03d0*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ea2000c1e1b00 */
/*03e0*/ IMAD.WIDE R18, R0, 0x8, R12 ; /* 0x0000000800127825 */
/* 0x000fe200078e020c */
/*03f0*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x0042860000000010 */
/*0400*/ IMAD.WIDE R16, R0, 0x8, R10 ; /* 0x0000000800107825 */
/* 0x002fc800078e020a */
/*0410*/ STG.E.64 [R12.64], R14 ; /* 0x0000000e0c007986 */
/* 0x0043e8000c101b04 */
/*0420*/ LDG.E.64 R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1b00 */
/*0430*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1b00 */
/*0440*/ IMAD.WIDE R6, R0, 0x8, R18 ; /* 0x0000000800067825 */
/* 0x001fe200078e0212 */
/*0450*/ DADD R4, R4, R20 ; /* 0x0000000004047229 */
/* 0x0040860000000014 */
/*0460*/ IMAD.WIDE R20, R0, 0x8, R16 ; /* 0x0000000800147825 */
/* 0x001fc800078e0210 */
/*0470*/ STG.E.64 [R18.64], R4 ; /* 0x0000000412007986 */
/* 0x0043e8000c101b04 */
/*0480*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1b00 */
/*0490*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04b0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04c0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*04d0*/ DADD R8, R8, R20 ; /* 0x0000000008087229 */
/* 0x004e0e0000000014 */
/*04e0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0013ea000c101b04 */
/*04f0*/ @!P0 BRA 0x330 ; /* 0xfffffe3000008947 */
/* 0x000fea000383ffff */
/*0500*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0510*/ BRA 0x510; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdS_
.globl _Z3addiPdS_
.p2align 8
.type _Z3addiPdS_,@function
_Z3addiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[6:7], off
v_add_co_u32 v2, s0, v2, s8
v_cmp_le_i32_e32 vcc_lo, s10, v1
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[8:9]
global_store_b64 v[6:7], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPdS_, .Lfunc_end0-_Z3addiPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addiPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010de61_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4206:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4206:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPdS_iPdS_
.type _Z25__device_stub__Z3addiPdS_iPdS_, @function
_Z25__device_stub__Z3addiPdS_iPdS_:
.LFB4228:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4228:
.size _Z25__device_stub__Z3addiPdS_iPdS_, .-_Z25__device_stub__Z3addiPdS_iPdS_
.globl _Z3addiPdS_
.type _Z3addiPdS_, @function
_Z3addiPdS_:
.LFB4229:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPdS_iPdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4229:
.size _Z3addiPdS_, .-_Z3addiPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Max Error: "
.text
.globl main
.type main, @function
main:
.LFB4203:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq _ZSt4cout(%rip), %rdx
movq _ZSt4cout(%rip), %rcx
movq %rdx, %rsi
addq -24(%rcx), %rsi
movl 24(%rsi), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rsi)
movq -24(%rcx), %rax
movq $20, 8(%rdx,%rax)
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8388608, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movsd .LC1(%rip), %xmm1
movsd .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movsd %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq $8388608, %rax
jne .L12
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4096, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
leaq 8388608(%rax), %rdx
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm2
movq .LC4(%rip), %xmm1
.L16:
movsd (%rax), %xmm0
subsd %xmm2, %xmm0
andpd %xmm1, %xmm0
maxsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $8, %rax
cmpq %rax, %rdx
jne .L16
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPdS_iPdS_
jmp .L13
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4203:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4231:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4231:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1074266112
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPdS_ # -- Begin function _Z18__device_stub__addiPdS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPdS_,@function
_Z18__device_stub__addiPdS_: # @_Z18__device_stub__addiPdS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPdS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPdS_, .Lfunc_end0-_Z18__device_stub__addiPdS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0xc008000000000000 # double -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $20, _ZSt4cout+8(%rax)
leaq 16(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $8388608, %esi # imm = 0x800000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
movabsq $4607182418800017408, %rsi # imm = 0x3FF0000000000000
movabsq $4611686018427387904, %rdi # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rsi, (%rax,%rcx,8)
movq %rdi, (%rdx,%rcx,8)
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967552, %rdx # imm = 0x100000100
leaq 3840(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPdS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorpd %xmm3, %xmm3
xorl %eax, %eax
movq 8(%rsp), %rcx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movapd %xmm3, %xmm2
movsd (%rcx,%rax,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
maxsd %xmm2, %xmm3
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movapd %xmm3, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movaps 128(%rsp), %xmm0 # 16-byte Reload
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPdS_,@object # @_Z3addiPdS_
.section .rodata,"a",@progbits
.globl _Z3addiPdS_
.p2align 3, 0x0
_Z3addiPdS_:
.quad _Z18__device_stub__addiPdS_
.size _Z3addiPdS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Max Error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPdS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_g, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
cudaFree(dev_a); cudaFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} | code for sm_80
Function : _Z7prescanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf0 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0050*/ LEA R0, R0, R9, 0x2 ; /* 0x0000000900007211 */
/* 0x001fe400078e10ff */
/*0060*/ ISETP.GT.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f04270 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f26270 */
/*0080*/ @P1 STS [R9.X4], RZ ; /* 0x000000ff09001388 */
/* 0x0001e20000004800 */
/*0090*/ @P1 BRA 0xe0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0043e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ ISETP.GT.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f44270 */
/*0110*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f25270 */
/*0120*/ @!P0 LDS.64 R2, [R9.X8] ; /* 0x0000000009028984 */
/* 0x002e640000008a00 */
/*0130*/ @!P0 FADD R2, R2, R3 ; /* 0x0000000302028221 */
/* 0x002fca0000000000 */
/*0140*/ @!P0 STS [R9.X8+0x4], R2 ; /* 0x0000040209008388 */
/* 0x000fe80000008800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P2 LDS R4, [R9.X16+0x4] ; /* 0x000004000904a984 */
/* 0x000fe8000000c800 */
/*0170*/ @!P2 LDS R3, [R9.X16+0xc] ; /* 0x00000c000903a984 */
/* 0x000e64000000c800 */
/*0180*/ @!P2 FADD R3, R3, R4 ; /* 0x000000040303a221 */
/* 0x002fca0000000000 */
/*0190*/ @!P2 STS [R9.X16+0xc], R3 ; /* 0x00000c030900a388 */
/* 0x0003e8000000c800 */
/*01a0*/ @!P1 STS [0xc], RZ ; /* 0x00000cffff009388 */
/* 0x000fe80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*01d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*01e0*/ @!P2 LDS R4, [R9.X16+0x4] ; /* 0x000004000904a984 */
/* 0x000fe8000000c800 */
/*01f0*/ @!P2 LDS R8, [R9.X16+0xc] ; /* 0x00000c000908a984 */
/* 0x000e64000000c800 */
/*0200*/ @!P2 FADD R4, R4, R8 ; /* 0x000000080404a221 */
/* 0x002fe40000000000 */
/*0210*/ @!P2 STS [R9.X16+0x4], R8 ; /* 0x000004080900a388 */
/* 0x000fe8000000c800 */
/*0220*/ @!P2 STS [R9.X16+0xc], R4 ; /* 0x00000c040900a388 */
/* 0x000fe8000000c800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 LDS.64 R6, [R9.X8] ; /* 0x0000000009068984 */
/* 0x000e640000008a00 */
/*0250*/ @!P0 FADD R11, R6, R7 ; /* 0x00000007060b8221 */
/* 0x002fe20000000000 */
/*0260*/ MOV R10, R7 ; /* 0x00000007000a7202 */
/* 0x000fca0000000f00 */
/*0270*/ @!P0 STS.64 [R9.X8], R10 ; /* 0x0000000a09008388 */
/* 0x000fe80000008a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R5, [R9.X4] ; /* 0x0000000009057984 */
/* 0x000e680000004800 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_g, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
cudaFree(dev_a); cudaFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} | .file "tmpxft_00187c70_00000000-6_m_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10myDiffTimeR7timevalS0_
.type _Z10myDiffTimeR7timevalS0_, @function
_Z10myDiffTimeR7timevalS0_:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
movsd .LC0(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsi), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rdi), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq (%rdi), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10myDiffTimeR7timevalS0_, .-_Z10myDiffTimeR7timevalS0_
.globl _Z7scanCPUPfS_i
.type _Z7scanCPUPfS_i, @function
_Z7scanCPUPfS_i:
.LFB2059:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
cmpl $1, %edx
jle .L4
leal -1(%rdx), %edx
movl $0, %eax
.L6:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, 4(%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L6
.L4:
ret
.cfi_endproc
.LFE2059:
.size _Z7scanCPUPfS_i, .-_Z7scanCPUPfS_i
.globl _Z29__device_stub__Z7prescanPfS_iPfS_i
.type _Z29__device_stub__Z7prescanPfS_iPfS_i, @function
_Z29__device_stub__Z7prescanPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7prescanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z7prescanPfS_iPfS_i, .-_Z29__device_stub__Z7prescanPfS_iPfS_i
.globl _Z7prescanPfS_i
.type _Z7prescanPfS_i, @function
_Z7prescanPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7prescanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7prescanPfS_i, .-_Z7prescanPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "a[%i] = %f\n"
.LC3:
.string "c[%i] = %0.3f, g[%i] = %0.3f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "GPU Time for scan size %i: %f\n"
.align 8
.LC5:
.string "CPU Time for scan size %i: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L17:
movl %ebx, %edx
addl $1, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss %xmm0, 0(%rbp)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpl $8, %ebx
jne .L17
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $32, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L18:
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
leaq 48(%rsp), %rbp
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10myDiffTimeR7timevalS0_
movsd %xmm0, (%rsp)
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $8, %edx
call _Z7scanCPUPfS_i
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10myDiffTimeR7timevalS0_
movsd %xmm0, 8(%rsp)
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L19:
movl %ebx, %edx
pxor %xmm0, %xmm0
cvtss2sd 112(%rsp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 144(%rsp,%rbx,4), %xmm1
movl %ebx, %ecx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L19
movsd (%rsp), %xmm0
movl $8, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
movl $8, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $8, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7prescanPfS_iPfS_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7prescanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
cudaDeviceSynchronize();
cudaMemcpy(g, dev_g, size, cudaMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
cudaFree(dev_a); cudaFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_g, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
hipFree(dev_a); hipFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_g, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
hipFree(dev_a); hipFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 8
.type _Z7prescanPfS_i,@function
_Z7prescanPfS_i:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v1, s15, 2, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_mov_b32 s2, 2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v4, 1, v0
v_lshl_add_u32 v6, v0, 2, 0
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v3, 1, v4
v_add_nc_u32_e32 v4, 2, v4
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s2, 1
s_lshl_b32 s3, s3, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s4
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v5, s3, v3
v_mul_lo_u32 v6, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, 0, -4
v_add3_u32 v6, v6, 0, -4
ds_load_b32 v5, v5
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v7
ds_store_b32 v6, v5
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
ds_store_b32 v4, v3 offset:12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v4, 1, v0
s_mov_b32 s3, 1
s_mov_b32 s2, 4
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, 1, v4
v_add_nc_u32_e32 v4, 2, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_12
.LBB0_10:
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_9
v_mul_u32_u24_e32 v5, s2, v4
v_mul_u32_u24_e32 v7, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v7, 2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, 0, -4
v_add3_u32 v7, v7, 0, -4
ds_load_b32 v6, v5
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(1)
ds_store_b32 v7, v6
ds_load_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v8, v6
ds_store_b32 v5, v6
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7prescanPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7prescanPfS_i, .Lfunc_end0-_Z7prescanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7prescanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7prescanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_start = (double)(start.tv_sec + start.tv_usec/1000000.0);
d_end = (double)(end.tv_sec + end.tv_usec/1000000.0);
return (d_end - d_start);
}
int main()
{
float a[N], c[N], g[N];
timeval start, end;
float *dev_a, *dev_g;
int size = N * sizeof(float);
double d_gpuTime, d_cpuTime;
// initialize matrices a
for (int i = 0; i < N; i++)
{
// a[i] = (float)(rand() % 1000000) / 1000.0;
a[i] = i+1;
printf("a[%i] = %f\n", i, a[i]);
}
// initialize a and b matrices here
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_g, size);
gettimeofday(&start, NULL);
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
prescan<<<block_num,thread_num,2*thread_num*sizeof(float)>>>(dev_g, dev_a, N);
hipDeviceSynchronize();
hipMemcpy(g, dev_g, size, hipMemcpyDeviceToHost);
gettimeofday(&end, NULL);
d_gpuTime = myDiffTime(start, end);
gettimeofday(&start, NULL);
scanCPU(c, a, N);
gettimeofday(&end, NULL);
d_cpuTime = myDiffTime(start, end);
hipFree(dev_a); hipFree(dev_g);
for (int i = 0; i < N; i++)
{
printf("c[%i] = %0.3f, g[%i] = %0.3f\n", i, c[i], i, g[i]);
}
printf("GPU Time for scan size %i: %f\n", N, d_gpuTime);
printf("CPU Time for scan size %i: %f\n", N, d_cpuTime);
}
__global__ void prescan(float *g_odata, float *g_idata, int n)
{
extern __shared__ float temp[];
// allocated on invocation
int thid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
if((bid * thread_num + thid)<n){ temp[thid] = g_idata[bid * thread_num + thid];
}else{ temp[thid] = 0;
} // Make the "empty" spots zeros, so it won't affect the final result.
for (int d = thread_num>>1; d > 0; d >>= 1)
// build sum in place up the tree
{
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
temp[bi] += temp[ai];
}
offset *= 2;
}
if (thid == 0)
{
temp[thread_num - 1] = 0;
}
// clear the last element
for (int d = 1; d < thread_num; d *= 2)
// traverse down tree & build scan
{
offset >>= 1;
__syncthreads();
if (thid < d)
{
int ai = offset*(2*thid+1)-1;
int bi = offset*(2*thid+2)-1;
float t = temp[ai];
temp[ai] = temp[ bi];
temp[bi] += t;
}
}
__syncthreads();
g_odata[bid * thread_num + thid] = temp[thid];
}
void scanCPU(float *f_out, float *f_in, int i_n)
{
f_out[0] = 0;
for (int i = 1; i < i_n; i++)
f_out[i] = f_out[i-1] + f_in[i-1];
} | .text
.file "m_add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10myDiffTimeR7timevalS0_: # @_Z10myDiffTimeR7timevalS0_
.cfi_startproc
# %bb.0:
cvtsi2sdq (%rdi), %xmm0
cvtsi2sdq 8(%rdi), %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
cvtsi2sdq (%rsi), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
divsd %xmm2, %xmm0
addsd %xmm3, %xmm0
subsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z10myDiffTimeR7timevalS0_, .Lfunc_end0-_Z10myDiffTimeR7timevalS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rsi), %rbx
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 192(%rsp,%rsi,4)
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movq %rbx, %rsi
cmpq $8, %rbx
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 2(%rdi), %rdx
movl $32, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $8, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 160(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 16(%rsp), %r13
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $0, 128(%rsp)
movl $1, %eax
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addss 188(%rsp,%rax,4), %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $8, %rax
jne .LBB1_5
# %bb.6: # %_Z7scanCPUPfS_i.exit
xorl %ebx, %ebx
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rbp
movq 56(%rsp), %r14
movq 8(%rsp), %r15
movq 16(%rsp), %r12
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 160(%rsp,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movl %ebx, %edx
movb $2, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB1_7
# %bb.8:
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsi2sd %r15, %xmm2
addsd %xmm0, %xmm2
movapd %xmm2, %xmm4
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %rbp, %xmm2
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
cvtsi2sd %r13, %xmm3
subsd %xmm2, %xmm4
movsd %xmm4, 64(%rsp) # 8-byte Spill
divsd %xmm1, %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0 # 8-byte Folded Reload
addsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 80(%rsp), %xmm2 # 8-byte Folded Reload
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
movl $.L.str.2, %edi
movl $8, %esi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movl $8, %esi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPfS_i # -- Begin function _Z22__device_stub__prescanPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__prescanPfS_i,@function
_Z22__device_stub__prescanPfS_i: # @_Z22__device_stub__prescanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__prescanPfS_i, .Lfunc_end2-_Z22__device_stub__prescanPfS_i
.cfi_endproc
# -- End function
.globl _Z7scanCPUPfS_i # -- Begin function _Z7scanCPUPfS_i
.p2align 4, 0x90
.type _Z7scanCPUPfS_i,@function
_Z7scanCPUPfS_i: # @_Z7scanCPUPfS_i
.cfi_startproc
# %bb.0:
movl $0, (%rdi)
cmpl $2, %edx
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
decq %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, 4(%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z7scanCPUPfS_i, .Lfunc_end3-_Z7scanCPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%i] = %f\n"
.size .L.str, 12
.type _Z7prescanPfS_i,@object # @_Z7prescanPfS_i
.section .rodata,"a",@progbits
.globl _Z7prescanPfS_i
.p2align 3, 0x0
_Z7prescanPfS_i:
.quad _Z22__device_stub__prescanPfS_i
.size _Z7prescanPfS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "c[%i] = %0.3f, g[%i] = %0.3f\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Time for scan size %i: %f\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU Time for scan size %i: %f\n"
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7prescanPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__prescanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7prescanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7prescanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf0 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0050*/ LEA R0, R0, R9, 0x2 ; /* 0x0000000900007211 */
/* 0x001fe400078e10ff */
/*0060*/ ISETP.GT.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fe40003f04270 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f26270 */
/*0080*/ @P1 STS [R9.X4], RZ ; /* 0x000000ff09001388 */
/* 0x0001e20000004800 */
/*0090*/ @P1 BRA 0xe0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0043e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0100*/ ISETP.GT.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe40003f44270 */
/*0110*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f25270 */
/*0120*/ @!P0 LDS.64 R2, [R9.X8] ; /* 0x0000000009028984 */
/* 0x002e640000008a00 */
/*0130*/ @!P0 FADD R2, R2, R3 ; /* 0x0000000302028221 */
/* 0x002fca0000000000 */
/*0140*/ @!P0 STS [R9.X8+0x4], R2 ; /* 0x0000040209008388 */
/* 0x000fe80000008800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P2 LDS R4, [R9.X16+0x4] ; /* 0x000004000904a984 */
/* 0x000fe8000000c800 */
/*0170*/ @!P2 LDS R3, [R9.X16+0xc] ; /* 0x00000c000903a984 */
/* 0x000e64000000c800 */
/*0180*/ @!P2 FADD R3, R3, R4 ; /* 0x000000040303a221 */
/* 0x002fca0000000000 */
/*0190*/ @!P2 STS [R9.X16+0xc], R3 ; /* 0x00000c030900a388 */
/* 0x0003e8000000c800 */
/*01a0*/ @!P1 STS [0xc], RZ ; /* 0x00000cffff009388 */
/* 0x000fe80000000800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x002fd400000001ff */
/*01d0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*01e0*/ @!P2 LDS R4, [R9.X16+0x4] ; /* 0x000004000904a984 */
/* 0x000fe8000000c800 */
/*01f0*/ @!P2 LDS R8, [R9.X16+0xc] ; /* 0x00000c000908a984 */
/* 0x000e64000000c800 */
/*0200*/ @!P2 FADD R4, R4, R8 ; /* 0x000000080404a221 */
/* 0x002fe40000000000 */
/*0210*/ @!P2 STS [R9.X16+0x4], R8 ; /* 0x000004080900a388 */
/* 0x000fe8000000c800 */
/*0220*/ @!P2 STS [R9.X16+0xc], R4 ; /* 0x00000c040900a388 */
/* 0x000fe8000000c800 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P0 LDS.64 R6, [R9.X8] ; /* 0x0000000009068984 */
/* 0x000e640000008a00 */
/*0250*/ @!P0 FADD R11, R6, R7 ; /* 0x00000007060b8221 */
/* 0x002fe20000000000 */
/*0260*/ MOV R10, R7 ; /* 0x00000007000a7202 */
/* 0x000fca0000000f00 */
/*0270*/ @!P0 STS.64 [R9.X8], R10 ; /* 0x0000000a09008388 */
/* 0x000fe80000008a00 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS R5, [R9.X4] ; /* 0x0000000009057984 */
/* 0x000e680000004800 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 8
.type _Z7prescanPfS_i,@function
_Z7prescanPfS_i:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v1, s15, 2, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_mov_b32 s2, 2
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x8
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v4, 1, v0
v_lshl_add_u32 v6, v0, 2, 0
s_mov_b32 s3, 1
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v3, 1, v4
v_add_nc_u32_e32 v4, 2, v4
s_waitcnt vmcnt(0)
ds_store_b32 v6, v5
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s2, 1
s_lshl_b32 s3, s3, 1
s_cmp_lt_u32 s2, 2
s_mov_b32 s2, s4
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v5, s3, v3
v_mul_lo_u32 v6, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v6, 2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, 0, -4
v_add3_u32 v6, v6, 0, -4
ds_load_b32 v5, v5
ds_load_b32 v7, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v5, v5, v7
ds_store_b32 v6, v5
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 0
ds_store_b32 v4, v3 offset:12
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_lshlrev_b32_e32 v4, 1, v0
s_mov_b32 s3, 1
s_mov_b32 s2, 4
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v3, 1, v4
v_add_nc_u32_e32 v4, 2, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s4, s3, 1
s_cmp_gt_u32 s3, 1
s_mov_b32 s3, s4
s_cbranch_scc1 .LBB0_12
.LBB0_10:
s_lshr_b32 s2, s2, 1
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_9
v_mul_u32_u24_e32 v5, s2, v4
v_mul_u32_u24_e32 v7, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b32_e32 v7, 2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v5, v5, 0, -4
v_add3_u32 v7, v7, 0, -4
ds_load_b32 v6, v5
ds_load_b32 v8, v7
s_waitcnt lgkmcnt(1)
ds_store_b32 v7, v6
ds_load_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v8, v6
ds_store_b32 v5, v6
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v3, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7prescanPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7prescanPfS_i, .Lfunc_end0-_Z7prescanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7prescanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7prescanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187c70_00000000-6_m_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10myDiffTimeR7timevalS0_
.type _Z10myDiffTimeR7timevalS0_, @function
_Z10myDiffTimeR7timevalS0_:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
movsd .LC0(%rip), %xmm2
divsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsi), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 8(%rdi), %xmm1
divsd %xmm2, %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq (%rdi), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z10myDiffTimeR7timevalS0_, .-_Z10myDiffTimeR7timevalS0_
.globl _Z7scanCPUPfS_i
.type _Z7scanCPUPfS_i, @function
_Z7scanCPUPfS_i:
.LFB2059:
.cfi_startproc
endbr64
movl $0x00000000, (%rdi)
cmpl $1, %edx
jle .L4
leal -1(%rdx), %edx
movl $0, %eax
.L6:
movss (%rdi,%rax,4), %xmm0
addss (%rsi,%rax,4), %xmm0
movss %xmm0, 4(%rdi,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L6
.L4:
ret
.cfi_endproc
.LFE2059:
.size _Z7scanCPUPfS_i, .-_Z7scanCPUPfS_i
.globl _Z29__device_stub__Z7prescanPfS_iPfS_i
.type _Z29__device_stub__Z7prescanPfS_iPfS_i, @function
_Z29__device_stub__Z7prescanPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7prescanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z7prescanPfS_iPfS_i, .-_Z29__device_stub__Z7prescanPfS_iPfS_i
.globl _Z7prescanPfS_i
.type _Z7prescanPfS_i, @function
_Z7prescanPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7prescanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7prescanPfS_i, .-_Z7prescanPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "a[%i] = %f\n"
.LC3:
.string "c[%i] = %0.3f, g[%i] = %0.3f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "GPU Time for scan size %i: %f\n"
.align 8
.LC5:
.string "CPU Time for scan size %i: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 80(%rsp), %rbp
movl $0, %ebx
leaq .LC2(%rip), %r12
.L17:
movl %ebx, %edx
addl $1, %ebx
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
movss %xmm0, 0(%rbp)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpl $8, %ebx
jne .L17
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $32, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L18:
call cudaDeviceSynchronize@PLT
leaq 144(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leaq 64(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
leaq 48(%rsp), %rbp
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10myDiffTimeR7timevalS0_
movsd %xmm0, (%rsp)
movl $0, %esi
movq %rbp, %rdi
call gettimeofday@PLT
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $8, %edx
call _Z7scanCPUPfS_i
movl $0, %esi
movq %rbx, %rdi
call gettimeofday@PLT
movq %rbx, %rsi
movq %rbp, %rdi
call _Z10myDiffTimeR7timevalS0_
movsd %xmm0, 8(%rsp)
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L19:
movl %ebx, %edx
pxor %xmm0, %xmm0
cvtss2sd 112(%rsp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 144(%rsp,%rbx,4), %xmm1
movl %ebx, %ecx
movq %rbp, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L19
movsd (%rsp), %xmm0
movl $8, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
movl $8, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $8, %edx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z7prescanPfS_iPfS_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z7prescanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "m_add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10myDiffTimeR7timevalS0_: # @_Z10myDiffTimeR7timevalS0_
.cfi_startproc
# %bb.0:
cvtsi2sdq (%rdi), %xmm0
cvtsi2sdq 8(%rdi), %xmm1
movsd .LCPI0_0(%rip), %xmm2 # xmm2 = mem[0],zero
divsd %xmm2, %xmm1
addsd %xmm0, %xmm1
cvtsi2sdq (%rsi), %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsi), %xmm0
divsd %xmm2, %xmm0
addsd %xmm3, %xmm0
subsd %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z10myDiffTimeR7timevalS0_, .Lfunc_end0-_Z10myDiffTimeR7timevalS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rsi), %rbx
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 192(%rsp,%rsi,4)
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
movb $1, %al
callq printf
movq %rbx, %rsi
cmpq $8, %rbx
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 2(%rdi), %rdx
movl $32, %r8d
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $8, 44(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 160(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
leaq 160(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 72(%rsp) # 8-byte Spill
movq 16(%rsp), %r13
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $0, 128(%rsp)
movl $1, %eax
xorpd %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addss 188(%rsp,%rax,4), %xmm0
movss %xmm0, 128(%rsp,%rax,4)
incq %rax
cmpq $8, %rax
jne .LBB1_5
# %bb.6: # %_Z7scanCPUPfS_i.exit
xorl %ebx, %ebx
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 48(%rsp), %rbp
movq 56(%rsp), %r14
movq 8(%rsp), %r15
movq 16(%rsp), %r12
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 160(%rsp,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %ebx, %esi
movl %ebx, %edx
movb $2, %al
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB1_7
# %bb.8:
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
cvtsi2sd %r15, %xmm2
addsd %xmm0, %xmm2
movapd %xmm2, %xmm4
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %rbp, %xmm2
divsd %xmm1, %xmm0
addsd %xmm0, %xmm2
cvtsi2sd %r13, %xmm3
subsd %xmm2, %xmm4
movsd %xmm4, 64(%rsp) # 8-byte Spill
divsd %xmm1, %xmm3
xorps %xmm0, %xmm0
cvtsi2sdq 72(%rsp), %xmm0 # 8-byte Folded Reload
addsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 80(%rsp), %xmm2 # 8-byte Folded Reload
divsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sdq 88(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
movl $.L.str.2, %edi
movl $8, %esi
movb $1, %al
callq printf
movl $.L.str.3, %edi
movl $8, %esi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPfS_i # -- Begin function _Z22__device_stub__prescanPfS_i
.p2align 4, 0x90
.type _Z22__device_stub__prescanPfS_i,@function
_Z22__device_stub__prescanPfS_i: # @_Z22__device_stub__prescanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z22__device_stub__prescanPfS_i, .Lfunc_end2-_Z22__device_stub__prescanPfS_i
.cfi_endproc
# -- End function
.globl _Z7scanCPUPfS_i # -- Begin function _Z7scanCPUPfS_i
.p2align 4, 0x90
.type _Z7scanCPUPfS_i,@function
_Z7scanCPUPfS_i: # @_Z7scanCPUPfS_i
.cfi_startproc
# %bb.0:
movl $0, (%rdi)
cmpl $2, %edx
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
movss (%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
decq %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, 4(%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z7scanCPUPfS_i, .Lfunc_end3-_Z7scanCPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "a[%i] = %f\n"
.size .L.str, 12
.type _Z7prescanPfS_i,@object # @_Z7prescanPfS_i
.section .rodata,"a",@progbits
.globl _Z7prescanPfS_i
.p2align 3, 0x0
_Z7prescanPfS_i:
.quad _Z22__device_stub__prescanPfS_i
.size _Z7prescanPfS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "c[%i] = %0.3f, g[%i] = %0.3f\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "GPU Time for scan size %i: %f\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU Time for scan size %i: %f\n"
.size .L.str.3, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7prescanPfS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__prescanPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7prescanPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void test()
{
__shared__ int i, mutex;
if (threadIdx.x == 0) {
i = 0;
mutex = 0;
}
__syncthreads();
while( atomicCAS(&mutex, 0, 1) != 0);
i++;
printf("thread %d: %d\n", threadIdx.x, i);
atomicExch(&mutex,0);
}
int main(void) {
// run GPU code
test<<<2, 32>>>();
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
} | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ BSSY B0, 0x100 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fda0003f05270 */
/*0060*/ @!P0 STS.64 [RZ], RZ ; /* 0x000000ffff008388 */
/* 0x000fe80000000a00 */
/*0070*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0080*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00b0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00c0*/ ATOMS.CAS R0, [0x4], R2, R3 ; /* 0x00000402ff00738d */
/* 0x000e240000000003 */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*00e0*/ @P0 BRA 0xa0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0100*/ LDS R9, [RZ] ; /* 0x00000000ff097984 */
/* 0x000e220000000800 */
/*0110*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0140*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*0150*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x001fca0007ffe0ff */
/*0160*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e80000100a00 */
/*0170*/ STS [RZ], R9 ; /* 0x00000009ff007388 */
/* 0x0001e40000000800 */
/*0180*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fe20000000000 */
/*0190*/ MOV R11, 0x200 ; /* 0x00000200000b7802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R20, 0x180 ; /* 0x0000018000147802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*01d0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01e0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01f0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0200*/ ATOMS.EXCH RZ, [0x4], RZ ; /* 0x000004ffffff738c */
/* 0x000fe20004000000 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void test()
{
__shared__ int i, mutex;
if (threadIdx.x == 0) {
i = 0;
mutex = 0;
}
__syncthreads();
while( atomicCAS(&mutex, 0, 1) != 0);
i++;
printf("thread %d: %d\n", threadIdx.x, i);
atomicExch(&mutex,0);
}
int main(void) {
// run GPU code
test<<<2, 32>>>();
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
} | .file "tmpxft_000389b0_00000000-6_stack_overflow_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
.weak _Z9gpuAssert9cudaErrorPcib
.type _Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
.text
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/soarlab/Gklee/master/gklee_tests/various_tests/stack_overlow_atomics/stack_overflow_atomics.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L20:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $35, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $36, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z22__device_stub__Z4testvv
jmp .L20
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void test()
{
__shared__ int i, mutex;
if (threadIdx.x == 0) {
i = 0;
mutex = 0;
}
__syncthreads();
while( atomicCAS(&mutex, 0, 1) != 0);
i++;
printf("thread %d: %d\n", threadIdx.x, i);
atomicExch(&mutex,0);
}
int main(void) {
// run GPU code
test<<<2, 32>>>();
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
} | #include <stdio.h>
#include <hip/hip_runtime.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void test()
{
__shared__ int i, mutex;
if (threadIdx.x == 0) {
i = 0;
mutex = 0;
}
__syncthreads();
while( atomicCAS(&mutex, 0, 1) != 0);
i++;
printf("thread %d: %d\n", threadIdx.x, i);
atomicExch(&mutex,0);
}
int main(void) {
// run GPU code
test<<<2, 32>>>();
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void test()
{
__shared__ int i, mutex;
if (threadIdx.x == 0) {
i = 0;
mutex = 0;
}
__syncthreads();
while( atomicCAS(&mutex, 0, 1) != 0);
i++;
printf("thread %d: %d\n", threadIdx.x, i);
atomicExch(&mutex,0);
}
int main(void) {
// run GPU code
test<<<2, 32>>>();
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
} | .text
.file "stack_overflow_atomics.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPcib.exit4
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $35, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $36, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/soarlab/Gklee/master/gklee_tests/various_tests/stack_overlow_atomics/stack_overflow_atomics.hip"
.size .L.str, 153
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000389b0_00000000-6_stack_overflow_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPcib,comdat
.weak _Z9gpuAssert9cudaErrorPcib
.type _Z9gpuAssert9cudaErrorPcib, @function
_Z9gpuAssert9cudaErrorPcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPcib, .-_Z9gpuAssert9cudaErrorPcib
.text
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4testv, .-_Z4testv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/soarlab/Gklee/master/gklee_tests/various_tests/stack_overlow_atomics/stack_overflow_atomics.cu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L20:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $35, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $36, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPcib
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z22__device_stub__Z4testvv
jmp .L20
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stack_overflow_atomics.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5: # %_Z9gpuAssert10hipError_tPcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_6
# %bb.7: # %_Z9gpuAssert10hipError_tPcib.exit4
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 80
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $35, %r8d
jmp .LBB1_4
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.1, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $36, %r8d
.LBB1_4:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/soarlab/Gklee/master/gklee_tests/various_tests/stack_overlow_atomics/stack_overflow_atomics.hip"
.size .L.str, 153
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.1, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
cudaDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
cudaMalloc((void**)&d_arr, arr.size() * sizeof(int));
cudaMalloc((void**)&d_out, sizeof(int));
cudaMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
cudaMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//run reduce operation
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
cudaEventRecord(stop, 0);
//wait for it to finish
cudaDeviceSynchronize();
//store answer on host
int ans;
cudaMemcpy(&ans, d_out, sizeof(int), cudaMemcpyDeviceToHost);
//find time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
cudaFree(d_arr);
cudaFree(d_intermediate);
cudaFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
cudaMalloc((void**)&d_arrb, arr.size() * sizeof(int));
cudaMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
cudaMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//cuda events
cudaEvent_t b1, b2;
cudaEventCreate(&b1);
cudaEventCreate(&b2);
//run parity
cudaEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
cudaEventRecord(b2, 0);
//calc time
float b_time;
cudaEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
cudaMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), cudaMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
cudaFree(d_arrb);
cudaFree(d_outb);
free(ans_arr);
return 0;
} | code for sm_80
Function : _Z13global_parityPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02c0*/ IMAD.HI R9, R8, 0x66666667, RZ ; /* 0x6666666708097827 */
/* 0x004fca00078e02ff */
/*02d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*02e0*/ LEA.HI.SX32 R9, R9, R10, 0x1e ; /* 0x0000000a09097211 */
/* 0x000fca00078ff2ff */
/*02f0*/ IMAD R9, R9, -0xa, R8 ; /* 0xfffffff609097824 */
/* 0x000fca00078e0208 */
/*0300*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x270 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0360*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x001fca00078e0208 */
/*0370*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD.HI R6, R2, 0x66666667, RZ ; /* 0x6666666702067827 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.U32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011606 */
/*03a0*/ LEA.HI.SX32 R9, R6, R7, 0x1e ; /* 0x0000000706097211 */
/* 0x000fe200078ff2ff */
/*03b0*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*03c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*03d0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0410*/ IMAD.HI R10, R2, 0x66666667, RZ ; /* 0x66666667020a7827 */
/* 0x004fca00078e02ff */
/*0420*/ SHF.R.U32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fc8000001160a */
/*0430*/ LEA.HI.SX32 R11, R10, R11, 0x1e ; /* 0x0000000b0a0b7211 */
/* 0x000fca00078ff2ff */
/*0440*/ IMAD R15, R11, -0xa, R2 ; /* 0xfffffff60b0f7824 */
/* 0x000fe400078e0202 */
/*0450*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0460*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.HI R12, R2, 0x66666667, RZ ; /* 0x66666667020c7827 */
/* 0x004fca00078e02ff */
/*0490*/ SHF.R.U32.HI R7, RZ, 0x1f, R12 ; /* 0x0000001fff077819 */
/* 0x001fc8000001160c */
/*04a0*/ LEA.HI.SX32 R9, R12, R7, 0x1e ; /* 0x000000070c097211 */
/* 0x000fe200078ff2ff */
/*04b0*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fc800078e0204 */
/*04c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*04d0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x000fc600078e020a */
/*04e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ IMAD.HI R2, R8, 0x66666667, RZ ; /* 0x6666666708027827 */
/* 0x004fca00078e02ff */
/*0540*/ SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x002fc80000011602 */
/*0550*/ LEA.HI.SX32 R11, R2, R5, 0x1e ; /* 0x00000005020b7211 */
/* 0x000fe200078ff2ff */
/*0560*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD R11, R11, -0xa, R8 ; /* 0xfffffff60b0b7824 */
/* 0x000fca00078e0208 */
/*0580*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101904 */
/*0590*/ @!P0 BRA 0x350 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20global_reduce_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1d0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf06070 */
/*00c0*/ BSSY B0, 0x190 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*00d0*/ @P0 BRA 0x180 ; /* 0x000000a000000947 */
/* 0x001fea0003800000 */
/*00e0*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fc8000fffe0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*0100*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0110*/ @P0 BRA 0x180 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea6000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0005 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0160*/ IMNMX R7, R6, R5, PT ; /* 0x0000000506077217 */
/* 0x004fca0003800200 */
/*0170*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @P0 BRA 0xb0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
cudaDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
cudaMalloc((void**)&d_arr, arr.size() * sizeof(int));
cudaMalloc((void**)&d_out, sizeof(int));
cudaMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
cudaMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//run reduce operation
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
cudaEventRecord(stop, 0);
//wait for it to finish
cudaDeviceSynchronize();
//store answer on host
int ans;
cudaMemcpy(&ans, d_out, sizeof(int), cudaMemcpyDeviceToHost);
//find time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
cudaFree(d_arr);
cudaFree(d_intermediate);
cudaFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
cudaMalloc((void**)&d_arrb, arr.size() * sizeof(int));
cudaMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
cudaMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//cuda events
cudaEvent_t b1, b2;
cudaEventCreate(&b1);
cudaEventCreate(&b2);
//run parity
cudaEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
cudaEventRecord(b2, 0);
//calc time
float b_time;
cudaEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
cudaMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), cudaMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
cudaFree(d_arrb);
cudaFree(d_outb);
free(ans_arr);
return 0;
} | .file "tmpxft_00133b00_00000000-6_q1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4179:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4179:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.type _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, @function
_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i:
.LFB4201:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4201:
.size _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i, .-_Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
.globl _Z20global_reduce_kernelPiS_i
.type _Z20global_reduce_kernelPiS_i, @function
_Z20global_reduce_kernelPiS_i:
.LFB4202:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4202:
.size _Z20global_reduce_kernelPiS_i, .-_Z20global_reduce_kernelPiS_i
.globl _Z6reducePiS_S_i
.type _Z6reducePiS_S_i, @function
_Z6reducePiS_S_i:
.LFB4163:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq %rdx, %r14
movl %ecx, %ebp
leal 511(%rcx), %ebx
testl %ecx, %ecx
cmovns %ecx, %ebx
sarl $9, %ebx
addl $1, %ebx
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %ebx, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
cmpl $1, %ebx
jle .L16
movl $1, %eax
.L14:
addl %eax, %eax
cmpl %eax, %ebx
jg .L14
.L13:
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl %ebp, %edx
movq %r14, %rsi
movq %r12, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L12
.L16:
movl $1, %eax
jmp .L13
.L20:
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z43__device_stub__Z20global_reduce_kernelPiS_iPiS_i
jmp .L11
.cfi_endproc
.LFE4163:
.size _Z6reducePiS_S_i, .-_Z6reducePiS_S_i
.globl _Z36__device_stub__Z13global_parityPiS_iPiS_i
.type _Z36__device_stub__Z13global_parityPiS_iPiS_i, @function
_Z36__device_stub__Z13global_parityPiS_iPiS_i:
.LFB4203:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13global_parityPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4203:
.size _Z36__device_stub__Z13global_parityPiS_iPiS_i, .-_Z36__device_stub__Z13global_parityPiS_iPiS_i
.globl _Z13global_parityPiS_i
.type _Z13global_parityPiS_i, @function
_Z13global_parityPiS_i:
.LFB4204:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13global_parityPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4204:
.size _Z13global_parityPiS_i, .-_Z13global_parityPiS_i
.globl _Z6parityPiS_i
.type _Z6parityPiS_i, @function
_Z6parityPiS_i:
.LFB4164:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal 511(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $9, %eax
addl $1, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L30:
call cudaDeviceSynchronize@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z36__device_stub__Z13global_parityPiS_iPiS_i
jmp .L30
.cfi_endproc
.LFE4164:
.size _Z6parityPiS_i, .-_Z6parityPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13global_parityPiS_i"
.LC1:
.string "_Z20global_reduce_kernelPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4206:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13global_parityPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z20global_reduce_kernelPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4206:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4532:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L38
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L38:
ret
.cfi_endproc
.LFE4532:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.type _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, @function
_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_:
.LFB4848:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L58
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L44
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L45
jmp .L52
.L58:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L59:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L47
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L51
.L44:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L52:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L45:
movq 8(%rsp), %rax
movl (%rax), %eax
movl %eax, (%r12,%r15)
testq %r15, %r15
jg .L59
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L49
.L47:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L49:
addq %rbp, %r15
testq %r13, %r13
je .L50
movq 16(%rbx), %rsi
subq %r13, %rsi
.L51:
movq %r13, %rdi
call _ZdlPvm@PLT
.L50:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4848:
.size _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_, .-_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
.section .rodata.str1.1
.LC3:
.string "inp.txt"
.LC4:
.string "stoi"
.LC5:
.string "Unable to open file"
.LC6:
.string "q1a.txt"
.LC7:
.string "q1b.txt"
.LC8:
.string ","
.text
.globl main
.type main, @function
main:
.LFB4165:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4165
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1736, %rsp
.cfi_def_cfa_offset 1792
movq %fs:40, %rax
movq %rax, 1720(%rsp)
xorl %eax, %eax
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
leaq 1200(%rsp), %rdi
movl $8, %edx
leaq .LC3(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq 1320(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L93
leaq 144(%rsp), %rax
movq %rax, 8(%rsp)
leaq 1200(%rsp), %r13
movl $2147483648, %r14d
movl $4294967295, %r15d
jmp .L61
.L100:
movq 1720(%rsp), %rax
subq %fs:40, %rax
jne .L97
leaq .LC4(%rip), %rdi
.LEHB1:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L97:
call __stack_chk_fail@PLT
.L65:
movq 1720(%rsp), %rax
subq %fs:40, %rax
jne .L98
leaq .LC4(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE1:
.L90:
endbr64
cmpl $0, (%rbx)
jne .L72
movl %r12d, (%rbx)
.L72:
movq %rax, %rbx
.L73:
leaq 1200(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L83:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1720(%rsp), %rax
subq %fs:40, %rax
je .L84
call __stack_chk_fail@PLT
.L98:
call __stack_chk_fail@PLT
.L101:
leaq 104(%rsp), %rdx
leaq 112(%rsp), %rdi
.LEHB2:
call _ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_
jmp .L61
.L102:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L99
movq 144(%rsp), %rbp
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r12d
movl $0, (%rax)
leaq 104(%rsp), %rsi
movl $10, %edx
movq %rbp, %rdi
call __isoc23_strtol@PLT
cmpq 104(%rsp), %rbp
je .L100
movl (%rbx), %edx
cmpl $34, %edx
je .L65
leaq (%rax,%r14), %rcx
cmpq %rcx, %r15
jb .L65
testl %edx, %edx
jne .L68
movl %r12d, (%rbx)
.L68:
movl %eax, 104(%rsp)
movq 120(%rsp), %rsi
cmpq 128(%rsp), %rsi
je .L101
movl %eax, (%rsi)
addq $4, %rsi
movq %rsi, 120(%rsp)
.L61:
movl $44, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L102
.L99:
leaq 1200(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
jmp .L76
.L93:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L76:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movq 112(%rsp), %rbp
movq 120(%rsp), %rbx
subq %rbp, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq %rbx, %r12
sarq $2, %r12
movl %r12d, %r13d
movl %r12d, %ecx
movq 56(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z6reducePiS_S_i
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 64(%rsp), %rsi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq 176(%rsp), %rdi
movl $16, %edx
leaq .LC6(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE2:
leaq 288(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L77
leaq 176(%rsp), %rdi
movl 28(%rsp), %esi
.LEHB3:
call _ZNSolsEi@PLT
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.L77:
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movl %r13d, %edx
movq 80(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z6parityPiS_i
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
leaq 36(%rsp), %rdi
movq 104(%rsp), %rdx
movq 96(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 88(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq 688(%rsp), %rdi
movl $16, %edx
leaq .LC7(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE3:
leaq 800(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
testb %al, %al
je .L78
leaq 688(%rsp), %rdi
movl 0(%rbp), %esi
.LEHB4:
call _ZNSolsEi@PLT
cmpq $4, %rbx
jbe .L79
movl $1, %ebx
leaq .LC8(%rip), %r13
jmp .L80
.L103:
movl 0(%rbp,%rbx,4), %esi
leaq 688(%rsp), %rdi
call _ZNSolsEi@PLT
addq $1, %rbx
cmpq %r12, %rbx
jnb .L79
.L80:
leaq 688(%rsp), %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L103
.L79:
leaq 688(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
.L78:
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
.LEHE4:
movq %rbp, %rdi
call free@PLT
leaq 688(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 1200(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 1720(%rsp), %rax
subq %fs:40, %rax
jne .L104
movl $0, %eax
addq $1736, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 688(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L82:
leaq 176(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L73
.L88:
endbr64
movq %rax, %rbx
jmp .L82
.L87:
endbr64
movq %rax, %rbx
jmp .L73
.L86:
endbr64
movq %rax, %rbx
jmp .L83
.L84:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4165:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4165:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4165-.LLSDACSB4165
.LLSDACSB4165:
.uleb128 .LEHB0-.LFB4165
.uleb128 .LEHE0-.LEHB0
.uleb128 .L86-.LFB4165
.uleb128 0
.uleb128 .LEHB1-.LFB4165
.uleb128 .LEHE1-.LEHB1
.uleb128 .L90-.LFB4165
.uleb128 0
.uleb128 .LEHB2-.LFB4165
.uleb128 .LEHE2-.LEHB2
.uleb128 .L87-.LFB4165
.uleb128 0
.uleb128 .LEHB3-.LFB4165
.uleb128 .LEHE3-.LEHB3
.uleb128 .L88-.LFB4165
.uleb128 0
.uleb128 .LEHB4-.LFB4165
.uleb128 .LEHE4-.LEHB4
.uleb128 .L89-.LFB4165
.uleb128 0
.uleb128 .LEHB5-.LFB4165
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE4165:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
cudaDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
cudaMalloc((void**)&d_arr, arr.size() * sizeof(int));
cudaMalloc((void**)&d_out, sizeof(int));
cudaMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
cudaMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//run reduce operation
cudaEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
cudaEventRecord(stop, 0);
//wait for it to finish
cudaDeviceSynchronize();
//store answer on host
int ans;
cudaMemcpy(&ans, d_out, sizeof(int), cudaMemcpyDeviceToHost);
//find time
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
cudaFree(d_arr);
cudaFree(d_intermediate);
cudaFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
cudaMalloc((void**)&d_arrb, arr.size() * sizeof(int));
cudaMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
cudaMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), cudaMemcpyHostToDevice);
//cuda events
cudaEvent_t b1, b2;
cudaEventCreate(&b1);
cudaEventCreate(&b2);
//run parity
cudaEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
cudaEventRecord(b2, 0);
//calc time
float b_time;
cudaEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
cudaMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), cudaMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
cudaFree(d_arrb);
cudaFree(d_outb);
free(ans_arr);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
hipDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
hipMalloc((void**)&d_arr, arr.size() * sizeof(int));
hipMalloc((void**)&d_out, sizeof(int));
hipMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
hipMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//run reduce operation
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
hipEventRecord(stop, 0);
//wait for it to finish
hipDeviceSynchronize();
//store answer on host
int ans;
hipMemcpy(&ans, d_out, sizeof(int), hipMemcpyDeviceToHost);
//find time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
hipFree(d_arr);
hipFree(d_intermediate);
hipFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
hipMalloc((void**)&d_arrb, arr.size() * sizeof(int));
hipMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
hipMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//cuda events
hipEvent_t b1, b2;
hipEventCreate(&b1);
hipEventCreate(&b2);
//run parity
hipEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
hipEventRecord(b2, 0);
//calc time
float b_time;
hipEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
hipMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), hipMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
hipFree(d_arrb);
hipFree(d_outb);
free(ans_arr);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
hipDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
hipMalloc((void**)&d_arr, arr.size() * sizeof(int));
hipMalloc((void**)&d_out, sizeof(int));
hipMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
hipMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//run reduce operation
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
hipEventRecord(stop, 0);
//wait for it to finish
hipDeviceSynchronize();
//store answer on host
int ans;
hipMemcpy(&ans, d_out, sizeof(int), hipMemcpyDeviceToHost);
//find time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
hipFree(d_arr);
hipFree(d_intermediate);
hipFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
hipMalloc((void**)&d_arrb, arr.size() * sizeof(int));
hipMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
hipMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//cuda events
hipEvent_t b1, b2;
hipEventCreate(&b1);
hipEventCreate(&b2);
//run parity
hipEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
hipEventRecord(b2, 0);
//calc time
float b_time;
hipEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
hipMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), hipMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
hipFree(d_arrb);
hipFree(d_outb);
free(ans_arr);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_cmp_lt_u32 s5, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_load_b32 s8, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v6, 0
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshr_b32 s9, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s9, v1
v_cmp_gt_u32_e64 s2, s9, v0
v_cmp_gt_u32_e64 s3, s8, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s6, v7
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
s_clause 0x1
global_load_b32 v5, v[3:4], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_reduce_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_reduce_kernelPiS_i, .Lfunc_end0-_Z20global_reduce_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13global_parityPiS_i
.globl _Z13global_parityPiS_i
.p2align 8
.type _Z13global_parityPiS_i,@function
_Z13global_parityPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_cmp_le_i32_e64 s0, s10, v1
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_mul_hi_i32 v4, v0, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 2, v4
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v4, 10
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_sub_nc_u32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13global_parityPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13global_parityPiS_i, .Lfunc_end1-_Z13global_parityPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_reduce_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_reduce_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13global_parityPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13global_parityPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
// do reduction in global mem
for (unsigned int cap = blockDim.x / 2; cap > 0; cap >>= 1)
{
//only compute if on lower portion of block
if (tid < cap)
{
//if thread out of range or threads comp out of range, do nothing
if(myId >= size || myId + cap >=size){
//do nothing
}
else{
// store minimum only between two valid elements in lower portion
d_in[myId] = min(d_in[myId], d_in[myId + cap]);
}
}
//wait for all threads to complete
__syncthreads();
}
// only thread 0 writes result for this block back to global mem
if (tid == 0)
{
d_out[blockIdx.x] = d_in[myId];
}
}
void reduce(int* d_out, int* d_intermediate, int* d_in, int size)
{
/*int threads_num, numProcs;
cudaDeviceGetAttribute(&threads_num, cudaDevAttrMaxThreadsPerMultiProcessor, 0);
printf("max threads per mp: %d\n", threads_num);
cudaDeviceGetAttribute(&numProcs,cudaDevAttrMultiProcessorCount, 0);
printf("mp count: %d\n", numProcs);*/
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock)+1;
global_reduce_kernel<<<blocks, threads >>>(d_intermediate, d_in, size);
// now we're down to one block left, so reduce it
threads = blocks; // launch one thread for each block in prev step
blocks = 1;
// set threads to multiple of two greater than or equal to size
int mult = 1;
while (mult < threads) mult *= 2;
//launch kernel with multiple of 2 threads, and size equal to number of valid entries
global_reduce_kernel<<<blocks, mult >>>(d_out, d_intermediate, threads);
}
__global__ void global_parity(int* d_out, int* d_in, int size) {
//indices
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
//idiomatic code from nvidia help
for (int i = index; i < size; i += stride) {
d_out[i] = d_in[i] % 10;
}
}
void parity(int* d_out, int* d_in, int size) {
const int maxThreadsPerBlock = 512;
int threads = maxThreadsPerBlock;
//ceiling of blocks required
int blocks = (size / maxThreadsPerBlock) + 1;
//run kernel
global_parity <<<blocks, threads>>> (d_out, d_in, size);
//wait for all threads to synch
hipDeviceSynchronize();
}
int main() {
vector<int> arr;
string line;
ifstream myfile("inp.txt");
if (myfile.is_open())
{
//gets next int
while (getline(myfile, line, ','))
{
arr.push_back(stoi(line, nullptr));
}
myfile.close();
}
else cout << "Unable to open file";
//timing stuff
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//allocated device memory
int *d_arr, *d_out, *d_intermediate;
hipMalloc((void**)&d_arr, arr.size() * sizeof(int));
hipMalloc((void**)&d_out, sizeof(int));
hipMalloc((void**)&d_intermediate, arr.size() * sizeof(int));
// treat pointer to start of vector as array pointer
hipMemcpy(d_arr, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//run reduce operation
hipEventRecord(start, 0);
reduce(d_out, d_intermediate, d_arr, arr.size());
hipEventRecord(stop, 0);
//wait for it to finish
hipDeviceSynchronize();
//store answer on host
int ans;
hipMemcpy(&ans, d_out, sizeof(int), hipMemcpyDeviceToHost);
//find time
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
//output to file
ofstream outfile("q1a.txt");
if (outfile.is_open())
{
outfile << ans;
outfile.close();
}
//else cout << "Unable to open file";
//print stuff
//cout << "minimum entry found: " << ans << endl;
//cout << "elapsted reduce time: " << elapsedTime << endl;
//free device memory
hipFree(d_arr);
hipFree(d_intermediate);
hipFree(d_out);
//////////////////////////////////***PARITY CODE***///////////////////////////////////////
//allocate device memory
int* d_arrb, * d_outb;
hipMalloc((void**)&d_arrb, arr.size() * sizeof(int));
hipMalloc((void**)&d_outb, arr.size() * sizeof(int));
//copy array A to device Memory
hipMemcpy(d_arrb, &arr[0], arr.size() * sizeof(int), hipMemcpyHostToDevice);
//cuda events
hipEvent_t b1, b2;
hipEventCreate(&b1);
hipEventCreate(&b2);
//run parity
hipEventRecord(b1, 0);
parity(d_outb, d_arrb, arr.size());
hipEventRecord(b2, 0);
//calc time
float b_time;
hipEventElapsedTime(&b_time, b1, b2);
//store answer on host
int* ans_arr = (int*)malloc(sizeof(int) * arr.size());
hipMemcpy(ans_arr, d_outb, sizeof(int) * arr.size(), hipMemcpyDeviceToHost);
//validate
/*for (int i = 0; i < arr.size(); i++) {
assert(arr[i] % 10 == ans_arr[i]);
}*/
//output to file
ofstream outfile2("q1b.txt");
if (outfile2.is_open())
{
//avoid comma at end of string
outfile2 << ans_arr[0];
for (int i = 1; i < arr.size(); i++) {
outfile2 << "," << ans_arr[i];
}
outfile2.close();
}
//else cout << "Unable to open file";
//time taken output
//cout << "Parity time taken: " << b_time << endl;
hipFree(d_arrb);
hipFree(d_outb);
free(ans_arr);
return 0;
} | .text
.file "q1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__global_reduce_kernelPiS_i # -- Begin function _Z35__device_stub__global_reduce_kernelPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__global_reduce_kernelPiS_i,@function
_Z35__device_stub__global_reduce_kernelPiS_i: # @_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__global_reduce_kernelPiS_i, .Lfunc_end0-_Z35__device_stub__global_reduce_kernelPiS_i
.cfi_endproc
# -- End function
.globl _Z6reducePiS_S_i # -- Begin function _Z6reducePiS_S_i
.p2align 4, 0x90
.type _Z6reducePiS_S_i,@function
_Z6reducePiS_S_i: # @_Z6reducePiS_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movq %rdx, %r13
movq %rsi, 72(%rsp) # 8-byte Spill
movq %rdi, 112(%rsp) # 8-byte Spill
movabsq $4294967296, %r15 # imm = 0x100000000
leal 511(%r12), %r14d
testl %ecx, %ecx
cmovnsl %ecx, %r14d
sarl $9, %r14d
leal 1(%r14), %ebp
leaq (%r15,%rbp), %rdi
leaq 512(%r15), %rdx
movl $1, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 72(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq %r13, 56(%rsp)
movl %r12d, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
leal (%rax,%rax), %ebx
cmpl %r14d, %eax
jle .LBB1_2
# %bb.3:
movl %eax, %edx
orq %r15, %rdx
incq %r15
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 112(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq 72(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movl %ebp, 4(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20global_reduce_kernelPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6reducePiS_S_i, .Lfunc_end1-_Z6reducePiS_S_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__global_parityPiS_i # -- Begin function _Z28__device_stub__global_parityPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__global_parityPiS_i,@function
_Z28__device_stub__global_parityPiS_i: # @_Z28__device_stub__global_parityPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13global_parityPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__global_parityPiS_i, .Lfunc_end2-_Z28__device_stub__global_parityPiS_i
.cfi_endproc
# -- End function
.globl _Z6parityPiS_i # -- Begin function _Z6parityPiS_i
.p2align 4, 0x90
.type _Z6parityPiS_i,@function
_Z6parityPiS_i: # @_Z6parityPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 511(%rbx), %edi
testl %edx, %edx
cmovnsl %edx, %edi
sarl $9, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13global_parityPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z6parityPiS_i, .Lfunc_end3-_Z6parityPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1728
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 104(%rsp), %r13
movq %r13, 88(%rsp)
movq $0, 96(%rsp)
movb $0, 104(%rsp)
.Ltmp0:
leaq 640(%rsp), %rdi
movl $.L.str, %esi
movl $8, %edx
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1:
leaq 760(%rsp), %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB4_42
# %bb.2: # %.preheader88.preheader
xorl %r14d, %r14d
movabsq $2305843009213693951, %r12 # imm = 0x1FFFFFFFFFFFFFFF
xorl %r13d, %r13d
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_17: # in Loop: Header=BB4_3 Depth=1
movl %eax, (%r14)
addq $4, %r14
.LBB4_3: # %.preheader88
# =>This Inner Loop Header: Depth=1
.Ltmp5:
leaq 640(%rsp), %rdi
leaq 88(%rsp), %rsi
movl $44, %edx
callq _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_
.Ltmp6:
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB4_39
# %bb.5: # in Loop: Header=BB4_3 Depth=1
movq 88(%rsp), %rbx
callq __errno_location
movq %rax, %rbp
movl (%rax), %r15d
movl $0, (%rax)
movq %rbx, %rdi
leaq 128(%rsp), %rsi
movl $10, %edx
callq __isoc23_strtol
cmpq %rbx, 128(%rsp)
je .LBB4_6
# %bb.10: # in Loop: Header=BB4_3 Depth=1
movslq %eax, %rcx
cmpq %rax, %rcx
jne .LBB4_12
# %bb.11: # in Loop: Header=BB4_3 Depth=1
movl (%rbp), %ecx
cmpl $34, %ecx
je .LBB4_12
# %bb.14: # in Loop: Header=BB4_3 Depth=1
testl %ecx, %ecx
je .LBB4_15
# %bb.16: # %_ZNSt7__cxx114stoiERKNS_12basic_stringIcSt11char_traitsIcESaIcEEEPmi.exit
# in Loop: Header=BB4_3 Depth=1
cmpq %r13, %r14
jne .LBB4_17
jmp .LBB4_18
.p2align 4, 0x90
.LBB4_15: # in Loop: Header=BB4_3 Depth=1
movl %r15d, (%rbp)
cmpq %r13, %r14
jne .LBB4_17
.LBB4_18: # in Loop: Header=BB4_3 Depth=1
movq (%rsp), %r13 # 8-byte Reload
subq %r13, %r14
movabsq $9223372036854775804, %rcx # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rcx, %r14
je .LBB4_19
# %bb.21: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
movq %r12, %rbx
movq %r14, %r15
sarq $2, %r15
cmpq $1, %r15
movq %r15, %rcx
adcq $0, %rcx
leaq (%rcx,%r15), %rdx
cmpq %r12, %rdx
jae .LBB4_22
# %bb.23: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
addq %r15, %rcx
jae .LBB4_24
.LBB4_25: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
testq %rbx, %rbx
je .LBB4_26
.LBB4_27: # in Loop: Header=BB4_3 Depth=1
movq %rax, %r13
leaq (,%rbx,4), %rdi
.Ltmp100:
callq _Znwm
.Ltmp101:
# %bb.28: # in Loop: Header=BB4_3 Depth=1
movq %rax, %rbp
movq %r13, %rax
movq (%rsp), %r13 # 8-byte Reload
jmp .LBB4_29
.LBB4_22: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
movq %rbx, %rdx
addq %r15, %rcx
jb .LBB4_25
.LBB4_24: # %_ZNKSt6vectorIiSaIiEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
movq %rdx, %rbx
testq %rbx, %rbx
jne .LBB4_27
.LBB4_26: # in Loop: Header=BB4_3 Depth=1
xorl %ebp, %ebp
.LBB4_29: # %_ZNSt12_Vector_baseIiSaIiEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
movl %eax, (%rbp,%r15,4)
testq %r14, %r14
jle .LBB4_31
# %bb.30: # in Loop: Header=BB4_3 Depth=1
movq %rbp, %rdi
movq %r13, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB4_31: # %_ZNSt6vectorIiSaIiEE11_S_relocateEPiS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB4_3 Depth=1
testq %r13, %r13
je .LBB4_33
# %bb.32: # in Loop: Header=BB4_3 Depth=1
movq %r13, %rdi
callq _ZdlPv
.LBB4_33: # %_ZNSt6vectorIiSaIiEE17_M_realloc_insertIJiEEEvN9__gnu_cxx17__normal_iteratorIPiS1_EEDpOT_.exit.i.i
# in Loop: Header=BB4_3 Depth=1
addq %rbp, %r14
leaq (,%rbx,4), %r13
addq %rbp, %r13
addq $4, %r14
movq %rbp, (%rsp) # 8-byte Spill
jmp .LBB4_3
.LBB4_42:
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
.Ltmp3:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
xorl %r14d, %r14d
jmp .LBB4_43
.LBB4_39:
leaq 656(%rsp), %rdi
.Ltmp8:
leaq 104(%rsp), %r13
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp9:
# %bb.40: # %.noexc42
testq %rax, %rax
jne .LBB4_43
# %bb.41:
movq 640(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $640, %rdi # imm = 0x280
movl 672(%rsp,%rax), %esi
orl $4, %esi
.Ltmp10:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp11:
.LBB4_43: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp13:
leaq 80(%rsp), %rdi
callq hipEventCreate
.Ltmp14:
# %bb.44:
.Ltmp15:
leaq 72(%rsp), %rdi
callq hipEventCreate
.Ltmp16:
# %bb.45:
subq (%rsp), %r14 # 8-byte Folded Reload
.Ltmp18:
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp19:
# %bb.46:
.Ltmp20:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
.Ltmp21:
# %bb.47:
.Ltmp22:
leaq 64(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp23:
# %bb.48:
movq 32(%rsp), %rdi
.Ltmp24:
movq (%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp25:
# %bb.49:
movq 80(%rsp), %rdi
.Ltmp26:
xorl %esi, %esi
callq hipEventRecord
.Ltmp27:
# %bb.50:
movq %r14, %r15
sarq $2, %r15
movq 24(%rsp), %rdi
movq 64(%rsp), %rsi
movq 32(%rsp), %rdx
.Ltmp28:
movl %r15d, %ecx
callq _Z6reducePiS_S_i
.Ltmp29:
# %bb.51:
movq 72(%rsp), %rdi
.Ltmp30:
xorl %esi, %esi
callq hipEventRecord
.Ltmp31:
# %bb.52:
.Ltmp32:
callq hipDeviceSynchronize
.Ltmp33:
# %bb.53:
movq 24(%rsp), %rsi
.Ltmp35:
leaq 44(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.54:
movq 80(%rsp), %rsi
movq 72(%rsp), %rdx
.Ltmp38:
leaq 124(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp39:
# %bb.55:
.Ltmp41:
leaq 128(%rsp), %rdi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp42:
# %bb.56:
leaq 240(%rsp), %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB4_61
# %bb.57:
movl 44(%rsp), %esi
.Ltmp44:
leaq 128(%rsp), %rdi
callq _ZNSolsEi
.Ltmp45:
# %bb.58:
leaq 136(%rsp), %rdi
.Ltmp46:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp47:
# %bb.59: # %.noexc46
testq %rax, %rax
jne .LBB4_61
# %bb.60:
movq 128(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $128, %rdi
movl 160(%rsp,%rax), %esi
orl $4, %esi
.Ltmp48:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp49:
.LBB4_61: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
movq 32(%rsp), %rdi
.Ltmp50:
callq hipFree
.Ltmp51:
# %bb.62:
movq 64(%rsp), %rdi
.Ltmp52:
callq hipFree
.Ltmp53:
# %bb.63:
movq 24(%rsp), %rdi
.Ltmp54:
callq hipFree
.Ltmp55:
# %bb.64:
.Ltmp57:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp58:
# %bb.65:
.Ltmp59:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
.Ltmp60:
# %bb.66:
movq 16(%rsp), %rdi
.Ltmp61:
movq (%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp62:
# %bb.67:
.Ltmp64:
leaq 56(%rsp), %rdi
callq hipEventCreate
.Ltmp65:
# %bb.68:
.Ltmp66:
leaq 48(%rsp), %rdi
callq hipEventCreate
.Ltmp67:
# %bb.69:
movq 56(%rsp), %rdi
.Ltmp68:
xorl %esi, %esi
callq hipEventRecord
.Ltmp69:
# %bb.70:
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp70:
movl %r15d, %edx
callq _Z6parityPiS_i
.Ltmp71:
# %bb.71:
movq 48(%rsp), %rdi
.Ltmp72:
xorl %esi, %esi
callq hipEventRecord
.Ltmp73:
# %bb.72:
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
.Ltmp75:
leaq 120(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp76:
# %bb.73:
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq 8(%rsp), %rsi
.Ltmp78:
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp79:
# %bb.74:
.Ltmp81:
leaq 1160(%rsp), %rdi
movl $.L.str.3, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp82:
# %bb.75:
leaq 1272(%rsp), %rdi
callq _ZNKSt12__basic_fileIcE7is_openEv
testb %al, %al
je .LBB4_85
# %bb.76:
movl (%r12), %esi
.Ltmp84:
leaq 1160(%rsp), %rdi
callq _ZNSolsEi
.Ltmp85:
# %bb.77: # %.preheader
cmpq $2, %r15
jb .LBB4_82
# %bb.78: # %.lr.ph.preheader
movl $1, %ebx
leaq 1160(%rsp), %r14
.p2align 4, 0x90
.LBB4_79: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.Ltmp86:
movl $.L.str.4, %esi
movl $1, %edx
movq %r14, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp87:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
# in Loop: Header=BB4_79 Depth=1
movl (%r12,%rbx,4), %esi
.Ltmp88:
movq %r14, %rdi
callq _ZNSolsEi
.Ltmp89:
# %bb.81: # in Loop: Header=BB4_79 Depth=1
incq %rbx
cmpq %rbx, %r15
jne .LBB4_79
.LBB4_82: # %._crit_edge
leaq 1168(%rsp), %rdi
.Ltmp91:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp92:
# %bb.83: # %.noexc49
testq %rax, %rax
jne .LBB4_85
# %bb.84:
movq 1160(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $1160, %rdi # imm = 0x488
movl 1192(%rsp,%rax), %esi
orl $4, %esi
.Ltmp93:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp94:
.LBB4_85: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit51
movq 16(%rsp), %rdi
.Ltmp95:
callq hipFree
.Ltmp96:
# %bb.86:
movq 8(%rsp), %rdi
.Ltmp97:
callq hipFree
.Ltmp98:
# %bb.87:
movq %r12, %rdi
callq free
leaq 1160(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq 88(%rsp), %rdi
cmpq %r13, %rdi
je .LBB4_89
# %bb.88: # %.critedge.i.i54
callq _ZdlPv
.LBB4_89: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq (%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB4_91
# %bb.90:
callq _ZdlPv
.LBB4_91: # %_ZNSt6vectorIiSaIiEED2Ev.exit
xorl %eax, %eax
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_6:
.cfi_def_cfa_offset 1728
.Ltmp108:
movl $.L.str.6, %edi
callq _ZSt24__throw_invalid_argumentPKc
.Ltmp109:
# %bb.7:
.LBB4_12: # %.critedge.i.i
.Ltmp106:
movl $.L.str.6, %edi
callq _ZSt20__throw_out_of_rangePKc
.Ltmp107:
# %bb.13:
.LBB4_19:
.Ltmp103:
movl $.L.str.5, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp104:
# %bb.20: # %.noexc
.LBB4_102:
.Ltmp83:
movq %rax, %r14
jmp .LBB4_106
.LBB4_101:
.Ltmp80:
movq %rax, %r14
jmp .LBB4_106
.LBB4_100:
.Ltmp77:
movq %rax, %r14
jmp .LBB4_106
.LBB4_96:
.Ltmp43:
movq %rax, %r14
jmp .LBB4_107
.LBB4_95:
.Ltmp40:
movq %rax, %r14
jmp .LBB4_107
.LBB4_94:
.Ltmp37:
movq %rax, %r14
jmp .LBB4_107
.LBB4_34:
.Ltmp2:
movq %rax, %r14
xorl %eax, %eax
movq %rax, (%rsp) # 8-byte Spill
jmp .LBB4_108
.LBB4_36: # %.loopexit.split-lp
.Ltmp12:
movq %rax, %r14
jmp .LBB4_107
.LBB4_92:
.Ltmp17:
movq %rax, %r14
jmp .LBB4_107
.LBB4_98:
.Ltmp63:
movq %rax, %r14
jmp .LBB4_106
.LBB4_104:
.Ltmp99:
jmp .LBB4_105
.LBB4_37: # %.loopexit89
.Ltmp102:
movq %rax, %r14
jmp .LBB4_107
.LBB4_97:
.Ltmp56:
movq %rax, %r14
jmp .LBB4_106
.LBB4_99:
.Ltmp74:
movq %rax, %r14
jmp .LBB4_106
.LBB4_38: # %.loopexit.split-lp90
.Ltmp105:
movq %rax, %r14
jmp .LBB4_107
.LBB4_93:
.Ltmp34:
movq %rax, %r14
jmp .LBB4_107
.LBB4_103:
.Ltmp90:
.LBB4_105:
movq %rax, %r14
leaq 1160(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.LBB4_106:
leaq 128(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
jmp .LBB4_107
.LBB4_35: # %.loopexit
.Ltmp7:
movq %rax, %r14
jmp .LBB4_107
.LBB4_8:
.Ltmp110:
movq %rax, %r14
cmpl $0, (%rbp)
jne .LBB4_107
# %bb.9:
movl %r15d, (%rbp)
.LBB4_107: # %.body
leaq 640(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 896(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
.LBB4_108:
movq 88(%rsp), %rdi
leaq 104(%rsp), %rax
cmpq %rax, %rdi
je .LBB4_110
# %bb.109: # %.critedge.i.i55
callq _ZdlPv
.LBB4_110: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit57
movq (%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB4_112
# %bb.111:
callq _ZdlPv
.LBB4_112: # %_ZNSt6vectorIiSaIiEED2Ev.exit59
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table4:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp100-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp101-.Ltmp100 # Call between .Ltmp100 and .Ltmp101
.uleb128 .Ltmp102-.Lfunc_begin0 # jumps to .Ltmp102
.byte 0 # On action: cleanup
.uleb128 .Ltmp101-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp3-.Ltmp101 # Call between .Ltmp101 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp11-.Ltmp3 # Call between .Ltmp3 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp16-.Ltmp13 # Call between .Ltmp13 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp33-.Ltmp18 # Call between .Ltmp18 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp36-.Ltmp35 # Call between .Ltmp35 and .Ltmp36
.uleb128 .Ltmp37-.Lfunc_begin0 # jumps to .Ltmp37
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin0 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp44-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp55-.Ltmp44 # Call between .Ltmp44 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp62-.Ltmp57 # Call between .Ltmp57 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin0 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp73-.Ltmp64 # Call between .Ltmp64 and .Ltmp73
.uleb128 .Ltmp74-.Lfunc_begin0 # jumps to .Ltmp74
.byte 0 # On action: cleanup
.uleb128 .Ltmp75-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp76-.Ltmp75 # Call between .Ltmp75 and .Ltmp76
.uleb128 .Ltmp77-.Lfunc_begin0 # jumps to .Ltmp77
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp79-.Ltmp78 # Call between .Ltmp78 and .Ltmp79
.uleb128 .Ltmp80-.Lfunc_begin0 # jumps to .Ltmp80
.byte 0 # On action: cleanup
.uleb128 .Ltmp81-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp82-.Ltmp81 # Call between .Ltmp81 and .Ltmp82
.uleb128 .Ltmp83-.Lfunc_begin0 # jumps to .Ltmp83
.byte 0 # On action: cleanup
.uleb128 .Ltmp84-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp85-.Ltmp84 # Call between .Ltmp84 and .Ltmp85
.uleb128 .Ltmp99-.Lfunc_begin0 # jumps to .Ltmp99
.byte 0 # On action: cleanup
.uleb128 .Ltmp86-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp89-.Ltmp86 # Call between .Ltmp86 and .Ltmp89
.uleb128 .Ltmp90-.Lfunc_begin0 # jumps to .Ltmp90
.byte 0 # On action: cleanup
.uleb128 .Ltmp91-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp98-.Ltmp91 # Call between .Ltmp91 and .Ltmp98
.uleb128 .Ltmp99-.Lfunc_begin0 # jumps to .Ltmp99
.byte 0 # On action: cleanup
.uleb128 .Ltmp108-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp107-.Ltmp108 # Call between .Ltmp108 and .Ltmp107
.uleb128 .Ltmp110-.Lfunc_begin0 # jumps to .Ltmp110
.byte 0 # On action: cleanup
.uleb128 .Ltmp103-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp104-.Ltmp103 # Call between .Ltmp103 and .Ltmp104
.uleb128 .Ltmp105-.Lfunc_begin0 # jumps to .Ltmp105
.byte 0 # On action: cleanup
.uleb128 .Ltmp104-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Lfunc_end4-.Ltmp104 # Call between .Ltmp104 and .Lfunc_end4
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20global_reduce_kernelPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13global_parityPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20global_reduce_kernelPiS_i,@object # @_Z20global_reduce_kernelPiS_i
.section .rodata,"a",@progbits
.globl _Z20global_reduce_kernelPiS_i
.p2align 3, 0x0
_Z20global_reduce_kernelPiS_i:
.quad _Z35__device_stub__global_reduce_kernelPiS_i
.size _Z20global_reduce_kernelPiS_i, 8
.type _Z13global_parityPiS_i,@object # @_Z13global_parityPiS_i
.globl _Z13global_parityPiS_i
.p2align 3, 0x0
_Z13global_parityPiS_i:
.quad _Z28__device_stub__global_parityPiS_i
.size _Z13global_parityPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "inp.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Unable to open file"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "q1a.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "q1b.txt"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz ","
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "vector::_M_realloc_insert"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "stoi"
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20global_reduce_kernelPiS_i"
.size .L__unnamed_1, 30
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13global_parityPiS_i"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__global_reduce_kernelPiS_i
.addrsig_sym _Z28__device_stub__global_parityPiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z20global_reduce_kernelPiS_i
.addrsig_sym _Z13global_parityPiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13global_parityPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R9, RZ, RZ, -R0 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a00 */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x0000000107070824 */
/* 0x000fe200078e0a00 */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fd200078e0004 */
/*0250*/ IMAD.WIDE R4, R3, R6, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0206 */
/*0260*/ IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fca00078e0206 */
/*0270*/ LDG.E R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0000a2000c1e1900 */
/*0280*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0290*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02c0*/ IMAD.HI R9, R8, 0x66666667, RZ ; /* 0x6666666708097827 */
/* 0x004fca00078e02ff */
/*02d0*/ SHF.R.U32.HI R10, RZ, 0x1f, R9 ; /* 0x0000001fff0a7819 */
/* 0x000fc80000011609 */
/*02e0*/ LEA.HI.SX32 R9, R9, R10, 0x1e ; /* 0x0000000a09097211 */
/* 0x000fca00078ff2ff */
/*02f0*/ IMAD R9, R9, -0xa, R8 ; /* 0xfffffff609097824 */
/* 0x000fca00078e0208 */
/*0300*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x270 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0360*/ IMAD.WIDE R4, R3, R8, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x001fca00078e0208 */
/*0370*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD.HI R6, R2, 0x66666667, RZ ; /* 0x6666666702067827 */
/* 0x004fca00078e02ff */
/*0390*/ SHF.R.U32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fc80000011606 */
/*03a0*/ LEA.HI.SX32 R9, R6, R7, 0x1e ; /* 0x0000000706097211 */
/* 0x000fe200078ff2ff */
/*03b0*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*03c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*03d0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R8.64] ; /* 0x0000000408027981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0410*/ IMAD.HI R10, R2, 0x66666667, RZ ; /* 0x66666667020a7827 */
/* 0x004fca00078e02ff */
/*0420*/ SHF.R.U32.HI R11, RZ, 0x1f, R10 ; /* 0x0000001fff0b7819 */
/* 0x000fc8000001160a */
/*0430*/ LEA.HI.SX32 R11, R10, R11, 0x1e ; /* 0x0000000b0a0b7211 */
/* 0x000fca00078ff2ff */
/*0440*/ IMAD R15, R11, -0xa, R2 ; /* 0xfffffff60b0f7824 */
/* 0x000fe400078e0202 */
/*0450*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*0460*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0003e8000c101904 */
/*0470*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea4000c1e1900 */
/*0480*/ IMAD.HI R12, R2, 0x66666667, RZ ; /* 0x66666667020c7827 */
/* 0x004fca00078e02ff */
/*0490*/ SHF.R.U32.HI R7, RZ, 0x1f, R12 ; /* 0x0000001fff077819 */
/* 0x001fc8000001160c */
/*04a0*/ LEA.HI.SX32 R9, R12, R7, 0x1e ; /* 0x000000070c097211 */
/* 0x000fe200078ff2ff */
/*04b0*/ IMAD.WIDE R6, R0, 0x4, R4 ; /* 0x0000000400067825 */
/* 0x000fc800078e0204 */
/*04c0*/ IMAD R13, R9, -0xa, R2 ; /* 0xfffffff6090d7824 */
/* 0x000fe400078e0202 */
/*04d0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x000fc600078e020a */
/*04e0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ IMAD.HI R2, R8, 0x66666667, RZ ; /* 0x6666666708027827 */
/* 0x004fca00078e02ff */
/*0540*/ SHF.R.U32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x002fc80000011602 */
/*0550*/ LEA.HI.SX32 R11, R2, R5, 0x1e ; /* 0x00000005020b7211 */
/* 0x000fe200078ff2ff */
/*0560*/ IMAD.WIDE R4, R0, 0x4, R6 ; /* 0x0000000400047825 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD R11, R11, -0xa, R8 ; /* 0xfffffff60b0b7824 */
/* 0x000fca00078e0208 */
/*0580*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e2000c101904 */
/*0590*/ @!P0 BRA 0x350 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20global_reduce_kernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0040*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0050*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0070*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0080*/ IMAD R0, R8, c[0x0][0x0], R9 ; /* 0x0000000008007a24 */
/* 0x001fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fd000078e0203 */
/*00a0*/ @!P0 BRA 0x1d0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R9, UR4, PT ; /* 0x0000000409007c0c */
/* 0x000fe2000bf06070 */
/*00c0*/ BSSY B0, 0x190 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*00d0*/ @P0 BRA 0x180 ; /* 0x000000a000000947 */
/* 0x001fea0003800000 */
/*00e0*/ IADD3 R4, R0, UR4, RZ ; /* 0x0000000400047c10 */
/* 0x000fc8000fffe0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fc80003f06070 */
/*0100*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0110*/ @P0 BRA 0x180 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea6000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0005 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea4000c1e1900 */
/*0160*/ IMNMX R7, R6, R5, PT ; /* 0x0000000506077217 */
/* 0x004fca0003800200 */
/*0170*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fea0000010000 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @P0 BRA 0xb0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01d0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x001ea2000c1e1900 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x160] ; /* 0x0000580008047625 */
/* 0x000fca00078e0005 */
/*0220*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_cmp_lt_u32 s5, 2
v_ashrrev_i32_e32 v2, 31, v1
s_cbranch_scc1 .LBB0_5
s_load_b32 s8, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v6, 0
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lt_u32 s5, 4
s_mov_b32 s5, s9
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_lshr_b32 s9, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, s9, v1
v_cmp_gt_u32_e64 s2, s9, v0
v_cmp_gt_u32_e64 s3, s8, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s6, v7
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
s_clause 0x1
global_load_b32 v5, v[3:4], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v5, v5, v7
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b64 s[2:3], s[4:5], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20global_reduce_kernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20global_reduce_kernelPiS_i, .Lfunc_end0-_Z20global_reduce_kernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13global_parityPiS_i
.globl _Z13global_parityPiS_i
.p2align 8
.type _Z13global_parityPiS_i,@function
_Z13global_parityPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s10, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s2, v1
global_load_b32 v0, v[4:5], off
v_cmp_le_i32_e64 s0, s10, v1
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_mul_hi_i32 v4, v0, 0x66666667
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 2, v4
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v6, v4, 10
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_sub_nc_u32_e32 v0, v0, v6
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13global_parityPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13global_parityPiS_i, .Lfunc_end1-_Z13global_parityPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20global_reduce_kernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20global_reduce_kernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13global_parityPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13global_parityPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .file "tmpxft_000a4f72_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
.type _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_, @function
_Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4nmfhPdiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_, .-_Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
.globl _Z4nmfhPdiiiS_S_S_
.type _Z4nmfhPdiiiS_S_S_, @function
_Z4nmfhPdiiiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4nmfhPdiiiS_S_S_, .-_Z4nmfhPdiiiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4nmfhPdiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4nmfhPdiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4nmfhPdiiiS_S_S_
.globl _Z4nmfhPdiiiS_S_S_
.p2align 8
.type _Z4nmfhPdiiiS_S_S_,@function
_Z4nmfhPdiiiS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0xc
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
s_clause 0x1
s_load_b32 s10, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[6:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v0
v_mov_b32_e32 v6, v1
s_mov_b32 s8, s10
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s8, 0
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 3, v[6:7]
v_add_nc_u32_e32 v6, s4, v6
v_add_nc_u32_e32 v4, s5, v4
v_add_co_u32 v7, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v[9:10], off
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[7:8], v[9:10], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[6:7], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s4, v[1:2]
s_cmp_lt_i32 s5, 1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b64 v[8:9], v[6:7], off
s_cbranch_scc1 .LBB0_11
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_gt_i32 s10, 0
s_mov_b32 s9, 0
s_cselect_b32 s11, -1, 0
s_mov_b32 s12, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s5
s_cbranch_scc1 .LBB0_12
.LBB0_8:
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[10:11], null, s12, s4, v[1:2]
s_mov_b32 s13, 0
s_mov_b32 s14, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b64 v[10:11], v[10:11], off
.p2align 6
.LBB0_10:
v_add_nc_u32_e32 v12, s13, v0
s_add_i32 s8, s12, s13
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[8:9], 3
s_add_u32 s16, s2, s16
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
s_addc_u32 s17, s3, s17
s_add_i32 s14, s14, -1
s_add_i32 s13, s13, s5
s_cmp_eq_u32 s14, 0
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_load_b64 s[16:17], s[16:17], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_load_b64 v[12:13], v[12:13], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[12:13], v[12:13], s[16:17]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[6:7], v[12:13], v[10:11], v[6:7]
s_cbranch_scc0 .LBB0_10
s_branch .LBB0_7
.LBB0_11:
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_waitcnt vmcnt(0)
v_mul_f64 v[0:1], v[2:3], v[8:9]
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_div_scale_f64 v[2:3], null, v[6:7], v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[2:3], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[2:3], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[0:1], v[6:7], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[2:3], -v[2:3], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[8:9], v[12:13]
v_div_fixup_f64 v[0:1], v[2:3], v[6:7], v[0:1]
v_lshlrev_b64 v[2:3], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4nmfhPdiiiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4nmfhPdiiiS_S_S_, .Lfunc_end0-_Z4nmfhPdiiiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4nmfhPdiiiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z4nmfhPdiiiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.0;
for (int i = 0; i < r; i++)
sum += w[i*k + row]*a[i*c+col];
temp = h[row*c+col]*sum;
//w'wh
sum = 0.0;
for (int i = 0; i < k; i++)
for (int j = 0; j < r; j++)
sum += w[j*k + row]*w[j*k + i]*h[i*c+col];
__syncthreads();
hcp[row*c+col] = temp/sum;
}
} | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPdiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPdiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPdiiiS_S_S_,@function
_Z19__device_stub__nmfhPdiiiS_S_S_: # @_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4nmfhPdiiiS_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__nmfhPdiiiS_S_S_, .Lfunc_end0-_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4nmfhPdiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4nmfhPdiiiS_S_S_,@object # @_Z4nmfhPdiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z4nmfhPdiiiS_S_S_
.p2align 3, 0x0
_Z4nmfhPdiiiS_S_S_:
.quad _Z19__device_stub__nmfhPdiiiS_S_S_
.size _Z4nmfhPdiiiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4nmfhPdiiiS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__nmfhPdiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4nmfhPdiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4f72_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
.type _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_, @function
_Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4nmfhPdiiiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_, .-_Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
.globl _Z4nmfhPdiiiS_S_S_
.type _Z4nmfhPdiiiS_S_S_, @function
_Z4nmfhPdiiiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z4nmfhPdiiiS_S_S_PdiiiS_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4nmfhPdiiiS_S_S_, .-_Z4nmfhPdiiiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4nmfhPdiiiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4nmfhPdiiiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPdiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPdiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPdiiiS_S_S_,@function
_Z19__device_stub__nmfhPdiiiS_S_S_: # @_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4nmfhPdiiiS_S_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z19__device_stub__nmfhPdiiiS_S_S_, .Lfunc_end0-_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4nmfhPdiiiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4nmfhPdiiiS_S_S_,@object # @_Z4nmfhPdiiiS_S_S_
.section .rodata,"a",@progbits
.globl _Z4nmfhPdiiiS_S_S_
.p2align 3, 0x0
_Z4nmfhPdiiiS_S_S_:
.quad _Z19__device_stub__nmfhPdiiiS_S_S_
.size _Z4nmfhPdiiiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4nmfhPdiiiS_S_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__nmfhPdiiiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4nmfhPdiiiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
cudaMallocManaged (&a, size);
cudaMallocManaged (&b, size);
cudaMallocManaged (&c_cpu, size);
cudaMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
cudaEvent_t start, end;
// Cria os eventos
cudaEventCreate(&start);
cudaEventCreate(&end);
// Registra o primeiro evento
cudaEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
cudaEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
cudaDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
cudaEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
cudaFree(a);
cudaFree(b);
cudaFree( c_cpu );
cudaFree( c_gpu );
} | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x2f3, PT ; /* 0x000002f30000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GT.OR P0, PT, R6, 0x2f3, P0 ; /* 0x000002f30600780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R6, R6, 0x2f4, RZ ; /* 0x000002f406067824 */
/* 0x000fe200078e02ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fe200078e0207 */
/*00f0*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R15, [R4.64+0xbd0] ; /* 0x000bd004040f7981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R17, [R4.64+0x17a0] ; /* 0x0017a00404117981 */
/* 0x000128000c1e1900 */
/*0140*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000328000c1e1900 */
/*0150*/ LDG.E R19, [R4.64+0x2370] ; /* 0x0023700404137981 */
/* 0x000168000c1e1900 */
/*0160*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000368000c1e1900 */
/*0170*/ LDG.E R21, [R4.64+0x2f40] ; /* 0x002f400404157981 */
/* 0x000168000c1e1900 */
/*0180*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000368000c1e1900 */
/*0190*/ LDG.E R23, [R4.64+0x3b10] ; /* 0x003b100404177981 */
/* 0x000168000c1e1900 */
/*01a0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000368000c1e1900 */
/*01b0*/ LDG.E R10, [R4.64+0x46e0] ; /* 0x0046e004040a7981 */
/* 0x000168000c1e1900 */
/*01c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000368000c1e1900 */
/*01d0*/ LDG.E R8, [R4.64+0x52b0] ; /* 0x0052b00404087981 */
/* 0x000168000c1e1900 */
/*01e0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x000362000c1e1900 */
/*01f0*/ IMAD R12, R12, R13, RZ ; /* 0x0000000d0c0c7224 */
/* 0x004fc800078e02ff */
/*0200*/ IMAD R12, R15, R14, R12 ; /* 0x0000000e0f0c7224 */
/* 0x008fe200078e020c */
/*0210*/ IADD3 R15, P0, R4, 0x5e80, RZ ; /* 0x00005e80040f7810 */
/* 0x000fe40007f1e0ff */
/*0220*/ IADD3 R14, P1, R2, 0x28, RZ ; /* 0x00000028020e7810 */
/* 0x000fe40007f3e0ff */
/*0230*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x001fe400007fe4ff */
/*0240*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe20000ffe4ff */
/*0250*/ IMAD R12, R17, R16, R12 ; /* 0x00000010110c7224 */
/* 0x010fc800078e020c */
/*0260*/ IMAD R12, R19, R18, R12 ; /* 0x00000012130c7224 */
/* 0x020fc800078e020c */
/*0270*/ IMAD R12, R21, R20, R12 ; /* 0x00000014150c7224 */
/* 0x000fc800078e020c */
/*0280*/ IMAD R12, R23, R22, R12 ; /* 0x00000016170c7224 */
/* 0x000fc800078e020c */
/*0290*/ IMAD R10, R10, R11, R12 ; /* 0x0000000b0a0a7224 */
/* 0x000fc800078e020c */
/*02a0*/ IMAD R13, R8, R9, R10 ; /* 0x00000009080d7224 */
/* 0x000fe200078e020a */
/*02b0*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0a7435 */
/* 0x000fe400000001ff */
/*02c0*/ MOV R4, R15 ; /* 0x0000000f00047202 */
/* 0x000fe40000000f00 */
/*02d0*/ MOV R2, R14 ; /* 0x0000000e00027202 */
/* 0x000fc60000000f00 */
/*02e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R19, [R2.64+-0x8] ; /* 0xfffff80402137981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R20, [R4.64+0xbd0] ; /* 0x000bd00404147981 */
/* 0x000ee8000c1e1900 */
/*0310*/ LDG.E R25, [R2.64+-0x4] ; /* 0xfffffc0402197981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R23, [R4.64+0x17a0] ; /* 0x0017a00404177981 */
/* 0x000f28000c1e1900 */
/*0330*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000f28000c1e1900 */
/*0340*/ LDG.E R22, [R4.64+0x2370] ; /* 0x0023700404167981 */
/* 0x000f68000c1e1900 */
/*0350*/ LDG.E R21, [R2.64+0x4] ; /* 0x0000040402157981 */
/* 0x000f68000c1e1900 */
/*0360*/ LDG.E R17, [R4.64+0x2f40] ; /* 0x002f400404117981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000f68000c1e1900 */
/*0380*/ LDG.E R8, [R4.64+0x3b10] ; /* 0x003b100404087981 */
/* 0x000f68000c1e1900 */
/*0390*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0402097981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R11, [R4.64+0x46e0] ; /* 0x0046e004040b7981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000f68000c1e1900 */
/*03c0*/ LDG.E R15, [R4.64+0x52b0] ; /* 0x0052b004040f7981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R16, [R2.64+0x14] ; /* 0x0000140402107981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R19, R14, R19, R13 ; /* 0x000000130e137224 */
/* 0x004fc600078e020d */
/*03f0*/ LDG.E R13, [R4.64+0x5e80] ; /* 0x005e8004040d7981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD R25, R20, R25, R19 ; /* 0x0000001914197224 */
/* 0x008fc600078e0213 */
/*0420*/ LDG.E R19, [R4.64+0x6a50] ; /* 0x006a500404137981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000ee2000c1e1900 */
/*0440*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*0450*/ LDG.E R23, [R4.64+0x7620] ; /* 0x0076200404177981 */
/* 0x000f28000c1e1900 */
/*0460*/ LDG.E R24, [R2.64+0x20] ; /* 0x0000200402187981 */
/* 0x000f22000c1e1900 */
/*0470*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0480*/ LDG.E R21, [R4.64+0x81f0] ; /* 0x0081f00404157981 */
/* 0x000f68000c1e1900 */
/*0490*/ LDG.E R22, [R2.64+0x24] ; /* 0x0000240402167981 */
/* 0x000f62000c1e1900 */
/*04a0*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*04b0*/ LDG.E R17, [R4.64+0x8dc0] ; /* 0x008dc00404117981 */
/* 0x000f68000c1e1900 */
/*04c0*/ LDG.E R18, [R2.64+0x28] ; /* 0x0000280402127981 */
/* 0x000f62000c1e1900 */
/*04d0*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*04e0*/ LDG.E R8, [R4.64+0x9990] ; /* 0x0099900404087981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R9, [R2.64+0x2c] ; /* 0x00002c0402097981 */
/* 0x000f62000c1e1900 */
/*0500*/ IMAD R25, R11, R12, R25 ; /* 0x0000000c0b197224 */
/* 0x000fc600078e0219 */
/*0510*/ LDG.E R11, [R4.64+0xa560] ; /* 0x00a56004040b7981 */
/* 0x000f68000c1e1900 */
/*0520*/ LDG.E R12, [R2.64+0x30] ; /* 0x00003004020c7981 */
/* 0x000f62000c1e1900 */
/*0530*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*0540*/ LDG.E R15, [R4.64+0xb130] ; /* 0x00b13004040f7981 */
/* 0x000f68000c1e1900 */
/*0550*/ LDG.E R16, [R2.64+0x34] ; /* 0x0000340402107981 */
/* 0x000f62000c1e1900 */
/*0560*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*0570*/ LDG.E R13, [R4.64+0xbd00] ; /* 0x00bd0004040d7981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*05a0*/ LDG.E R19, [R4.64+0xc8d0] ; /* 0x00c8d00404137981 */
/* 0x000ee8000c1e1900 */
/*05b0*/ LDG.E R20, [R2.64+0x3c] ; /* 0x00003c0402147981 */
/* 0x000ee2000c1e1900 */
/*05c0*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*05d0*/ LDG.E R23, [R4.64+0xd4a0] ; /* 0x00d4a00404177981 */
/* 0x000f28000c1e1900 */
/*05e0*/ LDG.E R24, [R2.64+0x40] ; /* 0x0000400402187981 */
/* 0x000f22000c1e1900 */
/*05f0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0600*/ LDG.E R21, [R4.64+0xe070] ; /* 0x00e0700404157981 */
/* 0x000f68000c1e1900 */
/*0610*/ LDG.E R22, [R2.64+0x44] ; /* 0x0000440402167981 */
/* 0x000f62000c1e1900 */
/*0620*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*0630*/ LDG.E R17, [R4.64+0xec40] ; /* 0x00ec400404117981 */
/* 0x000f68000c1e1900 */
/*0640*/ LDG.E R18, [R2.64+0x48] ; /* 0x0000480402127981 */
/* 0x000f62000c1e1900 */
/*0650*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*0660*/ LDG.E R8, [R4.64+0xf810] ; /* 0x00f8100404087981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R9, [R2.64+0x4c] ; /* 0x00004c0402097981 */
/* 0x000f62000c1e1900 */
/*0680*/ IMAD R25, R11, R12, R25 ; /* 0x0000000c0b197224 */
/* 0x000fc600078e0219 */
/*0690*/ LDG.E R12, [R4.64+0x103e0] ; /* 0x0103e004040c7981 */
/* 0x000f68000c1e1900 */
/*06a0*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000f62000c1e1900 */
/*06b0*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*06c0*/ LDG.E R15, [R4.64+0x10fb0] ; /* 0x010fb004040f7981 */
/* 0x000f68000c1e1900 */
/*06d0*/ LDG.E R16, [R2.64+0x54] ; /* 0x0000540402107981 */
/* 0x000f62000c1e1900 */
/*06e0*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*06f0*/ LDG.E R13, [R4.64+0x11b80] ; /* 0x011b8004040d7981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R14, [R2.64+0x58] ; /* 0x00005804020e7981 */
/* 0x000ea2000c1e1900 */
/*0710*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*0720*/ LDG.E R19, [R4.64+0x12750] ; /* 0x0127500404137981 */
/* 0x000ee8000c1e1900 */
/*0730*/ LDG.E R20, [R2.64+0x5c] ; /* 0x00005c0402147981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*0750*/ LDG.E R23, [R4.64+0x13320] ; /* 0x0133200404177981 */
/* 0x000f28000c1e1900 */
/*0760*/ LDG.E R24, [R2.64+0x60] ; /* 0x0000600402187981 */
/* 0x000f22000c1e1900 */
/*0770*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0780*/ LDG.E R21, [R4.64+0x13ef0] ; /* 0x013ef00404157981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R22, [R2.64+0x64] ; /* 0x0000640402167981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD R25, R17, R18, R25 ; /* 0x0000001211197224 */
/* 0x000fc600078e0219 */
/*07b0*/ LDG.E R18, [R4.64+0x14ac0] ; /* 0x014ac00404127981 */
/* 0x000f68000c1e1900 */
/*07c0*/ LDG.E R17, [R2.64+0x68] ; /* 0x0000680402117981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*07e0*/ LDG.E R8, [R4.64+0x15690] ; /* 0x0156900404087981 */
/* 0x000f68000c1e1900 */
/*07f0*/ LDG.E R9, [R2.64+0x6c] ; /* 0x00006c0402097981 */
/* 0x000f62000c1e1900 */
/*0800*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0810*/ LDG.E R12, [R4.64+0x16260] ; /* 0x01626004040c7981 */
/* 0x000f68000c1e1900 */
/*0820*/ LDG.E R11, [R2.64+0x70] ; /* 0x00007004020b7981 */
/* 0x000f62000c1e1900 */
/*0830*/ IMAD R25, R15, R16, R25 ; /* 0x000000100f197224 */
/* 0x000fc600078e0219 */
/*0840*/ LDG.E R16, [R4.64+0x16e30] ; /* 0x016e300404107981 */
/* 0x000f68000c1e1900 */
/*0850*/ LDG.E R15, [R2.64+0x74] ; /* 0x00007404020f7981 */
/* 0x000f62000c1e1900 */
/*0860*/ IMAD R25, R13, R14, R25 ; /* 0x0000000e0d197224 */
/* 0x004fc600078e0219 */
/*0870*/ LDG.E R14, [R4.64+0x17a00] ; /* 0x017a0004040e7981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R13, [R2.64+0x78] ; /* 0x00007804020d7981 */
/* 0x000ea2000c1e1900 */
/*0890*/ IMAD R25, R19, R20, R25 ; /* 0x0000001413197224 */
/* 0x008fc600078e0219 */
/*08a0*/ LDG.E R20, [R4.64+0x185d0] ; /* 0x0185d00404147981 */
/* 0x000ee8000c1e1900 */
/*08b0*/ LDG.E R19, [R2.64+0x7c] ; /* 0x00007c0402137981 */
/* 0x000ee2000c1e1900 */
/*08c0*/ IMAD R25, R23, R24, R25 ; /* 0x0000001817197224 */
/* 0x010fc600078e0219 */
/*08d0*/ LDG.E R24, [R4.64+0x191a0] ; /* 0x0191a00404187981 */
/* 0x000f28000c1e1900 */
/*08e0*/ LDG.E R23, [R2.64+0x80] ; /* 0x0000800402177981 */
/* 0x000f22000c1e1900 */
/*08f0*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0900*/ LDG.E R21, [R4.64+0x19d70] ; /* 0x019d700404157981 */
/* 0x000f68000c1e1900 */
/*0910*/ LDG.E R22, [R2.64+0x84] ; /* 0x0000840402167981 */
/* 0x000f62000c1e1900 */
/*0920*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x000fc600078e0219 */
/*0930*/ LDG.E R18, [R4.64+0x1a940] ; /* 0x01a9400404127981 */
/* 0x000f68000c1e1900 */
/*0940*/ LDG.E R17, [R2.64+0x88] ; /* 0x0000880402117981 */
/* 0x000f62000c1e1900 */
/*0950*/ IMAD R25, R8, R9, R25 ; /* 0x0000000908197224 */
/* 0x000fc600078e0219 */
/*0960*/ LDG.E R8, [R4.64+0x1b510] ; /* 0x01b5100404087981 */
/* 0x000f68000c1e1900 */
/*0970*/ LDG.E R9, [R2.64+0x8c] ; /* 0x00008c0402097981 */
/* 0x000f62000c1e1900 */
/*0980*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0990*/ LDG.E R11, [R4.64+0x1c0e0] ; /* 0x01c0e004040b7981 */
/* 0x000f68000c1e1900 */
/*09a0*/ LDG.E R12, [R2.64+0x90] ; /* 0x00009004020c7981 */
/* 0x000f62000c1e1900 */
/*09b0*/ IMAD R25, R16, R15, R25 ; /* 0x0000000f10197224 */
/* 0x000fc600078e0219 */
/*09c0*/ LDG.E R15, [R4.64+0x1ccb0] ; /* 0x01ccb004040f7981 */
/* 0x000f68000c1e1900 */
/*09d0*/ LDG.E R16, [R2.64+0x94] ; /* 0x0000940402107981 */
/* 0x000f62000c1e1900 */
/*09e0*/ IMAD R25, R14, R13, R25 ; /* 0x0000000d0e197224 */
/* 0x004fc600078e0219 */
/*09f0*/ LDG.E R13, [R4.64+0x1d880] ; /* 0x01d88004040d7981 */
/* 0x0000a8000c1e1900 */
/*0a00*/ LDG.E R14, [R2.64+0x98] ; /* 0x00009804020e7981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x008fc600078e0219 */
/*0a20*/ LDG.E R19, [R4.64+0x1e450] ; /* 0x01e4500404137981 */
/* 0x0000e8000c1e1900 */
/*0a30*/ LDG.E R20, [R2.64+0x9c] ; /* 0x00009c0402147981 */
/* 0x0002e2000c1e1900 */
/*0a40*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x010fc600078e0219 */
/*0a50*/ LDG.E R24, [R4.64+0x1f020] ; /* 0x01f0200404187981 */
/* 0x000128000c1e1900 */
/*0a60*/ LDG.E R23, [R2.64+0xa0] ; /* 0x0000a00402177981 */
/* 0x000322000c1e1900 */
/*0a70*/ IMAD R25, R21, R22, R25 ; /* 0x0000001615197224 */
/* 0x020fc600078e0219 */
/*0a80*/ LDG.E R21, [R4.64+0x1fbf0] ; /* 0x01fbf00404157981 */
/* 0x000168000c1e1900 */
/*0a90*/ LDG.E R22, [R2.64+0xa4] ; /* 0x0000a40402167981 */
/* 0x000362000c1e1900 */
/*0aa0*/ IADD3 R10, R10, 0x2c, RZ ; /* 0x0000002c0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ IMAD R17, R18, R17, R25 ; /* 0x0000001112117224 */
/* 0x000fc600078e0219 */
/*0ac0*/ ISETP.NE.AND P0, PT, R10, 0x2f4, PT ; /* 0x000002f40a00780c */
/* 0x000fe20003f05270 */
/*0ad0*/ IMAD R8, R8, R9, R17 ; /* 0x0000000908087224 */
/* 0x000fc800078e0211 */
/*0ae0*/ IMAD R8, R11, R12, R8 ; /* 0x0000000c0b087224 */
/* 0x000fc800078e0208 */
/*0af0*/ IMAD R8, R15, R16, R8 ; /* 0x000000100f087224 */
/* 0x000fe200078e0208 */
/*0b00*/ IADD3 R15, P1, R4, 0x207c0, RZ ; /* 0x000207c0040f7810 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x001fe20000ffe4ff */
/*0b20*/ IMAD R13, R13, R14, R8 ; /* 0x0000000e0d0d7224 */
/* 0x004fe200078e0208 */
/*0b30*/ IADD3 R14, P2, R2, 0xb0, RZ ; /* 0x000000b0020e7810 */
/* 0x000fc80007f5e0ff */
/*0b40*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x002fe200017fe4ff */
/*0b50*/ IMAD R13, R19, R20, R13 ; /* 0x00000014130d7224 */
/* 0x008fc800078e020d */
/*0b60*/ IMAD R13, R24, R23, R13 ; /* 0x00000017180d7224 */
/* 0x010fc800078e020d */
/*0b70*/ IMAD R13, R21, R22, R13 ; /* 0x00000016150d7224 */
/* 0x020fe200078e020d */
/*0b80*/ @P0 BRA 0x2c0 ; /* 0xfffff73000000947 */
/* 0x000fea000383ffff */
/*0b90*/ IADD3 R2, R0, R6, RZ ; /* 0x0000000600027210 */
/* 0x000fca0007ffe0ff */
/*0ba0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0bb0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
cudaMallocManaged (&a, size);
cudaMallocManaged (&b, size);
cudaMallocManaged (&c_cpu, size);
cudaMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
cudaEvent_t start, end;
// Cria os eventos
cudaEventCreate(&start);
cudaEventCreate(&end);
// Registra o primeiro evento
cudaEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
cudaEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
cudaDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
cudaEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
cudaFree(a);
cudaFree(b);
cudaFree( c_cpu );
cudaFree( c_gpu );
} | .file "tmpxft_0012ccca_00000000-6_exemplo3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12matrixMulCPUPiS_S_
.type _Z12matrixMulCPUPiS_S_, @function
_Z12matrixMulCPUPiS_S_:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %rbx
movl $0, %r11d
.L4:
leaq 2286144(%rbp), %rdi
imulq $3024, %r11, %r9
leaq (%r12,%r9), %r10
addq %rbx, %r9
movl $0, %r8d
.L8:
leaq -2286144(%rdi), %rax
movq %r10, %rcx
movl $0, %esi
.L5:
movl (%rcx), %edx
imull (%rax), %edx
addl %edx, %esi
addq $4, %rcx
addq $3024, %rax
cmpq %rdi, %rax
jne .L5
movl %esi, (%r9,%r8,4)
addq $1, %r8
addq $4, %rdi
cmpq $756, %r8
jne .L8
addq $1, %r11
cmpq $756, %r11
jne .L4
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z12matrixMulCPUPiS_S_, .-_Z12matrixMulCPUPiS_S_
.globl _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.type _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, @function
_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_, .-_Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
.globl _Z12matrixMulGPUPiS_S_
.type _Z12matrixMulGPUPiS_S_, @function
_Z12matrixMulGPUPiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z12matrixMulGPUPiS_S_, .-_Z12matrixMulGPUPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Tempo de processamento na GPU igual a "
.align 8
.LC1:
.string " msec (aproximadamente 0.01108 segundos)"
.align 8
.LC3:
.string "Tempo de processamento na CPU igual a "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string " sec"
.LC5:
.string "FOUND ERROR at c[%d][%d]\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Successo! As duas matrizes s\303\243o iguais, sendo executadas na CPU e na GPU!\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 48(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
leaq 56(%rsp), %rdi
movl $1, %edx
movl $2286144, %esi
call cudaMallocManaged@PLT
movl $3024, %edi
movl $0, %esi
.L20:
leaq -3024(%rdi), %rax
movl $2, %edx
.L21:
movq 32(%rsp), %rcx
movl %esi, (%rcx,%rax)
movq 40(%rsp), %rcx
movl %edx, (%rcx,%rax)
movq 48(%rsp), %rcx
movl $0, (%rcx,%rax)
movq 56(%rsp), %rcx
movl $0, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq %rdi, %rax
jne .L21
addl $1, %esi
addq $3024, %rdi
cmpl $756, %esi
jne .L20
movl $1, 88(%rsp)
movl $48, 92(%rsp)
movl $48, 96(%rsp)
movl $1, 100(%rsp)
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 80(%rsp)
movl $16, 84(%rsp)
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L23:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call clock@PLT
movq %rax, %rbp
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z12matrixMulCPUPiS_S_
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rcx
movq 56(%rsp), %rdx
movl $0, %esi
jmp .L24
.L34:
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z36__device_stub__Z12matrixMulGPUPiS_S_PiS_S_
jmp .L23
.L36:
movl %eax, %ecx
movl %esi, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
addl $1, %esi
addq $3024, %rcx
addq $3024, %rdx
cmpl $756, %esi
je .L28
.L24:
movl $0, %eax
.L27:
movl (%rdx,%rax,4), %ebx
cmpl %ebx, (%rcx,%rax,4)
jne .L36
addq $1, %rax
cmpq $756, %rax
jne .L27
jmp .L37
.L28:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z12matrixMulGPUPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z12matrixMulGPUPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
cudaMallocManaged (&a, size);
cudaMallocManaged (&b, size);
cudaMallocManaged (&c_cpu, size);
cudaMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
cudaEvent_t start, end;
// Cria os eventos
cudaEventCreate(&start);
cudaEventCreate(&end);
// Registra o primeiro evento
cudaEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
cudaEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
cudaDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
cudaEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
cudaFree(a);
cudaFree(b);
cudaFree( c_cpu );
cudaFree( c_gpu );
} | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
hipMallocManaged (&a, size);
hipMallocManaged (&b, size);
hipMallocManaged (&c_cpu, size);
hipMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
hipEvent_t start, end;
// Cria os eventos
hipEventCreate(&start);
hipEventCreate(&end);
// Registra o primeiro evento
hipEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
hipEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
hipDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
hipEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
hipFree(a);
hipFree(b);
hipFree( c_cpu );
hipFree( c_gpu );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col < N)
{
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
void matrixMulCPU( int * a, int * b, int * c )
{
int val = 0;
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
val = 0;
for ( int k = 0; k < N; ++k )
val += a[row * N + k] * b[k * N + col];
c[row * N + col] = val;
}
}
int main()
{
int *a, *b, *c_cpu, *c_gpu;
// Número de bytes de uma matriz N x N
int size = N * N * sizeof (int);
// Aloca memória
hipMallocManaged (&a, size);
hipMallocManaged (&b, size);
hipMallocManaged (&c_cpu, size);
hipMallocManaged (&c_gpu, size);
// Inicializa memória
for( int row = 0; row < N; ++row )
for( int col = 0; col < N; ++col )
{
a[row * N + col] = row;
b[row * N + col] = col+2;
c_cpu[row * N + col] = 0;
c_gpu[row * N + col] = 0;
}
// Bloco de threads 16 x 16
dim3 threads_per_block (16, 16, 1);
dim3 number_of_blocks ((N / threads_per_block.x) + 1, (N / threads_per_block.y) + 1, 1);
// Define 2 eventos CUDA
hipEvent_t start, end;
// Cria os eventos
hipEventCreate(&start);
hipEventCreate(&end);
// Registra o primeiro evento
hipEventRecord(start);
// Chamada ao kernel
matrixMulGPU <<< number_of_blocks, threads_per_block >>> ( a, b, c_gpu );
// Registra o segundo evento
hipEventRecord(end);
// Aguarda a GPU finalizar seu trabalho
hipDeviceSynchronize();
// Calcula o tempo usado no processamento
float elapsed;
hipEventElapsedTime(&elapsed, start, end);
cout << "Tempo de processamento na GPU igual a " << elapsed << " msec (aproximadamente 0.01108 segundos)" << endl;
clock_t start1, end1;
double cpu_time_used;
start1 = clock();
// Chama a versão para CPU para checar nosso trabalho
matrixMulCPU( a, b, c_cpu );
// Calcula o tempo usado no processamento
end1 = clock();
cpu_time_used = ((double) (end1 - start1)) / CLOCKS_PER_SEC;
cout << "Tempo de processamento na CPU igual a " << cpu_time_used << " sec" << endl;
// Compara as duas respostas para garantir que elas sejam iguais
bool error = false;
for( int row = 0; row < N && !error; ++row )
for( int col = 0; col < N && !error; ++col )
if (c_cpu[row * N + col] != c_gpu[row * N + col])
{
printf("FOUND ERROR at c[%d][%d]\n", row, col);
error = true;
break;
}
if (!error)
printf("Successo! As duas matrizes são iguais, sendo executadas na CPU e na GPU!\n");
// Libera a memória
hipFree(a);
hipFree(b);
hipFree( c_cpu );
hipFree( c_gpu );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2f4, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, 0x2f4
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v5, vcc_lo, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x2f4, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0xbd0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v9, v3, v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v4, v5
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, 0x2f4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12matrixMulGPUPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12matrixMulGPUPiS_S_, .Lfunc_end0-_Z12matrixMulGPUPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12matrixMulGPUPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12matrixMulGPUPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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