system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <curand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matrix
* tpd and thetas : a M * K matrix
*... | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matr... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
/**
* Some kernel functions for LDA
*
* @author Lin Chi-Min (v381654729@gmail.com)
*/
/**
* wpt[k][v] : words per topic
* wt[k] : total words per topic
* tpd[m][k] : topics per document
* td[m] : total topics per document
*
* wpt and phis : a K * V matr... | .text
.file "CudaLDAFunctions.hip"
.globl __device_stub__drawLatentVariables # -- Begin function __device_stub__drawLatentVariables
.p2align 4, 0x90
.type __device_stub__drawLatentVariables,@function
__device_stub__drawLatentVariables: # @__device_stub__drawLatentVariables
.cfi_startproc
# %bb.0:
subq $216, %rsp
.c... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d5749_00000000-6_CudaLDAFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2243:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "CudaLDAFunctions.hip"
.globl __device_stub__drawLatentVariables # -- Begin function __device_stub__drawLatentVariables
.p2align 4, 0x90
.type __device_stub__drawLatentVariables,@function
__device_stub__drawLatentVariables: # @__device_stub__drawLatentVariables
.cfi_startproc
# %bb.0:
subq $216, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf... | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf... | .file "tmpxft_001b1d6d_00000000-6_Exercise_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf... | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);... | .text
.file "Exercise_2.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_de... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b1d6d_00000000-6_Exercise_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "Exercise_2.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) -... | .file "tmpxft_001638b3_00000000-6_nlmSharedKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FILTER_RADIUS (((FILTER_SIZE) -... | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FI... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FI... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9nlmSimpleiPKdPdf
.globl _Z9nlmSimpleiPKdPdf
.p2align 8
.type _Z9nlmSimpleiPKdPdf,@function
_Z9nlmSimpleiPKdPdf:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b32_e32 v3... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
// Array access macros
#define INPUT(i,j) input_grid[(j) + (i)*(N)]
#define TEMP(i,j) temp_grid[(j) + (i)*(N)]
#define WINDOW_SIZE (7)
#define NEIGHBOR_SIZE (3)
#define BLOCK_SIZE (512)
#define FILTER_SIZE ((WINDOW_SIZE) + (NEIGHBOR_SIZE) - 1)
#define FI... | .text
.file "nlmSharedKernel.hip"
.globl _Z24__device_stub__nlmSimpleiPKdPdf # -- Begin function _Z24__device_stub__nlmSimpleiPKdPdf
.p2align 4, 0x90
.type _Z24__device_stub__nlmSimpleiPKdPdf,@function
_Z24__device_stub__nlmSimpleiPKdPdf: # @_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_startproc
# %bb.0:
subq $120, %rsp... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001638b3_00000000-6_nlmSharedKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "nlmSharedKernel.hip"
.globl _Z24__device_stub__nlmSimpleiPKdPdf # -- Begin function _Z24__device_stub__nlmSimpleiPKdPdf
.p2align 4, 0x90
.type _Z24__device_stub__nlmSimpleiPKdPdf,@function
_Z24__device_stub__nlmSimpleiPKdPdf: # @_Z24__device_stub__nlmSimpleiPKdPdf
.cfi_startproc
# %bb.0:
subq $120, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;... | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;... | .file "tmpxft_001205af_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
d... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
d... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_w... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
d... | .text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_w... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001205af_00000000-6_matmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "matmul.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | code for sm_80
Function : _Z25BaseNeuronSetFloatPtArrayPfPiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e28000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .file "tmpxft_00191108_00000000-6_BaseNeuronSetFloatPtArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25BaseNeuronSetFloatPtArrayPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 8
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_w... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BaseNeuronSetFloatPtArray(float *arr, int *pos, int n_elem, int step, float val)
{
int array_idx = threadIdx.x + blockIdx.x * blockDim.x;
if (array_idx<n_elem) {
arr[pos[array_idx]*step] = val;
}
} | .text
.file "BaseNeuronSetFloatPtArray.hip"
.globl _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif # -- Begin function _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.p2align 4, 0x90
.type _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif: # @_Z40... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25BaseNeuronSetFloatPtArrayPfPiiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e28000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25BaseNeuronSetFloatPtArrayPfPiiif
.globl _Z25BaseNeuronSetFloatPtArrayPfPiiif
.p2align 8
.type _Z25BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z25BaseNeuronSetFloatPtArrayPfPiiif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_w... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00191108_00000000-6_BaseNeuronSetFloatPtArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@... | .text
.file "BaseNeuronSetFloatPtArray.hip"
.globl _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif # -- Begin function _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif
.p2align 4, 0x90
.type _Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif,@function
_Z40__device_stub__BaseNeuronSetFloatPtArrayPfPiiif: # @_Z40... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*******************************************************************************
*
******************************************************************************/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
*
******************************************************************************/ | .file "tmpxft_000f63fd_00000000-6_CuMain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
*
******************************************************************************/ | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*******************************************************************************
*
******************************************************************************/ | .text
.file "CuMain.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project r... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f63fd_00000000-6_CuMain.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "CuMain.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project r... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... | code for sm_80
Function : _Z14countOddKernelPilS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... | .file "tmpxft_00111175_00000000-6_oddInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countOddKernelPilS_
.globl _Z14countOddKernelPilS_
.p2align 8
.type _Z14countOddKernelPilS_,@function
_Z14countOddKernelPilS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This program finds the count of Odd numbers in an input integer array.
* The program uses shared memory to count the occurence of odd number in each block.
* The shared memory counter is then added using parallel reduction algorithm.
* Bank conflicts are avoided using padding in the shared memory.
* Output of each ... | .text
.file "oddInt.hip"
.globl _Z29__device_stub__countOddKernelPilS_ # -- Begin function _Z29__device_stub__countOddKernelPilS_
.p2align 4, 0x90
.type _Z29__device_stub__countOddKernelPilS_,@function
_Z29__device_stub__countOddKernelPilS_: # @_Z29__device_stub__countOddKernelPilS_
.cfi_startproc
# %bb.0:
subq $104, %... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14countOddKernelPilS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14countOddKernelPilS_
.globl _Z14countOddKernelPilS_
.p2align 8
.type _Z14countOddKernelPilS_,@function
_Z14countOddKernelPilS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111175_00000000-6_oddInt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "oddInt.hip"
.globl _Z29__device_stub__countOddKernelPilS_ # -- Begin function _Z29__device_stub__countOddKernelPilS_
.p2align 4, 0x90
.type _Z29__device_stub__countOddKernelPilS_,@function
_Z29__device_stub__countOddKernelPilS_: # @_Z29__device_stub__countOddKernelPilS_
.cfi_startproc
# %bb.0:
subq $104, %... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel... | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__global__
void colorJPLKernel... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <set>
#include <sstream>
#include <string>
#include <fstream>
#include <iostream>
#include <cstring>
#include <math.h>
#include <thrust/count.h>
#define MAXBLOCKS 1<<30
using namespace std;
//jones plassmann luby algorithm for graphcoloring
__... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14colorJPLKerneliiPiS_S_S_S_
.globl _Z14colorJPLKerneliiPiS_S_S_S_
.p2align 8
.type _Z14colorJPLKerneliiPiS_S_S_S_,@function
_Z14colorJPLKerneliiPiS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea000380... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14colorJPLKerneliiPiS_S_S_S_
.globl _Z14colorJPLKerneliiPiS_S_S_S_
.p2align 8
.type _Z14colorJPLKerneliiPiS_S_S_S_,@function
_Z14colorJPLKerneliiPiS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy... | .file "tmpxft_0007ed2c_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy... | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14gpuYoloLayerV3Pfjjj
.globl _Z14gpuYoloLayerV3Pfjjj
.p2align 8
.type _Z14gpuYoloLayerV3Pfjjj,@function
_Z14gpuYoloLayerV3Pfjjj:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
MIT License
Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved.
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy... | .text
.file "kernels.hip"
.globl _Z29__device_stub__gpuYoloLayerV3Pfjjj # -- Begin function _Z29__device_stub__gpuYoloLayerV3Pfjjj
.p2align 4, 0x90
.type _Z29__device_stub__gpuYoloLayerV3Pfjjj,@function
_Z29__device_stub__gpuYoloLayerV3Pfjjj: # @_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_startproc
# %bb.0:
subq $120, ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007ed2c_00000000-6_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "kernels.hip"
.globl _Z29__device_stub__gpuYoloLayerV3Pfjjj # -- Begin function _Z29__device_stub__gpuYoloLayerV3Pfjjj
.p2align 4, 0x90
.type _Z29__device_stub__gpuYoloLayerV3Pfjjj,@function
_Z29__device_stub__gpuYoloLayerV3Pfjjj: # @_Z29__device_stub__gpuYoloLayerV3Pfjjj
.cfi_startproc
# %bb.0:
subq $120, ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)... | .file "tmpxft_0007272d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;
x = (float *)... | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
#include <stdlib.h>
extern "C" void max_stride(float* src, float*dst, int stride, int src_ldx, int dst_ldx, int step, int size,int batch_size,int num_stride, int *mask);
int main()
{
int i;
float *x;
float *x_gpu;
int *mask;
int *mask_cpu;... | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_d... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007272d_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "test.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_d... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + thread... | code for sm_80
Function : _Z8matrix_tPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000f... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + thread... | .file "tmpxft_0005acf0_00000000-6_matrix_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blockIdx.y * CHUNK_SIZE + thread... | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blo... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blo... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matrix_tPiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.p2align 8
.type _Z8matrix_tPiS_S_S_,@function
_Z8matrix_tPiS_S_S_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
WRITE CUDA KERNEL FOR TRANSPOSE HERE
*/
const int CHUNK_SIZE = 32;
const int CHUNK_ROWS = 8;
__global__ void matrix_t(int* data, int* out, int* rows, int* cols){
__shared__ int chunk[CHUNK_SIZE][CHUNK_SIZE];
int x = blockIdx.x * CHUNK_SIZE + threadIdx.x;
int y = blo... | .text
.file "matrix_t.hip"
.globl _Z23__device_stub__matrix_tPiS_S_S_ # -- Begin function _Z23__device_stub__matrix_tPiS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__matrix_tPiS_S_S_,@function
_Z23__device_stub__matrix_tPiS_S_S_: # @_Z23__device_stub__matrix_tPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_d... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8matrix_tPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000f... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8matrix_tPiS_S_S_
.globl _Z8matrix_tPiS_S_S_
.p2align 8
.type _Z8matrix_tPiS_S_S_,@function
_Z8matrix_tPiS_S_S_:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b64 s[2:3], s[0:1], 0x0
v_bfe_u32 v2, v0, 10, 10
s_lshl_b32 s6, s15... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005acf0_00000000-6_matrix_t.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "matrix_t.hip"
.globl _Z23__device_stub__matrix_tPiS_S_S_ # -- Begin function _Z23__device_stub__matrix_tPiS_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__matrix_tPiS_S_S_,@function
_Z23__device_stub__matrix_tPiS_S_S_: # @_Z23__device_stub__matrix_tPiS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_d... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::... | code for sm_80
Function : _Z3addiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::... | .file "tmpxft_0010de61_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4206:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
int main(){
std::cout << std::... | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdS_
.globl _Z3addiPdS_
.p2align 8
.type _Z3addiPdS_,@function
_Z3addiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <algorithm>
#include <iomanip>
typedef double Real;
__global__
void add(int n, Real* x, Real* y){
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(int i=index; i<n; i+=stride){
y[i] = x[i] + y[i];
}
}
i... | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPdS_ # -- Begin function _Z18__device_stub__addiPdS_
.p2align 4, 0x90
.type ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPdS_
.globl _Z3addiPdS_
.p2align 8
.type _Z3addiPdS_,@function
_Z3addiPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s10, s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_a... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010de61_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4206:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregi... | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPdS_ # -- Begin function _Z18__device_stub__addiPdS_
.p2align 4, 0x90
.type ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_sta... | code for sm_80
Function : _Z7prescanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_sta... | .file "tmpxft_00187c70_00000000-6_m_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{
double d_start, d_end;
d_sta... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 8
.type _Z7prescanPfS_i,@function
_Z7prescanPfS_i:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v1, s15, 2, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define N 8
#define thread_num 4
#define block_num 2
__global__ void prescan(float *g_odata, float *g_idata, int n);
void scanCPU(float *f_out, float *f_in, int i_n);
double myDiffTime(struct timeval &start, struct timeval &end)
{... | .text
.file "m_add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10m... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7prescanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7prescanPfS_i
.globl _Z7prescanPfS_i
.p2align 8
.type _Z7prescanPfS_i,@function
_Z7prescanPfS_i:
s_load_b32 s2, s[0:1], 0x10
v_lshl_add_u32 v1, s15, 2, v0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00187c70_00000000-6_m_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "m_add.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10myDiffTimeR7timevalS0_
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z10myDiffTimeR7timevalS0_
.p2align 4, 0x90
.type _Z10myDiffTimeR7timevalS0_,@function
_Z10m... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != ... | code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != ... | .file "tmpxft_000389b0_00000000-6_stack_overflow_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != ... | #include <stdio.h>
#include <hip/hip_runtime.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// from http://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if... | .text
.file "stack_overflow_atomics.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000389b0_00000000-6_stack_overflow_atomics.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... | .text
.file "stack_overflow_atomics.hip"
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * bl... | code for sm_80
Function : _Z13global_parityPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * bl... | .file "tmpxft_00133b00_00000000-6_q1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4179:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregis... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * bl... | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_w... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <string>
#include <vector>
#include <cassert>
using namespace std;
__global__ void global_reduce_kernel(int* d_out, int* d_in, int size)
{ //indices
int myId = threadIdx.x + blockDim.x * blockIdx.x;
int tid = threadIdx.x;
/... | .text
.file "q1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z35__device_stub__global_reduce_kernelPiS_i # -- Begin function _Z35__device_stub__global_reduce_kernel... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13global_parityPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20global_reduce_kernelPiS_i
.globl _Z20global_reduce_kernelPiS_i
.p2align 8
.type _Z20global_reduce_kernelPiS_i,@function
_Z20global_reduce_kernelPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x8
s_mov_b32 s4, s15
s_w... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.... | .file "tmpxft_000a4f72_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double temp = 0.0;
double sum;
sum = 0.... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double tem... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double tem... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4nmfhPdiiiS_S_S_
.globl _Z4nmfhPdiiiS_S_S_
.p2align 8
.type _Z4nmfhPdiiiS_S_S_,@function
_Z4nmfhPdiiiS_S_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0xc
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff,... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void nmfh(double *a, int r, int c, int k, double *w, double *h, double *hcp)//must be block synchronized!!!
{
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
//compute H
if (row < k && col < c) {
//w'a
double tem... | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPdiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPdiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPdiiiS_S_S_,@function
_Z19__device_stub__nmfhPdiiiS_S_S_: # @_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_o... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4f72_00000000-6_nmfh.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "nmfh.hip"
.globl _Z19__device_stub__nmfhPdiiiS_S_S_ # -- Begin function _Z19__device_stub__nmfhPdiiiS_S_S_
.p2align 4, 0x90
.type _Z19__device_stub__nmfhPdiiiS_S_S_,@function
_Z19__device_stub__nmfhPdiiiS_S_S_: # @_Z19__device_stub__nmfhPdiiiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_o... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.... | code for sm_80
Function : _Z12matrixMulGPUPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.... | .file "tmpxft_0012ccca_00000000-6_exemplo3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.... | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include "hip/hip_runtime.h"
#include <iostream>
#include <time.h>
using namespace std;
#define N 756
// kernel
__global__ void matrixMulGPU( int * a, int * b, int * c )
{
int val = 0;
int row = blockIdx.x * blockDim.x + threadIdx.x;
int col = blockIdx.y * blockDim.y + threadIdx.y;
if (row < N && col... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12matrixMulGPUPiS_S_
.globl _Z12matrixMulGPUPiS_S_
.p2align 8
.type _Z12matrixMulGPUPiS_S_,@function
_Z12matrixMulGPUPiS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s... |
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