system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b59db_00000000-6_vectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
.globl _Z9vectorAddPiS_S_i
.type _Z9vectorAddPiS_S_i, @function
_Z9vectorAddPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9vectorAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vectorAddPiS_S_i, .-_Z9vectorAddPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vectorAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vectorAdd.hip"
.globl _Z24__device_stub__vectorAddPiS_S_i # -- Begin function _Z24__device_stub__vectorAddPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__vectorAddPiS_S_i,@function
_Z24__device_stub__vectorAddPiS_S_i: # @_Z24__device_stub__vectorAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vectorAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__vectorAddPiS_S_i, .Lfunc_end0-_Z24__device_stub__vectorAddPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vectorAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vectorAddPiS_S_i,@object # @_Z9vectorAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9vectorAddPiS_S_i
.p2align 3, 0x0
_Z9vectorAddPiS_S_i:
.quad _Z24__device_stub__vectorAddPiS_S_i
.size _Z9vectorAddPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vectorAddPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vectorAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vectorAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#define CHECK(cmnd) { \
cudaError_t ierr = cmnd; \
if (ierr != cudaSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, cudaGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
cudaDeviceProp dev_prop;
CHECK(cudaSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(cudaMalloc((float **)&d_a, n_byte));
CHECK(cudaMalloc((float **)&d_b, n_byte));
CHECK(cudaMalloc((float **)&d_c, n_byte));
CHECK(cudaMemcpy(d_a, h_a, n_byte, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_b, h_b, n_byte, cudaMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(cudaDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(cudaMemcpy(h_res, d_c, n_byte, cudaMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(cudaFree(d_a)); CHECK(cudaFree(d_b)); CHECK(cudaFree(d_c));
return 0;
} | code for sm_80
Function : _Z13Add_on_devicePKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00d0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00e0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0140*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#define CHECK(cmnd) { \
cudaError_t ierr = cmnd; \
if (ierr != cudaSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, cudaGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
cudaDeviceProp dev_prop;
CHECK(cudaSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(cudaMalloc((float **)&d_a, n_byte));
CHECK(cudaMalloc((float **)&d_b, n_byte));
CHECK(cudaMalloc((float **)&d_c, n_byte));
CHECK(cudaMemcpy(d_a, h_a, n_byte, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_b, h_b, n_byte, cudaMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(cudaDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(cudaMemcpy(h_res, d_c, n_byte, cudaMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(cudaFree(d_a)); CHECK(cudaFree(d_b)); CHECK(cudaFree(d_c));
return 0;
} | .file "tmpxft_0003f2b2_00000000-6_2.5-GPUTiming.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPfi
.type _Z8initDataPfi, @function
_Z8initDataPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L3
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8initDataPfi, .-_Z8initDataPfi
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z11Add_on_hostPKfS0_Pfi
.type _Z11Add_on_hostPKfS0_Pfi, @function
_Z11Add_on_hostPKfS0_Pfi:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L14
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L16:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L16
.L14:
ret
.cfi_endproc
.LFE2059:
.size _Z11Add_on_hostPKfS0_Pfi, .-_Z11Add_on_hostPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error: check_result: diff=%16.12f at k=%d\n"
.align 8
.LC5:
.string "Success: all elements match better than epsilon=%16.12f\n"
.text
.globl _Z12check_resultPKfS0_i
.type _Z12check_resultPKfS0_i, @function
_Z12check_resultPKfS0_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L19
movslq %edx, %rax
movl $0, %edx
movss .LC2(%rip), %xmm2
movsd .LC3(%rip), %xmm1
.L23:
movss (%rdi,%rdx,4), %xmm0
subss (%rsi,%rdx,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L28
addq $1, %rdx
cmpq %rax, %rdx
jne .L23
.L19:
movsd .LC3(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L18:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z12check_resultPKfS0_i, .-_Z12check_resultPKfS0_i
.globl _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Add_on_devicePKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
.globl _Z13Add_on_devicePKfS0_Pfi
.type _Z13Add_on_devicePKfS0_Pfi, @function
_Z13Add_on_devicePKfS0_Pfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13Add_on_devicePKfS0_Pfi, .-_Z13Add_on_devicePKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Info: Starting %s ... \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/moravveji/CUDA-C/master/book-exercises/chapters/02/2.5-GPUTiming.cu"
.section .rodata.str1.1
.LC8:
.string "Error: %s:%d: "
.LC9:
.string "Info: device #%d is: %s\n"
.LC10:
.string "Timing results ..."
.LC11:
.string "\n%s\n"
.LC12:
.string "dt_host: %12.8f (sec)\n"
.LC13:
.string "dt_h2d: %12.8f (sec)\n"
.LC14:
.string "dt_kern: %12.8f (sec)\n"
.LC15:
.string "dt_d2h: %12.8f (sec)\n"
.LC16:
.string "dt_gpu: %12.8f (sec)\n"
.LC17:
.string "dt_host / dt_gpu = %6.2f \n"
.LC18:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $128, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $131072, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
call _Z9cpuSecondv
movsd %xmm0, (%rsp)
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $16777216, %esi
movq %rbp, %rdi
call _Z8initDataPfi
movl $16777216, %esi
movq %rbx, %rdi
call _Z8initDataPfi
movl $67108864, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
movl $67108864, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
movl $16777216, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11Add_on_hostPKfS0_Pfi
call _Z9cpuSecondv
movapd %xmm0, %xmm4
subsd (%rsp), %xmm4
movq %xmm4, %r15
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L52
leaq 80(%rsp), %rcx
movl $0, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, (%rsp)
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L53
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L54
leaq 48(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L55
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L56
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L57
call _Z9cpuSecondv
subsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L44:
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L59
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
call _Z9cpuSecondv
movsd %xmm0, 16(%rsp)
movl $2, %ecx
movl $67108864, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L60
call _Z9cpuSecondv
subsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
movl $16777216, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z12check_resultPKfS0_i
movsd (%rsp), %xmm2
addsd 8(%rsp), %xmm2
movapd %xmm2, %xmm3
addsd 16(%rsp), %xmm3
movsd %xmm3, 24(%rsp)
leaq .LC10(%rip), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %xmm6
divsd 24(%rsp), %xmm6
movapd %xmm6, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $83, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $88, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $89, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $90, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $92, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $93, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L58:
movl $16777216, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
jmp .L44
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $100, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $106, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z13Add_on_devicePKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Add_on_devicePKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -500134854
.long 1044740494
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#define CHECK(cmnd) { \
cudaError_t ierr = cmnd; \
if (ierr != cudaSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, cudaGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
cudaDeviceProp dev_prop;
CHECK(cudaSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(cudaMalloc((float **)&d_a, n_byte));
CHECK(cudaMalloc((float **)&d_b, n_byte));
CHECK(cudaMalloc((float **)&d_c, n_byte));
CHECK(cudaMemcpy(d_a, h_a, n_byte, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(d_b, h_b, n_byte, cudaMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(cudaDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(cudaMemcpy(h_res, d_c, n_byte, cudaMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(cudaFree(d_a)); CHECK(cudaFree(d_b)); CHECK(cudaFree(d_c));
return 0;
} | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define CHECK(cmnd) { \
hipError_t ierr = cmnd; \
if (ierr != hipSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, hipGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
hipDeviceProp_t dev_prop;
CHECK(hipSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(hipMalloc((float **)&d_a, n_byte));
CHECK(hipMalloc((float **)&d_b, n_byte));
CHECK(hipMalloc((float **)&d_c, n_byte));
CHECK(hipMemcpy(d_a, h_a, n_byte, hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_b, h_b, n_byte, hipMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(hipDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(hipMemcpy(h_res, d_c, n_byte, hipMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(hipFree(d_a)); CHECK(hipFree(d_b)); CHECK(hipFree(d_c));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define CHECK(cmnd) { \
hipError_t ierr = cmnd; \
if (ierr != hipSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, hipGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
hipDeviceProp_t dev_prop;
CHECK(hipSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(hipMalloc((float **)&d_a, n_byte));
CHECK(hipMalloc((float **)&d_b, n_byte));
CHECK(hipMalloc((float **)&d_c, n_byte));
CHECK(hipMemcpy(d_a, h_a, n_byte, hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_b, h_b, n_byte, hipMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(hipDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(hipMemcpy(h_res, d_c, n_byte, hipMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(hipFree(d_a)); CHECK(hipFree(d_b)); CHECK(hipFree(d_c));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Add_on_devicePKfS0_Pfi
.globl _Z13Add_on_devicePKfS0_Pfi
.p2align 8
.type _Z13Add_on_devicePKfS0_Pfi,@function
_Z13Add_on_devicePKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Add_on_devicePKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Add_on_devicePKfS0_Pfi, .Lfunc_end0-_Z13Add_on_devicePKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Add_on_devicePKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Add_on_devicePKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define CHECK(cmnd) { \
hipError_t ierr = cmnd; \
if (ierr != hipSuccess) { \
printf("Error: %s:%d: ", __FILE__, __LINE__, hipGetErrorString(ierr)); \
exit(ierr); \
} \
}
void initData(float * arr, const int n) {
time_t t;
srand((unsigned int) time(&t));
for (int k=0; k<n; k++) arr[k] = (float)(rand() & 0xFF) / 10.0;
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)tp.tv_sec + (double)tp.tv_usec*1.0e-6;
}
void Add_on_host(const float * a, const float * b, float * c, const int n) {
for (int k=0; k<n; k++) c[k] = a[k] + b[k];
}
__global__ void Add_on_device(const float * a, const float * b, float * c, const int n) {
size_t k = threadIdx.x + blockIdx.x * blockDim.x;
if (k < n) c[k] = a[k] + b[k];
}
void check_result(const float *a, const float *b, const int n){
const double epsilon = 1.0e-8;
double diff = 0.0;
bool match = 1;
for (int k=0; k<n; k++){
diff = abs(a[k] - b[k]);
if (diff > epsilon){
match = 0;
printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
break;
}
}
if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
}
int main(int argc, char ** argv) {
printf("Info: Starting %s ... \n", argv[0]);
// problem sizes and kernel configs
const int n_elem = 1 << 24;
const size_t n_byte = n_elem * sizeof(float);
const int tpb_x = 128;
dim3 tpb(tpb_x, 1, 1);
dim3 nblocks((n_elem + tpb_x - 1) / tpb_x, 1, 1);
// timing
double t0, dt_host, dt_gpu, dt_h2d, dt_kern, dt_d2h;
// addition on host
t0 = cpuSecond();
float *h_a, *h_b, *h_ref; //, *d_ref;
h_a = (float *)malloc(n_byte);
h_b = (float *)malloc(n_byte);
h_ref = (float *)malloc(n_byte); // reference result from host
// d_ref = (float *)malloc(n_byte); // reference result from device
initData(h_a, n_elem);
initData(h_b, n_elem);
memset(h_a, 0, n_byte);
memset(h_b, 0, n_byte);
Add_on_host(h_a, h_b, h_ref, n_elem);
dt_host = cpuSecond() - t0;
// device addition
const int dev = 0;
hipDeviceProp_t dev_prop;
CHECK(hipSetDevice(dev));
printf("Info: device #%d is: %s\n", dev, dev_prop.name);
t0 = cpuSecond();
float *d_a, *d_b, *d_c;
CHECK(hipMalloc((float **)&d_a, n_byte));
CHECK(hipMalloc((float **)&d_b, n_byte));
CHECK(hipMalloc((float **)&d_c, n_byte));
CHECK(hipMemcpy(d_a, h_a, n_byte, hipMemcpyHostToDevice));
CHECK(hipMemcpy(d_b, h_b, n_byte, hipMemcpyHostToDevice));
dt_h2d = cpuSecond() - t0;
// Kernel launch
t0 = cpuSecond();
Add_on_device<<<nblocks, tpb>>>(d_a, d_b, d_c, n_elem);
CHECK(hipDeviceSynchronize());
dt_kern = cpuSecond() - t0;
float * h_res;
h_res = (float *)malloc(n_byte);
t0 = cpuSecond();
CHECK(hipMemcpy(h_res, d_c, n_byte, hipMemcpyDeviceToHost));
dt_d2h = cpuSecond() - t0;
check_result(h_ref, h_res, n_elem);
// {
// const double epsilon = 1.0e-8;
// double diff = 0.0;
// bool match = 1;
// for (int k=0; k<n_elem; k++){
// diff = abs(h_ref[k] - d_ref[k]);
// if (diff > epsilon){
// match = 0;
// printf("Error: check_result: diff=%16.12f at k=%d\n", diff, k);
// break;
// }
// }
// if (match) printf("Success: all elements match better than epsilon=%16.12f\n", epsilon);
// }
dt_gpu = dt_h2d + dt_kern + dt_d2h;
printf("\n%s\n", "Timing results ...");
printf("dt_host: %12.8f (sec)\n", dt_host);
printf("dt_h2d: %12.8f (sec)\n", dt_h2d);
printf("dt_kern: %12.8f (sec)\n", dt_kern);
printf("dt_d2h: %12.8f (sec)\n", dt_d2h);
printf("dt_gpu: %12.8f (sec)\n", dt_gpu);
printf("dt_host / dt_gpu = %6.2f \n", dt_host / dt_gpu);
printf("\n");
// Free up the memory on host and device
free(h_a); free(h_b); free(h_ref); free(h_res);
CHECK(hipFree(d_a)); CHECK(hipFree(d_b)); CHECK(hipFree(d_c));
return 0;
} | .text
.file "2.5-GPUTiming.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8initDataPfi
.LCPI0_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z8initDataPfi
.p2align 4, 0x90
.type _Z8initDataPfi,@function
_Z8initDataPfi: # @_Z8initDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8initDataPfi, .Lfunc_end0-_Z8initDataPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9cpuSecondv, .Lfunc_end1-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z11Add_on_hostPKfS0_Pfi # -- Begin function _Z11Add_on_hostPKfS0_Pfi
.p2align 4, 0x90
.type _Z11Add_on_hostPKfS0_Pfi,@function
_Z11Add_on_hostPKfS0_Pfi: # @_Z11Add_on_hostPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11Add_on_hostPKfS0_Pfi, .Lfunc_end2-_Z11Add_on_hostPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Add_on_devicePKfS0_Pfi # -- Begin function _Z28__device_stub__Add_on_devicePKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__Add_on_devicePKfS0_Pfi,@function
_Z28__device_stub__Add_on_devicePKfS0_Pfi: # @_Z28__device_stub__Add_on_devicePKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Add_on_devicePKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z28__device_stub__Add_on_devicePKfS0_Pfi, .Lfunc_end3-_Z28__device_stub__Add_on_devicePKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12check_resultPKfS0_i
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z12check_resultPKfS0_i
.p2align 4, 0x90
.type _Z12check_resultPKfS0_i,@function
_Z12check_resultPKfS0_i: # @_Z12check_resultPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %ecx
xorl %eax, %eax
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%rax,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB4_5
# %bb.3: # in Loop: Header=BB4_2 Depth=1
incq %rax
cmpq %rax, %rcx
jne .LBB4_2
.LBB4_4: # %.critedge
movsd .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
jmp printf # TAILCALL
.LBB4_5:
movl $.L.str, %edi
movl %eax, %esi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z12check_resultPKfS0_i, .Lfunc_end4-_Z12check_resultPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI5_1:
.quad 0x4024000000000000 # double 10
.LCPI5_3:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 1776
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
xorl %r12d, %r12d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 248(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 248(%rsp), %r13
cvtsi2sdq 256(%rsp), %xmm0
mulsd .LCPI5_0(%rip), %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
leaq 248(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_1
# %bb.2: # %_Z8initDataPfi.exit
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 248(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i90
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_3
# %bb.4: # %_Z8initDataPfi.exit94
xorl %r12d, %r12d
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i95
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_5
# %bb.6: # %_Z11Add_on_hostPKfS0_Pfi.exit
leaq 248(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 248(%rsp), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 256(%rsp), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_7
# %bb.9:
leaq 248(%rsp), %rdx
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 168(%rsp) # 8-byte Spill
leaq 104(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_10
# %bb.11:
leaq 96(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.13:
leaq 88(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_14
# %bb.15:
movq 104(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_16
# %bb.17:
movq 96(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_18
# %bb.19:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 72(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 130944(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_21
# %bb.20:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl $16777216, 116(%rsp) # imm = 0x1000000
leaq 240(%rsp), %rax
movq %rax, 16(%rsp)
leaq 232(%rsp), %rax
movq %rax, 24(%rsp)
leaq 224(%rsp), %rax
movq %rax, 32(%rsp)
leaq 116(%rsp), %rax
movq %rax, 40(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13Add_on_devicePKfS0_Pfi, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_22
# %bb.23:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %rbp
movq 88(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_24
# %bb.25:
movsd .LCPI5_0(%rip), %xmm3 # xmm3 = mem[0],zero
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI5_0(%rip), %xmm0
addsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movsd 168(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd .LCPI5_0(%rip), %xmm2
addsd 160(%rsp), %xmm2 # 8-byte Folded Reload
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm3, %xmm1
addsd 136(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm2, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm1, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd 152(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd 144(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %r13, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 120(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 128(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, 64(%rsp) # 8-byte Spill
xorl %r13d, %r13d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI5_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movaps .LCPI5_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB5_26: # %.lr.ph.i99
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r12,%r13,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB5_27
# %bb.28: # in Loop: Header=BB5_26 Depth=1
incq %r13
cmpq $16777216, %r13 # imm = 0x1000000
jne .LBB5_26
# %bb.29: # %.critedge.i
movsd .LCPI5_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB5_30
.LBB5_27:
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
.LBB5_30: # %_Z12check_resultPKfS0_i.exit
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 64(%rsp), %xmm0 # 8-byte Folded Reload
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 56(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.9, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.10, %edi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.11, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.12, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.32:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.33:
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.34:
xorl %eax, %eax
addq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_31:
.cfi_def_cfa_offset 1776
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $137, %edx
jmp .LBB5_8
.LBB5_7:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $83, %edx
jmp .LBB5_8
.LBB5_10:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $88, %edx
jmp .LBB5_8
.LBB5_12:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $89, %edx
jmp .LBB5_8
.LBB5_14:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $90, %edx
jmp .LBB5_8
.LBB5_16:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $92, %edx
jmp .LBB5_8
.LBB5_18:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $93, %edx
jmp .LBB5_8
.LBB5_22:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $100, %edx
jmp .LBB5_8
.LBB5_24:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $106, %edx
.LBB5_8:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Add_on_devicePKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Add_on_devicePKfS0_Pfi,@object # @_Z13Add_on_devicePKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13Add_on_devicePKfS0_Pfi
.p2align 3, 0x0
_Z13Add_on_devicePKfS0_Pfi:
.quad _Z28__device_stub__Add_on_devicePKfS0_Pfi
.size _Z13Add_on_devicePKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: check_result: diff=%16.12f at k=%d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Success: all elements match better than epsilon=%16.12f\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Info: Starting %s ... \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: %s:%d: "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/moravveji/CUDA-C/master/book-exercises/chapters/02/2.5-GPUTiming.hip"
.size .L.str.4, 126
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Info: device #%d is: %s\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n%s\n"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Timing results ..."
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "dt_host: %12.8f (sec)\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "dt_h2d: %12.8f (sec)\n"
.size .L.str.9, 23
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "dt_kern: %12.8f (sec)\n"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "dt_d2h: %12.8f (sec)\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "dt_gpu: %12.8f (sec)\n"
.size .L.str.12, 23
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "dt_host / dt_gpu = %6.2f \n"
.size .L.str.13, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13Add_on_devicePKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Add_on_devicePKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Add_on_devicePKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Add_on_devicePKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R6, R0, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R0, RZ, 0x1e, R0 ; /* 0x0000001eff007819 */
/* 0x000fe20000011600 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00c0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x040fe40007f1e0ff */
/*00d0*/ IADD3 R2, P1, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fe40007f3e0ff */
/*00e0*/ IADD3.X R5, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000057a10 */
/* 0x040fe400007fe4ff */
/*00f0*/ IADD3.X R3, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000037a10 */
/* 0x000fc80000ffe4ff */
/*0100*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fc80007f1e0ff */
/*0130*/ IADD3.X R7, R0, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0000077a10 */
/* 0x000fe200007fe4ff */
/*0140*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Add_on_devicePKfS0_Pfi
.globl _Z13Add_on_devicePKfS0_Pfi
.p2align 8
.type _Z13Add_on_devicePKfS0_Pfi,@function
_Z13Add_on_devicePKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Add_on_devicePKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Add_on_devicePKfS0_Pfi, .Lfunc_end0-_Z13Add_on_devicePKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Add_on_devicePKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Add_on_devicePKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003f2b2_00000000-6_2.5-GPUTiming.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8initDataPfi
.type _Z8initDataPfi, @function
_Z8initDataPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebp, %ebp
jle .L3
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %rbp
.L5:
call rand@PLT
movzbl %al, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z8initDataPfi, .-_Z8initDataPfi
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z11Add_on_hostPKfS0_Pfi
.type _Z11Add_on_hostPKfS0_Pfi, @function
_Z11Add_on_hostPKfS0_Pfi:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L14
movslq %ecx, %rcx
salq $2, %rcx
movl $0, %eax
.L16:
movss (%rdi,%rax), %xmm0
addss (%rsi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L16
.L14:
ret
.cfi_endproc
.LFE2059:
.size _Z11Add_on_hostPKfS0_Pfi, .-_Z11Add_on_hostPKfS0_Pfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Error: check_result: diff=%16.12f at k=%d\n"
.align 8
.LC5:
.string "Success: all elements match better than epsilon=%16.12f\n"
.text
.globl _Z12check_resultPKfS0_i
.type _Z12check_resultPKfS0_i, @function
_Z12check_resultPKfS0_i:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testl %edx, %edx
jle .L19
movslq %edx, %rax
movl $0, %edx
movss .LC2(%rip), %xmm2
movsd .LC3(%rip), %xmm1
.L23:
movss (%rdi,%rdx,4), %xmm0
subss (%rsi,%rdx,4), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L28
addq $1, %rdx
cmpq %rax, %rdx
jne .L23
.L19:
movsd .LC3(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L18:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L18
.cfi_endproc
.LFE2060:
.size _Z12check_resultPKfS0_i, .-_Z12check_resultPKfS0_i
.globl _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
.type _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi, @function
_Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13Add_on_devicePKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi, .-_Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
.globl _Z13Add_on_devicePKfS0_Pfi
.type _Z13Add_on_devicePKfS0_Pfi, @function
_Z13Add_on_devicePKfS0_Pfi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13Add_on_devicePKfS0_Pfi, .-_Z13Add_on_devicePKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "Info: Starting %s ... \n"
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/moravveji/CUDA-C/master/book-exercises/chapters/02/2.5-GPUTiming.cu"
.section .rodata.str1.1
.LC8:
.string "Error: %s:%d: "
.LC9:
.string "Info: device #%d is: %s\n"
.LC10:
.string "Timing results ..."
.LC11:
.string "\n%s\n"
.LC12:
.string "dt_host: %12.8f (sec)\n"
.LC13:
.string "dt_h2d: %12.8f (sec)\n"
.LC14:
.string "dt_kern: %12.8f (sec)\n"
.LC15:
.string "dt_d2h: %12.8f (sec)\n"
.LC16:
.string "dt_gpu: %12.8f (sec)\n"
.LC17:
.string "dt_host / dt_gpu = %6.2f \n"
.LC18:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $128, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $131072, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
call _Z9cpuSecondv
movsd %xmm0, (%rsp)
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $16777216, %esi
movq %rbp, %rdi
call _Z8initDataPfi
movl $16777216, %esi
movq %rbx, %rdi
call _Z8initDataPfi
movl $67108864, %edx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
movl $67108864, %edx
movl $0, %esi
movq %rbx, %rdi
call memset@PLT
movl $16777216, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z11Add_on_hostPKfS0_Pfi
call _Z9cpuSecondv
movapd %xmm0, %xmm4
subsd (%rsp), %xmm4
movq %xmm4, %r15
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L52
leaq 80(%rsp), %rcx
movl $0, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z9cpuSecondv
movsd %xmm0, (%rsp)
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L53
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L54
leaq 48(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L55
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L56
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L57
call _Z9cpuSecondv
subsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L44:
call cudaDeviceSynchronize@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L59
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
call _Z9cpuSecondv
movsd %xmm0, 16(%rsp)
movl $2, %ecx
movl $67108864, %edx
movq 48(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L60
call _Z9cpuSecondv
subsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
movl $16777216, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z12check_resultPKfS0_i
movsd (%rsp), %xmm2
addsd 8(%rsp), %xmm2
movapd %xmm2, %xmm3
addsd 16(%rsp), %xmm3
movsd %xmm3, 24(%rsp)
leaq .LC10(%rip), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd (%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %xmm6
divsd 24(%rsp), %xmm6
movapd %xmm6, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
movq 1112(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $83, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $88, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $89, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $90, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $92, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $93, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L58:
movl $16777216, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z40__device_stub__Z13Add_on_devicePKfS0_PfiPKfS0_Pfi
jmp .L44
.L59:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $100, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $106, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $137, %ecx
leaq .LC7(%rip), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z13Add_on_devicePKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Add_on_devicePKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1092616192
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC3:
.long -500134854
.long 1044740494
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2.5-GPUTiming.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8initDataPfi
.LCPI0_0:
.quad 0x4024000000000000 # double 10
.text
.globl _Z8initDataPfi
.p2align 4, 0x90
.type _Z8initDataPfi,@function
_Z8initDataPfi: # @_Z8initDataPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movq %rsp, %rdi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z8initDataPfi, .Lfunc_end0-_Z8initDataPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI1_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z9cpuSecondv, .Lfunc_end1-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z11Add_on_hostPKfS0_Pfi # -- Begin function _Z11Add_on_hostPKfS0_Pfi
.p2align 4, 0x90
.type _Z11Add_on_hostPKfS0_Pfi,@function
_Z11Add_on_hostPKfS0_Pfi: # @_Z11Add_on_hostPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rsi,%rcx,4), %xmm0
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11Add_on_hostPKfS0_Pfi, .Lfunc_end2-_Z11Add_on_hostPKfS0_Pfi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__Add_on_devicePKfS0_Pfi # -- Begin function _Z28__device_stub__Add_on_devicePKfS0_Pfi
.p2align 4, 0x90
.type _Z28__device_stub__Add_on_devicePKfS0_Pfi,@function
_Z28__device_stub__Add_on_devicePKfS0_Pfi: # @_Z28__device_stub__Add_on_devicePKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13Add_on_devicePKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z28__device_stub__Add_on_devicePKfS0_Pfi, .Lfunc_end3-_Z28__device_stub__Add_on_devicePKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12check_resultPKfS0_i
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.text
.globl _Z12check_resultPKfS0_i
.p2align 4, 0x90
.type _Z12check_resultPKfS0_i,@function
_Z12check_resultPKfS0_i: # @_Z12check_resultPKfS0_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_4
# %bb.1: # %.lr.ph.preheader
movl %edx, %ecx
xorl %eax, %eax
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%rsi,%rax,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB4_5
# %bb.3: # in Loop: Header=BB4_2 Depth=1
incq %rax
cmpq %rax, %rcx
jne .LBB4_2
.LBB4_4: # %.critedge
movsd .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
jmp printf # TAILCALL
.LBB4_5:
movl $.L.str, %edi
movl %eax, %esi
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end4:
.size _Z12check_resultPKfS0_i, .Lfunc_end4-_Z12check_resultPKfS0_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI5_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI5_1:
.quad 0x4024000000000000 # double 10
.LCPI5_3:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI5_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 1776
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq (%rsi), %rsi
xorl %r12d, %r12d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 248(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 248(%rsp), %r13
cvtsi2sdq 256(%rsp), %xmm0
mulsd .LCPI5_0(%rip), %xmm0
movsd %xmm0, 64(%rsp) # 8-byte Spill
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
leaq 248(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
.p2align 4, 0x90
.LBB5_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_1
# %bb.2: # %_Z8initDataPfi.exit
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
leaq 248(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_3: # %.lr.ph.i90
# =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI5_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_3
# %bb.4: # %_Z8initDataPfi.exit94
xorl %r12d, %r12d
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB5_5: # %.lr.ph.i95
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r14,%r12,4), %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB5_5
# %bb.6: # %_Z11Add_on_hostPKfS0_Pfi.exit
leaq 248(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 248(%rsp), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 256(%rsp), %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB5_7
# %bb.9:
leaq 248(%rsp), %rdx
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 160(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 168(%rsp) # 8-byte Spill
leaq 104(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_10
# %bb.11:
leaq 96(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_12
# %bb.13:
leaq 88(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB5_14
# %bb.15:
movq 104(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_16
# %bb.17:
movq 96(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_18
# %bb.19:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 72(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 144(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 130944(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_21
# %bb.20:
movq 104(%rsp), %rax
movq 96(%rsp), %rcx
movq 88(%rsp), %rdx
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl $16777216, 116(%rsp) # imm = 0x1000000
leaq 240(%rsp), %rax
movq %rax, 16(%rsp)
leaq 232(%rsp), %rax
movq %rax, 24(%rsp)
leaq 224(%rsp), %rax
movq %rax, 32(%rsp)
leaq 116(%rsp), %rax
movq %rax, 40(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13Add_on_devicePKfS0_Pfi, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_21:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB5_22
# %bb.23:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 24(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %r13
movq 24(%rsp), %rbp
movq 88(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB5_24
# %bb.25:
movsd .LCPI5_0(%rip), %xmm3 # xmm3 = mem[0],zero
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI5_0(%rip), %xmm0
addsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movsd 168(%rsp), %xmm2 # 8-byte Reload
# xmm2 = mem[0],zero
mulsd .LCPI5_0(%rip), %xmm2
addsd 160(%rsp), %xmm2 # 8-byte Folded Reload
movsd 72(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm3, %xmm1
addsd 136(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm2, %xmm1
movsd %xmm1, 72(%rsp) # 8-byte Spill
movsd 64(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 8(%rsp), %xmm1 # 8-byte Folded Reload
subsd %xmm1, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movsd 152(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd %xmm3, %xmm1
xorps %xmm0, %xmm0
cvtsi2sd %rbp, %xmm0
addsd 144(%rsp), %xmm1 # 8-byte Folded Reload
mulsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %r13, %xmm2
addsd %xmm0, %xmm2
movsd %xmm2, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 120(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm3, %xmm0
xorps %xmm2, %xmm2
cvtsi2sdq 128(%rsp), %xmm2 # 8-byte Folded Reload
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, 64(%rsp) # 8-byte Spill
xorl %r13d, %r13d
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 24(%rsp), %xmm1
mulsd .LCPI5_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 8(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 8(%rsp) # 8-byte Spill
movaps .LCPI5_2(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_3(%rip), %xmm2 # xmm2 = mem[0],zero
.p2align 4, 0x90
.LBB5_26: # %.lr.ph.i99
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r12,%r13,4), %xmm0
andps %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd %xmm2, %xmm0
ja .LBB5_27
# %bb.28: # in Loop: Header=BB5_26 Depth=1
incq %r13
cmpq $16777216, %r13 # imm = 0x1000000
jne .LBB5_26
# %bb.29: # %.critedge.i
movsd .LCPI5_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
jmp .LBB5_30
.LBB5_27:
movl $.L.str, %edi
movl %r13d, %esi
movb $1, %al
callq printf
.LBB5_30: # %_Z12check_resultPKfS0_i.exit
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 64(%rsp), %xmm0 # 8-byte Folded Reload
addsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 56(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
movl $.L.str.8, %edi
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.9, %edi
movsd 72(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.10, %edi
movsd 64(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.11, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.12, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.13, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 104(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.32:
movq 96(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.33:
movq 88(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB5_31
# %bb.34:
xorl %eax, %eax
addq $1720, %rsp # imm = 0x6B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB5_31:
.cfi_def_cfa_offset 1776
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $137, %edx
jmp .LBB5_8
.LBB5_7:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $83, %edx
jmp .LBB5_8
.LBB5_10:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $88, %edx
jmp .LBB5_8
.LBB5_12:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $89, %edx
jmp .LBB5_8
.LBB5_14:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $90, %edx
jmp .LBB5_8
.LBB5_16:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $92, %edx
jmp .LBB5_8
.LBB5_18:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $93, %edx
jmp .LBB5_8
.LBB5_22:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $100, %edx
jmp .LBB5_8
.LBB5_24:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %esi
movl $106, %edx
.LBB5_8:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Add_on_devicePKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13Add_on_devicePKfS0_Pfi,@object # @_Z13Add_on_devicePKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z13Add_on_devicePKfS0_Pfi
.p2align 3, 0x0
_Z13Add_on_devicePKfS0_Pfi:
.quad _Z28__device_stub__Add_on_devicePKfS0_Pfi
.size _Z13Add_on_devicePKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: check_result: diff=%16.12f at k=%d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Success: all elements match better than epsilon=%16.12f\n"
.size .L.str.1, 57
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Info: Starting %s ... \n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: %s:%d: "
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/moravveji/CUDA-C/master/book-exercises/chapters/02/2.5-GPUTiming.hip"
.size .L.str.4, 126
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Info: device #%d is: %s\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\n%s\n"
.size .L.str.6, 5
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Timing results ..."
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "dt_host: %12.8f (sec)\n"
.size .L.str.8, 23
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "dt_h2d: %12.8f (sec)\n"
.size .L.str.9, 23
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "dt_kern: %12.8f (sec)\n"
.size .L.str.10, 23
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "dt_d2h: %12.8f (sec)\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "dt_gpu: %12.8f (sec)\n"
.size .L.str.12, 23
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "dt_host / dt_gpu = %6.2f \n"
.size .L.str.13, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13Add_on_devicePKfS0_Pfi"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Add_on_devicePKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13Add_on_devicePKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(cudaMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
// copyback and sum
gpuErrchk(cudaMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, cudaMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
cudaFree(devC);
return 0;
} | code for sm_80
Function : _Z10mul_reduceijjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x650 ; /* 0x0000062000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD.SHL.U32 R9, R2, 0x10, RZ ; /* 0x0000001002097824 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R2, R9, 0x10, RZ ; /* 0x0000001009027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ IMNMX R2, R2, c[0x0][0x160], PT ; /* 0x0000580002027a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 BRA 0x640 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x001fe20000000800 */
/*00d0*/ IADD3 R5, -R9, -0x11, RZ ; /* 0xffffffef09057810 */
/* 0x000fe20007ffe1ff */
/*00e0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1f ; /* 0x0000001fff067424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x2e0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*0120*/ IMNMX R10, R5, UR4, !PT ; /* 0x00000004050a7c17 */
/* 0x000fc8000f800200 */
/*0130*/ LOP3.LUT R5, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a057812 */
/* 0x000fe400078ec0ff */
/*0140*/ IADD3 R7, -R9, -0x2, -R10 ; /* 0xfffffffe09077810 */
/* 0x000fe40007ffe90a */
/*0150*/ ISETP.NE.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f25270 */
/*0160*/ LOP3.LUT R5, R6.reuse, c[0x0][0x164], RZ, 0xc0, !PT ; /* 0x0000590006057a12 */
/* 0x040fe400078ec0ff */
/*0170*/ LOP3.LUT R6, R6, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0006067a12 */
/* 0x000fe400078ec0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fc40003f06070 */
/*0190*/ IADD3 R8, -R5, 0x20, RZ ; /* 0x0000002005087810 */
/* 0x000fe40007ffe1ff */
/*01a0*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fc60007ffe1ff */
/*01b0*/ @!P1 BRA 0x2d0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc, !PT ; /* 0x000000030a0a7812 */
/* 0x000fe200078e0cff */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*01e0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ SHF.R.U32.HI R12, RZ, R8, R9.reuse ; /* 0x00000008ff0c7219 */
/* 0x100fe40000011609 */
/*0200*/ SHF.L.U32 R13, R9.reuse, R5, RZ ; /* 0x00000005090d7219 */
/* 0x040fe400000006ff */
/*0210*/ SHF.R.U32.HI R14, RZ, R7, R9 ; /* 0x00000007ff0e7219 */
/* 0x000fe40000011609 */
/*0220*/ SHF.L.U32 R15, R9, R6, RZ ; /* 0x00000006090f7219 */
/* 0x000fe400000006ff */
/*0230*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc40003f25270 */
/*0240*/ LOP3.LUT R12, R12, R13, RZ, 0xfc, !PT ; /* 0x0000000d0c0c7212 */
/* 0x000fe400078efcff */
/*0250*/ LOP3.LUT R14, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fe400078efcff */
/*0260*/ IADD3 R12, R12, c[0x0][0x164], RZ ; /* 0x000059000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ IADD3 R14, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0280*/ LOP3.LUT R12, R12, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000c0c7a12 */
/* 0x000fe400078e3cff */
/*0290*/ LOP3.LUT R14, R14, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000e0e7a12 */
/* 0x000fc400078e3cff */
/*02a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD R11, R12, R14, R11 ; /* 0x0000000e0c0b7224 */
/* 0x000fe200078e020b */
/*02c0*/ @P1 BRA 0x1e0 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02e0*/ BSSY B1, 0x630 ; /* 0x0000034000017945 */
/* 0x000fe20003800000 */
/*02f0*/ @!P0 BRA 0x620 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0300*/ SHF.R.U32.HI R10, RZ, R8, R9.reuse ; /* 0x00000008ff0a7219 */
/* 0x100fe40000011609 */
/*0310*/ SHF.L.U32 R13, R9.reuse, R5, RZ ; /* 0x00000005090d7219 */
/* 0x040fe400000006ff */
/*0320*/ IADD3 R15, R9.reuse, 0x1, RZ ; /* 0x00000001090f7810 */
/* 0x040fe40007ffe0ff */
/*0330*/ SHF.R.U32.HI R14, RZ, R7, R9 ; /* 0x00000007ff0e7219 */
/* 0x000fe40000011609 */
/*0340*/ SHF.L.U32 R17, R9, R6, RZ ; /* 0x0000000609117219 */
/* 0x000fc400000006ff */
/*0350*/ LOP3.LUT R20, R10, R13, RZ, 0xfc, !PT ; /* 0x0000000d0a147212 */
/* 0x000fe400078efcff */
/*0360*/ SHF.L.U32 R10, R15.reuse, R5, RZ ; /* 0x000000050f0a7219 */
/* 0x040fe400000006ff */
/*0370*/ SHF.R.U32.HI R13, RZ, R8, R15.reuse ; /* 0x00000008ff0d7219 */
/* 0x100fe4000001160f */
/*0380*/ SHF.L.U32 R12, R15, R6, RZ ; /* 0x000000060f0c7219 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.U32.HI R15, RZ, R7, R15 ; /* 0x00000007ff0f7219 */
/* 0x000fe4000001160f */
/*03a0*/ LOP3.LUT R22, R14, R17, RZ, 0xfc, !PT ; /* 0x000000110e167212 */
/* 0x000fc400078efcff */
/*03b0*/ IADD3 R14, R9, 0x2, RZ ; /* 0x00000002090e7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LOP3.LUT R10, R13, R10, RZ, 0xfc, !PT ; /* 0x0000000a0d0a7212 */
/* 0x000fe400078efcff */
/*03d0*/ LOP3.LUT R12, R15, R12, RZ, 0xfc, !PT ; /* 0x0000000c0f0c7212 */
/* 0x000fe400078efcff */
/*03e0*/ IADD3 R21, R20, c[0x0][0x164], RZ ; /* 0x0000590014157a10 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R23, R22, c[0x0][0x168], RZ ; /* 0x00005a0016177a10 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R17, R9, 0x3, RZ ; /* 0x0000000309117810 */
/* 0x000fc40007ffe0ff */
/*0410*/ SHF.L.U32 R13, R14.reuse, R5, RZ ; /* 0x000000050e0d7219 */
/* 0x040fe400000006ff */
/*0420*/ SHF.R.U32.HI R16, RZ, R8, R14.reuse ; /* 0x00000008ff107219 */
/* 0x100fe4000001160e */
/*0430*/ SHF.L.U32 R15, R14, R6, RZ ; /* 0x000000060e0f7219 */
/* 0x000fe400000006ff */
/*0440*/ SHF.R.U32.HI R14, RZ, R7, R14 ; /* 0x00000007ff0e7219 */
/* 0x000fe4000001160e */
/*0450*/ LOP3.LUT R22, R21, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590015167a12 */
/* 0x000fe400078e3cff */
/*0460*/ LOP3.LUT R23, R23, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0017177a12 */
/* 0x000fc400078e3cff */
/*0470*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0480*/ SHF.L.U32 R18, R17.reuse, R5, RZ ; /* 0x0000000511127219 */
/* 0x040fe200000006ff */
/*0490*/ IMAD R22, R22, R23, R11 ; /* 0x0000001716167224 */
/* 0x000fe200078e020b */
/*04a0*/ SHF.R.U32.HI R19, RZ, R8, R17.reuse ; /* 0x00000008ff137219 */
/* 0x100fe40000011611 */
/*04b0*/ SHF.L.U32 R20, R17, R6, RZ ; /* 0x0000000611147219 */
/* 0x000fe400000006ff */
/*04c0*/ SHF.R.U32.HI R17, RZ, R7, R17 ; /* 0x00000007ff117219 */
/* 0x000fe40000011611 */
/*04d0*/ LOP3.LUT R13, R16, R13, RZ, 0xfc, !PT ; /* 0x0000000d100d7212 */
/* 0x000fc400078efcff */
/*04e0*/ LOP3.LUT R14, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fe400078efcff */
/*04f0*/ IADD3 R10, R10, c[0x0][0x164], RZ ; /* 0x000059000a0a7a10 */
/* 0x000fe40007ffe0ff */
/*0500*/ IADD3 R12, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0510*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe40003f06270 */
/*0520*/ LOP3.LUT R18, R19, R18, RZ, 0xfc, !PT ; /* 0x0000001213127212 */
/* 0x000fe400078efcff */
/*0530*/ LOP3.LUT R17, R17, R20, RZ, 0xfc, !PT ; /* 0x0000001411117212 */
/* 0x000fc400078efcff */
/*0540*/ IADD3 R13, R13, c[0x0][0x164], RZ ; /* 0x000059000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R14, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0560*/ LOP3.LUT R10, R10, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000a0a7a12 */
/* 0x000fe400078e3cff */
/*0570*/ LOP3.LUT R11, R12, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000c0b7a12 */
/* 0x000fe400078e3cff */
/*0580*/ IADD3 R18, R18, c[0x0][0x164], RZ ; /* 0x0000590012127a10 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3 R17, R17, c[0x0][0x168], RZ ; /* 0x00005a0011117a10 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD R10, R10, R11, R22 ; /* 0x0000000b0a0a7224 */
/* 0x000fe200078e0216 */
/*05b0*/ LOP3.LUT R13, R13, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000d0d7a12 */
/* 0x000fc400078e3cff */
/*05c0*/ LOP3.LUT R14, R14, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000e0e7a12 */
/* 0x000fe400078e3cff */
/*05d0*/ LOP3.LUT R11, R18, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900120b7a12 */
/* 0x000fe400078e3cff */
/*05e0*/ LOP3.LUT R17, R17, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0011117a12 */
/* 0x000fe200078e3cff */
/*05f0*/ IMAD R10, R13, R14, R10 ; /* 0x0000000e0d0a7224 */
/* 0x000fc800078e020a */
/*0600*/ IMAD R11, R11, R17, R10 ; /* 0x000000110b0b7224 */
/* 0x000fe200078e020a */
/*0610*/ @!P0 BRA 0x300 ; /* 0xfffffce000008947 */
/* 0x000fea000383ffff */
/*0620*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0630*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e40000004800 */
/*0640*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0650*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0670*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0680*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0690*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*06a0*/ @!P1 BRA 0x760 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fca000f8e00ff */
/*06c0*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f26270 */
/*06d0*/ @!P1 IMAD R2, R5, 0x4, R4 ; /* 0x0000000405029824 */
/* 0x000fe200078e0204 */
/*06e0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe20000004800 */
/*06f0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011605 */
/*0700*/ @!P1 LDS R7, [R2] ; /* 0x0000000002079984 */
/* 0x000e240000000800 */
/*0710*/ @!P1 IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106079824 */
/* 0x001fca00078e0207 */
/*0720*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x0001e80000004800 */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0740*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0750*/ @P1 BRA 0x6c0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0760*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0770*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0790*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*07a0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*07b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mulijjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x650 ; /* 0x0000061000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x10, RZ ; /* 0x0000001000027824 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R3, R2, 0x10, RZ ; /* 0x0000001002037810 */
/* 0x000fc80007ffe0ff */
/*0090*/ IMNMX R3, R3, c[0x0][0x160], PT ; /* 0x0000580003037a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 BRA 0x640 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IADD3 R3, -R2, -0x11, RZ ; /* 0xffffffef02037810 */
/* 0x000fe20007ffe1ff */
/*00e0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1f ; /* 0x0000001fff077424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x540 ; /* 0x0000043000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0120*/ IMNMX R3, R3, UR4, !PT ; /* 0x0000000403037c17 */
/* 0x000fc8000f800200 */
/*0130*/ IADD3 R4, -R2, -0x2, -R3 ; /* 0xfffffffe02047810 */
/* 0x000fe40007ffe903 */
/*0140*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe400078e33ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc60003f26070 */
/*0160*/ IMAD.IADD R8, R5, 0x1, -R2 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a02 */
/*0170*/ LOP3.LUT R5, R7.reuse, c[0x0][0x164], RZ, 0xc0, !PT ; /* 0x0000590007057a12 */
/* 0x040fe400078ec0ff */
/*0180*/ LOP3.LUT R7, R7, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0007077a12 */
/* 0x000fe400078ec0ff */
/*0190*/ LOP3.LUT R3, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308037812 */
/* 0x000fe400078ec0ff */
/*01a0*/ IADD3 R9, -R5, 0x20, RZ ; /* 0x0000002005097810 */
/* 0x000fe40007ffe1ff */
/*01b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*01c0*/ IADD3 R11, -R7, 0x20, RZ ; /* 0x00000020070b7810 */
/* 0x000fe20007ffe1ff */
/*01d0*/ @!P1 BRA 0x530 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.IADD R4, R8, 0x1, -R3 ; /* 0x0000000108047824 */
/* 0x000fe400078e0a03 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0200*/ SHF.R.U32.HI R8, RZ, R9, R2 ; /* 0x00000009ff087219 */
/* 0x000fe40000011602 */
/*0210*/ SHF.L.U32 R13, R2, R5, RZ ; /* 0x00000005020d7219 */
/* 0x000fc400000006ff */
/*0220*/ IADD3 R12, R2.reuse, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x040fe40007ffe0ff */
/*0230*/ SHF.R.U32.HI R10, RZ, R11, R2 ; /* 0x0000000bff0a7219 */
/* 0x000fe40000011602 */
/*0240*/ SHF.L.U32 R15, R2, R7, RZ ; /* 0x00000007020f7219 */
/* 0x000fe400000006ff */
/*0250*/ LOP3.LUT R13, R8, R13, RZ, 0xfc, !PT ; /* 0x0000000d080d7212 */
/* 0x000fe400078efcff */
/*0260*/ SHF.L.U32 R8, R12, R5, RZ ; /* 0x000000050c087219 */
/* 0x000fe400000006ff */
/*0270*/ SHF.R.U32.HI R17, RZ, R9, R12 ; /* 0x00000009ff117219 */
/* 0x000fc4000001160c */
/*0280*/ SHF.L.U32 R14, R12, R7, RZ ; /* 0x000000070c0e7219 */
/* 0x000fe400000006ff */
/*0290*/ SHF.R.U32.HI R19, RZ, R11, R12 ; /* 0x0000000bff137219 */
/* 0x000fe4000001160c */
/*02a0*/ LOP3.LUT R15, R10, R15, RZ, 0xfc, !PT ; /* 0x0000000f0a0f7212 */
/* 0x000fe400078efcff */
/*02b0*/ IADD3 R12, R2, 0x2, RZ ; /* 0x00000002020c7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ LOP3.LUT R8, R17, R8, RZ, 0xfc, !PT ; /* 0x0000000811087212 */
/* 0x000fe400078efcff */
/*02d0*/ LOP3.LUT R10, R19, R14, RZ, 0xfc, !PT ; /* 0x0000000e130a7212 */
/* 0x000fc400078efcff */
/*02e0*/ IADD3 R18, R2, 0x3, RZ ; /* 0x0000000302127810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ SHF.L.U32 R14, R12.reuse, R5, RZ ; /* 0x000000050c0e7219 */
/* 0x040fe400000006ff */
/*0300*/ SHF.R.U32.HI R17, RZ, R9, R12.reuse ; /* 0x00000009ff117219 */
/* 0x100fe4000001160c */
/*0310*/ SHF.L.U32 R16, R12, R7, RZ ; /* 0x000000070c107219 */
/* 0x000fe400000006ff */
/*0320*/ SHF.R.U32.HI R19, RZ, R11, R12 ; /* 0x0000000bff137219 */
/* 0x000fe4000001160c */
/*0330*/ IADD3 R13, R13, c[0x0][0x164], RZ ; /* 0x000059000d0d7a10 */
/* 0x000fc40007ffe0ff */
/*0340*/ IADD3 R15, R15, c[0x0][0x168], RZ ; /* 0x00005a000f0f7a10 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0360*/ SHF.L.U32 R12, R18.reuse, R5, RZ ; /* 0x00000005120c7219 */
/* 0x040fe400000006ff */
/*0370*/ SHF.R.U32.HI R21, RZ, R9, R18.reuse ; /* 0x00000009ff157219 */
/* 0x100fe40000011612 */
/*0380*/ SHF.L.U32 R20, R18, R7, RZ ; /* 0x0000000712147219 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.U32.HI R23, RZ, R11, R18 ; /* 0x0000000bff177219 */
/* 0x000fc40000011612 */
/*03a0*/ LOP3.LUT R13, R13, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000d0d7a12 */
/* 0x000fe400078e3cff */
/*03b0*/ LOP3.LUT R15, R15, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000f0f7a12 */
/* 0x000fe400078e3cff */
/*03c0*/ LOP3.LUT R14, R17, R14, RZ, 0xfc, !PT ; /* 0x0000000e110e7212 */
/* 0x000fe400078efcff */
/*03d0*/ LOP3.LUT R16, R19, R16, RZ, 0xfc, !PT ; /* 0x0000001013107212 */
/* 0x000fe200078efcff */
/*03e0*/ IMAD R13, R13, R15, R6 ; /* 0x0000000f0d0d7224 */
/* 0x000fe200078e0206 */
/*03f0*/ IADD3 R8, R8, c[0x0][0x164], RZ ; /* 0x0000590008087a10 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R10, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0a7a10 */
/* 0x000fc40007ffe0ff */
/*0410*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0420*/ LOP3.LUT R12, R21, R12, RZ, 0xfc, !PT ; /* 0x0000000c150c7212 */
/* 0x000fe400078efcff */
/*0430*/ LOP3.LUT R20, R23, R20, RZ, 0xfc, !PT ; /* 0x0000001417147212 */
/* 0x000fe400078efcff */
/*0440*/ IADD3 R14, R14, c[0x0][0x164], RZ ; /* 0x000059000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R16, R16, c[0x0][0x168], RZ ; /* 0x00005a0010107a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ LOP3.LUT R8, R8, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590008087a12 */
/* 0x000fc400078e3cff */
/*0470*/ LOP3.LUT R10, R10, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000a0a7a12 */
/* 0x000fe400078e3cff */
/*0480*/ IADD3 R12, R12, c[0x0][0x164], RZ ; /* 0x000059000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R20, R20, c[0x0][0x168], RZ ; /* 0x00005a0014147a10 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD R8, R8, R10, R13 ; /* 0x0000000a08087224 */
/* 0x000fe200078e020d */
/*04b0*/ LOP3.LUT R15, R14, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000e0f7a12 */
/* 0x000fe400078e3cff */
/*04c0*/ LOP3.LUT R16, R16, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0010107a12 */
/* 0x000fe400078e3cff */
/*04d0*/ LOP3.LUT R13, R12, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000c0d7a12 */
/* 0x000fc400078e3cff */
/*04e0*/ LOP3.LUT R20, R20, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0014147a12 */
/* 0x000fe200078e3cff */
/*04f0*/ IMAD R8, R15, R16, R8 ; /* 0x000000100f087224 */
/* 0x000fe200078e0208 */
/*0500*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD R6, R13, R20, R8 ; /* 0x000000140d067224 */
/* 0x000fe200078e0208 */
/*0520*/ @P1 BRA 0x200 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ @!P0 BRA 0x640 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0560*/ SHF.R.U32.HI R4, RZ, R9, R2.reuse ; /* 0x00000009ff047219 */
/* 0x100fe40000011602 */
/*0570*/ SHF.L.U32 R13, R2.reuse, R5, RZ ; /* 0x00000005020d7219 */
/* 0x040fe400000006ff */
/*0580*/ SHF.R.U32.HI R8, RZ, R11, R2 ; /* 0x0000000bff087219 */
/* 0x000fe40000011602 */
/*0590*/ SHF.L.U32 R15, R2, R7, RZ ; /* 0x00000007020f7219 */
/* 0x000fe400000006ff */
/*05a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f05270 */
/*05b0*/ LOP3.LUT R4, R4, R13, RZ, 0xfc, !PT ; /* 0x0000000d04047212 */
/* 0x000fe400078efcff */
/*05c0*/ LOP3.LUT R8, R8, R15, RZ, 0xfc, !PT ; /* 0x0000000f08087212 */
/* 0x000fe400078efcff */
/*05d0*/ IADD3 R4, R4, c[0x0][0x164], RZ ; /* 0x0000590004047a10 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R8, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007ffe0ff */
/*05f0*/ LOP3.LUT R13, R4, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900040d7a12 */
/* 0x000fe400078e3cff */
/*0600*/ LOP3.LUT R8, R8, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0008087a12 */
/* 0x000fc400078e3cff */
/*0610*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc60007ffe0ff */
/*0620*/ IMAD R6, R13, R8, R6 ; /* 0x000000080d067224 */
/* 0x000fe200078e0206 */
/*0630*/ @P0 BRA 0x550 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0640*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0670*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101906 */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ BRA 0x690; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(cudaMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
// copyback and sum
gpuErrchk(cudaMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, cudaMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
cudaFree(devC);
return 0;
} | .file "tmpxft_000bb70d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11rotate_leftjj
.type _Z11rotate_leftjj, @function
_Z11rotate_leftjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11rotate_leftjj, .-_Z11rotate_leftjj
.globl _Z7encryptjj
.type _Z7encryptjj, @function
_Z7encryptjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7encryptjj, .-_Z7encryptjj
.globl _Z7divCeilii
.type _Z7divCeilii, @function
_Z7divCeilii:
.LFB2060:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
imull %eax, %esi
cmpl %edi, %esi
setl %dl
movzbl %dl, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z7divCeilii, .-_Z7divCeilii
.globl _Z25__device_stub__Z3mulijjPjijjPj
.type _Z25__device_stub__Z3mulijjPjijjPj, @function
_Z25__device_stub__Z3mulijjPjijjPj:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulijjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z3mulijjPjijjPj, .-_Z25__device_stub__Z3mulijjPjijjPj
.globl _Z3mulijjPj
.type _Z3mulijjPj, @function
_Z3mulijjPj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3mulijjPjijjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3mulijjPj, .-_Z3mulijjPj
.globl _Z33__device_stub__Z10mul_reduceijjPjijjPj
.type _Z33__device_stub__Z10mul_reduceijjPjijjPj, @function
_Z33__device_stub__Z10mul_reduceijjPjijjPj:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_reduceijjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z10mul_reduceijjPjijjPj, .-_Z33__device_stub__Z10mul_reduceijjPjijjPj
.globl _Z10mul_reduceijjPj
.type _Z10mul_reduceijjPj, @function
_Z10mul_reduceijjPj:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mul_reduceijjPjijjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10mul_reduceijjPj, .-_Z10mul_reduceijjPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/George0828Zhang/cuda-practice/main/DotProduct/main.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.LC2:
.string "%u\n"
.LC3:
.string "%d %u %u"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %r12
testl %eax, %eax
jne .L40
.L26:
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $3, %eax
jne .L41
movl $16, %esi
movl 12(%rsp), %edi
call _Z7divCeilii
movl %eax, %edi
movl $256, %esi
call _Z7divCeilii
movl %eax, %ebp
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L27:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
movslq %ebp, %rdx
leaq 0(,%rdx,4), %r13
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
leaq C(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq C(%rip), %rax
leaq 0(%r13,%rax), %rdx
testl %ebp, %ebp
jle .L32
.L33:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L32:
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L40:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L42:
movq 24(%rsp), %rcx
movl 20(%rsp), %edx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
call _Z33__device_stub__Z10mul_reduceijjPjijjPj
jmp .L27
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $90, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $91, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $94, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L41:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10mul_reduceijjPj"
.LC5:
.string "_Z3mulijjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_reduceijjPj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulijjPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C
.bss
.align 32
.type C, @object
.size C, 67108864
C:
.zero 67108864
.globl B
.align 32
.type B, @object
.size B, 67108864
B:
.zero 67108864
.globl A
.align 32
.type A, @object
.size A, 67108864
A:
.zero 67108864
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(cudaMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaDeviceSynchronize());
// copyback and sum
gpuErrchk(cudaMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, cudaMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
cudaFree(devC);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(hipMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
// copyback and sum
gpuErrchk(hipMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, hipMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
hipFree(devC);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(hipMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
// copyback and sum
gpuErrchk(hipMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, hipMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
hipFree(devC);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulijjPj
.globl _Z3mulijjPj
.p2align 8
.type _Z3mulijjPj,@function
_Z3mulijjPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshlrev_b32_e32 v2, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, 16, v2
v_min_i32_e32 v3, s3, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s6, 0, s2
s_sub_i32 s7, 0, s3
.LBB0_2:
v_alignbit_b32 v4, v2, v2, s6
v_alignbit_b32 v5, v2, v2, s7
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, s2, v4
v_add_nc_u32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v2, v3
v_xor_b32_e32 v6, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, s3, v5
s_or_b32 s5, vcc_lo, s5
v_mad_u64_u32 v[4:5], null, v6, v7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulijjPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulijjPj, .Lfunc_end0-_Z3mulijjPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10mul_reduceijjPj
.globl _Z10mul_reduceijjPj
.p2align 8
.type _Z10mul_reduceijjPj,@function
_Z10mul_reduceijjPj:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s2, s15
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s3
v_add_lshl_u32 v5, s5, v0, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 16, v5
v_min_i32_e32 v6, s4, v1
v_mov_b32_e32 v1, 0
ds_store_b32 v4, v1
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB1_4
s_load_b64 s[4:5], s[0:1], 0x4
ds_load_b32 v1, v4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, 0, s4
s_sub_i32 s9, 0, s5
.LBB1_2:
v_alignbit_b32 v2, v5, v5, s8
v_alignbit_b32 v3, v5, v5, s9
v_add_nc_u32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, s4, v2
v_add_nc_u32_e32 v3, s5, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v5, v6
v_xor_b32_e32 v7, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, s5, v3
s_or_b32 s7, vcc_lo, s7
v_mad_u64_u32 v[2:3], null, v7, v8, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v2
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s7
ds_store_b32 v4, v2
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_5
v_add_lshl_u32 v1, s4, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v4, v1
s_branch .LBB1_5
.LBB1_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_reduceijjPj
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10mul_reduceijjPj, .Lfunc_end1-_Z10mul_reduceijjPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulijjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulijjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_reduceijjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_reduceijjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <inttypes.h>
#include <stdint.h>
// #include "utils.h"
#define CHUNKSIZE 16
#define THREADS_PER_BLOCK 256
#define MAXN 16777216
#define MAXBLOCKS (MAXN / CHUNKSIZE / THREADS_PER_BLOCK)
uint32_t A[MAXN], B[MAXN], C[MAXN];
// function for debugging.
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__device__ uint32_t rotate_left(uint32_t x, uint32_t n) {
return (x << n) | (x >> (32-n));
}
__device__ uint32_t encrypt(uint32_t m, uint32_t key) {
return (rotate_left(m, key&31) + key)^key;
}
// 1. kernel
__global__ void mul(int N, uint32_t key1, uint32_t key2, uint32_t* out){
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
uint32_t res = 0;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
for(int k = start; k < end; k++){
res += encrypt(k, key1) * encrypt(k, key2);
}
out[chunk_id] = res;
}
// 2. add reduction
__global__ void mul_reduce(int N, uint32_t key1, uint32_t key2, uint32_t* out){
__shared__ uint32_t sdata[THREADS_PER_BLOCK]; // for reduction
int tid = threadIdx.x;
int chunk_id = threadIdx.x + blockIdx.x * blockDim.x;
// process chunk
int start = chunk_id * CHUNKSIZE;
int end = (chunk_id+1)*CHUNKSIZE;
end = N < end ? N : end;
sdata[tid] = 0;
for(int k = start; k < end; k++){
sdata[tid] += encrypt(k, key1) * encrypt(k, key2);
}
__syncthreads();
for(int s = blockDim.x / 2; s > 0; s >>= 1) {
if (tid < s) {
sdata[tid] += sdata[tid + s];
}
__syncthreads();
}
if (tid == 0) out[blockIdx.x] = sdata[0];
}
int divCeil(int a, int b){
int c = a / b;
if (c * b < a){
c++;
}
return c;
}
int main(int argc, char *argv[]) {
int N, N_CHUNKS, BLOCKS;
uint32_t key1, key2;
uint32_t *devC;
gpuErrchk(hipMalloc(&devC, sizeof(uint32_t) * MAXN));
while (scanf("%d %" PRIu32 " %" PRIu32, &N, &key1, &key2) == 3) {
N_CHUNKS = divCeil(N, CHUNKSIZE);
BLOCKS = divCeil(N_CHUNKS, THREADS_PER_BLOCK);
mul_reduce <<< BLOCKS, THREADS_PER_BLOCK >>> (N, key1, key2, devC);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipDeviceSynchronize());
// copyback and sum
gpuErrchk(hipMemcpy(C, devC, sizeof(uint32_t) * BLOCKS, hipMemcpyDeviceToHost));
uint32_t sum = 0;
for (int i = 0; i < BLOCKS; i++){
sum += C[i];
}
printf("%" PRIu32 "\n", sum);
}
hipFree(devC);
return 0;
} | .text
.file "main.hip"
.globl _Z18__device_stub__mulijjPj # -- Begin function _Z18__device_stub__mulijjPj
.p2align 4, 0x90
.type _Z18__device_stub__mulijjPj,@function
_Z18__device_stub__mulijjPj: # @_Z18__device_stub__mulijjPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulijjPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__mulijjPj, .Lfunc_end0-_Z18__device_stub__mulijjPj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mul_reduceijjPj # -- Begin function _Z25__device_stub__mul_reduceijjPj
.p2align 4, 0x90
.type _Z25__device_stub__mul_reduceijjPj,@function
_Z25__device_stub__mul_reduceijjPj: # @_Z25__device_stub__mul_reduceijjPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_reduceijjPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__mul_reduceijjPj, .Lfunc_end1-_Z25__device_stub__mul_reduceijjPj
.cfi_endproc
# -- End function
.globl _Z7divCeilii # -- Begin function _Z7divCeilii
.p2align 4, 0x90
.type _Z7divCeilii,@function
_Z7divCeilii: # @_Z7divCeilii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
imull %eax, %esi
xorl %ecx, %ecx
cmpl %edi, %esi
setl %cl
addl %ecx, %eax
retq
.Lfunc_end2:
.size _Z7divCeilii, .Lfunc_end2-_Z7divCeilii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB3_7
# %bb.1: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
leaq 4(%rsp), %rsi
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $3, %eax
jne .LBB3_15
# %bb.2: # %.lr.ph29
movabsq $4294967296, %rax # imm = 0x100000000
leaq 256(%rax), %rbx
leaq 4(%rsp), %r14
leaq 12(%rsp), %r15
leaq 8(%rsp), %r12
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
xorl %esi, %esi
.LBB3_14: # %_Z9gpuAssert10hipError_tPKcib.exit
# in Loop: Header=BB3_3 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $3, %eax
jne .LBB3_15
.LBB3_3: # =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
movl 4(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movl %ecx, %edx
sarl $4, %edx
andl $-16, %ecx
xorl %esi, %esi
cmpl %eax, %ecx
setl %sil
leal (%rdx,%rsi), %eax
addl $255, %eax
movl %edx, %ecx
addl %esi, %ecx
cmovnsl %ecx, %eax
movl %eax, %edx
sarl $8, %edx
andl $-256, %eax
xorl %ebp, %ebp
cmpl %ecx, %eax
setl %bpl
addl %edx, %ebp
movq %rbp, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl 4(%rsp), %eax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movq 16(%rsp), %rsi
movl %eax, 36(%rsp)
movl %ecx, 32(%rsp)
movl %edx, 28(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z10mul_reduceijjPj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB3_6
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit14
# in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit16
# in Loop: Header=BB3_3 Depth=1
movq 16(%rsp), %rsi
movslq %ebp, %rdx
shlq $2, %rdx
movl $C, %edi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit18.preheader
# in Loop: Header=BB3_3 Depth=1
testl %ebp, %ebp
jle .LBB3_13
# %bb.16: # %_Z9gpuAssert10hipError_tPKcib.exit18.preheader30
# in Loop: Header=BB3_3 Depth=1
movl %ebp, %eax
shlq $2, %rax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_17: # %_Z9gpuAssert10hipError_tPKcib.exit18
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
addl C(%rcx), %esi
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB3_17
jmp .LBB3_14
.LBB3_15: # %_Z9gpuAssert10hipError_tPKcib.exit._crit_edge
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB3_8
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
.LBB3_8:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB3_6:
movl %eax, %r13d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %r8d
xorl %eax, %eax
callq fprintf
movl %r13d, %edi
callq exit
.LBB3_7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB3_8
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulijjPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_reduceijjPj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 67108864
.size A, 67108864
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 67108864
.size B, 67108864
.type C,@object # @C
.globl C
.p2align 4, 0x0
C:
.zero 67108864
.size C, 67108864
.type _Z3mulijjPj,@object # @_Z3mulijjPj
.section .rodata,"a",@progbits
.globl _Z3mulijjPj
.p2align 3, 0x0
_Z3mulijjPj:
.quad _Z18__device_stub__mulijjPj
.size _Z3mulijjPj, 8
.type _Z10mul_reduceijjPj,@object # @_Z10mul_reduceijjPj
.globl _Z10mul_reduceijjPj
.p2align 3, 0x0
_Z10mul_reduceijjPj:
.quad _Z25__device_stub__mul_reduceijjPj
.size _Z10mul_reduceijjPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/George0828Zhang/cuda-practice/main/DotProduct/main.hip"
.size .L.str, 112
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %u %u"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%u\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulijjPj"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10mul_reduceijjPj"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulijjPj
.addrsig_sym _Z25__device_stub__mul_reduceijjPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym C
.addrsig_sym _Z3mulijjPj
.addrsig_sym _Z10mul_reduceijjPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mul_reduceijjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ BSSY B0, 0x650 ; /* 0x0000062000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R0.X4], RZ ; /* 0x000000ff00007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x002fc800078e0200 */
/*0070*/ IMAD.SHL.U32 R9, R2, 0x10, RZ ; /* 0x0000001002097824 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R2, R9, 0x10, RZ ; /* 0x0000001009027810 */
/* 0x000fc80007ffe0ff */
/*0090*/ IMNMX R2, R2, c[0x0][0x160], PT ; /* 0x0000580002027a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 BRA 0x640 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x001fe20000000800 */
/*00d0*/ IADD3 R5, -R9, -0x11, RZ ; /* 0xffffffef09057810 */
/* 0x000fe20007ffe1ff */
/*00e0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1f ; /* 0x0000001fff067424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x2e0 ; /* 0x000001d000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*0120*/ IMNMX R10, R5, UR4, !PT ; /* 0x00000004050a7c17 */
/* 0x000fc8000f800200 */
/*0130*/ LOP3.LUT R5, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a057812 */
/* 0x000fe400078ec0ff */
/*0140*/ IADD3 R7, -R9, -0x2, -R10 ; /* 0xfffffffe09077810 */
/* 0x000fe40007ffe90a */
/*0150*/ ISETP.NE.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f25270 */
/*0160*/ LOP3.LUT R5, R6.reuse, c[0x0][0x164], RZ, 0xc0, !PT ; /* 0x0000590006057a12 */
/* 0x040fe400078ec0ff */
/*0170*/ LOP3.LUT R6, R6, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0006067a12 */
/* 0x000fe400078ec0ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fc40003f06070 */
/*0190*/ IADD3 R8, -R5, 0x20, RZ ; /* 0x0000002005087810 */
/* 0x000fe40007ffe1ff */
/*01a0*/ IADD3 R7, -R6, 0x20, RZ ; /* 0x0000002006077810 */
/* 0x000fc60007ffe1ff */
/*01b0*/ @!P1 BRA 0x2d0 ; /* 0x0000011000009947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc, !PT ; /* 0x000000030a0a7812 */
/* 0x000fe200078e0cff */
/*01d0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*01e0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ SHF.R.U32.HI R12, RZ, R8, R9.reuse ; /* 0x00000008ff0c7219 */
/* 0x100fe40000011609 */
/*0200*/ SHF.L.U32 R13, R9.reuse, R5, RZ ; /* 0x00000005090d7219 */
/* 0x040fe400000006ff */
/*0210*/ SHF.R.U32.HI R14, RZ, R7, R9 ; /* 0x00000007ff0e7219 */
/* 0x000fe40000011609 */
/*0220*/ SHF.L.U32 R15, R9, R6, RZ ; /* 0x00000006090f7219 */
/* 0x000fe400000006ff */
/*0230*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc40003f25270 */
/*0240*/ LOP3.LUT R12, R12, R13, RZ, 0xfc, !PT ; /* 0x0000000d0c0c7212 */
/* 0x000fe400078efcff */
/*0250*/ LOP3.LUT R14, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fe400078efcff */
/*0260*/ IADD3 R12, R12, c[0x0][0x164], RZ ; /* 0x000059000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0270*/ IADD3 R14, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0280*/ LOP3.LUT R12, R12, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000c0c7a12 */
/* 0x000fe400078e3cff */
/*0290*/ LOP3.LUT R14, R14, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000e0e7a12 */
/* 0x000fc400078e3cff */
/*02a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe0ff */
/*02b0*/ IMAD R11, R12, R14, R11 ; /* 0x0000000e0c0b7224 */
/* 0x000fe200078e020b */
/*02c0*/ @P1 BRA 0x1e0 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02e0*/ BSSY B1, 0x630 ; /* 0x0000034000017945 */
/* 0x000fe20003800000 */
/*02f0*/ @!P0 BRA 0x620 ; /* 0x0000032000008947 */
/* 0x000fea0003800000 */
/*0300*/ SHF.R.U32.HI R10, RZ, R8, R9.reuse ; /* 0x00000008ff0a7219 */
/* 0x100fe40000011609 */
/*0310*/ SHF.L.U32 R13, R9.reuse, R5, RZ ; /* 0x00000005090d7219 */
/* 0x040fe400000006ff */
/*0320*/ IADD3 R15, R9.reuse, 0x1, RZ ; /* 0x00000001090f7810 */
/* 0x040fe40007ffe0ff */
/*0330*/ SHF.R.U32.HI R14, RZ, R7, R9 ; /* 0x00000007ff0e7219 */
/* 0x000fe40000011609 */
/*0340*/ SHF.L.U32 R17, R9, R6, RZ ; /* 0x0000000609117219 */
/* 0x000fc400000006ff */
/*0350*/ LOP3.LUT R20, R10, R13, RZ, 0xfc, !PT ; /* 0x0000000d0a147212 */
/* 0x000fe400078efcff */
/*0360*/ SHF.L.U32 R10, R15.reuse, R5, RZ ; /* 0x000000050f0a7219 */
/* 0x040fe400000006ff */
/*0370*/ SHF.R.U32.HI R13, RZ, R8, R15.reuse ; /* 0x00000008ff0d7219 */
/* 0x100fe4000001160f */
/*0380*/ SHF.L.U32 R12, R15, R6, RZ ; /* 0x000000060f0c7219 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.U32.HI R15, RZ, R7, R15 ; /* 0x00000007ff0f7219 */
/* 0x000fe4000001160f */
/*03a0*/ LOP3.LUT R22, R14, R17, RZ, 0xfc, !PT ; /* 0x000000110e167212 */
/* 0x000fc400078efcff */
/*03b0*/ IADD3 R14, R9, 0x2, RZ ; /* 0x00000002090e7810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ LOP3.LUT R10, R13, R10, RZ, 0xfc, !PT ; /* 0x0000000a0d0a7212 */
/* 0x000fe400078efcff */
/*03d0*/ LOP3.LUT R12, R15, R12, RZ, 0xfc, !PT ; /* 0x0000000c0f0c7212 */
/* 0x000fe400078efcff */
/*03e0*/ IADD3 R21, R20, c[0x0][0x164], RZ ; /* 0x0000590014157a10 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R23, R22, c[0x0][0x168], RZ ; /* 0x00005a0016177a10 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R17, R9, 0x3, RZ ; /* 0x0000000309117810 */
/* 0x000fc40007ffe0ff */
/*0410*/ SHF.L.U32 R13, R14.reuse, R5, RZ ; /* 0x000000050e0d7219 */
/* 0x040fe400000006ff */
/*0420*/ SHF.R.U32.HI R16, RZ, R8, R14.reuse ; /* 0x00000008ff107219 */
/* 0x100fe4000001160e */
/*0430*/ SHF.L.U32 R15, R14, R6, RZ ; /* 0x000000060e0f7219 */
/* 0x000fe400000006ff */
/*0440*/ SHF.R.U32.HI R14, RZ, R7, R14 ; /* 0x00000007ff0e7219 */
/* 0x000fe4000001160e */
/*0450*/ LOP3.LUT R22, R21, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590015167a12 */
/* 0x000fe400078e3cff */
/*0460*/ LOP3.LUT R23, R23, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0017177a12 */
/* 0x000fc400078e3cff */
/*0470*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007ffe0ff */
/*0480*/ SHF.L.U32 R18, R17.reuse, R5, RZ ; /* 0x0000000511127219 */
/* 0x040fe200000006ff */
/*0490*/ IMAD R22, R22, R23, R11 ; /* 0x0000001716167224 */
/* 0x000fe200078e020b */
/*04a0*/ SHF.R.U32.HI R19, RZ, R8, R17.reuse ; /* 0x00000008ff137219 */
/* 0x100fe40000011611 */
/*04b0*/ SHF.L.U32 R20, R17, R6, RZ ; /* 0x0000000611147219 */
/* 0x000fe400000006ff */
/*04c0*/ SHF.R.U32.HI R17, RZ, R7, R17 ; /* 0x00000007ff117219 */
/* 0x000fe40000011611 */
/*04d0*/ LOP3.LUT R13, R16, R13, RZ, 0xfc, !PT ; /* 0x0000000d100d7212 */
/* 0x000fc400078efcff */
/*04e0*/ LOP3.LUT R14, R14, R15, RZ, 0xfc, !PT ; /* 0x0000000f0e0e7212 */
/* 0x000fe400078efcff */
/*04f0*/ IADD3 R10, R10, c[0x0][0x164], RZ ; /* 0x000059000a0a7a10 */
/* 0x000fe40007ffe0ff */
/*0500*/ IADD3 R12, R12, c[0x0][0x168], RZ ; /* 0x00005a000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0510*/ ISETP.GE.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe40003f06270 */
/*0520*/ LOP3.LUT R18, R19, R18, RZ, 0xfc, !PT ; /* 0x0000001213127212 */
/* 0x000fe400078efcff */
/*0530*/ LOP3.LUT R17, R17, R20, RZ, 0xfc, !PT ; /* 0x0000001411117212 */
/* 0x000fc400078efcff */
/*0540*/ IADD3 R13, R13, c[0x0][0x164], RZ ; /* 0x000059000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R14, R14, c[0x0][0x168], RZ ; /* 0x00005a000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0560*/ LOP3.LUT R10, R10, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000a0a7a12 */
/* 0x000fe400078e3cff */
/*0570*/ LOP3.LUT R11, R12, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000c0b7a12 */
/* 0x000fe400078e3cff */
/*0580*/ IADD3 R18, R18, c[0x0][0x164], RZ ; /* 0x0000590012127a10 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3 R17, R17, c[0x0][0x168], RZ ; /* 0x00005a0011117a10 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD R10, R10, R11, R22 ; /* 0x0000000b0a0a7224 */
/* 0x000fe200078e0216 */
/*05b0*/ LOP3.LUT R13, R13, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000d0d7a12 */
/* 0x000fc400078e3cff */
/*05c0*/ LOP3.LUT R14, R14, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000e0e7a12 */
/* 0x000fe400078e3cff */
/*05d0*/ LOP3.LUT R11, R18, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900120b7a12 */
/* 0x000fe400078e3cff */
/*05e0*/ LOP3.LUT R17, R17, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0011117a12 */
/* 0x000fe200078e3cff */
/*05f0*/ IMAD R10, R13, R14, R10 ; /* 0x0000000e0d0a7224 */
/* 0x000fc800078e020a */
/*0600*/ IMAD R11, R11, R17, R10 ; /* 0x000000110b0b7224 */
/* 0x000fe200078e020a */
/*0610*/ @!P0 BRA 0x300 ; /* 0xfffffce000008947 */
/* 0x000fea000383ffff */
/*0620*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0630*/ STS [R0.X4], R11 ; /* 0x0000000b00007388 */
/* 0x0001e40000004800 */
/*0640*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0650*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0660*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0670*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0680*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0690*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*06a0*/ @!P1 BRA 0x760 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.U32 R5, RZ, RZ, UR4 ; /* 0x00000004ff057e24 */
/* 0x000fca000f8e00ff */
/*06c0*/ ISETP.GE.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f26270 */
/*06d0*/ @!P1 IMAD R2, R5, 0x4, R4 ; /* 0x0000000405029824 */
/* 0x000fe200078e0204 */
/*06e0*/ @!P1 LDS R6, [R0.X4] ; /* 0x0000000000069984 */
/* 0x000fe20000004800 */
/*06f0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011605 */
/*0700*/ @!P1 LDS R7, [R2] ; /* 0x0000000002079984 */
/* 0x000e240000000800 */
/*0710*/ @!P1 IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106079824 */
/* 0x001fca00078e0207 */
/*0720*/ @!P1 STS [R0.X4], R7 ; /* 0x0000000700009388 */
/* 0x0001e80000004800 */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0740*/ ISETP.NE.AND P1, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f25270 */
/*0750*/ @P1 BRA 0x6c0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0760*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0770*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0790*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*07a0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*07b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*07c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07d0*/ BRA 0x7d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3mulijjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x650 ; /* 0x0000061000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0060*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD.SHL.U32 R2, R0, 0x10, RZ ; /* 0x0000001000027824 */
/* 0x000fca00078e00ff */
/*0080*/ IADD3 R3, R2, 0x10, RZ ; /* 0x0000001002037810 */
/* 0x000fc80007ffe0ff */
/*0090*/ IMNMX R3, R3, c[0x0][0x160], PT ; /* 0x0000580003037a17 */
/* 0x000fc80003800200 */
/*00a0*/ ISETP.GE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fda0003f06270 */
/*00b0*/ @P0 BRA 0x640 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ IADD3 R3, -R2, -0x11, RZ ; /* 0xffffffef02037810 */
/* 0x000fe20007ffe1ff */
/*00e0*/ ULOP3.LUT UR4, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f047292 */
/* 0x000fe2000f8e333f */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1f ; /* 0x0000001fff077424 */
/* 0x000fe200078e00ff */
/*0100*/ BSSY B1, 0x540 ; /* 0x0000043000017945 */
/* 0x000fe20003800000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0120*/ IMNMX R3, R3, UR4, !PT ; /* 0x0000000403037c17 */
/* 0x000fc8000f800200 */
/*0130*/ IADD3 R4, -R2, -0x2, -R3 ; /* 0xfffffffe02047810 */
/* 0x000fe40007ffe903 */
/*0140*/ LOP3.LUT R5, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff057212 */
/* 0x000fe400078e33ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fc60003f26070 */
/*0160*/ IMAD.IADD R8, R5, 0x1, -R2 ; /* 0x0000000105087824 */
/* 0x000fe200078e0a02 */
/*0170*/ LOP3.LUT R5, R7.reuse, c[0x0][0x164], RZ, 0xc0, !PT ; /* 0x0000590007057a12 */
/* 0x040fe400078ec0ff */
/*0180*/ LOP3.LUT R7, R7, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0007077a12 */
/* 0x000fe400078ec0ff */
/*0190*/ LOP3.LUT R3, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308037812 */
/* 0x000fe400078ec0ff */
/*01a0*/ IADD3 R9, -R5, 0x20, RZ ; /* 0x0000002005097810 */
/* 0x000fe40007ffe1ff */
/*01b0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*01c0*/ IADD3 R11, -R7, 0x20, RZ ; /* 0x00000020070b7810 */
/* 0x000fe20007ffe1ff */
/*01d0*/ @!P1 BRA 0x530 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.IADD R4, R8, 0x1, -R3 ; /* 0x0000000108047824 */
/* 0x000fe400078e0a03 */
/*01f0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0200*/ SHF.R.U32.HI R8, RZ, R9, R2 ; /* 0x00000009ff087219 */
/* 0x000fe40000011602 */
/*0210*/ SHF.L.U32 R13, R2, R5, RZ ; /* 0x00000005020d7219 */
/* 0x000fc400000006ff */
/*0220*/ IADD3 R12, R2.reuse, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x040fe40007ffe0ff */
/*0230*/ SHF.R.U32.HI R10, RZ, R11, R2 ; /* 0x0000000bff0a7219 */
/* 0x000fe40000011602 */
/*0240*/ SHF.L.U32 R15, R2, R7, RZ ; /* 0x00000007020f7219 */
/* 0x000fe400000006ff */
/*0250*/ LOP3.LUT R13, R8, R13, RZ, 0xfc, !PT ; /* 0x0000000d080d7212 */
/* 0x000fe400078efcff */
/*0260*/ SHF.L.U32 R8, R12, R5, RZ ; /* 0x000000050c087219 */
/* 0x000fe400000006ff */
/*0270*/ SHF.R.U32.HI R17, RZ, R9, R12 ; /* 0x00000009ff117219 */
/* 0x000fc4000001160c */
/*0280*/ SHF.L.U32 R14, R12, R7, RZ ; /* 0x000000070c0e7219 */
/* 0x000fe400000006ff */
/*0290*/ SHF.R.U32.HI R19, RZ, R11, R12 ; /* 0x0000000bff137219 */
/* 0x000fe4000001160c */
/*02a0*/ LOP3.LUT R15, R10, R15, RZ, 0xfc, !PT ; /* 0x0000000f0a0f7212 */
/* 0x000fe400078efcff */
/*02b0*/ IADD3 R12, R2, 0x2, RZ ; /* 0x00000002020c7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ LOP3.LUT R8, R17, R8, RZ, 0xfc, !PT ; /* 0x0000000811087212 */
/* 0x000fe400078efcff */
/*02d0*/ LOP3.LUT R10, R19, R14, RZ, 0xfc, !PT ; /* 0x0000000e130a7212 */
/* 0x000fc400078efcff */
/*02e0*/ IADD3 R18, R2, 0x3, RZ ; /* 0x0000000302127810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ SHF.L.U32 R14, R12.reuse, R5, RZ ; /* 0x000000050c0e7219 */
/* 0x040fe400000006ff */
/*0300*/ SHF.R.U32.HI R17, RZ, R9, R12.reuse ; /* 0x00000009ff117219 */
/* 0x100fe4000001160c */
/*0310*/ SHF.L.U32 R16, R12, R7, RZ ; /* 0x000000070c107219 */
/* 0x000fe400000006ff */
/*0320*/ SHF.R.U32.HI R19, RZ, R11, R12 ; /* 0x0000000bff137219 */
/* 0x000fe4000001160c */
/*0330*/ IADD3 R13, R13, c[0x0][0x164], RZ ; /* 0x000059000d0d7a10 */
/* 0x000fc40007ffe0ff */
/*0340*/ IADD3 R15, R15, c[0x0][0x168], RZ ; /* 0x00005a000f0f7a10 */
/* 0x000fe40007ffe0ff */
/*0350*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0360*/ SHF.L.U32 R12, R18.reuse, R5, RZ ; /* 0x00000005120c7219 */
/* 0x040fe400000006ff */
/*0370*/ SHF.R.U32.HI R21, RZ, R9, R18.reuse ; /* 0x00000009ff157219 */
/* 0x100fe40000011612 */
/*0380*/ SHF.L.U32 R20, R18, R7, RZ ; /* 0x0000000712147219 */
/* 0x000fe400000006ff */
/*0390*/ SHF.R.U32.HI R23, RZ, R11, R18 ; /* 0x0000000bff177219 */
/* 0x000fc40000011612 */
/*03a0*/ LOP3.LUT R13, R13, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000d0d7a12 */
/* 0x000fe400078e3cff */
/*03b0*/ LOP3.LUT R15, R15, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000f0f7a12 */
/* 0x000fe400078e3cff */
/*03c0*/ LOP3.LUT R14, R17, R14, RZ, 0xfc, !PT ; /* 0x0000000e110e7212 */
/* 0x000fe400078efcff */
/*03d0*/ LOP3.LUT R16, R19, R16, RZ, 0xfc, !PT ; /* 0x0000001013107212 */
/* 0x000fe200078efcff */
/*03e0*/ IMAD R13, R13, R15, R6 ; /* 0x0000000f0d0d7224 */
/* 0x000fe200078e0206 */
/*03f0*/ IADD3 R8, R8, c[0x0][0x164], RZ ; /* 0x0000590008087a10 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R10, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0a7a10 */
/* 0x000fc40007ffe0ff */
/*0410*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0420*/ LOP3.LUT R12, R21, R12, RZ, 0xfc, !PT ; /* 0x0000000c150c7212 */
/* 0x000fe400078efcff */
/*0430*/ LOP3.LUT R20, R23, R20, RZ, 0xfc, !PT ; /* 0x0000001417147212 */
/* 0x000fe400078efcff */
/*0440*/ IADD3 R14, R14, c[0x0][0x164], RZ ; /* 0x000059000e0e7a10 */
/* 0x000fe40007ffe0ff */
/*0450*/ IADD3 R16, R16, c[0x0][0x168], RZ ; /* 0x00005a0010107a10 */
/* 0x000fe40007ffe0ff */
/*0460*/ LOP3.LUT R8, R8, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x0000590008087a12 */
/* 0x000fc400078e3cff */
/*0470*/ LOP3.LUT R10, R10, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a000a0a7a12 */
/* 0x000fe400078e3cff */
/*0480*/ IADD3 R12, R12, c[0x0][0x164], RZ ; /* 0x000059000c0c7a10 */
/* 0x000fe40007ffe0ff */
/*0490*/ IADD3 R20, R20, c[0x0][0x168], RZ ; /* 0x00005a0014147a10 */
/* 0x000fe20007ffe0ff */
/*04a0*/ IMAD R8, R8, R10, R13 ; /* 0x0000000a08087224 */
/* 0x000fe200078e020d */
/*04b0*/ LOP3.LUT R15, R14, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000e0f7a12 */
/* 0x000fe400078e3cff */
/*04c0*/ LOP3.LUT R16, R16, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0010107a12 */
/* 0x000fe400078e3cff */
/*04d0*/ LOP3.LUT R13, R12, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x000059000c0d7a12 */
/* 0x000fc400078e3cff */
/*04e0*/ LOP3.LUT R20, R20, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0014147a12 */
/* 0x000fe200078e3cff */
/*04f0*/ IMAD R8, R15, R16, R8 ; /* 0x000000100f087224 */
/* 0x000fe200078e0208 */
/*0500*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0510*/ IMAD R6, R13, R20, R8 ; /* 0x000000140d067224 */
/* 0x000fe200078e0208 */
/*0520*/ @P1 BRA 0x200 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ @!P0 BRA 0x640 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0550*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0560*/ SHF.R.U32.HI R4, RZ, R9, R2.reuse ; /* 0x00000009ff047219 */
/* 0x100fe40000011602 */
/*0570*/ SHF.L.U32 R13, R2.reuse, R5, RZ ; /* 0x00000005020d7219 */
/* 0x040fe400000006ff */
/*0580*/ SHF.R.U32.HI R8, RZ, R11, R2 ; /* 0x0000000bff087219 */
/* 0x000fe40000011602 */
/*0590*/ SHF.L.U32 R15, R2, R7, RZ ; /* 0x00000007020f7219 */
/* 0x000fe400000006ff */
/*05a0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc40003f05270 */
/*05b0*/ LOP3.LUT R4, R4, R13, RZ, 0xfc, !PT ; /* 0x0000000d04047212 */
/* 0x000fe400078efcff */
/*05c0*/ LOP3.LUT R8, R8, R15, RZ, 0xfc, !PT ; /* 0x0000000f08087212 */
/* 0x000fe400078efcff */
/*05d0*/ IADD3 R4, R4, c[0x0][0x164], RZ ; /* 0x0000590004047a10 */
/* 0x000fe40007ffe0ff */
/*05e0*/ IADD3 R8, R8, c[0x0][0x168], RZ ; /* 0x00005a0008087a10 */
/* 0x000fe40007ffe0ff */
/*05f0*/ LOP3.LUT R13, R4, c[0x0][0x164], RZ, 0x3c, !PT ; /* 0x00005900040d7a12 */
/* 0x000fe400078e3cff */
/*0600*/ LOP3.LUT R8, R8, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0008087a12 */
/* 0x000fc400078e3cff */
/*0610*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc60007ffe0ff */
/*0620*/ IMAD R6, R13, R8, R6 ; /* 0x000000080d067224 */
/* 0x000fe200078e0206 */
/*0630*/ @P0 BRA 0x550 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0640*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0660*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0670*/ STG.E [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101906 */
/*0680*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0690*/ BRA 0x690; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulijjPj
.globl _Z3mulijjPj
.p2align 8
.type _Z3mulijjPj,@function
_Z3mulijjPj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_lshlrev_b32_e32 v2, 4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, 16, v2
v_min_i32_e32 v3, s3, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e64 v2, v3
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x4
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s6, 0, s2
s_sub_i32 s7, 0, s3
.LBB0_2:
v_alignbit_b32 v4, v2, v2, s6
v_alignbit_b32 v5, v2, v2, s7
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, s2, v4
v_add_nc_u32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v2, v3
v_xor_b32_e32 v6, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v7, s3, v5
s_or_b32 s5, vcc_lo, s5
v_mad_u64_u32 v[4:5], null, v6, v7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v4
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulijjPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulijjPj, .Lfunc_end0-_Z3mulijjPj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10mul_reduceijjPj
.globl _Z10mul_reduceijjPj
.p2align 8
.type _Z10mul_reduceijjPj,@function
_Z10mul_reduceijjPj:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
v_lshlrev_b32_e32 v4, 2, v0
s_mov_b32 s2, s15
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s3
v_add_lshl_u32 v5, s5, v0, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, 16, v5
v_min_i32_e32 v6, s4, v1
v_mov_b32_e32 v1, 0
ds_store_b32 v4, v1
v_cmpx_lt_i32_e64 v5, v6
s_cbranch_execz .LBB1_4
s_load_b64 s[4:5], s[0:1], 0x4
ds_load_b32 v1, v4
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, 0, s4
s_sub_i32 s9, 0, s5
.LBB1_2:
v_alignbit_b32 v2, v5, v5, s8
v_alignbit_b32 v3, v5, v5, s9
v_add_nc_u32_e32 v5, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, s4, v2
v_add_nc_u32_e32 v3, s5, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v5, v6
v_xor_b32_e32 v7, s4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, s5, v3
s_or_b32 s7, vcc_lo, s7
v_mad_u64_u32 v[2:3], null, v7, v8, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v1, v2
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s7
ds_store_b32 v4, v2
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
s_cmp_lt_u32 s3, 2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_6:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_9
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_5
v_add_lshl_u32 v1, s4, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v2, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
ds_store_b32 v4, v1
s_branch .LBB1_5
.LBB1_9:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB1_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mul_reduceijjPj
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10mul_reduceijjPj, .Lfunc_end1-_Z10mul_reduceijjPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulijjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulijjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mul_reduceijjPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10mul_reduceijjPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bb70d_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11rotate_leftjj
.type _Z11rotate_leftjj, @function
_Z11rotate_leftjj:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z11rotate_leftjj, .-_Z11rotate_leftjj
.globl _Z7encryptjj
.type _Z7encryptjj, @function
_Z7encryptjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z7encryptjj, .-_Z7encryptjj
.globl _Z7divCeilii
.type _Z7divCeilii, @function
_Z7divCeilii:
.LFB2060:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
imull %eax, %esi
cmpl %edi, %esi
setl %dl
movzbl %dl, %edx
addl %edx, %eax
ret
.cfi_endproc
.LFE2060:
.size _Z7divCeilii, .-_Z7divCeilii
.globl _Z25__device_stub__Z3mulijjPjijjPj
.type _Z25__device_stub__Z3mulijjPjijjPj, @function
_Z25__device_stub__Z3mulijjPjijjPj:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulijjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z25__device_stub__Z3mulijjPjijjPj, .-_Z25__device_stub__Z3mulijjPjijjPj
.globl _Z3mulijjPj
.type _Z3mulijjPj, @function
_Z3mulijjPj:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3mulijjPjijjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z3mulijjPj, .-_Z3mulijjPj
.globl _Z33__device_stub__Z10mul_reduceijjPjijjPj
.type _Z33__device_stub__Z10mul_reduceijjPjijjPj, @function
_Z33__device_stub__Z10mul_reduceijjPjijjPj:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mul_reduceijjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z10mul_reduceijjPjijjPj, .-_Z33__device_stub__Z10mul_reduceijjPjijjPj
.globl _Z10mul_reduceijjPj
.type _Z10mul_reduceijjPj, @function
_Z10mul_reduceijjPj:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mul_reduceijjPjijjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10mul_reduceijjPj, .-_Z10mul_reduceijjPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/George0828Zhang/cuda-practice/main/DotProduct/main.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.LC2:
.string "%u\n"
.LC3:
.string "%d %u %u"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq .LC3(%rip), %r12
testl %eax, %eax
jne .L40
.L26:
leaq 20(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $3, %eax
jne .L41
movl $16, %esi
movl 12(%rsp), %edi
call _Z7divCeilii
movl %eax, %edi
movl $256, %esi
call _Z7divCeilii
movl %eax, %ebp
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L27:
call cudaPeekAtLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L44
movslq %ebp, %rdx
leaq 0(,%rdx,4), %r13
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
leaq C(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L30
leaq C(%rip), %rax
leaq 0(%r13,%rax), %rdx
testl %ebp, %ebp
jle .L32
.L33:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L32:
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L40:
movl %eax, %ebx
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $84, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L42:
movq 24(%rsp), %rcx
movl 20(%rsp), %edx
movl 16(%rsp), %esi
movl 12(%rsp), %edi
call _Z33__device_stub__Z10mul_reduceijjPjijjPj
jmp .L27
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $90, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $91, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $94, %r9d
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L41:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L45
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10mul_reduceijjPj"
.LC5:
.string "_Z3mulijjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mul_reduceijjPj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulijjPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl C
.bss
.align 32
.type C, @object
.size C, 67108864
C:
.zero 67108864
.globl B
.align 32
.type B, @object
.size B, 67108864
B:
.zero 67108864
.globl A
.align 32
.type A, @object
.size A, 67108864
A:
.zero 67108864
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__mulijjPj # -- Begin function _Z18__device_stub__mulijjPj
.p2align 4, 0x90
.type _Z18__device_stub__mulijjPj,@function
_Z18__device_stub__mulijjPj: # @_Z18__device_stub__mulijjPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulijjPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__mulijjPj, .Lfunc_end0-_Z18__device_stub__mulijjPj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mul_reduceijjPj # -- Begin function _Z25__device_stub__mul_reduceijjPj
.p2align 4, 0x90
.type _Z25__device_stub__mul_reduceijjPj,@function
_Z25__device_stub__mul_reduceijjPj: # @_Z25__device_stub__mul_reduceijjPj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mul_reduceijjPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__mul_reduceijjPj, .Lfunc_end1-_Z25__device_stub__mul_reduceijjPj
.cfi_endproc
# -- End function
.globl _Z7divCeilii # -- Begin function _Z7divCeilii
.p2align 4, 0x90
.type _Z7divCeilii,@function
_Z7divCeilii: # @_Z7divCeilii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
imull %eax, %esi
xorl %ecx, %ecx
cmpl %edi, %esi
setl %cl
addl %ecx, %eax
retq
.Lfunc_end2:
.size _Z7divCeilii, .Lfunc_end2-_Z7divCeilii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
testl %eax, %eax
jne .LBB3_7
# %bb.1: # %_Z9gpuAssert10hipError_tPKcib.exit.preheader
leaq 4(%rsp), %rsi
leaq 12(%rsp), %rdx
leaq 8(%rsp), %rcx
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $3, %eax
jne .LBB3_15
# %bb.2: # %.lr.ph29
movabsq $4294967296, %rax # imm = 0x100000000
leaq 256(%rax), %rbx
leaq 4(%rsp), %r14
leaq 12(%rsp), %r15
leaq 8(%rsp), %r12
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
xorl %esi, %esi
.LBB3_14: # %_Z9gpuAssert10hipError_tPKcib.exit
# in Loop: Header=BB3_3 Depth=1
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movq %r14, %rsi
movq %r15, %rdx
movq %r12, %rcx
xorl %eax, %eax
callq __isoc23_scanf
cmpl $3, %eax
jne .LBB3_15
.LBB3_3: # =>This Loop Header: Depth=1
# Child Loop BB3_17 Depth 2
movl 4(%rsp), %eax
leal 15(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
movl %ecx, %edx
sarl $4, %edx
andl $-16, %ecx
xorl %esi, %esi
cmpl %eax, %ecx
setl %sil
leal (%rdx,%rsi), %eax
addl $255, %eax
movl %edx, %ecx
addl %esi, %ecx
cmovnsl %ecx, %eax
movl %eax, %edx
sarl $8, %edx
andl $-256, %eax
xorl %ebp, %ebp
cmpl %ecx, %eax
setl %bpl
addl %edx, %ebp
movq %rbp, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movl 4(%rsp), %eax
movl 12(%rsp), %ecx
movl 8(%rsp), %edx
movq 16(%rsp), %rsi
movl %eax, 36(%rsp)
movl %ecx, 32(%rsp)
movl %edx, 28(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z10mul_reduceijjPj, %edi
leaq 96(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB3_6
# %bb.9: # %_Z9gpuAssert10hipError_tPKcib.exit14
# in Loop: Header=BB3_3 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB3_10
# %bb.11: # %_Z9gpuAssert10hipError_tPKcib.exit16
# in Loop: Header=BB3_3 Depth=1
movq 16(%rsp), %rsi
movslq %ebp, %rdx
shlq $2, %rdx
movl $C, %edi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_18
# %bb.12: # %_Z9gpuAssert10hipError_tPKcib.exit18.preheader
# in Loop: Header=BB3_3 Depth=1
testl %ebp, %ebp
jle .LBB3_13
# %bb.16: # %_Z9gpuAssert10hipError_tPKcib.exit18.preheader30
# in Loop: Header=BB3_3 Depth=1
movl %ebp, %eax
shlq $2, %rax
xorl %ecx, %ecx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_17: # %_Z9gpuAssert10hipError_tPKcib.exit18
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
addl C(%rcx), %esi
addq $4, %rcx
cmpq %rcx, %rax
jne .LBB3_17
jmp .LBB3_14
.LBB3_15: # %_Z9gpuAssert10hipError_tPKcib.exit._crit_edge
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_18:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB3_8
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
.LBB3_8:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.LBB3_6:
movl %eax, %r13d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %r8d
xorl %eax, %eax
callq fprintf
movl %r13d, %edi
callq exit
.LBB3_7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $86, %r8d
jmp .LBB3_8
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulijjPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mul_reduceijjPj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type A,@object # @A
.bss
.globl A
.p2align 4, 0x0
A:
.zero 67108864
.size A, 67108864
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 67108864
.size B, 67108864
.type C,@object # @C
.globl C
.p2align 4, 0x0
C:
.zero 67108864
.size C, 67108864
.type _Z3mulijjPj,@object # @_Z3mulijjPj
.section .rodata,"a",@progbits
.globl _Z3mulijjPj
.p2align 3, 0x0
_Z3mulijjPj:
.quad _Z18__device_stub__mulijjPj
.size _Z3mulijjPj, 8
.type _Z10mul_reduceijjPj,@object # @_Z10mul_reduceijjPj
.globl _Z10mul_reduceijjPj
.p2align 3, 0x0
_Z10mul_reduceijjPj:
.quad _Z25__device_stub__mul_reduceijjPj
.size _Z10mul_reduceijjPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/George0828Zhang/cuda-practice/main/DotProduct/main.hip"
.size .L.str, 112
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %u %u"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%u\n"
.size .L.str.2, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.3, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulijjPj"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10mul_reduceijjPj"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulijjPj
.addrsig_sym _Z25__device_stub__mul_reduceijjPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym C
.addrsig_sym _Z3mulijjPj
.addrsig_sym _Z10mul_reduceijjPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} | code for sm_80
Function : _Z16sigmoidDeriv_f32PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ UMOV UR4, 0x3f000000 ; /* 0x3f00000000047882 */
/* 0x000fe20000000000 */
/*00b0*/ BSSY B1, 0x1d0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe2000f8e00ff */
/*00d0*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSEL R4, -R2, R2, !P0 ; /* 0x0000000202047208 */
/* 0x000fca0004000100 */
/*00f0*/ FADD R4, R4, 1 ; /* 0x3f80000004047421 */
/* 0x000fc80000000000 */
/*0100*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*0110*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e300000001000 */
/*0120*/ FCHK P0, -R7, R4 ; /* 0x0000000407007302 */
/* 0x000e620000000100 */
/*0130*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*0140*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*0150*/ FFMA R3, R6, -0.5, RZ ; /* 0xbf00000006037823 */
/* 0x000fc800000000ff */
/*0160*/ FFMA R2, -R4, R3, -0.5 ; /* 0xbf00000004027423 */
/* 0x000fc80000000103 */
/*0170*/ FFMA R5, R6, R2, R3 ; /* 0x0000000206057223 */
/* 0x000fe20000000003 */
/*0180*/ @!P0 BRA 0x1c0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0190*/ MOV R2, 0x1b0 ; /* 0x000001b000027802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x210 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0006 */
/*01c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0220*/ BSSY B0, 0x7f0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B2, 0x3e0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0250*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc800078ec0ff */
/*0260*/ IADD3 R7, R3, -0x1, RZ ; /* 0xffffffff03077810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fda0003f04070 */
/*0280*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x3d0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*02b0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*02c0*/ @P0 BRA 0x7d0 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x41000000 ; /* 0xbf000000ff057424 */
/* 0x000fca00078e00ff */
/*02e0*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*02f0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0300*/ @!P0 BRA 0x7b0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0320*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0340*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0350*/ @P0 BRA 0x790 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0370*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 BRA 0x760 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd800078e00ff */
/*03b0*/ @!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004068823 */
/* 0x000fe200000000ff */
/*03c0*/ @!P0 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008088810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03e0*/ LEA R5, R3, 0xc0800000, 0x17 ; /* 0xc080000003057811 */
/* 0x000fe200078eb8ff */
/*03f0*/ UMOV UR4, 0xbf000000 ; /* 0xbf00000000047882 */
/* 0x000fe20000000000 */
/*0400*/ IADD3 R3, R8, 0x7e, -R3 ; /* 0x0000007e08037810 */
/* 0x000fe20007ffe803 */
/*0410*/ UIADD3 UR4, UR4, 0x800000, URZ ; /* 0x0080000004047890 */
/* 0x000fe2000fffe03f */
/*0420*/ BSSY B2, 0x750 ; /* 0x0000032000027945 */
/* 0x000fe20003800000 */
/*0430*/ IMAD.IADD R5, R6, 0x1, -R5 ; /* 0x0000000106057824 */
/* 0x000fc800078e0a05 */
/*0440*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*0450*/ FADD.FTZ R7, -R5, -RZ ; /* 0x800000ff05077221 */
/* 0x000fc80000010100 */
/*0460*/ FFMA R9, R4, R7, 1 ; /* 0x3f80000004097423 */
/* 0x001fc80000000007 */
/*0470*/ FFMA R10, R4, R9, R4 ; /* 0x00000009040a7223 */
/* 0x000fc80000000004 */
/*0480*/ FFMA R4, R10, UR4, RZ ; /* 0x000000040a047c23 */
/* 0x000fc800080000ff */
/*0490*/ FFMA R9, R7, R4, UR4 ; /* 0x0000000407097e23 */
/* 0x000fc80008000004 */
/*04a0*/ FFMA R9, R10, R9, R4 ; /* 0x000000090a097223 */
/* 0x000fc80000000004 */
/*04b0*/ FFMA R7, R7, R9, UR4 ; /* 0x0000000407077e23 */
/* 0x000fc80008000009 */
/*04c0*/ FFMA R6, R10, R7, R9 ; /* 0x000000070a067223 */
/* 0x000fca0000000009 */
/*04d0*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fc80000011606 */
/*04e0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*04f0*/ IMAD.IADD R11, R4, 0x1, R3 ; /* 0x00000001040b7824 */
/* 0x000fca00078e0203 */
/*0500*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0520*/ @!P0 BRA 0x730 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0540*/ @P0 BRA 0x700 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0560*/ @P0 BRA 0x740 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0580*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0590*/ @!P0 BRA 0x740 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FFMA.RZ R3, R10.reuse, R7.reuse, R9.reuse ; /* 0x000000070a037223 */
/* 0x1c0fe2000000c009 */
/*05b0*/ IADD3 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x040fe20007ffe0ff */
/*05c0*/ FFMA.RM R4, R10.reuse, R7.reuse, R9.reuse ; /* 0x000000070a047223 */
/* 0x1c0fe20000004009 */
/*05d0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*05e0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*05f0*/ FFMA.RP R3, R10, R7, R9 ; /* 0x000000070a037223 */
/* 0x000fe20000008009 */
/*0600*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0610*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0620*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*0630*/ FSETP.NEU.FTZ.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fc40003f1d000 */
/*0640*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*0650*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0660*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0670*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0690*/ SHF.R.U32.HI R8, RZ, 0x1, R4 ; /* 0x00000001ff087819 */
/* 0x000fc40000011604 */
/*06a0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*06b0*/ LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef808 */
/*06c0*/ LOP3.LUT R3, R3, R4, RZ, 0xc0, !PT ; /* 0x0000000403037212 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R3, R8, 0x1, R3 ; /* 0x0000000108037824 */
/* 0x000fca00078e0203 */
/*06e0*/ LOP3.LUT R6, R3, R6, RZ, 0xfc, !PT ; /* 0x0000000603067212 */
/* 0x000fe200078efcff */
/*06f0*/ BRA 0x740 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0700*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0710*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x740 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD R6, R3, 0x800000, R6 ; /* 0x0080000003067824 */
/* 0x000fe400078e0206 */
/*0740*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x7e0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078e4805 */
/*0770*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078e4805 */
/*07a0*/ BRA 0x7e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07b0*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*07c0*/ BRA 0x7e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07d0*/ FADD.FTZ R6, R4, -0.5 ; /* 0xbf00000004067421 */
/* 0x000fe40000010000 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0800*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7f002007950 */
/* 0x000fea0003c3ffff */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} | .file "tmpxft_0007bc88_00000000-6_sigmoidDeriv_f32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
.type _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i, @function
_Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sigmoidDeriv_f32PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i, .-_Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
.globl _Z16sigmoidDeriv_f32PfS_i
.type _Z16sigmoidDeriv_f32PfS_i, @function
_Z16sigmoidDeriv_f32PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sigmoidDeriv_f32PfS_i, .-_Z16sigmoidDeriv_f32PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16sigmoidDeriv_f32PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sigmoidDeriv_f32PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sigmoidDeriv_f32PfS_i
.globl _Z16sigmoidDeriv_f32PfS_i
.p2align 8
.type _Z16sigmoidDeriv_f32PfS_i,@function
_Z16sigmoidDeriv_f32PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, v2, -v2, vcc_lo
v_add_f32_e32 v2, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_div_scale_f32 v3, null, v2, v2, -0.5
v_div_scale_f32 v6, vcc_lo, -0.5, v2, -0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v2, v3, v2, -0.5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sigmoidDeriv_f32PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sigmoidDeriv_f32PfS_i, .Lfunc_end0-_Z16sigmoidDeriv_f32PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sigmoidDeriv_f32PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sigmoidDeriv_f32PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sigmoidDeriv_f32 (float* vector, float* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
float tmp = 1.0 + (vector[idx] < 0.0 ? -vector[idx] : vector[idx]); output[idx] = - 0.5 / (tmp*tmp);
}
} | .text
.file "sigmoidDeriv_f32.hip"
.globl _Z31__device_stub__sigmoidDeriv_f32PfS_i # -- Begin function _Z31__device_stub__sigmoidDeriv_f32PfS_i
.p2align 4, 0x90
.type _Z31__device_stub__sigmoidDeriv_f32PfS_i,@function
_Z31__device_stub__sigmoidDeriv_f32PfS_i: # @_Z31__device_stub__sigmoidDeriv_f32PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sigmoidDeriv_f32PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__sigmoidDeriv_f32PfS_i, .Lfunc_end0-_Z31__device_stub__sigmoidDeriv_f32PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sigmoidDeriv_f32PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sigmoidDeriv_f32PfS_i,@object # @_Z16sigmoidDeriv_f32PfS_i
.section .rodata,"a",@progbits
.globl _Z16sigmoidDeriv_f32PfS_i
.p2align 3, 0x0
_Z16sigmoidDeriv_f32PfS_i:
.quad _Z31__device_stub__sigmoidDeriv_f32PfS_i
.size _Z16sigmoidDeriv_f32PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sigmoidDeriv_f32PfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sigmoidDeriv_f32PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sigmoidDeriv_f32PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16sigmoidDeriv_f32PfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ UMOV UR4, 0x3f000000 ; /* 0x3f00000000047882 */
/* 0x000fe20000000000 */
/*00b0*/ BSSY B1, 0x1d0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x000fe2000f8e00ff */
/*00d0*/ FSETP.GEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f0e000 */
/*00e0*/ FSEL R4, -R2, R2, !P0 ; /* 0x0000000202047208 */
/* 0x000fca0004000100 */
/*00f0*/ FADD R4, R4, 1 ; /* 0x3f80000004047421 */
/* 0x000fc80000000000 */
/*0100*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*0110*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x000e300000001000 */
/*0120*/ FCHK P0, -R7, R4 ; /* 0x0000000407007302 */
/* 0x000e620000000100 */
/*0130*/ FFMA R6, -R4, R5, 1 ; /* 0x3f80000004067423 */
/* 0x001fc80000000105 */
/*0140*/ FFMA R6, R5, R6, R5 ; /* 0x0000000605067223 */
/* 0x000fc80000000005 */
/*0150*/ FFMA R3, R6, -0.5, RZ ; /* 0xbf00000006037823 */
/* 0x000fc800000000ff */
/*0160*/ FFMA R2, -R4, R3, -0.5 ; /* 0xbf00000004027423 */
/* 0x000fc80000000103 */
/*0170*/ FFMA R5, R6, R2, R3 ; /* 0x0000000206057223 */
/* 0x000fe20000000003 */
/*0180*/ @!P0 BRA 0x1c0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0190*/ MOV R2, 0x1b0 ; /* 0x000001b000027802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x210 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0006 */
/*01c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0220*/ BSSY B0, 0x7f0 ; /* 0x000005c000007945 */
/* 0x000fe20003800000 */
/*0230*/ BSSY B2, 0x3e0 ; /* 0x000001a000027945 */
/* 0x000fe20003800000 */
/*0240*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*0250*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fc800078ec0ff */
/*0260*/ IADD3 R7, R3, -0x1, RZ ; /* 0xffffffff03077810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GT.U32.AND P0, PT, R7, 0xfd, PT ; /* 0x000000fd0700780c */
/* 0x000fda0003f04070 */
/*0280*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff088224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x3d0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*02b0*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*02c0*/ @P0 BRA 0x7d0 ; /* 0x0000050000000947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.MOV.U32 R5, RZ, RZ, -0x41000000 ; /* 0xbf000000ff057424 */
/* 0x000fca00078e00ff */
/*02e0*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*02f0*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0300*/ @!P0 BRA 0x7b0 ; /* 0x000004a000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1d200 */
/*0320*/ LOP3.LUT P1, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000782c0ff */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0340*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0350*/ @P0 BRA 0x790 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c0ff */
/*0370*/ @!P0 BREAK B2 ; /* 0x0000000000028942 */
/* 0x000fe20003800000 */
/*0380*/ @!P0 BRA 0x760 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd800078e00ff */
/*03b0*/ @!P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004068823 */
/* 0x000fe200000000ff */
/*03c0*/ @!P0 IADD3 R8, R8, 0x40, RZ ; /* 0x0000004008088810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*03e0*/ LEA R5, R3, 0xc0800000, 0x17 ; /* 0xc080000003057811 */
/* 0x000fe200078eb8ff */
/*03f0*/ UMOV UR4, 0xbf000000 ; /* 0xbf00000000047882 */
/* 0x000fe20000000000 */
/*0400*/ IADD3 R3, R8, 0x7e, -R3 ; /* 0x0000007e08037810 */
/* 0x000fe20007ffe803 */
/*0410*/ UIADD3 UR4, UR4, 0x800000, URZ ; /* 0x0080000004047890 */
/* 0x000fe2000fffe03f */
/*0420*/ BSSY B2, 0x750 ; /* 0x0000032000027945 */
/* 0x000fe20003800000 */
/*0430*/ IMAD.IADD R5, R6, 0x1, -R5 ; /* 0x0000000106057824 */
/* 0x000fc800078e0a05 */
/*0440*/ MUFU.RCP R4, R5 ; /* 0x0000000500047308 */
/* 0x000e220000001000 */
/*0450*/ FADD.FTZ R7, -R5, -RZ ; /* 0x800000ff05077221 */
/* 0x000fc80000010100 */
/*0460*/ FFMA R9, R4, R7, 1 ; /* 0x3f80000004097423 */
/* 0x001fc80000000007 */
/*0470*/ FFMA R10, R4, R9, R4 ; /* 0x00000009040a7223 */
/* 0x000fc80000000004 */
/*0480*/ FFMA R4, R10, UR4, RZ ; /* 0x000000040a047c23 */
/* 0x000fc800080000ff */
/*0490*/ FFMA R9, R7, R4, UR4 ; /* 0x0000000407097e23 */
/* 0x000fc80008000004 */
/*04a0*/ FFMA R9, R10, R9, R4 ; /* 0x000000090a097223 */
/* 0x000fc80000000004 */
/*04b0*/ FFMA R7, R7, R9, UR4 ; /* 0x0000000407077e23 */
/* 0x000fc80008000009 */
/*04c0*/ FFMA R6, R10, R7, R9 ; /* 0x000000070a067223 */
/* 0x000fca0000000009 */
/*04d0*/ SHF.R.U32.HI R4, RZ, 0x17, R6 ; /* 0x00000017ff047819 */
/* 0x000fc80000011606 */
/*04e0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*04f0*/ IMAD.IADD R11, R4, 0x1, R3 ; /* 0x00000001040b7824 */
/* 0x000fca00078e0203 */
/*0500*/ IADD3 R4, R11, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x000fc80007ffe0ff */
/*0510*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0520*/ @!P0 BRA 0x730 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0540*/ @P0 BRA 0x700 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0550*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0560*/ @P0 BRA 0x740 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0580*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fd600078ec0ff */
/*0590*/ @!P0 BRA 0x740 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FFMA.RZ R3, R10.reuse, R7.reuse, R9.reuse ; /* 0x000000070a037223 */
/* 0x1c0fe2000000c009 */
/*05b0*/ IADD3 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087810 */
/* 0x040fe20007ffe0ff */
/*05c0*/ FFMA.RM R4, R10.reuse, R7.reuse, R9.reuse ; /* 0x000000070a047223 */
/* 0x1c0fe20000004009 */
/*05d0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*05e0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe200078ec0ff */
/*05f0*/ FFMA.RP R3, R10, R7, R9 ; /* 0x000000070a037223 */
/* 0x000fe20000008009 */
/*0600*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*0610*/ IMAD.MOV R7, RZ, RZ, -R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a0b */
/*0620*/ LOP3.LUT R5, R5, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000005057812 */
/* 0x000fe400078efcff */
/*0630*/ FSETP.NEU.FTZ.AND P0, PT, R3, R4, PT ; /* 0x000000040300720b */
/* 0x000fc40003f1d000 */
/*0640*/ SHF.L.U32 R8, R5, R8, RZ ; /* 0x0000000805087219 */
/* 0x000fe400000006ff */
/*0650*/ SEL R4, R7, RZ, P2 ; /* 0x000000ff07047207 */
/* 0x000fe40001000000 */
/*0660*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0670*/ SHF.R.U32.HI R4, RZ, R4, R5 ; /* 0x00000004ff047219 */
/* 0x000fe40000011605 */
/*0680*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0690*/ SHF.R.U32.HI R8, RZ, 0x1, R4 ; /* 0x00000001ff087819 */
/* 0x000fc40000011604 */
/*06a0*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fc80004000000 */
/*06b0*/ LOP3.LUT R3, R3, 0x1, R8, 0xf8, !PT ; /* 0x0000000103037812 */
/* 0x000fc800078ef808 */
/*06c0*/ LOP3.LUT R3, R3, R4, RZ, 0xc0, !PT ; /* 0x0000000403037212 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R3, R8, 0x1, R3 ; /* 0x0000000108037824 */
/* 0x000fca00078e0203 */
/*06e0*/ LOP3.LUT R6, R3, R6, RZ, 0xfc, !PT ; /* 0x0000000603067212 */
/* 0x000fe200078efcff */
/*06f0*/ BRA 0x740 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0700*/ LOP3.LUT R6, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078ec0ff */
/*0710*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x740 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD R6, R3, 0x800000, R6 ; /* 0x0080000003067824 */
/* 0x000fe400078e0206 */
/*0740*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x7e0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0760*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fc800078e4805 */
/*0770*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000006067812 */
/* 0x000fe200078efcff */
/*0780*/ BRA 0x7e0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R6, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006067812 */
/* 0x000fe200078e4805 */
/*07a0*/ BRA 0x7e0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07b0*/ MUFU.RSQ R6, -QNAN ; /* 0xffc0000000067908 */
/* 0x000e220000001400 */
/*07c0*/ BRA 0x7e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07d0*/ FADD.FTZ R6, R4, -0.5 ; /* 0xbf00000004067421 */
/* 0x000fe40000010000 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0800*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7f002007950 */
/* 0x000fea0003c3ffff */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16sigmoidDeriv_f32PfS_i
.globl _Z16sigmoidDeriv_f32PfS_i
.p2align 8
.type _Z16sigmoidDeriv_f32PfS_i,@function
_Z16sigmoidDeriv_f32PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, v2, -v2, vcc_lo
v_add_f32_e32 v2, 1.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v2
v_div_scale_f32 v3, null, v2, v2, -0.5
v_div_scale_f32 v6, vcc_lo, -0.5, v2, -0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_div_fixup_f32 v2, v3, v2, -0.5
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16sigmoidDeriv_f32PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16sigmoidDeriv_f32PfS_i, .Lfunc_end0-_Z16sigmoidDeriv_f32PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16sigmoidDeriv_f32PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16sigmoidDeriv_f32PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007bc88_00000000-6_sigmoidDeriv_f32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
.type _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i, @function
_Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16sigmoidDeriv_f32PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i, .-_Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
.globl _Z16sigmoidDeriv_f32PfS_i
.type _Z16sigmoidDeriv_f32PfS_i, @function
_Z16sigmoidDeriv_f32PfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16sigmoidDeriv_f32PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16sigmoidDeriv_f32PfS_i, .-_Z16sigmoidDeriv_f32PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16sigmoidDeriv_f32PfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16sigmoidDeriv_f32PfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sigmoidDeriv_f32.hip"
.globl _Z31__device_stub__sigmoidDeriv_f32PfS_i # -- Begin function _Z31__device_stub__sigmoidDeriv_f32PfS_i
.p2align 4, 0x90
.type _Z31__device_stub__sigmoidDeriv_f32PfS_i,@function
_Z31__device_stub__sigmoidDeriv_f32PfS_i: # @_Z31__device_stub__sigmoidDeriv_f32PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16sigmoidDeriv_f32PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__sigmoidDeriv_f32PfS_i, .Lfunc_end0-_Z31__device_stub__sigmoidDeriv_f32PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16sigmoidDeriv_f32PfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16sigmoidDeriv_f32PfS_i,@object # @_Z16sigmoidDeriv_f32PfS_i
.section .rodata,"a",@progbits
.globl _Z16sigmoidDeriv_f32PfS_i
.p2align 3, 0x0
_Z16sigmoidDeriv_f32PfS_i:
.quad _Z31__device_stub__sigmoidDeriv_f32PfS_i
.size _Z16sigmoidDeriv_f32PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16sigmoidDeriv_f32PfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__sigmoidDeriv_f32PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16sigmoidDeriv_f32PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "device_functions.h"
#include "device_launch_parameters.h"
#include <chrono>
#include <stdio.h> | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "device_functions.h"
#include "device_launch_parameters.h"
#include <chrono>
#include <stdio.h> | .file "tmpxft_000c395c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2158:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2158:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2181:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2181:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
#include "cuda_runtime.h"
#include "cuda_runtime_api.h"
#include "device_functions.h"
#include "device_launch_parameters.h"
#include <chrono>
#include <stdio.h> | #include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include "hip/device_functions.h"
#include <chrono>
#include <stdio.h> |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include "hip/device_functions.h"
#include <chrono>
#include <stdio.h> | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include "hip/device_functions.h"
#include <chrono>
#include <stdio.h> | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c395c_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2158:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2158:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2181:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2181:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=cudaSuccess)\
printf("error %s,at %d\n",cudaGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,curandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,curandState *states);
__global__ void g_S_init(int *S,int size,curandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
cudaError_t err;
curandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
cudaMalloc((curandState **)&states,sizeof(curandState)*nthreads);
cudaMalloc((T **)&dS,sizeof(T)*size);
cudaMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(cudaMemcpy(S,dS,sizeof(int)*size,cudaMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
cudaFree(states);
cudaFree(dS);
cudaFree(dE);
cudaDeviceReset();
}
__global__ void g_rand_init(int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
curand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(curand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = curand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} | code for sm_80
Function : _Z10g_simulateifPiS_iiP17curandStateXORWOWi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ BSSY B0, 0x940 ; /* 0x0000091000007945 */
/* 0x000fe60003800000 */
/*0030*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 BRA 0x930 ; /* 0x0000088000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.IADD R2, R5, 0x1, R0 ; /* 0x0000000105027824 */
/* 0x000fca00078e0200 */
/*00c0*/ LEA.HI R3, R2, R2, RZ, 0x1 ; /* 0x0000000202037211 */
/* 0x000fc800078f08ff */
/*00d0*/ LOP3.LUT R3, R3, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe03037812 */
/* 0x000fc800078ec0ff */
/*00e0*/ IADD3 R3, R2, -R3, RZ ; /* 0x8000000302037210 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.NE.AND P0, PT, R3, c[0x0][0x188], PT ; /* 0x0000620003007a0c */
/* 0x000fda0003f05270 */
/*0100*/ @P0 BRA 0x930 ; /* 0x0000082000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IMAD R15, R5, c[0x0][0x17c], R0 ; /* 0x00005f00050f7a24 */
/* 0x000fc800078e0200 */
/*0140*/ IMAD.WIDE R2, R15, R4, c[0x0][0x168] ; /* 0x00005a000f027625 */
/* 0x000fca00078e0204 */
/*0150*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f06270 */
/*0170*/ IMAD.WIDE R14, R15, R4, c[0x0][0x170] ; /* 0x00005c000f0e7625 */
/* 0x000fc600078e0204 */
/*0180*/ SEL R7, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005077a07 */
/* 0x000fc80000000000 */
/*0190*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fe400078e0200 */
/*01b0*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x004fe400078e0a06 */
/*01c0*/ IMAD.WIDE R6, R7, R4, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc600078e0204 */
/*01d0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e8000c101906 */
/*01e0*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x000fe8000c101906 */
/*01f0*/ LDG.E R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ee2000c1e1900 */
/*0210*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0220*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fc40000000800 */
/*0230*/ UIADD3 UR4, -UR4, URZ, URZ ; /* 0x0000003f04047290 */
/* 0x000fe2000fffe13f */
/*0240*/ SEL R10, R0, c[0x0][0x178], P0 ; /* 0x00005e00000a7a07 */
/* 0x000fca0000000000 */
/*0250*/ IMAD R10, R5, c[0x0][0x17c], R10 ; /* 0x00005f00050a7a24 */
/* 0x000fca00078e020a */
/*0260*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x001fe20007ffe0ff */
/*0270*/ IMAD R8, R8, UR4, RZ ; /* 0x0000000408087c24 */
/* 0x004fc8000f8e02ff */
/*0280*/ IMAD R11, R8, R7, RZ ; /* 0x00000007080b7224 */
/* 0x008fe400078e02ff */
/*0290*/ IMAD.WIDE R8, R9, R4, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc600078e0204 */
/*02a0*/ STG.E [R14.64], R11 ; /* 0x0000000b0e007986 */
/* 0x0001e8000c101906 */
/*02b0*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*02d0*/ IADD3 R7, R5, 0x1, RZ ; /* 0x0000000105077810 */
/* 0x000fc80007ffe0ff */
/*02e0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fc80003f06270 */
/*02f0*/ SEL R7, R7, RZ, !P0 ; /* 0x000000ff07077207 */
/* 0x000fca0004000000 */
/*0300*/ IMAD R7, R7, c[0x0][0x17c], R0 ; /* 0x00005f0007077a24 */
/* 0x000fe400078e0200 */
/*0310*/ IMAD R6, R6, UR4, RZ ; /* 0x0000000406067c24 */
/* 0x004fc8000f8e02ff */
/*0320*/ IMAD R13, R6, R8, R11 ; /* 0x00000008060d7224 */
/* 0x008fe400078e020b */
/*0330*/ IMAD.WIDE R6, R7, R4, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc600078e0204 */
/*0340*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0003e8000c101906 */
/*0350*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000e22000c1e1900 */
/*0370*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x000fc80003f06270 */
/*0390*/ SEL R8, R8, RZ, !P0 ; /* 0x000000ff08087207 */
/* 0x000fca0004000000 */
/*03a0*/ IMAD R9, R5, c[0x0][0x17c], R8 ; /* 0x00005f0005097a24 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc800078e0204 */
/*03c0*/ IMAD R10, R10, UR4, RZ ; /* 0x000000040a0a7c24 */
/* 0x004fc8000f8e02ff */
/*03d0*/ IMAD R11, R10, R6, R13 ; /* 0x000000060a0b7224 */
/* 0x001fca00078e020d */
/*03e0*/ STG.E [R14.64], R11 ; /* 0x0000000b0e007986 */
/* 0x0003e8000c101906 */
/*03f0*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R8, [R8.64] ; /* 0x0000000608087981 */
/* 0x000ee2000c1e1900 */
/*0410*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0420*/ IMAD R4, R4, UR4, RZ ; /* 0x0000000404047c24 */
/* 0x004fe2000f8e02ff */
/*0430*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*0440*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0450*/ IMAD R7, R4, R8, R11 ; /* 0x0000000804077224 */
/* 0x008fca00078e020b */
/*0460*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*0470*/ STG.E [R14.64], R7 ; /* 0x000000070e007986 */
/* 0x0003e2000c101906 */
/*0480*/ IMAD R12, R0, UR4, R5 ; /* 0x00000004000c7c24 */
/* 0x000fd6000f8e0205 */
/*0490*/ @!P0 BRA 0x930 ; /* 0x0000049000008947 */
/* 0x000fea0003800000 */
/*04a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.86102294921875e-06 ; /* 0x00000030ff0d7435 */
/* 0x002fe200000001ff */
/*04b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*04c0*/ IMAD.WIDE R12, R12, R13, c[0x0][0x180] ; /* 0x000060000c0c7625 */
/* 0x000fca00078e020d */
/*04d0*/ LDG.E.64 R4, [R12.64] ; /* 0x000000040c047981 */
/* 0x000ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x000ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R10, [R12.64+0x8] ; /* 0x000008040c0a7981 */
/* 0x000f22000c1e1b00 */
/*0500*/ SHF.R.U32.HI R0, RZ, 0x2, R5 ; /* 0x00000002ff007819 */
/* 0x004fe40000011605 */
/*0510*/ IADD3 R4, R4, 0x587c5, RZ ; /* 0x000587c504047810 */
/* 0x000fc40007ffe0ff */
/*0520*/ LOP3.LUT R0, R0, R5, RZ, 0x3c, !PT ; /* 0x0000000500007212 */
/* 0x000fe200078e3cff */
/*0530*/ IMAD.SHL.U32 R7, R9, 0x10, RZ ; /* 0x0000001009077824 */
/* 0x008fe200078e00ff */
/*0540*/ MOV R19, R8 ; /* 0x0000000800137202 */
/* 0x000fe20000000f00 */
/*0550*/ IMAD.MOV.U32 R18, RZ, RZ, R11 ; /* 0x000000ffff127224 */
/* 0x010fe200078e000b */
/*0560*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0570*/ IMAD.SHL.U32 R5, R0, 0x2, RZ ; /* 0x0000000200057824 */
/* 0x000fc600078e00ff */
/*0580*/ STG.E.64 [R12.64+0x8], R18 ; /* 0x000008120c007986 */
/* 0x000fe4000c101b04 */
/*0590*/ LOP3.LUT R0, R9, R5, R0, 0x96, !PT ; /* 0x0000000509007212 */
/* 0x000fe200078e9600 */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fc600078e000a */
/*05b0*/ LOP3.LUT R7, R0, R7, RZ, 0x3c, !PT ; /* 0x0000000700077212 */
/* 0x000fe400078e3cff */
/*05c0*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x000fe8000c101b04 */
/*05d0*/ STG.E.64 [R12.64+0x10], R6 ; /* 0x000010060c007986 */
/* 0x0001e8000c101b04 */
/*05e0*/ LDG.E R0, [R14.64] ; /* 0x000000040e007981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ F2F.F64.F32 R10, c[0x0][0x164] ; /* 0x00005900000a7b10 */
/* 0x000fe20000201800 */
/*0600*/ IMAD.MOV.U32 R16, RZ, RZ, 0x652b82fe ; /* 0x652b82feff107424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R17, 0x3ff71547 ; /* 0x3ff7154700117802 */
/* 0x000fe20000000f00 */
/*0620*/ IMAD.MOV.U32 R20, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff147424 */
/* 0x000fe200078e00ff */
/*0630*/ MOV R21, 0x3e5ade15 ; /* 0x3e5ade1500157802 */
/* 0x000fe20000000f00 */
/*0640*/ BSSY B1, 0x8d0 ; /* 0x0000028000017945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD.IADD R7, R7, 0x1, R4 ; /* 0x0000000107077824 */
/* 0x001fcc00078e0204 */
/*0660*/ I2F.U32 R7, R7 ; /* 0x0000000700077306 */
/* 0x000e300000201000 */
/*0670*/ I2F.F64 R8, R0 ; /* 0x0000000000087312 */
/* 0x0042a40000201c00 */
/*0680*/ MOV R0, 0x2f800000 ; /* 0x2f80000000007802 */
/* 0x002fe20000000f00 */
/*0690*/ DMUL R8, R8, -2 ; /* 0xc000000008087828 */
/* 0x004e4c0000000000 */
/*06a0*/ DMUL R8, R8, R10 ; /* 0x0000000a08087228 */
/* 0x002e4c0000000000 */
/*06b0*/ DFMA R10, R8, R16, 6.75539944105574400000e+15 ; /* 0x43380000080a742b */
/* 0x002e480000000010 */
/*06c0*/ FSETP.GEU.AND P0, PT, |R9|, 4.1917929649353027344, PT ; /* 0x4086232b0900780b */
/* 0x000fe40003f0e200 */
/*06d0*/ DADD R16, R10, -6.75539944105574400000e+15 ; /* 0xc33800000a107429 */
/* 0x002e4c0000000000 */
/*06e0*/ DFMA R18, R16, c[0x2][0x0], R8 ; /* 0x0080000010127a2b */
/* 0x002e4c0000000008 */
/*06f0*/ DFMA R12, R16, c[0x2][0x8], R18 ; /* 0x00800200100c7a2b */
/* 0x002e4c0000000012 */
/*0700*/ DFMA R14, R12, R20, c[0x2][0x10] ; /* 0x008004000c0e762b */
/* 0x002e4c0000000014 */
/*0710*/ DFMA R14, R12, R14, c[0x2][0x18] ; /* 0x008006000c0e762b */
/* 0x002e4c000000000e */
/*0720*/ DFMA R14, R12, R14, c[0x2][0x20] ; /* 0x008008000c0e762b */
/* 0x002e4c000000000e */
/*0730*/ DFMA R14, R12, R14, c[0x2][0x28] ; /* 0x00800a000c0e762b */
/* 0x002e4c000000000e */
/*0740*/ DFMA R14, R12, R14, c[0x2][0x30] ; /* 0x00800c000c0e762b */
/* 0x002e4c000000000e */
/*0750*/ DFMA R14, R12, R14, c[0x2][0x38] ; /* 0x00800e000c0e762b */
/* 0x002e4c000000000e */
/*0760*/ DFMA R14, R12, R14, c[0x2][0x40] ; /* 0x008010000c0e762b */
/* 0x002e4c000000000e */
/*0770*/ DFMA R14, R12, R14, c[0x2][0x48] ; /* 0x008012000c0e762b */
/* 0x002e4c000000000e */
/*0780*/ DFMA R14, R12, R14, c[0x2][0x50] ; /* 0x008014000c0e762b */
/* 0x002e4c000000000e */
/*0790*/ DFMA R14, R12, R14, 1 ; /* 0x3ff000000c0e742b */
/* 0x002e4c000000000e */
/*07a0*/ DFMA R14, R12, R14, 1 ; /* 0x3ff000000c0e742b */
/* 0x002064000000000e */
/*07b0*/ FFMA R12, R7, R0, 1.1641532182693481445e-10 ; /* 0x2f000000070c7423 */
/* 0x001fcc0000000000 */
/*07c0*/ F2F.F64.F32 R12, R12 ; /* 0x0000000c000c7310 */
/* 0x000e240000201800 */
/*07d0*/ IMAD R5, R10, 0x100000, R15 ; /* 0x001000000a057824 */
/* 0x002fe200078e020f */
/*07e0*/ MOV R4, R14 ; /* 0x0000000e00047202 */
/* 0x000fe20000000f00 */
/*07f0*/ @!P0 BRA 0x8c0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0800*/ FSETP.GEU.AND P1, PT, |R9|, 4.2275390625, PT ; /* 0x408748000900780b */
/* 0x000fe20003f2e200 */
/*0810*/ DADD R4, R8, +INF ; /* 0x7ff0000008047429 */
/* 0x000fc80000000000 */
/*0820*/ DSETP.GEU.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x000e4c0003f0e000 */
/*0830*/ FSEL R4, R4, RZ, P0 ; /* 0x000000ff04047208 */
/* 0x002fe40000000000 */
/*0840*/ @!P1 LEA.HI R0, R10, R10, RZ, 0x1 ; /* 0x0000000a0a009211 */
/* 0x000fe400078f08ff */
/*0850*/ FSEL R5, R5, RZ, P0 ; /* 0x000000ff05057208 */
/* 0x000fe40000000000 */
/*0860*/ @!P1 SHF.R.S32.HI R7, RZ, 0x1, R0 ; /* 0x00000001ff079819 */
/* 0x000fc80000011400 */
/*0870*/ @!P1 LEA R15, R7, R15, 0x14 ; /* 0x0000000f070f9211 */
/* 0x000fe200078ea0ff */
/*0880*/ @!P1 IMAD.IADD R6, R10, 0x1, -R7 ; /* 0x000000010a069824 */
/* 0x000fca00078e0a07 */
/*0890*/ @!P1 LEA R7, R6, 0x3ff00000, 0x14 ; /* 0x3ff0000006079811 */
/* 0x000fe200078ea0ff */
/*08a0*/ @!P1 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff069224 */
/* 0x000fcc00078e00ff */
/*08b0*/ @!P1 DMUL R4, R14, R6 ; /* 0x000000060e049228 */
/* 0x00028c0000000000 */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ DSETP.GEU.AND P0, PT, R4, R12, PT ; /* 0x0000000c0400722a */
/* 0x005e1c0003f0e000 */
/*08e0*/ @P0 BRA 0x930 ; /* 0x0000004000000947 */
/* 0x001fea0003800000 */
/*08f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0900*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0910*/ IADD3 R5, -R0, RZ, RZ ; /* 0x000000ff00057210 */
/* 0x004fca0007ffe1ff */
/*0920*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0930*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0940*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0950*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0960*/ BRA 0x960; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8g_S_initPiiP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.86102294921875e-06 ; /* 0x00000030ff037435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00d0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x10] ; /* 0x0000100402067981 */
/* 0x000ee8000c1e1b00 */
/*00f0*/ LDG.E.64 R4, [R2.64+0x8] ; /* 0x0000080402047981 */
/* 0x000f22000c1e1b00 */
/*0100*/ SHF.R.U32.HI R10, RZ, 0x2, R9 ; /* 0x00000002ff0a7819 */
/* 0x004fe40000011609 */
/*0110*/ IADD3 R8, R8, 0x587c5, RZ ; /* 0x000587c508087810 */
/* 0x000fc40007ffe0ff */
/*0120*/ LOP3.LUT R10, R10, R9, RZ, 0x3c, !PT ; /* 0x000000090a0a7212 */
/* 0x000fe200078e3cff */
/*0130*/ IMAD.MOV.U32 R16, RZ, RZ, R7 ; /* 0x000000ffff107224 */
/* 0x008fe200078e0007 */
/*0140*/ SHF.L.U32 R9, R7, 0x4, RZ ; /* 0x0000000407097819 */
/* 0x000fe400000006ff */
/*0150*/ MOV R15, R6 ; /* 0x00000006000f7202 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.SHL.U32 R11, R10, 0x2, RZ ; /* 0x000000020a0b7824 */
/* 0x000fe200078e00ff */
/*0170*/ MOV R14, R5 ; /* 0x00000005000e7202 */
/* 0x010fc80000000f00 */
/*0180*/ LOP3.LUT R10, R7, R11, R10, 0x96, !PT ; /* 0x0000000b070a7212 */
/* 0x000fe200078e960a */
/*0190*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*01a0*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0001e4000c101b04 */
/*01b0*/ LOP3.LUT R17, R10, R9, RZ, 0x3c, !PT ; /* 0x000000090a117212 */
/* 0x000fe200078e3cff */
/*01c0*/ HFMA2.MMA R9, -RZ, RZ, 0.1171875, 0 ; /* 0x2f800000ff097435 */
/* 0x000fe200000001ff */
/*01d0*/ IMAD.WIDE R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fc600078e020b */
/*01e0*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x0001e2000c101b04 */
/*01f0*/ IMAD.IADD R12, R17, 0x1, R8 ; /* 0x00000001110c7824 */
/* 0x000fcc00078e0208 */
/*0200*/ I2F.U32 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x000e640000201000 */
/*0210*/ FFMA R9, R12, R9, 1.1641532182693481445e-10 ; /* 0x2f0000000c097423 */
/* 0x002fca0000000009 */
/*0220*/ FSETP.GTU.AND P0, PT, R9, 0.5, PT ; /* 0x3f0000000900780b */
/* 0x000fe20003f0c000 */
/*0230*/ IMAD.MOV.U32 R9, RZ, RZ, R4 ; /* 0x000000ffff097224 */
/* 0x000fca00078e0004 */
/*0240*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x0001ee000c101b04 */
/*0250*/ @!P0 MOV R5, 0xffffffff ; /* 0xffffffff00058802 */
/* 0x000fca0000000f00 */
/*0260*/ @!P0 STG.E [R10.64], R5 ; /* 0x000000050a008986 */
/* 0x0001e2000c101904 */
/*0270*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x001fca00078e00ff */
/*0290*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x000fe2000c101904 */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11g_rand_initiP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x30 ; /* 0x00000030ff077424 */
/* 0x000fe200078e00ff */
/*00c0*/ LOP3.LUT R2, R0, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4900027812 */
/* 0x000fe200078e3cff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ LOP3.LUT R3, R3, 0xf7dcefdd, RZ, 0x3c, !PT ; /* 0xf7dcefdd03037812 */
/* 0x000fc600078e3cff */
/*00f0*/ IMAD R4, R2, 0x4182bed5, RZ ; /* 0x4182bed502047824 */
/* 0x000fe400078e02ff */
/*0100*/ IMAD R5, R3, -0x658354e5, RZ ; /* 0x9a7cab1b03057824 */
/* 0x000fe400078e02ff */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R7, R4.reuse, 0x75bcd15, RZ ; /* 0x075bcd1504077810 */
/* 0x040fe40007ffe0ff */
/*0130*/ IADD3 R6, R4.reuse, 0x64f0c9, R5 ; /* 0x0064f0c904067810 */
/* 0x040fe40007ffe005 */
/*0140*/ LOP3.LUT R8, R4, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e504087812 */
/* 0x000fe200078e3cff */
/*0150*/ STG.E.64 [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe2000c101b04 */
/*0160*/ IADD3 R9, R5, 0x1f123bb5, RZ ; /* 0x1f123bb505097810 */
/* 0x000fc40007ffe0ff */
/*0170*/ IADD3 R11, R4, 0x583f19, RZ ; /* 0x00583f19040b7810 */
/* 0x000fe20007ffe0ff */
/*0180*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b04 */
/*0190*/ LOP3.LUT R10, R5, 0x5491333, RZ, 0x3c, !PT ; /* 0x05491333050a7812 */
/* 0x000fc600078e3cff */
/*01a0*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x000fe8000c101b04 */
/*01b0*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E.64 [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101b04 */
/*01d0*/ STG.E.64 [R2.64+0x10], R10 ; /* 0x0000100a02007986 */
/* 0x000fe2000c101b04 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=cudaSuccess)\
printf("error %s,at %d\n",cudaGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,curandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,curandState *states);
__global__ void g_S_init(int *S,int size,curandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
cudaError_t err;
curandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
cudaMalloc((curandState **)&states,sizeof(curandState)*nthreads);
cudaMalloc((T **)&dS,sizeof(T)*size);
cudaMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(cudaMemcpy(S,dS,sizeof(int)*size,cudaMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
cudaFree(states);
cudaFree(dS);
cudaFree(dE);
cudaDeviceReset();
}
__global__ void g_rand_init(int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
curand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(curand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = curand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} | .file "tmpxft_000657c9_00000000-6_2d_ising.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3892:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3892:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
.type _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, @function
_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW:
.LFB3914:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11g_rand_initiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3914:
.size _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, .-_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
.globl _Z11g_rand_initiP17curandStateXORWOW
.type _Z11g_rand_initiP17curandStateXORWOW, @function
_Z11g_rand_initiP17curandStateXORWOW:
.LFB3915:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3915:
.size _Z11g_rand_initiP17curandStateXORWOW, .-_Z11g_rand_initiP17curandStateXORWOW
.globl _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
.type _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, @function
_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW:
.LFB3916:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8g_S_initPiiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3916:
.size _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, .-_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
.globl _Z8g_S_initPiiP17curandStateXORWOW
.type _Z8g_S_initPiiP17curandStateXORWOW, @function
_Z8g_S_initPiiP17curandStateXORWOW:
.LFB3917:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3917:
.size _Z8g_S_initPiiP17curandStateXORWOW, .-_Z8g_S_initPiiP17curandStateXORWOW
.globl _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
.type _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, @function
_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi:
.LFB3918:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3918:
.size _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, .-_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
.globl _Z10g_simulateifPiS_iiP17curandStateXORWOWi
.type _Z10g_simulateifPiS_iiP17curandStateXORWOWi, @function
_Z10g_simulateifPiS_iiP17curandStateXORWOWi:
.LFB3919:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3919:
.size _Z10g_simulateifPiS_iiP17curandStateXORWOWi, .-_Z10g_simulateifPiS_iiP17curandStateXORWOWi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10g_simulateifPiS_iiP17curandStateXORWOWi"
.align 8
.LC1:
.string "_Z8g_S_initPiiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z11g_rand_initiP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3921:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8g_S_initPiiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11g_rand_initiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3921:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
.align 2
.weak _ZN5isingIiED2Ev
.type _ZN5isingIiED2Ev, @function
_ZN5isingIiED2Ev:
.LFB4225:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4225
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 80(%rdi), %rdi
call free@PLT
movq 88(%rbx), %rdi
call free@PLT
movq 96(%rbx), %rdi
call free@PLT
movq 72(%rbx), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4225:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN5isingIiED2Ev,"aG",@progbits,_ZN5isingIiED5Ev,comdat
.LLSDA4225:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4225-.LLSDACSB4225
.LLSDACSB4225:
.LLSDACSE4225:
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
.size _ZN5isingIiED2Ev, .-_ZN5isingIiED2Ev
.weak _ZN5isingIiED1Ev
.set _ZN5isingIiED1Ev,_ZN5isingIiED2Ev
.section .rodata.str1.1
.LC13:
.string "w"
.LC14:
.string "result.dat"
.LC15:
.string "Error at opening file.\n"
.LC16:
.string "#%9d%9d\n"
.LC17:
.string "grid=[%d,%d],block[%d,%d]\n"
.LC18:
.string "error %s,at %d\n"
.LC19:
.string "%3d"
.text
.globl main
.type main, @function
main:
.LFB3889:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3889
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %rbx
subq $152, %rsp
.cfi_offset 3, -24
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
movl $1, -128(%rbp)
movl $1, -124(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $1, -112(%rbp)
movl $1, -108(%rbp)
movl $10752, -160(%rbp)
movl $10752, -156(%rbp)
movl $115605504, -152(%rbp)
movl $1, -148(%rbp)
movl $0x40000000, -96(%rbp)
movl $0, -100(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -80(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -72(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -64(%rbp)
leaq .LC13(%rip), %rsi
leaq .LC14(%rip), %rdi
.LEHB0:
call fopen@PLT
movq %rax, -88(%rbp)
testq %rax, %rax
je .L55
movq %rax, %rdi
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE0:
movl -152(%rbp), %eax
testl %eax, %eax
jle .L33
cltq
leaq 0(,%rax,4), %rcx
movl $0, %eax
.L34:
movq -80(%rbp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L34
.L33:
movl $4194304, -104(%rbp)
movl $64, -128(%rbp)
movl $64, -124(%rbp)
movl $1, -120(%rbp)
movl $32, -116(%rbp)
movl $32, -112(%rbp)
movl $1, -108(%rbp)
movl $32, %r9d
movl $32, %r8d
movl $64, %ecx
movl $64, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
jmp .L56
.L55:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
movl $0, %edi
call exit@PLT
.L56:
movslq -104(%rbp), %rax
leaq (%rax,%rax,2), %rsi
salq $4, %rsi
leaq -48(%rbp), %rdi
.LEHB3:
call cudaMalloc@PLT
movslq -152(%rbp), %rsi
salq $2, %rsi
leaq -40(%rbp), %rdi
call cudaMalloc@PLT
movslq -152(%rbp), %rsi
salq $2, %rsi
leaq -32(%rbp), %rdi
call cudaMalloc@PLT
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L35:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L58
.L57:
movq -48(%rbp), %rsi
movl -152(%rbp), %edi
call _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
jmp .L35
.L58:
testl %eax, %eax
je .L59
.L36:
movslq -152(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -40(%rbp), %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
jmp .L60
.L59:
movq -48(%rbp), %rdx
movl -152(%rbp), %esi
movq -40(%rbp), %rdi
call _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
jmp .L36
.L60:
testl %eax, %eax
jne .L37
.L40:
movl $0, %ebx
cmpl $0, -152(%rbp)
jg .L38
.L39:
movl $100, %ebx
jmp .L43
.L37:
movslq -152(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -40(%rbp), %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $127, %ecx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.L61:
addq $1, %rbx
cmpl %ebx, -152(%rbp)
jle .L39
.L38:
movq -80(%rbp), %rax
movl (%rax,%rbx,4), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq -88(%rbp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L61
.L66:
testl %eax, %eax
je .L62
.L41:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L63
.L62:
subq $8, %rsp
pushq $0
movq -48(%rbp), %r9
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
movq -32(%rbp), %rdx
movq -40(%rbp), %rsi
movss -96(%rbp), %xmm0
movl -148(%rbp), %edi
.cfi_escape 0x2e,0x10
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $16, %rsp
jmp .L41
.L63:
testl %eax, %eax
je .L64
.L42:
subl $1, %ebx
je .L65
.L43:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
.cfi_escape 0x2e,0
call __cudaPushCallConfiguration@PLT
jmp .L66
.L64:
subq $8, %rsp
pushq $1
movq -48(%rbp), %r9
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
movq -32(%rbp), %rdx
movq -40(%rbp), %rsi
movss -96(%rbp), %xmm0
movl -148(%rbp), %edi
.cfi_escape 0x2e,0x10
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $16, %rsp
jmp .L42
.L65:
movq -48(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaFree@PLT
movq -40(%rbp), %rdi
call cudaFree@PLT
movq -32(%rbp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
.LEHE3:
leaq -160(%rbp), %rdi
call _ZN5isingIiED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
movq -8(%rbp), %rbx
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -160(%rbp), %rdi
call _ZN5isingIiED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3889:
.section .gcc_except_table,"a",@progbits
.LLSDA3889:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3889-.LLSDACSB3889
.LLSDACSB3889:
.uleb128 .LEHB0-.LFB3889
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3889
.uleb128 .LEHE1-.LEHB1
.uleb128 .L48-.LFB3889
.uleb128 0
.uleb128 .LEHB2-.LFB3889
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3889
.uleb128 .LEHE3-.LEHB3
.uleb128 .L48-.LFB3889
.uleb128 0
.uleb128 .LEHB4-.LFB3889
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3889:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand.h>
#include <curand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=cudaSuccess)\
printf("error %s,at %d\n",cudaGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,curandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,curandState *states);
__global__ void g_S_init(int *S,int size,curandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
cudaError_t err;
curandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
cudaMalloc((curandState **)&states,sizeof(curandState)*nthreads);
cudaMalloc((T **)&dS,sizeof(T)*size);
cudaMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(cudaMemcpy(S,dS,sizeof(int)*size,cudaMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
cudaFree(states);
cudaFree(dS);
cudaFree(dE);
cudaDeviceReset();
}
__global__ void g_rand_init(int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
curand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,curandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(curand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,curandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = curand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=hipSuccess)\
printf("error %s,at %d\n",hipGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,hiprandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,hiprandState *states);
__global__ void g_S_init(int *S,int size,hiprandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
hipError_t err;
hiprandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
hipMalloc((hiprandState **)&states,sizeof(hiprandState)*nthreads);
hipMalloc((T **)&dS,sizeof(T)*size);
hipMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(hipMemcpy(S,dS,sizeof(int)*size,hipMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
hipFree(states);
hipFree(dS);
hipFree(dE);
hipDeviceReset();
}
__global__ void g_rand_init(int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
hiprand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(hiprand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = hiprand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=hipSuccess)\
printf("error %s,at %d\n",hipGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,hiprandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,hiprandState *states);
__global__ void g_S_init(int *S,int size,hiprandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
hipError_t err;
hiprandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
hipMalloc((hiprandState **)&states,sizeof(hiprandState)*nthreads);
hipMalloc((T **)&dS,sizeof(T)*size);
hipMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(hipMemcpy(S,dS,sizeof(int)*size,hipMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
hipFree(states);
hipFree(dS);
hipFree(dE);
hipDeviceReset();
}
__global__ void g_rand_init(int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
hiprand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(hiprand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = hiprand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11g_rand_initiP12hiprandState
.globl _Z11g_rand_initiP12hiprandState
.p2align 8
.type _Z11g_rand_initiP12hiprandState,@function
_Z11g_rand_initiP12hiprandState:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_xor_b32_e32 v2, 0x2c7f967f, v0
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v1, 0x8a5d614f
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v2, 0x493c4aa1
v_dual_mov_b32 v6, v5 :: v_dual_cndmask_b32 v1, 0xfa091aa4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, 0x1f123bb5, v1
v_add3_u32 v4, v9, v1, 0x64f0c9
v_xor_b32_e32 v3, 0x5491333, v1
v_xor_b32_e32 v1, 0x159a55e5, v9
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[7:8], null, v0, 48, s[0:1]
v_add_nc_u32_e32 v0, 0x75bcd15, v9
v_add_nc_u32_e32 v9, 0x583f19, v9
s_clause 0x2
global_store_b96 v[7:8], v[4:6], off
global_store_b128 v[7:8], v[0:3], off offset:24
global_store_b32 v[7:8], v9, off offset:40
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11g_rand_initiP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11g_rand_initiP12hiprandState, .Lfunc_end0-_Z11g_rand_initiP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8g_S_initPiiP12hiprandState
.globl _Z8g_S_initPiiP12hiprandState
.p2align 8
.type _Z8g_S_initPiiP12hiprandState,@function
_Z8g_S_initPiiP12hiprandState:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[6:7], null, v0, 48, s[2:3]
s_clause 0x2
global_load_b128 v[1:4], v[6:7], off offset:24
global_load_b32 v5, v[6:7], off offset:40
global_load_b32 v8, v[6:7], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v9, 2, v1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 0x587c5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, v9, v1
v_lshlrev_b32_e32 v9, 4, v5
v_lshlrev_b32_e32 v10, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v9, v10, v9
v_xor3_b32 v9, v9, v1, v5
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v10, v8, v9
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v10, v10
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_fmaak_f32 v10, 0x2f800000, v10, 0x2f800000
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nge_f32_e32 vcc_lo, 0.5, v10
v_cndmask_b32_e64 v10, -1, 1, vcc_lo
s_clause 0x2
global_store_b32 v[6:7], v9, off offset:40
global_store_b128 v[6:7], v[2:5], off offset:24
global_store_b32 v[6:7], v8, off
global_store_b32 v[0:1], v10, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8g_S_initPiiP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8g_S_initPiiP12hiprandState, .Lfunc_end1-_Z8g_S_initPiiP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10g_simulateifPiS_iiP12hiprandStatei
.globl _Z10g_simulateifPiS_iiP12hiprandStatei
.p2align 8
.type _Z10g_simulateifPiS_iiP12hiprandStatei,@function
_Z10g_simulateifPiS_iiP12hiprandStatei:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_add_u32 s8, s0, 48
s_addc_u32 s9, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s10, v2
v_cmp_gt_i32_e64 s2, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s4, vcc_lo, s2
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB2_5
v_add_nc_u32_e32 v0, v3, v2
s_load_b32 s4, s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 31, v0
v_add_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, -2, v1
v_sub_nc_u32_e32 v0, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, s4, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
v_mul_lo_u32 v11, v2, s11
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v11, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 1, v2
global_load_b32 v8, v[0:1], off
v_cndmask_b32_e64 v6, v2, s11, vcc_lo
v_add_nc_u32_e32 v9, -1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[6:7], null, v9, s11, v[3:4]
v_mov_b32_e32 v9, 0
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_load_b32 s6, s[0:1], 0x0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_cmp_gt_i32_e32 vcc_lo, 1, v3
s_waitcnt lgkmcnt(0)
s_sub_i32 s6, 0, s6
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v8, 0, v8
global_store_b32 v[0:1], v8, off
global_store_b32 v[4:5], v9, off
s_clause 0x1
global_load_b32 v8, v[0:1], off
global_load_b32 v9, v[6:7], off
v_cndmask_b32_e64 v6, v3, s10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v11, v6, -1
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_waitcnt vmcnt(1)
v_mul_lo_u32 v8, v8, s6
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v9
global_store_b32 v[4:5], v8, off
s_clause 0x1
global_load_b32 v9, v[0:1], off
global_load_b32 v12, v[6:7], off
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s10, v6
v_cndmask_b32_e32 v10, 0, v6, vcc_lo
v_mad_u64_u32 v[6:7], null, v10, s11, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_waitcnt vmcnt(1)
v_mul_lo_u32 v13, v9, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, v13, v12, v[8:9]
global_store_b32 v[4:5], v9, off
s_clause 0x1
global_load_b32 v8, v[0:1], off
global_load_b32 v7, v[6:7], off
v_add_nc_u32_e32 v6, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s11, v6
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_add_nc_u32_e32 v6, v6, v11
s_waitcnt vmcnt(1)
v_mul_lo_u32 v8, v8, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v8, v7, v[9:10]
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
global_store_b32 v[4:5], v10, off
global_load_b32 v8, v[0:1], off
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(1)
v_mul_lo_u32 v8, v8, s6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, v8, v9, v[10:11]
v_cmp_lt_i32_e32 vcc_lo, -1, v6
global_store_b32 v[4:5], v6, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
s_load_b32 s6, s[8:9], 0x0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b32 s0, s[0:1], 0x4
s_mov_b32 s1, 0x3ff71547
s_waitcnt lgkmcnt(0)
s_mul_i32 s6, s6, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s6, v3, v[2:3]
v_mad_i64_i32 v[2:3], null, v6, 48, s[4:5]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_clause 0x2
global_load_b128 v[6:9], v[2:3], off offset:24
global_load_b32 v10, v[2:3], off offset:40
global_load_b32 v11, v[2:3], off
s_waitcnt vmcnt(2)
v_lshrrev_b32_e32 v12, 2, v6
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 0x587c5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v12, v6
v_lshlrev_b32_e32 v12, 4, v10
v_lshlrev_b32_e32 v13, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v12, v13, v12
v_xor3_b32 v12, v12, v6, v10
s_clause 0x2
global_store_b32 v[2:3], v11, off
global_store_b128 v[2:3], v[7:10], off offset:24
global_store_b32 v[2:3], v12, off offset:40
global_load_b32 v2, v[4:5], off
v_cvt_f64_f32_e32 v[4:5], s0
s_mov_b32 s0, 0x652b82fe
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], -2.0
v_mul_f64 v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
v_rndne_f64_e32 v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
v_cvt_i32_f64_e32 v10, v[4:5]
v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], s[4:5], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
v_add_nc_u32_e32 v6, v11, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v6, v6
v_fmaak_f32 v2, 0x2f800000, v6, 0x2f800000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_ldexp_f64 v[4:5], v[4:5], v10
v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
s_and_b32 vcc_lo, s0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cndmask_b32_e64 v5, 0, v5, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, v[4:5], v[2:3]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_5
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v2, 0, v2
global_store_b32 v[0:1], v2, off
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10g_simulateifPiS_iiP12hiprandStatei
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10g_simulateifPiS_iiP12hiprandStatei, .Lfunc_end2-_Z10g_simulateifPiS_iiP12hiprandStatei
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11g_rand_initiP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11g_rand_initiP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8g_S_initPiiP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8g_S_initPiiP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
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.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10g_simulateifPiS_iiP12hiprandStatei
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10g_simulateifPiS_iiP12hiprandStatei.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdio.h>
using namespace std;
#define D_CHECK(err){\
if(err !=hipSuccess)\
printf("error %s,at %d\n",hipGetErrorString(err),__LINE__); \
}
//#define ROW 10752
#define ROW 10752
//#define COL 10752
#define COL 10752
__global__ void g_rand_init(int size,hiprandState *states);
__global__ void g_calc_energy(int J,int *S,int *E,int row,int col,hiprandState *states);
__global__ void g_S_init(int *S,int size,hiprandState *states);
__global__ void g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag);
template <typename T>
class ising{
public:
// host values
int row;
int col;
int size;
T J;
// 交換相互作用エネルギー
int block_x,block_y;
int thread_x,thread_y;
dim3 grid,block;
int nthreads;
int sumE;
float invT;
FILE *fp;
T *S;
// スピンの情報
T *E;
// 各スピンのエネルギー
T *hE;
// エネルギー計算用
// device values
hipError_t err;
hiprandState *states;
//乱数列生成用
T *dS;
// デバイス側のスピン
T *dE;
// デバイス側の各スピンのエネルギー
//functions
ising(int row_,int col_,T J_,float temperature);
~ising();
void devInit(int bx,int by,int tx,int ty);
// デバイス側の初期化
void toFile();
// ファイルの書き出し
void checkEnergy();
// 系のエネルギーのチェック
void run();
//シミュレーションのスタート
void devEnd();
// デバイスの変数の解放
};
template <typename T>
ising<T>::ising(int row_,int col_,T J_,float temperature_){
row = row_;
col = col_;
size = row_ * col_;
J = J_;
invT = 1.0/temperature_;
sumE = 0;
S = (T *) malloc(sizeof(T) * size);
E = (T *) malloc(sizeof(T) * size);
hE = (T *) malloc(sizeof(T) * size);
if((fp = fopen("result.dat","w")) == NULL){
printf("Error at opening file.\n");
exit(0);
}
fprintf(fp,"#%9d%9d\n",row,col);
for(int i=0;i<size;i++)
S[i] = 0;
}
template <typename T>
ising<T>::~ising(){
free(S);
free(E);
free(hE);
fclose(fp);
}
template <typename T>
void ising<T>::devInit(int bx,int by,int tx,int ty){
nthreads = bx * by * tx * ty;
dim3 grid_(bx,by),block_(tx,ty);
grid = grid_;
block = block_;
printf("grid=[%d,%d],block[%d,%d]\n",grid.x,grid.y,block.x,block.y);
hipMalloc((hiprandState **)&states,sizeof(hiprandState)*nthreads);
hipMalloc((T **)&dS,sizeof(T)*size);
hipMalloc((T **)&dE,sizeof(T)*size);
g_rand_init<<<grid,block>>>(size,states);
g_S_init<<<grid,block>>>(dS,size,states);
D_CHECK(hipMemcpy(S,dS,sizeof(int)*size,hipMemcpyDeviceToHost));
}
template <typename T>
void ising<T>::devEnd(){
hipFree(states);
hipFree(dS);
hipFree(dE);
hipDeviceReset();
}
__global__ void g_rand_init(int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
hiprand_init(idx,0,0,&states[idx]);
}
}
__global__ void g_S_init(int *S,int size,hiprandState *states){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
if(idx < size){
if(hiprand_uniform(&states[idx]) <= 0.5)
S[idx] = -1;
else
S[idx] = 1;
}
}
template <typename T>
void ising<T>::run(){
int flag;
flag = 0;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
flag = 1;
g_simulate<<<grid,block>>>(J,invT,dS,dE,row,col,states,flag);
}
template <typename T>
void ising<T>::toFile(){
for(int i=0;i<size;i++)
fprintf(fp,"%3d",S[i]);
return;
}
__global__ void
g_simulate(int J,float invT,int *S,int *E,int row,int col,hiprandState *states,int flag)
{
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int idx = x + y*gridDim.x*blockDim.x;
int nx;
int ny;
float prob;
if( x < row && y < col){
if((x+y)% 2 == flag){
S[x*col+y] = -S[x*col+y];
E[x*col+y] = 0;
nx = x-1;
ny = y;
if(nx < 0)
nx = col-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y-1;
if(ny < 0)
ny = row-1;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x+1;
ny = y;
if(nx >= row)
nx = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
nx = x;
ny = y+1;
if(ny >= col)
ny = 0;
E[x*col+y] += -J*S[x*col+y]*S[nx*col+ny];
if( E[x*col+y]>=0){
prob = hiprand_uniform(&states[idx]);
if(prob > exp(-2.0*E[x*col+y]*invT)){
S[x*col+y] = -S[x*col+y];
}
}
}
}
__syncthreads();
}
int main(void){
int row = ROW;
int col = COL;
int J = 1;
ising<int> ising2d(row,col,J,0.5);
ising2d.devInit(64,64,32,32);
ising2d.toFile();
for(int i=0;i<100;i++){
ising2d.run();
//ising2d.checkEnergy();
//ising2d.toFile();
}
ising2d.devEnd();
return 0;
} | .text
.file "2d_ising.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__g_rand_initiP12hiprandState # -- Begin function _Z26__device_stub__g_rand_initiP12hiprandState
.p2align 4, 0x90
.type _Z26__device_stub__g_rand_initiP12hiprandState,@function
_Z26__device_stub__g_rand_initiP12hiprandState: # @_Z26__device_stub__g_rand_initiP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11g_rand_initiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__g_rand_initiP12hiprandState, .Lfunc_end0-_Z26__device_stub__g_rand_initiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z23__device_stub__g_S_initPiiP12hiprandState # -- Begin function _Z23__device_stub__g_S_initPiiP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__g_S_initPiiP12hiprandState,@function
_Z23__device_stub__g_S_initPiiP12hiprandState: # @_Z23__device_stub__g_S_initPiiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8g_S_initPiiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__g_S_initPiiP12hiprandState, .Lfunc_end1-_Z23__device_stub__g_S_initPiiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei # -- Begin function _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.p2align 4, 0x90
.type _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei,@function
_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei: # @_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei, .Lfunc_end2-_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rbx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdi
movl $10752, %esi # imm = 0x2A00
movl $10752, %edx # imm = 0x2A00
movl $1, %ecx
callq _ZN5isingIiEC2Eiiif
.Ltmp0:
movq %rbx, %rdi
movl $64, %esi
movl $64, %edx
movl $32, %ecx
movl $32, %r8d
callq _ZN5isingIiE7devInitEiiii
.Ltmp1:
# %bb.1:
cmpl $0, 8(%rsp)
jle .LBB3_2
# %bb.10: # %.lr.ph.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_11: # =>This Inner Loop Header: Depth=1
movq 72(%rsp), %rdi
movq 80(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
incq %rbx
movslq 8(%rsp), %rax
cmpq %rax, %rbx
jl .LBB3_11
.LBB3_2: # %_ZN5isingIiE6toFileEv.exit.preheader
movl $100, %ebp
movq %rsp, %rbx
.p2align 4, 0x90
.LBB3_3: # %_ZN5isingIiE6toFileEv.exit
# =>This Inner Loop Header: Depth=1
.Ltmp2:
movq %rbx, %rdi
callq _ZN5isingIiE3runEv
.Ltmp3:
# %bb.4: # in Loop: Header=BB3_3 Depth=1
decl %ebp
jne .LBB3_3
# %bb.5:
movq 112(%rsp), %rdi
.Ltmp5:
callq hipFree
.Ltmp6:
# %bb.6: # %.noexc
movq 120(%rsp), %rdi
.Ltmp7:
callq hipFree
.Ltmp8:
# %bb.7: # %.noexc10
movq 128(%rsp), %rdi
.Ltmp9:
callq hipFree
.Ltmp10:
# %bb.8: # %.noexc11
.Ltmp11:
callq hipDeviceReset
.Ltmp12:
# %bb.9: # %_ZN5isingIiE6devEndEv.exit
movq 80(%rsp), %rdi
callq free
movq 88(%rsp), %rdi
callq free
movq 96(%rsp), %rdi
callq free
movq 72(%rsp), %rdi
callq fclose
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 160
.Ltmp13:
jmp .LBB3_13
.LBB3_14:
.Ltmp4:
.LBB3_13:
movq %rax, %rbx
movq %rsp, %rdi
callq _ZN5isingIiED2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp12-.Ltmp5 # Call between .Ltmp5 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp12 # Call between .Ltmp12 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN5isingIiEC2Eiiif
.LCPI4_0:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x3f800000 # float 1
.section .text._ZN5isingIiEC2Eiiif,"axG",@progbits,_ZN5isingIiEC2Eiiif,comdat
.weak _ZN5isingIiEC2Eiiif
.p2align 4, 0x90
.type _ZN5isingIiEC2Eiiif,@function
_ZN5isingIiEC2Eiiif: # @_ZN5isingIiEC2Eiiif
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [1,1,1,1]
movups %xmm1, 32(%rdi)
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 48(%rdi)
movl %esi, (%rdi)
movl %edx, 4(%rdi)
imull %esi, %edx
movl %edx, 8(%rdi)
movl %ecx, 12(%rdi)
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 64(%rdi)
movl $0, 60(%rdi)
movslq %edx, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, 80(%rbx)
movq %r14, %rdi
callq malloc
movq %rax, 88(%rbx)
movq %r14, %rdi
callq malloc
movq %rax, 96(%rbx)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 72(%rbx)
testq %rax, %rax
je .LBB4_5
# %bb.1:
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 8(%rbx)
jle .LBB4_4
# %bb.2: # %.lr.ph
movq 80(%rbx), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rcx,4)
incq %rcx
movslq 8(%rbx), %rdx
cmpq %rdx, %rcx
jl .LBB4_3
.LBB4_4: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_5:
.cfi_def_cfa_offset 32
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size _ZN5isingIiEC2Eiiif, .Lfunc_end4-_ZN5isingIiEC2Eiiif
.cfi_endproc
# -- End function
.section .text._ZN5isingIiE7devInitEiiii,"axG",@progbits,_ZN5isingIiE7devInitEiiii,comdat
.weak _ZN5isingIiE7devInitEiiii # -- Begin function _ZN5isingIiE7devInitEiiii
.p2align 4, 0x90
.type _ZN5isingIiE7devInitEiiii,@function
_ZN5isingIiE7devInitEiiii: # @_ZN5isingIiE7devInitEiiii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl %edx, %eax
imull %esi, %eax
movl %ecx, %edi
imull %r8d, %edi
imull %eax, %edi
movl %edi, 56(%rbx)
movl %esi, 32(%rbx)
movl %edx, 36(%rbx)
movl $1, 40(%rbx)
movl %ecx, 44(%rbx)
movl %r8d, 48(%rbx)
movl $1, 52(%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 112(%rbx), %rdi
movslq 56(%rbx), %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
callq hipMalloc
leaq 120(%rbx), %rdi
movslq 8(%rbx), %rsi
shlq $2, %rsi
callq hipMalloc
leaq 128(%rbx), %rdi
movslq 8(%rbx), %rsi
shlq $2, %rsi
callq hipMalloc
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movl 8(%rbx), %eax
movq 112(%rbx), %rcx
movl %eax, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11g_rand_initiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 120(%rbx), %rax
movl 8(%rbx), %ecx
movq 112(%rbx), %rdx
movq %rax, 64(%rsp)
movl %ecx, 76(%rsp)
movq %rdx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 76(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8g_S_initPiiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq 80(%rbx), %rdi
movq 120(%rbx), %rsi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB5_6
# %bb.5:
movq 80(%rbx), %rdi
movq 120(%rbx), %rsi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
movl $127, %edx
xorl %eax, %eax
callq printf
.LBB5_6:
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _ZN5isingIiE7devInitEiiii, .Lfunc_end5-_ZN5isingIiE7devInitEiiii
.cfi_endproc
# -- End function
.section .text._ZN5isingIiE3runEv,"axG",@progbits,_ZN5isingIiE3runEv,comdat
.weak _ZN5isingIiE3runEv # -- Begin function _ZN5isingIiE3runEv
.p2align 4, 0x90
.type _ZN5isingIiE3runEv,@function
_ZN5isingIiE3runEv: # @_ZN5isingIiE3runEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 32(%rdi), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movl 12(%rbx), %eax
movss 64(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 120(%rbx), %rcx
movq 128(%rbx), %rdx
movl (%rbx), %esi
movl 4(%rbx), %edi
movq 112(%rbx), %r8
movl %eax, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 12(%rsp)
movl %edi, 8(%rsp)
movq %r8, 72(%rsp)
movl $0, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movl 12(%rbx), %eax
movss 64(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 120(%rbx), %rcx
movq 128(%rbx), %rdx
movl (%rbx), %esi
movl 4(%rbx), %edi
movq 112(%rbx), %r8
movl %eax, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 12(%rsp)
movl %edi, 8(%rsp)
movq %r8, 72(%rsp)
movl $1, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZN5isingIiE3runEv, .Lfunc_end6-_ZN5isingIiE3runEv
.cfi_endproc
# -- End function
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED2Ev,comdat
.weak _ZN5isingIiED2Ev # -- Begin function _ZN5isingIiED2Ev
.p2align 4, 0x90
.type _ZN5isingIiED2Ev,@function
_ZN5isingIiED2Ev: # @_ZN5isingIiED2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 80(%rdi), %rdi
callq free
movq 88(%rbx), %rdi
callq free
movq 96(%rbx), %rdi
callq free
movq 72(%rbx), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end7:
.size _ZN5isingIiED2Ev, .Lfunc_end7-_ZN5isingIiED2Ev
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11g_rand_initiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8g_S_initPiiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11g_rand_initiP12hiprandState,@object # @_Z11g_rand_initiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z11g_rand_initiP12hiprandState
.p2align 3, 0x0
_Z11g_rand_initiP12hiprandState:
.quad _Z26__device_stub__g_rand_initiP12hiprandState
.size _Z11g_rand_initiP12hiprandState, 8
.type _Z8g_S_initPiiP12hiprandState,@object # @_Z8g_S_initPiiP12hiprandState
.globl _Z8g_S_initPiiP12hiprandState
.p2align 3, 0x0
_Z8g_S_initPiiP12hiprandState:
.quad _Z23__device_stub__g_S_initPiiP12hiprandState
.size _Z8g_S_initPiiP12hiprandState, 8
.type _Z10g_simulateifPiS_iiP12hiprandStatei,@object # @_Z10g_simulateifPiS_iiP12hiprandStatei
.globl _Z10g_simulateifPiS_iiP12hiprandStatei
.p2align 3, 0x0
_Z10g_simulateifPiS_iiP12hiprandStatei:
.quad _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.size _Z10g_simulateifPiS_iiP12hiprandStatei, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result.dat"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "#%9d%9d\n"
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid=[%d,%d],block[%d,%d]\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error %s,at %d\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%3d"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11g_rand_initiP12hiprandState"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8g_S_initPiiP12hiprandState"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10g_simulateifPiS_iiP12hiprandStatei"
.size .L__unnamed_3, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error at opening file."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__g_rand_initiP12hiprandState
.addrsig_sym _Z23__device_stub__g_S_initPiiP12hiprandState
.addrsig_sym _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11g_rand_initiP12hiprandState
.addrsig_sym _Z8g_S_initPiiP12hiprandState
.addrsig_sym _Z10g_simulateifPiS_iiP12hiprandStatei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000657c9_00000000-6_2d_ising.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3892:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3892:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
.type _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, @function
_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW:
.LFB3914:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11g_rand_initiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3914:
.size _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW, .-_Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
.globl _Z11g_rand_initiP17curandStateXORWOW
.type _Z11g_rand_initiP17curandStateXORWOW, @function
_Z11g_rand_initiP17curandStateXORWOW:
.LFB3915:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3915:
.size _Z11g_rand_initiP17curandStateXORWOW, .-_Z11g_rand_initiP17curandStateXORWOW
.globl _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
.type _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, @function
_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW:
.LFB3916:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8g_S_initPiiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3916:
.size _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW, .-_Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
.globl _Z8g_S_initPiiP17curandStateXORWOW
.type _Z8g_S_initPiiP17curandStateXORWOW, @function
_Z8g_S_initPiiP17curandStateXORWOW:
.LFB3917:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3917:
.size _Z8g_S_initPiiP17curandStateXORWOW, .-_Z8g_S_initPiiP17curandStateXORWOW
.globl _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
.type _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, @function
_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi:
.LFB3918:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movss %xmm0, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3918:
.size _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi, .-_Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
.globl _Z10g_simulateifPiS_iiP17curandStateXORWOWi
.type _Z10g_simulateifPiS_iiP17curandStateXORWOWi, @function
_Z10g_simulateifPiS_iiP17curandStateXORWOWi:
.LFB3919:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3919:
.size _Z10g_simulateifPiS_iiP17curandStateXORWOWi, .-_Z10g_simulateifPiS_iiP17curandStateXORWOWi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z10g_simulateifPiS_iiP17curandStateXORWOWi"
.align 8
.LC1:
.string "_Z8g_S_initPiiP17curandStateXORWOW"
.align 8
.LC2:
.string "_Z11g_rand_initiP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "precalc_xorwow_matrix"
.LC4:
.string "precalc_xorwow_offset_matrix"
.LC5:
.string "mrg32k3aM1"
.LC6:
.string "mrg32k3aM2"
.LC7:
.string "mrg32k3aM1SubSeq"
.LC8:
.string "mrg32k3aM2SubSeq"
.LC9:
.string "mrg32k3aM1Seq"
.LC10:
.string "mrg32k3aM2Seq"
.LC11:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3921:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10g_simulateifPiS_iiP17curandStateXORWOWi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8g_S_initPiiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11g_rand_initiP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3921:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
.align 2
.weak _ZN5isingIiED2Ev
.type _ZN5isingIiED2Ev, @function
_ZN5isingIiED2Ev:
.LFB4225:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4225
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 80(%rdi), %rdi
call free@PLT
movq 88(%rbx), %rdi
call free@PLT
movq 96(%rbx), %rdi
call free@PLT
movq 72(%rbx), %rdi
call fclose@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4225:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN5isingIiED2Ev,"aG",@progbits,_ZN5isingIiED5Ev,comdat
.LLSDA4225:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4225-.LLSDACSB4225
.LLSDACSB4225:
.LLSDACSE4225:
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED5Ev,comdat
.size _ZN5isingIiED2Ev, .-_ZN5isingIiED2Ev
.weak _ZN5isingIiED1Ev
.set _ZN5isingIiED1Ev,_ZN5isingIiED2Ev
.section .rodata.str1.1
.LC13:
.string "w"
.LC14:
.string "result.dat"
.LC15:
.string "Error at opening file.\n"
.LC16:
.string "#%9d%9d\n"
.LC17:
.string "grid=[%d,%d],block[%d,%d]\n"
.LC18:
.string "error %s,at %d\n"
.LC19:
.string "%3d"
.text
.globl main
.type main, @function
main:
.LFB3889:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3889
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %rbx
subq $152, %rsp
.cfi_offset 3, -24
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
movl $1, -128(%rbp)
movl $1, -124(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $1, -112(%rbp)
movl $1, -108(%rbp)
movl $10752, -160(%rbp)
movl $10752, -156(%rbp)
movl $115605504, -152(%rbp)
movl $1, -148(%rbp)
movl $0x40000000, -96(%rbp)
movl $0, -100(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -80(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -72(%rbp)
movl $462422016, %edi
call malloc@PLT
movq %rax, -64(%rbp)
leaq .LC13(%rip), %rsi
leaq .LC14(%rip), %rdi
.LEHB0:
call fopen@PLT
movq %rax, -88(%rbp)
testq %rax, %rax
je .L55
movq %rax, %rdi
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
leaq .LC16(%rip), %rdx
movl $2, %esi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE0:
movl -152(%rbp), %eax
testl %eax, %eax
jle .L33
cltq
leaq 0(,%rax,4), %rcx
movl $0, %eax
.L34:
movq -80(%rbp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L34
.L33:
movl $4194304, -104(%rbp)
movl $64, -128(%rbp)
movl $64, -124(%rbp)
movl $1, -120(%rbp)
movl $32, -116(%rbp)
movl $32, -112(%rbp)
movl $1, -108(%rbp)
movl $32, %r9d
movl $32, %r8d
movl $64, %ecx
movl $64, %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB1:
call __printf_chk@PLT
.LEHE1:
jmp .L56
.L55:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB2:
call __printf_chk@PLT
.LEHE2:
movl $0, %edi
call exit@PLT
.L56:
movslq -104(%rbp), %rax
leaq (%rax,%rax,2), %rsi
salq $4, %rsi
leaq -48(%rbp), %rdi
.LEHB3:
call cudaMalloc@PLT
movslq -152(%rbp), %rsi
salq $2, %rsi
leaq -40(%rbp), %rdi
call cudaMalloc@PLT
movslq -152(%rbp), %rsi
salq $2, %rsi
leaq -32(%rbp), %rdi
call cudaMalloc@PLT
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L35:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L58
.L57:
movq -48(%rbp), %rsi
movl -152(%rbp), %edi
call _Z50__device_stub__Z11g_rand_initiP17curandStateXORWOWiP17curandStateXORWOW
jmp .L35
.L58:
testl %eax, %eax
je .L59
.L36:
movslq -152(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -40(%rbp), %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
jmp .L60
.L59:
movq -48(%rbp), %rdx
movl -152(%rbp), %esi
movq -40(%rbp), %rdi
call _Z48__device_stub__Z8g_S_initPiiP17curandStateXORWOWPiiP17curandStateXORWOW
jmp .L36
.L60:
testl %eax, %eax
jne .L37
.L40:
movl $0, %ebx
cmpl $0, -152(%rbp)
jg .L38
.L39:
movl $100, %ebx
jmp .L43
.L37:
movslq -152(%rbp), %rdx
salq $2, %rdx
movl $2, %ecx
movq -40(%rbp), %rsi
movq -80(%rbp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $127, %ecx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L40
.L61:
addq $1, %rbx
cmpl %ebx, -152(%rbp)
jle .L39
.L38:
movq -80(%rbp), %rax
movl (%rax,%rbx,4), %ecx
leaq .LC19(%rip), %rdx
movl $2, %esi
movq -88(%rbp), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L61
.L66:
testl %eax, %eax
je .L62
.L41:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
call __cudaPushCallConfiguration@PLT
jmp .L63
.L62:
subq $8, %rsp
pushq $0
movq -48(%rbp), %r9
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
movq -32(%rbp), %rdx
movq -40(%rbp), %rsi
movss -96(%rbp), %xmm0
movl -148(%rbp), %edi
.cfi_escape 0x2e,0x10
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $16, %rsp
jmp .L41
.L63:
testl %eax, %eax
je .L64
.L42:
subl $1, %ebx
je .L65
.L43:
movl -108(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -116(%rbp), %rdx
movq -128(%rbp), %rdi
movl -120(%rbp), %esi
.cfi_escape 0x2e,0
call __cudaPushCallConfiguration@PLT
jmp .L66
.L64:
subq $8, %rsp
pushq $1
movq -48(%rbp), %r9
movl -156(%rbp), %r8d
movl -160(%rbp), %ecx
movq -32(%rbp), %rdx
movq -40(%rbp), %rsi
movss -96(%rbp), %xmm0
movl -148(%rbp), %edi
.cfi_escape 0x2e,0x10
call _Z57__device_stub__Z10g_simulateifPiS_iiP17curandStateXORWOWiifPiS_iiP17curandStateXORWOWi
addq $16, %rsp
jmp .L42
.L65:
movq -48(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaFree@PLT
movq -40(%rbp), %rdi
call cudaFree@PLT
movq -32(%rbp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
.LEHE3:
leaq -160(%rbp), %rdi
call _ZN5isingIiED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
movq -8(%rbp), %rbx
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L48:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -160(%rbp), %rdi
call _ZN5isingIiED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
je .L45
call __stack_chk_fail@PLT
.L45:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3889:
.section .gcc_except_table,"a",@progbits
.LLSDA3889:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3889-.LLSDACSB3889
.LLSDACSB3889:
.uleb128 .LEHB0-.LFB3889
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3889
.uleb128 .LEHE1-.LEHB1
.uleb128 .L48-.LFB3889
.uleb128 0
.uleb128 .LEHB2-.LFB3889
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3889
.uleb128 .LEHE3-.LEHB3
.uleb128 .L48-.LFB3889
.uleb128 0
.uleb128 .LEHB4-.LFB3889
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE3889:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2d_ising.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__g_rand_initiP12hiprandState # -- Begin function _Z26__device_stub__g_rand_initiP12hiprandState
.p2align 4, 0x90
.type _Z26__device_stub__g_rand_initiP12hiprandState,@function
_Z26__device_stub__g_rand_initiP12hiprandState: # @_Z26__device_stub__g_rand_initiP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11g_rand_initiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__g_rand_initiP12hiprandState, .Lfunc_end0-_Z26__device_stub__g_rand_initiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z23__device_stub__g_S_initPiiP12hiprandState # -- Begin function _Z23__device_stub__g_S_initPiiP12hiprandState
.p2align 4, 0x90
.type _Z23__device_stub__g_S_initPiiP12hiprandState,@function
_Z23__device_stub__g_S_initPiiP12hiprandState: # @_Z23__device_stub__g_S_initPiiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8g_S_initPiiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__g_S_initPiiP12hiprandState, .Lfunc_end1-_Z23__device_stub__g_S_initPiiP12hiprandState
.cfi_endproc
# -- End function
.globl _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei # -- Begin function _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.p2align 4, 0x90
.type _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei,@function
_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei: # @_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end2:
.size _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei, .Lfunc_end2-_Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3f000000 # float 0.5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rbx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdi
movl $10752, %esi # imm = 0x2A00
movl $10752, %edx # imm = 0x2A00
movl $1, %ecx
callq _ZN5isingIiEC2Eiiif
.Ltmp0:
movq %rbx, %rdi
movl $64, %esi
movl $64, %edx
movl $32, %ecx
movl $32, %r8d
callq _ZN5isingIiE7devInitEiiii
.Ltmp1:
# %bb.1:
cmpl $0, 8(%rsp)
jle .LBB3_2
# %bb.10: # %.lr.ph.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_11: # =>This Inner Loop Header: Depth=1
movq 72(%rsp), %rdi
movq 80(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
incq %rbx
movslq 8(%rsp), %rax
cmpq %rax, %rbx
jl .LBB3_11
.LBB3_2: # %_ZN5isingIiE6toFileEv.exit.preheader
movl $100, %ebp
movq %rsp, %rbx
.p2align 4, 0x90
.LBB3_3: # %_ZN5isingIiE6toFileEv.exit
# =>This Inner Loop Header: Depth=1
.Ltmp2:
movq %rbx, %rdi
callq _ZN5isingIiE3runEv
.Ltmp3:
# %bb.4: # in Loop: Header=BB3_3 Depth=1
decl %ebp
jne .LBB3_3
# %bb.5:
movq 112(%rsp), %rdi
.Ltmp5:
callq hipFree
.Ltmp6:
# %bb.6: # %.noexc
movq 120(%rsp), %rdi
.Ltmp7:
callq hipFree
.Ltmp8:
# %bb.7: # %.noexc10
movq 128(%rsp), %rdi
.Ltmp9:
callq hipFree
.Ltmp10:
# %bb.8: # %.noexc11
.Ltmp11:
callq hipDeviceReset
.Ltmp12:
# %bb.9: # %_ZN5isingIiE6devEndEv.exit
movq 80(%rsp), %rdi
callq free
movq 88(%rsp), %rdi
callq free
movq 96(%rsp), %rdi
callq free
movq 72(%rsp), %rdi
callq fclose
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_12:
.cfi_def_cfa_offset 160
.Ltmp13:
jmp .LBB3_13
.LBB3_14:
.Ltmp4:
.LBB3_13:
movq %rax, %rbx
movq %rsp, %rdi
callq _ZN5isingIiED2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp2-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp2 # Call between .Ltmp2 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp12-.Ltmp5 # Call between .Ltmp5 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end3-.Ltmp12 # Call between .Ltmp12 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _ZN5isingIiEC2Eiiif
.LCPI4_0:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x3f800000 # float 1
.section .text._ZN5isingIiEC2Eiiif,"axG",@progbits,_ZN5isingIiEC2Eiiif,comdat
.weak _ZN5isingIiEC2Eiiif
.p2align 4, 0x90
.type _ZN5isingIiEC2Eiiif,@function
_ZN5isingIiEC2Eiiif: # @_ZN5isingIiEC2Eiiif
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movaps .LCPI4_0(%rip), %xmm1 # xmm1 = [1,1,1,1]
movups %xmm1, 32(%rdi)
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 48(%rdi)
movl %esi, (%rdi)
movl %edx, 4(%rdi)
imull %esi, %edx
movl %edx, 8(%rdi)
movl %ecx, 12(%rdi)
movss .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, 64(%rdi)
movl $0, 60(%rdi)
movslq %edx, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, 80(%rbx)
movq %r14, %rdi
callq malloc
movq %rax, 88(%rbx)
movq %r14, %rdi
callq malloc
movq %rax, 96(%rbx)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 72(%rbx)
testq %rax, %rax
je .LBB4_5
# %bb.1:
movl (%rbx), %edx
movl 4(%rbx), %ecx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
cmpl $0, 8(%rbx)
jle .LBB4_4
# %bb.2: # %.lr.ph
movq 80(%rbx), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_3: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rcx,4)
incq %rcx
movslq 8(%rbx), %rdx
cmpq %rdx, %rcx
jl .LBB4_3
.LBB4_4: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB4_5:
.cfi_def_cfa_offset 32
movl $.Lstr, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size _ZN5isingIiEC2Eiiif, .Lfunc_end4-_ZN5isingIiEC2Eiiif
.cfi_endproc
# -- End function
.section .text._ZN5isingIiE7devInitEiiii,"axG",@progbits,_ZN5isingIiE7devInitEiiii,comdat
.weak _ZN5isingIiE7devInitEiiii # -- Begin function _ZN5isingIiE7devInitEiiii
.p2align 4, 0x90
.type _ZN5isingIiE7devInitEiiii,@function
_ZN5isingIiE7devInitEiiii: # @_ZN5isingIiE7devInitEiiii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl %edx, %eax
imull %esi, %eax
movl %ecx, %edi
imull %r8d, %edi
imull %eax, %edi
movl %edi, 56(%rbx)
movl %esi, 32(%rbx)
movl %edx, 36(%rbx)
movl $1, 40(%rbx)
movl %ecx, 44(%rbx)
movl %r8d, 48(%rbx)
movl $1, 52(%rbx)
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
leaq 112(%rbx), %rdi
movslq 56(%rbx), %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
callq hipMalloc
leaq 120(%rbx), %rdi
movslq 8(%rbx), %rsi
shlq $2, %rsi
callq hipMalloc
leaq 128(%rbx), %rdi
movslq 8(%rbx), %rsi
shlq $2, %rsi
callq hipMalloc
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movl 8(%rbx), %eax
movq 112(%rbx), %rcx
movl %eax, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11g_rand_initiP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3:
movq 120(%rbx), %rax
movl 8(%rbx), %ecx
movq 112(%rbx), %rdx
movq %rax, 64(%rsp)
movl %ecx, 76(%rsp)
movq %rdx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 76(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8g_S_initPiiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_4:
movq 80(%rbx), %rdi
movq 120(%rbx), %rsi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB5_6
# %bb.5:
movq 80(%rbx), %rdi
movq 120(%rbx), %rsi
movslq 8(%rbx), %rdx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
movl $127, %edx
xorl %eax, %eax
callq printf
.LBB5_6:
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _ZN5isingIiE7devInitEiiii, .Lfunc_end5-_ZN5isingIiE7devInitEiiii
.cfi_endproc
# -- End function
.section .text._ZN5isingIiE3runEv,"axG",@progbits,_ZN5isingIiE3runEv,comdat
.weak _ZN5isingIiE3runEv # -- Begin function _ZN5isingIiE3runEv
.p2align 4, 0x90
.type _ZN5isingIiE3runEv,@function
_ZN5isingIiE3runEv: # @_ZN5isingIiE3runEv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $160, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 32(%rdi), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_2
# %bb.1:
movl 12(%rbx), %eax
movss 64(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 120(%rbx), %rcx
movq 128(%rbx), %rdx
movl (%rbx), %esi
movl 4(%rbx), %edi
movq 112(%rbx), %r8
movl %eax, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 12(%rsp)
movl %edi, 8(%rsp)
movq %r8, 72(%rsp)
movl $0, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_2:
movq 32(%rbx), %rdi
movl 40(%rbx), %esi
movq 44(%rbx), %rdx
movl 52(%rbx), %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_4
# %bb.3:
movl 12(%rbx), %eax
movss 64(%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq 120(%rbx), %rcx
movq 128(%rbx), %rdx
movl (%rbx), %esi
movl 4(%rbx), %edi
movq 112(%rbx), %r8
movl %eax, 20(%rsp)
movss %xmm0, 16(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
movl %esi, 12(%rsp)
movl %edi, 8(%rsp)
movq %r8, 72(%rsp)
movl $1, 4(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_4:
addq $160, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZN5isingIiE3runEv, .Lfunc_end6-_ZN5isingIiE3runEv
.cfi_endproc
# -- End function
.section .text._ZN5isingIiED2Ev,"axG",@progbits,_ZN5isingIiED2Ev,comdat
.weak _ZN5isingIiED2Ev # -- Begin function _ZN5isingIiED2Ev
.p2align 4, 0x90
.type _ZN5isingIiED2Ev,@function
_ZN5isingIiED2Ev: # @_ZN5isingIiED2Ev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq 80(%rdi), %rdi
callq free
movq 88(%rbx), %rdi
callq free
movq 96(%rbx), %rdi
callq free
movq 72(%rbx), %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end7:
.size _ZN5isingIiED2Ev, .Lfunc_end7-_ZN5isingIiED2Ev
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11g_rand_initiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8g_S_initPiiP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10g_simulateifPiS_iiP12hiprandStatei, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11g_rand_initiP12hiprandState,@object # @_Z11g_rand_initiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z11g_rand_initiP12hiprandState
.p2align 3, 0x0
_Z11g_rand_initiP12hiprandState:
.quad _Z26__device_stub__g_rand_initiP12hiprandState
.size _Z11g_rand_initiP12hiprandState, 8
.type _Z8g_S_initPiiP12hiprandState,@object # @_Z8g_S_initPiiP12hiprandState
.globl _Z8g_S_initPiiP12hiprandState
.p2align 3, 0x0
_Z8g_S_initPiiP12hiprandState:
.quad _Z23__device_stub__g_S_initPiiP12hiprandState
.size _Z8g_S_initPiiP12hiprandState, 8
.type _Z10g_simulateifPiS_iiP12hiprandStatei,@object # @_Z10g_simulateifPiS_iiP12hiprandStatei
.globl _Z10g_simulateifPiS_iiP12hiprandStatei
.p2align 3, 0x0
_Z10g_simulateifPiS_iiP12hiprandStatei:
.quad _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.size _Z10g_simulateifPiS_iiP12hiprandStatei, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result.dat"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "w"
.size .L.str.1, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "#%9d%9d\n"
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid=[%d,%d],block[%d,%d]\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error %s,at %d\n"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%3d"
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11g_rand_initiP12hiprandState"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8g_S_initPiiP12hiprandState"
.size .L__unnamed_2, 30
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10g_simulateifPiS_iiP12hiprandStatei"
.size .L__unnamed_3, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Error at opening file."
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__g_rand_initiP12hiprandState
.addrsig_sym _Z23__device_stub__g_S_initPiiP12hiprandState
.addrsig_sym _Z25__device_stub__g_simulateifPiS_iiP12hiprandStatei
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z11g_rand_initiP12hiprandState
.addrsig_sym _Z8g_S_initPiiP12hiprandState
.addrsig_sym _Z10g_simulateifPiS_iiP12hiprandStatei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define TRADITIONAL 1
#define N 1024
typedef struct MatrixStruct {
double **data;
int height, width;
} Matrix;
void nrerror(string s){
printf("Numerical Recipes run-time error...\n");
printf("%s\n",s.c_str());
printf("...now exiting to system...\n");
exit(1);
}
double *dvector(int nl, int nh){
double *v;
v = (double *) calloc((unsigned) (nh-nl+1), sizeof(double));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
float *vector(int nl, int nh){
float *v;
v = (float *) calloc((unsigned) (nh-nl+1), sizeof(float));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
void free_dvector(double *v, int nl, int nh){
free((char*) (v+nl));
}
void free_vector(float *v, int nl, int nh){
free((char*) (v+nl));
}
float **matrix(int nrl,int nrh,int ncl,int nch){
float **m;
m = (float **) malloc((unsigned) (nrh-nrl+1)*sizeof(float*));
if (!m) nrerror("allocation failure 1 in matrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i]=(float *) malloc((unsigned) (nch-ncl+1)*sizeof(float));
if (!m[i]) nrerror("allocation failure 2 in matrix()");
m[i] -= ncl;
}
return m;
}
void free_matrix(float **m,int nrl,int nrh,int ncl,int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
double **dmatrix(int nrl, int nrh, int ncl, int nch){
double **m;
m = (double **) calloc((unsigned) (nrh-nrl+1), sizeof(double*));
if (!m) nrerror("allocation failure 1 in dmatrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i] = (double *) calloc((unsigned) (nch-ncl+1), sizeof(double));
if (!m[i]) nrerror("allocation failure 2 in dmatrix()");
m[i] -= ncl;
}
return m;
}
void free_dmatrix(double **m, int nrl, int nrh, int ncl, int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
/*
double log2(double x){
return log10(x) / log10( 2.0 );
}
*/
void CreateMatrix(Matrix **M, int hei, int wid){
Matrix *tmp;
tmp = (Matrix *) calloc(1, sizeof(Matrix));
tmp->data = (double **) calloc(hei, sizeof(double *));
if (!(tmp->data)) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
for (int h = 0 ; h < hei ; h++) {
tmp->data[h] = (double *) calloc(wid, sizeof(double));
if (!(tmp->data[h])) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
}
tmp->height = hei;
tmp->width = wid;
*M = tmp;
}
void FreeMatrix(Matrix *M){
int hei = M->height;
for(int h = 0 ; h < hei ; h++){
free(M->data[h]);
}
free(M->data);
free(M);
}
void four1(double *data, int nn, int isign){
int n, mmax, m, j, istep, i;
double wtemp, wr, wpr, wpi, wi, theta;
double tempr, tempi;
n = nn << 1;
j = 1;
for (i=1;i<n;i+=2) {
if (j > i) {
swap(data[j],data[i]);
swap(data[j+1],data[i+1]);
}
m = n >> 1;
while (m >= 2 && j > m) {
j -= m;
m >>= 1;
}
j += m;
}
mmax = 2;
while (n > mmax) {
istep = 2*mmax;
theta = 6.28318530717959/(isign*mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1;m<mmax;m+=2) {
for (i=m;i<=n;i+=istep) {
j = i+mmax;
tempr = wr*data[j]-wi*data[j+1];
tempi = wr*data[j+1]+wi*data[j];
data[j] = data[i]-tempr;
data[j+1] = data[i+1]-tempi;
data[i] += tempr;
data[i+1] += tempi;
}
wr = (wtemp=wr)*wpr-wi*wpi+wr;
wi = wi*wpr+wtemp*wpi+wi;
}
mmax = istep;
}
}
void four2(double **fftr, double **ffti, double **rdata, double **idata, int rs, int cs, int isign){
/************************************************************
2-D fourier transform of data with real part stored in
"rdata" and imaginary part in "idata" with size "rs" x
"cs". The result is in "fftr" and "ffti". The isign is
"isign" = 1 forward, and "isign" = -1 inverse
*************************************************************/
double **T, *tmp1, *tmp2;
int i, j;
tmp1 = dvector(1,2*cs);
tmp2 = dvector(1,2*rs);
T = dmatrix(1,2*rs,1,cs);
for (i=1;i<=rs;i++) {
for (j=1;j<=cs;j++) {
tmp1[j*2-1] = rdata[i][j];
tmp1[j*2] = idata[i][j];
}
four1(tmp1, cs, isign);
for (j=1;j<=cs;j++) {
T[i*2-1][j] = tmp1[j*2-1];
T[i*2][j] = tmp1[j*2];
}
}
for (i=1;i<=cs;i++) {
for (j=1;j<=rs;j++) {
tmp2[j*2-1] = T[j*2-1][i];
tmp2[j*2] = T[j*2][i];
}
four1(tmp2,rs,isign);
for (j=1;j<=rs;j++) {
fftr[j][i] = tmp2[j*2-1];
ffti[j][i] = tmp2[j*2];
}
}
free_dvector(tmp1, 1, 2*cs);
free_dvector(tmp2, 1, 2*rs);
free_dmatrix(T, 1, 2*rs, 1, cs);
}
void Mat_FFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, 1); /* 2-D FFT */
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j];
Output_imag->data[i-1][j-1] = Fi[i][j];
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_IFFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi, NN;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, -1); /* 2-D IFFT */
NN = (double) (xs*ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j]/NN;
Output_imag->data[i-1][j-1] = Fi[i][j]/NN;
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_Copy(Matrix *A, Matrix *B, int h_target, int w_target, int h_begin, int w_begin, int h_end, int w_end){
int i, j, h, w, h_done, w_done;
if ((h_target >= 0)&&(h_target < A->height)&&(w_target >= 0)&&(w_target < A->width)) {
if ((h_begin >= 0)&&(h_begin < B->height)&&(w_begin >= 0)&&(w_begin < B->width)) {
h = h_end-h_begin+1;
w = w_end-w_begin+1;
if ((h >= 1)&&(w >= 1)) {
h_done = h_target+h-1;
w_done = w_target+w-1;
if ((h_done < A->height)&&(w_done < A->width)) {
for (i=0;i<h;i++) {
for (j=0;j<w;j++) {
A->data[i+h_target][j+w_target] = B->data[i+h_begin][j+w_begin];
}
}
}
}
}
}
else {
printf("matrix dimension error!\n");
exit(1);
}
}
void Mat_Product(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]*C->data[h][w];
}
void Mat_Sum(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A-> height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]+C->data[h][w];
}
void Mat_Substract(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]-C->data[h][w];
}
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag);
void GaborFilteredImg(Matrix *FilteredImg_real, Matrix *FilteredImg_imag, Matrix *img, int side, double Ul, double Uh, int scale, int orientation, int flag){
int h, w, xs, ys, border, r1, r2, r3, r4, hei, wid, s, n, base;
Matrix *IMG, *IMG_imag, *Gr, *Gi, *Tmp_1, *Tmp_2, *F_1, *F_2, *G_real, *G_imag, *F_real, *F_imag,*F;
double m, v;
base = scale*orientation;
double *features; //exact memory
features = (double *)malloc( 2 * scale * orientation * sizeof(double) );
border = side;
hei = img->height;
wid = img->width;
/* FFT2 */
xs = (int) pow(2.0, ceil(log2((double)(img->height+2.0*border))));
ys = (int) pow(2.0, ceil(log2((double)(img->width+2.0*border))));
CreateMatrix(&IMG, xs, ys);
r1 = img->width+border;
r2 = img->width+2*border;
for (h=0;h<border;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[border-1-h][border-1-w];
for (w=border;w<r1;w++)
IMG->data[h][w] = img->data[border-1-h][w-border];
for (w=r1;w<r2;w++)
IMG->data[h][w] = img->data[border-1-h][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->width+border;
r3 = img->width+2*border;
for (h=border;h<r1;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[h-border][border-1-w];
for (w=border;w<r2;w++)
IMG->data[h][w] = img->data[h-border][w-border];
for (w=r2;w<r3;w++)
IMG->data[h][w] = img->data[h-border][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->height+2*border;
r3 = img->width+border;
r4 = img->width+2*border;
for (h=r1;h<r2;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][border-1-w];
for (w=border;w<r3;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][w-border];
for (w=r3;w<r4;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][2*img->width-w+border-1];
}
CreateMatrix(&F_real, xs, ys);
CreateMatrix(&F_imag, xs, ys);
CreateMatrix(&IMG_imag, xs, ys);
Mat_FFT2(F_real, F_imag, IMG, IMG_imag);
/* ----------- compute the Gabor filtered output ------------- */
CreateMatrix(&Gr, 2*side+1, 2*side+1);
CreateMatrix(&Gi, 2*side+1, 2*side+1);
CreateMatrix(&Tmp_1, xs, ys);
CreateMatrix(&Tmp_2, xs, ys);
CreateMatrix(&F_1, xs, ys);
CreateMatrix(&F_2, xs, ys);
CreateMatrix(&G_real, xs, ys);
CreateMatrix(&G_imag, xs, ys);
CreateMatrix(&F, hei, wid);
for (s=0;s<scale;s++){
for (n=0;n<orientation;n++) {
Gabor(Gr, Gi, s+1, n+1, Ul, Uh, scale, orientation, flag);//CUDA- 2 normales y logn
Mat_Copy(F_1, Gr, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_Copy(F_2, Gi, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_FFT2(G_real, G_imag, F_1, F_2);//CUDA-no definido
Mat_Product(Tmp_1, G_real, F_real);//CUDA
Mat_Product(Tmp_2, G_imag, F_imag);//CUDA
Mat_Substract(IMG, Tmp_1, Tmp_2);//CUDA
Mat_Product(Tmp_1, G_real, F_imag);//CUDA
Mat_Product(Tmp_2, G_imag, F_real);//CUDA
Mat_Sum(IMG_imag, Tmp_1, Tmp_2);//CUDA
Mat_IFFT2(Tmp_1, Tmp_2, IMG, IMG_imag);//CUDA-no definido
//CUDA - logn
m = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++) {
F->data[h][w] = sqrt(pow(IMG->data[h][w], 2.0)+pow(IMG_imag->data[h][w], 2.0));
m += F->data[h][w];
}
m /= (double) (hei*wid);
features[s*orientation+n] = (float) m;
//CUDA - logn
v = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++)
v += (F->data[h][w]-m)*(F->data[h][w]-m);
v /= (double) (hei*wid);
features[base+s*orientation+n] = (float) sqrt(v);
Mat_Copy(FilteredImg_real, Tmp_1, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
Mat_Copy(FilteredImg_imag, Tmp_2, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
}
}
for(int i = 0 ; i < (2 * scale * orientation) ; i++)
printf("%.8lf ",features[i]);
printf("\n");
cout << 2 * scale * orientation << endl;
FreeMatrix(Gr);
FreeMatrix(Gi);
FreeMatrix(Tmp_1);
FreeMatrix(Tmp_2);
FreeMatrix(F_1);
FreeMatrix(F_2);
FreeMatrix(G_real);
FreeMatrix(G_imag);
FreeMatrix(F_real);
FreeMatrix(F_imag);
FreeMatrix(IMG);
FreeMatrix(IMG_imag);
}
/* ------------------------------------------------------------------------------------------------------
The Gabor function generates a Gabor filter with the selected index 's' and 'n' (scale and orientation,
respectively) from a Gabor filter bank. This filter bank is designed by giving the range of spatial
frequency (Uh and Ul) and the total number of scales and orientations used to partition the spectrum.
The returned filter is stored in 'Gr' (real part) and 'Gi' (imaginary part).
--------------------------------------------------------------------------------------------------------*/
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag){
double base, a, u0, z, Uvar, Vvar, Xvar, Yvar, X, Y, G, t1, t2, m;
int x, y, side;
base = Uh/Ul;
a = pow(base, 1.0/(double)(scale-1));
u0 = Uh/pow(a, (double) scale-s);
Uvar = (a-1.0)*u0/((a+1.0)*sqrt(2.0*log(2.0)));
z = -2.0*log(2.0)*(Uvar*Uvar)/u0;
Vvar = tan(pi/(2*orientation))*(u0+z)/sqrt(2.0*log(2.0)-z*z/(Uvar*Uvar));
Xvar = 1.0/(2.0*pi*Uvar);
Yvar = 1.0/(2.0*pi*Vvar);
t1 = cos(pi/orientation*(n-1.0));
t2 = sin(pi/orientation*(n-1.0));
side = (int) (Gr->height-1)/2;
//CUDA
for (x=0;x<2*side+1;x++) {
for (y=0;y<2*side+1;y++) {
X = (double) (x-side)*t1+ (double) (y-side)*t2;
Y = (double) -(x-side)*t2+ (double) (y-side)*t1;
G = 1.0/(2.0*pi*Xvar*Yvar)*pow(a, (double) scale-s)*exp(-0.5*((X*X)/(Xvar*Xvar)+(Y*Y)/(Yvar*Yvar)));
Gr->data[x][y] = G*cos(2.0*pi*u0*X);
Gi->data[x][y] = G*sin(2.0*pi*u0*X);
}
}
/* if flag = 1, then remove the DC from the filter */
if (flag == 1) {
//CUDA - logn
m = 0;
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
m += Gr->data[x][y];
m /= pow((double) 2.0*side+1, 2.0);
//CUDA
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
Gr->data[x][y] -= m;
}
}
int main(int argc, char **argv){
int hei, wid, side, scale, orientation, flag;//, s, n;
//Matrix *Gabor_r, *Gabor_i, *Gr, *Gi, *img, *F_r, *F_i;
Matrix *img , *F_r , *F_i;
FILE *fp;
unsigned char *tmp;
//float *output;
double Ul, Uh;
/* --------------------------- Example --------------------------------
scale = 3,
orientation = 4,
Uh (highest spatial frequency) = 0.4,
Ul (lowest spatial frequency) = 0.1,
flag (removing the DC term) = 0 (False),
side (filter dimension = (2*side+1)*(2*side+1)) = 60
----------------------------------------------------------------------- */
scale = 3;
orientation = 4;
Ul = 0.1;
Uh = 0.4;
flag = 0;
side = 60;
if (argc != 4) {
printf("usage: %s <image_name> <height> <width>\n",argv[0]);
exit(0);
}
hei = atoi(argv[2]);
wid = atoi(argv[3]);
tmp = (unsigned char *) calloc(hei*wid, sizeof(unsigned char));
if ((fp = fopen(argv[1],"r")) == NULL) {
printf("%s can not be open!\n", argv[1]);
exit(0);
}
fread(tmp, sizeof(unsigned char), hei*wid, fp);
fclose(fp);
CreateMatrix(&img, hei, wid);
for(int i = 0 ; i < hei ; i++)
for(int j = 0 ; j < wid ; j++)
img->data[i][j] = (double) (tmp[i*wid+j]);
free(tmp);
CreateMatrix(&F_r, hei*scale, wid*orientation);
CreateMatrix(&F_i, hei*scale, wid*orientation);
GaborFilteredImg(F_r, F_i, img, side, Ul, Uh, scale, orientation, flag);
FreeMatrix(F_r);
FreeMatrix(F_i);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define TRADITIONAL 1
#define N 1024
typedef struct MatrixStruct {
double **data;
int height, width;
} Matrix;
void nrerror(string s){
printf("Numerical Recipes run-time error...\n");
printf("%s\n",s.c_str());
printf("...now exiting to system...\n");
exit(1);
}
double *dvector(int nl, int nh){
double *v;
v = (double *) calloc((unsigned) (nh-nl+1), sizeof(double));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
float *vector(int nl, int nh){
float *v;
v = (float *) calloc((unsigned) (nh-nl+1), sizeof(float));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
void free_dvector(double *v, int nl, int nh){
free((char*) (v+nl));
}
void free_vector(float *v, int nl, int nh){
free((char*) (v+nl));
}
float **matrix(int nrl,int nrh,int ncl,int nch){
float **m;
m = (float **) malloc((unsigned) (nrh-nrl+1)*sizeof(float*));
if (!m) nrerror("allocation failure 1 in matrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i]=(float *) malloc((unsigned) (nch-ncl+1)*sizeof(float));
if (!m[i]) nrerror("allocation failure 2 in matrix()");
m[i] -= ncl;
}
return m;
}
void free_matrix(float **m,int nrl,int nrh,int ncl,int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
double **dmatrix(int nrl, int nrh, int ncl, int nch){
double **m;
m = (double **) calloc((unsigned) (nrh-nrl+1), sizeof(double*));
if (!m) nrerror("allocation failure 1 in dmatrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i] = (double *) calloc((unsigned) (nch-ncl+1), sizeof(double));
if (!m[i]) nrerror("allocation failure 2 in dmatrix()");
m[i] -= ncl;
}
return m;
}
void free_dmatrix(double **m, int nrl, int nrh, int ncl, int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
/*
double log2(double x){
return log10(x) / log10( 2.0 );
}
*/
void CreateMatrix(Matrix **M, int hei, int wid){
Matrix *tmp;
tmp = (Matrix *) calloc(1, sizeof(Matrix));
tmp->data = (double **) calloc(hei, sizeof(double *));
if (!(tmp->data)) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
for (int h = 0 ; h < hei ; h++) {
tmp->data[h] = (double *) calloc(wid, sizeof(double));
if (!(tmp->data[h])) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
}
tmp->height = hei;
tmp->width = wid;
*M = tmp;
}
void FreeMatrix(Matrix *M){
int hei = M->height;
for(int h = 0 ; h < hei ; h++){
free(M->data[h]);
}
free(M->data);
free(M);
}
void four1(double *data, int nn, int isign){
int n, mmax, m, j, istep, i;
double wtemp, wr, wpr, wpi, wi, theta;
double tempr, tempi;
n = nn << 1;
j = 1;
for (i=1;i<n;i+=2) {
if (j > i) {
swap(data[j],data[i]);
swap(data[j+1],data[i+1]);
}
m = n >> 1;
while (m >= 2 && j > m) {
j -= m;
m >>= 1;
}
j += m;
}
mmax = 2;
while (n > mmax) {
istep = 2*mmax;
theta = 6.28318530717959/(isign*mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1;m<mmax;m+=2) {
for (i=m;i<=n;i+=istep) {
j = i+mmax;
tempr = wr*data[j]-wi*data[j+1];
tempi = wr*data[j+1]+wi*data[j];
data[j] = data[i]-tempr;
data[j+1] = data[i+1]-tempi;
data[i] += tempr;
data[i+1] += tempi;
}
wr = (wtemp=wr)*wpr-wi*wpi+wr;
wi = wi*wpr+wtemp*wpi+wi;
}
mmax = istep;
}
}
void four2(double **fftr, double **ffti, double **rdata, double **idata, int rs, int cs, int isign){
/************************************************************
2-D fourier transform of data with real part stored in
"rdata" and imaginary part in "idata" with size "rs" x
"cs". The result is in "fftr" and "ffti". The isign is
"isign" = 1 forward, and "isign" = -1 inverse
*************************************************************/
double **T, *tmp1, *tmp2;
int i, j;
tmp1 = dvector(1,2*cs);
tmp2 = dvector(1,2*rs);
T = dmatrix(1,2*rs,1,cs);
for (i=1;i<=rs;i++) {
for (j=1;j<=cs;j++) {
tmp1[j*2-1] = rdata[i][j];
tmp1[j*2] = idata[i][j];
}
four1(tmp1, cs, isign);
for (j=1;j<=cs;j++) {
T[i*2-1][j] = tmp1[j*2-1];
T[i*2][j] = tmp1[j*2];
}
}
for (i=1;i<=cs;i++) {
for (j=1;j<=rs;j++) {
tmp2[j*2-1] = T[j*2-1][i];
tmp2[j*2] = T[j*2][i];
}
four1(tmp2,rs,isign);
for (j=1;j<=rs;j++) {
fftr[j][i] = tmp2[j*2-1];
ffti[j][i] = tmp2[j*2];
}
}
free_dvector(tmp1, 1, 2*cs);
free_dvector(tmp2, 1, 2*rs);
free_dmatrix(T, 1, 2*rs, 1, cs);
}
void Mat_FFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, 1); /* 2-D FFT */
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j];
Output_imag->data[i-1][j-1] = Fi[i][j];
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_IFFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi, NN;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, -1); /* 2-D IFFT */
NN = (double) (xs*ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j]/NN;
Output_imag->data[i-1][j-1] = Fi[i][j]/NN;
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_Copy(Matrix *A, Matrix *B, int h_target, int w_target, int h_begin, int w_begin, int h_end, int w_end){
int i, j, h, w, h_done, w_done;
if ((h_target >= 0)&&(h_target < A->height)&&(w_target >= 0)&&(w_target < A->width)) {
if ((h_begin >= 0)&&(h_begin < B->height)&&(w_begin >= 0)&&(w_begin < B->width)) {
h = h_end-h_begin+1;
w = w_end-w_begin+1;
if ((h >= 1)&&(w >= 1)) {
h_done = h_target+h-1;
w_done = w_target+w-1;
if ((h_done < A->height)&&(w_done < A->width)) {
for (i=0;i<h;i++) {
for (j=0;j<w;j++) {
A->data[i+h_target][j+w_target] = B->data[i+h_begin][j+w_begin];
}
}
}
}
}
}
else {
printf("matrix dimension error!\n");
exit(1);
}
}
void Mat_Product(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]*C->data[h][w];
}
void Mat_Sum(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A-> height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]+C->data[h][w];
}
void Mat_Substract(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]-C->data[h][w];
}
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag);
void GaborFilteredImg(Matrix *FilteredImg_real, Matrix *FilteredImg_imag, Matrix *img, int side, double Ul, double Uh, int scale, int orientation, int flag){
int h, w, xs, ys, border, r1, r2, r3, r4, hei, wid, s, n, base;
Matrix *IMG, *IMG_imag, *Gr, *Gi, *Tmp_1, *Tmp_2, *F_1, *F_2, *G_real, *G_imag, *F_real, *F_imag,*F;
double m, v;
base = scale*orientation;
double *features; //exact memory
features = (double *)malloc( 2 * scale * orientation * sizeof(double) );
border = side;
hei = img->height;
wid = img->width;
/* FFT2 */
xs = (int) pow(2.0, ceil(log2((double)(img->height+2.0*border))));
ys = (int) pow(2.0, ceil(log2((double)(img->width+2.0*border))));
CreateMatrix(&IMG, xs, ys);
r1 = img->width+border;
r2 = img->width+2*border;
for (h=0;h<border;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[border-1-h][border-1-w];
for (w=border;w<r1;w++)
IMG->data[h][w] = img->data[border-1-h][w-border];
for (w=r1;w<r2;w++)
IMG->data[h][w] = img->data[border-1-h][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->width+border;
r3 = img->width+2*border;
for (h=border;h<r1;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[h-border][border-1-w];
for (w=border;w<r2;w++)
IMG->data[h][w] = img->data[h-border][w-border];
for (w=r2;w<r3;w++)
IMG->data[h][w] = img->data[h-border][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->height+2*border;
r3 = img->width+border;
r4 = img->width+2*border;
for (h=r1;h<r2;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][border-1-w];
for (w=border;w<r3;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][w-border];
for (w=r3;w<r4;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][2*img->width-w+border-1];
}
CreateMatrix(&F_real, xs, ys);
CreateMatrix(&F_imag, xs, ys);
CreateMatrix(&IMG_imag, xs, ys);
Mat_FFT2(F_real, F_imag, IMG, IMG_imag);
/* ----------- compute the Gabor filtered output ------------- */
CreateMatrix(&Gr, 2*side+1, 2*side+1);
CreateMatrix(&Gi, 2*side+1, 2*side+1);
CreateMatrix(&Tmp_1, xs, ys);
CreateMatrix(&Tmp_2, xs, ys);
CreateMatrix(&F_1, xs, ys);
CreateMatrix(&F_2, xs, ys);
CreateMatrix(&G_real, xs, ys);
CreateMatrix(&G_imag, xs, ys);
CreateMatrix(&F, hei, wid);
for (s=0;s<scale;s++){
for (n=0;n<orientation;n++) {
Gabor(Gr, Gi, s+1, n+1, Ul, Uh, scale, orientation, flag);//CUDA- 2 normales y logn
Mat_Copy(F_1, Gr, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_Copy(F_2, Gi, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_FFT2(G_real, G_imag, F_1, F_2);//CUDA-no definido
Mat_Product(Tmp_1, G_real, F_real);//CUDA
Mat_Product(Tmp_2, G_imag, F_imag);//CUDA
Mat_Substract(IMG, Tmp_1, Tmp_2);//CUDA
Mat_Product(Tmp_1, G_real, F_imag);//CUDA
Mat_Product(Tmp_2, G_imag, F_real);//CUDA
Mat_Sum(IMG_imag, Tmp_1, Tmp_2);//CUDA
Mat_IFFT2(Tmp_1, Tmp_2, IMG, IMG_imag);//CUDA-no definido
//CUDA - logn
m = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++) {
F->data[h][w] = sqrt(pow(IMG->data[h][w], 2.0)+pow(IMG_imag->data[h][w], 2.0));
m += F->data[h][w];
}
m /= (double) (hei*wid);
features[s*orientation+n] = (float) m;
//CUDA - logn
v = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++)
v += (F->data[h][w]-m)*(F->data[h][w]-m);
v /= (double) (hei*wid);
features[base+s*orientation+n] = (float) sqrt(v);
Mat_Copy(FilteredImg_real, Tmp_1, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
Mat_Copy(FilteredImg_imag, Tmp_2, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
}
}
for(int i = 0 ; i < (2 * scale * orientation) ; i++)
printf("%.8lf ",features[i]);
printf("\n");
cout << 2 * scale * orientation << endl;
FreeMatrix(Gr);
FreeMatrix(Gi);
FreeMatrix(Tmp_1);
FreeMatrix(Tmp_2);
FreeMatrix(F_1);
FreeMatrix(F_2);
FreeMatrix(G_real);
FreeMatrix(G_imag);
FreeMatrix(F_real);
FreeMatrix(F_imag);
FreeMatrix(IMG);
FreeMatrix(IMG_imag);
}
/* ------------------------------------------------------------------------------------------------------
The Gabor function generates a Gabor filter with the selected index 's' and 'n' (scale and orientation,
respectively) from a Gabor filter bank. This filter bank is designed by giving the range of spatial
frequency (Uh and Ul) and the total number of scales and orientations used to partition the spectrum.
The returned filter is stored in 'Gr' (real part) and 'Gi' (imaginary part).
--------------------------------------------------------------------------------------------------------*/
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag){
double base, a, u0, z, Uvar, Vvar, Xvar, Yvar, X, Y, G, t1, t2, m;
int x, y, side;
base = Uh/Ul;
a = pow(base, 1.0/(double)(scale-1));
u0 = Uh/pow(a, (double) scale-s);
Uvar = (a-1.0)*u0/((a+1.0)*sqrt(2.0*log(2.0)));
z = -2.0*log(2.0)*(Uvar*Uvar)/u0;
Vvar = tan(pi/(2*orientation))*(u0+z)/sqrt(2.0*log(2.0)-z*z/(Uvar*Uvar));
Xvar = 1.0/(2.0*pi*Uvar);
Yvar = 1.0/(2.0*pi*Vvar);
t1 = cos(pi/orientation*(n-1.0));
t2 = sin(pi/orientation*(n-1.0));
side = (int) (Gr->height-1)/2;
//CUDA
for (x=0;x<2*side+1;x++) {
for (y=0;y<2*side+1;y++) {
X = (double) (x-side)*t1+ (double) (y-side)*t2;
Y = (double) -(x-side)*t2+ (double) (y-side)*t1;
G = 1.0/(2.0*pi*Xvar*Yvar)*pow(a, (double) scale-s)*exp(-0.5*((X*X)/(Xvar*Xvar)+(Y*Y)/(Yvar*Yvar)));
Gr->data[x][y] = G*cos(2.0*pi*u0*X);
Gi->data[x][y] = G*sin(2.0*pi*u0*X);
}
}
/* if flag = 1, then remove the DC from the filter */
if (flag == 1) {
//CUDA - logn
m = 0;
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
m += Gr->data[x][y];
m /= pow((double) 2.0*side+1, 2.0);
//CUDA
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
Gr->data[x][y] -= m;
}
}
int main(int argc, char **argv){
int hei, wid, side, scale, orientation, flag;//, s, n;
//Matrix *Gabor_r, *Gabor_i, *Gr, *Gi, *img, *F_r, *F_i;
Matrix *img , *F_r , *F_i;
FILE *fp;
unsigned char *tmp;
//float *output;
double Ul, Uh;
/* --------------------------- Example --------------------------------
scale = 3,
orientation = 4,
Uh (highest spatial frequency) = 0.4,
Ul (lowest spatial frequency) = 0.1,
flag (removing the DC term) = 0 (False),
side (filter dimension = (2*side+1)*(2*side+1)) = 60
----------------------------------------------------------------------- */
scale = 3;
orientation = 4;
Ul = 0.1;
Uh = 0.4;
flag = 0;
side = 60;
if (argc != 4) {
printf("usage: %s <image_name> <height> <width>\n",argv[0]);
exit(0);
}
hei = atoi(argv[2]);
wid = atoi(argv[3]);
tmp = (unsigned char *) calloc(hei*wid, sizeof(unsigned char));
if ((fp = fopen(argv[1],"r")) == NULL) {
printf("%s can not be open!\n", argv[1]);
exit(0);
}
fread(tmp, sizeof(unsigned char), hei*wid, fp);
fclose(fp);
CreateMatrix(&img, hei, wid);
for(int i = 0 ; i < hei ; i++)
for(int j = 0 ; j < wid ; j++)
img->data[i][j] = (double) (tmp[i*wid+j]);
free(tmp);
CreateMatrix(&F_r, hei*scale, wid*orientation);
CreateMatrix(&F_i, hei*scale, wid*orientation);
GaborFilteredImg(F_r, F_i, img, side, Ul, Uh, scale, orientation, flag);
FreeMatrix(F_r);
FreeMatrix(F_i);
return 0;
} | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define TRADITIONAL 1
#define N 1024
typedef struct MatrixStruct {
double **data;
int height, width;
} Matrix;
void nrerror(string s){
printf("Numerical Recipes run-time error...\n");
printf("%s\n",s.c_str());
printf("...now exiting to system...\n");
exit(1);
}
double *dvector(int nl, int nh){
double *v;
v = (double *) calloc((unsigned) (nh-nl+1), sizeof(double));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
float *vector(int nl, int nh){
float *v;
v = (float *) calloc((unsigned) (nh-nl+1), sizeof(float));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
void free_dvector(double *v, int nl, int nh){
free((char*) (v+nl));
}
void free_vector(float *v, int nl, int nh){
free((char*) (v+nl));
}
float **matrix(int nrl,int nrh,int ncl,int nch){
float **m;
m = (float **) malloc((unsigned) (nrh-nrl+1)*sizeof(float*));
if (!m) nrerror("allocation failure 1 in matrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i]=(float *) malloc((unsigned) (nch-ncl+1)*sizeof(float));
if (!m[i]) nrerror("allocation failure 2 in matrix()");
m[i] -= ncl;
}
return m;
}
void free_matrix(float **m,int nrl,int nrh,int ncl,int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
double **dmatrix(int nrl, int nrh, int ncl, int nch){
double **m;
m = (double **) calloc((unsigned) (nrh-nrl+1), sizeof(double*));
if (!m) nrerror("allocation failure 1 in dmatrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i] = (double *) calloc((unsigned) (nch-ncl+1), sizeof(double));
if (!m[i]) nrerror("allocation failure 2 in dmatrix()");
m[i] -= ncl;
}
return m;
}
void free_dmatrix(double **m, int nrl, int nrh, int ncl, int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
/*
double log2(double x){
return log10(x) / log10( 2.0 );
}
*/
void CreateMatrix(Matrix **M, int hei, int wid){
Matrix *tmp;
tmp = (Matrix *) calloc(1, sizeof(Matrix));
tmp->data = (double **) calloc(hei, sizeof(double *));
if (!(tmp->data)) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
for (int h = 0 ; h < hei ; h++) {
tmp->data[h] = (double *) calloc(wid, sizeof(double));
if (!(tmp->data[h])) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
}
tmp->height = hei;
tmp->width = wid;
*M = tmp;
}
void FreeMatrix(Matrix *M){
int hei = M->height;
for(int h = 0 ; h < hei ; h++){
free(M->data[h]);
}
free(M->data);
free(M);
}
void four1(double *data, int nn, int isign){
int n, mmax, m, j, istep, i;
double wtemp, wr, wpr, wpi, wi, theta;
double tempr, tempi;
n = nn << 1;
j = 1;
for (i=1;i<n;i+=2) {
if (j > i) {
swap(data[j],data[i]);
swap(data[j+1],data[i+1]);
}
m = n >> 1;
while (m >= 2 && j > m) {
j -= m;
m >>= 1;
}
j += m;
}
mmax = 2;
while (n > mmax) {
istep = 2*mmax;
theta = 6.28318530717959/(isign*mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1;m<mmax;m+=2) {
for (i=m;i<=n;i+=istep) {
j = i+mmax;
tempr = wr*data[j]-wi*data[j+1];
tempi = wr*data[j+1]+wi*data[j];
data[j] = data[i]-tempr;
data[j+1] = data[i+1]-tempi;
data[i] += tempr;
data[i+1] += tempi;
}
wr = (wtemp=wr)*wpr-wi*wpi+wr;
wi = wi*wpr+wtemp*wpi+wi;
}
mmax = istep;
}
}
void four2(double **fftr, double **ffti, double **rdata, double **idata, int rs, int cs, int isign){
/************************************************************
2-D fourier transform of data with real part stored in
"rdata" and imaginary part in "idata" with size "rs" x
"cs". The result is in "fftr" and "ffti". The isign is
"isign" = 1 forward, and "isign" = -1 inverse
*************************************************************/
double **T, *tmp1, *tmp2;
int i, j;
tmp1 = dvector(1,2*cs);
tmp2 = dvector(1,2*rs);
T = dmatrix(1,2*rs,1,cs);
for (i=1;i<=rs;i++) {
for (j=1;j<=cs;j++) {
tmp1[j*2-1] = rdata[i][j];
tmp1[j*2] = idata[i][j];
}
four1(tmp1, cs, isign);
for (j=1;j<=cs;j++) {
T[i*2-1][j] = tmp1[j*2-1];
T[i*2][j] = tmp1[j*2];
}
}
for (i=1;i<=cs;i++) {
for (j=1;j<=rs;j++) {
tmp2[j*2-1] = T[j*2-1][i];
tmp2[j*2] = T[j*2][i];
}
four1(tmp2,rs,isign);
for (j=1;j<=rs;j++) {
fftr[j][i] = tmp2[j*2-1];
ffti[j][i] = tmp2[j*2];
}
}
free_dvector(tmp1, 1, 2*cs);
free_dvector(tmp2, 1, 2*rs);
free_dmatrix(T, 1, 2*rs, 1, cs);
}
void Mat_FFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, 1); /* 2-D FFT */
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j];
Output_imag->data[i-1][j-1] = Fi[i][j];
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_IFFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi, NN;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, -1); /* 2-D IFFT */
NN = (double) (xs*ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j]/NN;
Output_imag->data[i-1][j-1] = Fi[i][j]/NN;
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_Copy(Matrix *A, Matrix *B, int h_target, int w_target, int h_begin, int w_begin, int h_end, int w_end){
int i, j, h, w, h_done, w_done;
if ((h_target >= 0)&&(h_target < A->height)&&(w_target >= 0)&&(w_target < A->width)) {
if ((h_begin >= 0)&&(h_begin < B->height)&&(w_begin >= 0)&&(w_begin < B->width)) {
h = h_end-h_begin+1;
w = w_end-w_begin+1;
if ((h >= 1)&&(w >= 1)) {
h_done = h_target+h-1;
w_done = w_target+w-1;
if ((h_done < A->height)&&(w_done < A->width)) {
for (i=0;i<h;i++) {
for (j=0;j<w;j++) {
A->data[i+h_target][j+w_target] = B->data[i+h_begin][j+w_begin];
}
}
}
}
}
}
else {
printf("matrix dimension error!\n");
exit(1);
}
}
void Mat_Product(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]*C->data[h][w];
}
void Mat_Sum(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A-> height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]+C->data[h][w];
}
void Mat_Substract(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]-C->data[h][w];
}
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag);
void GaborFilteredImg(Matrix *FilteredImg_real, Matrix *FilteredImg_imag, Matrix *img, int side, double Ul, double Uh, int scale, int orientation, int flag){
int h, w, xs, ys, border, r1, r2, r3, r4, hei, wid, s, n, base;
Matrix *IMG, *IMG_imag, *Gr, *Gi, *Tmp_1, *Tmp_2, *F_1, *F_2, *G_real, *G_imag, *F_real, *F_imag,*F;
double m, v;
base = scale*orientation;
double *features; //exact memory
features = (double *)malloc( 2 * scale * orientation * sizeof(double) );
border = side;
hei = img->height;
wid = img->width;
/* FFT2 */
xs = (int) pow(2.0, ceil(log2((double)(img->height+2.0*border))));
ys = (int) pow(2.0, ceil(log2((double)(img->width+2.0*border))));
CreateMatrix(&IMG, xs, ys);
r1 = img->width+border;
r2 = img->width+2*border;
for (h=0;h<border;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[border-1-h][border-1-w];
for (w=border;w<r1;w++)
IMG->data[h][w] = img->data[border-1-h][w-border];
for (w=r1;w<r2;w++)
IMG->data[h][w] = img->data[border-1-h][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->width+border;
r3 = img->width+2*border;
for (h=border;h<r1;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[h-border][border-1-w];
for (w=border;w<r2;w++)
IMG->data[h][w] = img->data[h-border][w-border];
for (w=r2;w<r3;w++)
IMG->data[h][w] = img->data[h-border][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->height+2*border;
r3 = img->width+border;
r4 = img->width+2*border;
for (h=r1;h<r2;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][border-1-w];
for (w=border;w<r3;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][w-border];
for (w=r3;w<r4;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][2*img->width-w+border-1];
}
CreateMatrix(&F_real, xs, ys);
CreateMatrix(&F_imag, xs, ys);
CreateMatrix(&IMG_imag, xs, ys);
Mat_FFT2(F_real, F_imag, IMG, IMG_imag);
/* ----------- compute the Gabor filtered output ------------- */
CreateMatrix(&Gr, 2*side+1, 2*side+1);
CreateMatrix(&Gi, 2*side+1, 2*side+1);
CreateMatrix(&Tmp_1, xs, ys);
CreateMatrix(&Tmp_2, xs, ys);
CreateMatrix(&F_1, xs, ys);
CreateMatrix(&F_2, xs, ys);
CreateMatrix(&G_real, xs, ys);
CreateMatrix(&G_imag, xs, ys);
CreateMatrix(&F, hei, wid);
for (s=0;s<scale;s++){
for (n=0;n<orientation;n++) {
Gabor(Gr, Gi, s+1, n+1, Ul, Uh, scale, orientation, flag);//CUDA- 2 normales y logn
Mat_Copy(F_1, Gr, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_Copy(F_2, Gi, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_FFT2(G_real, G_imag, F_1, F_2);//CUDA-no definido
Mat_Product(Tmp_1, G_real, F_real);//CUDA
Mat_Product(Tmp_2, G_imag, F_imag);//CUDA
Mat_Substract(IMG, Tmp_1, Tmp_2);//CUDA
Mat_Product(Tmp_1, G_real, F_imag);//CUDA
Mat_Product(Tmp_2, G_imag, F_real);//CUDA
Mat_Sum(IMG_imag, Tmp_1, Tmp_2);//CUDA
Mat_IFFT2(Tmp_1, Tmp_2, IMG, IMG_imag);//CUDA-no definido
//CUDA - logn
m = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++) {
F->data[h][w] = sqrt(pow(IMG->data[h][w], 2.0)+pow(IMG_imag->data[h][w], 2.0));
m += F->data[h][w];
}
m /= (double) (hei*wid);
features[s*orientation+n] = (float) m;
//CUDA - logn
v = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++)
v += (F->data[h][w]-m)*(F->data[h][w]-m);
v /= (double) (hei*wid);
features[base+s*orientation+n] = (float) sqrt(v);
Mat_Copy(FilteredImg_real, Tmp_1, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
Mat_Copy(FilteredImg_imag, Tmp_2, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
}
}
for(int i = 0 ; i < (2 * scale * orientation) ; i++)
printf("%.8lf ",features[i]);
printf("\n");
cout << 2 * scale * orientation << endl;
FreeMatrix(Gr);
FreeMatrix(Gi);
FreeMatrix(Tmp_1);
FreeMatrix(Tmp_2);
FreeMatrix(F_1);
FreeMatrix(F_2);
FreeMatrix(G_real);
FreeMatrix(G_imag);
FreeMatrix(F_real);
FreeMatrix(F_imag);
FreeMatrix(IMG);
FreeMatrix(IMG_imag);
}
/* ------------------------------------------------------------------------------------------------------
The Gabor function generates a Gabor filter with the selected index 's' and 'n' (scale and orientation,
respectively) from a Gabor filter bank. This filter bank is designed by giving the range of spatial
frequency (Uh and Ul) and the total number of scales and orientations used to partition the spectrum.
The returned filter is stored in 'Gr' (real part) and 'Gi' (imaginary part).
--------------------------------------------------------------------------------------------------------*/
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag){
double base, a, u0, z, Uvar, Vvar, Xvar, Yvar, X, Y, G, t1, t2, m;
int x, y, side;
base = Uh/Ul;
a = pow(base, 1.0/(double)(scale-1));
u0 = Uh/pow(a, (double) scale-s);
Uvar = (a-1.0)*u0/((a+1.0)*sqrt(2.0*log(2.0)));
z = -2.0*log(2.0)*(Uvar*Uvar)/u0;
Vvar = tan(pi/(2*orientation))*(u0+z)/sqrt(2.0*log(2.0)-z*z/(Uvar*Uvar));
Xvar = 1.0/(2.0*pi*Uvar);
Yvar = 1.0/(2.0*pi*Vvar);
t1 = cos(pi/orientation*(n-1.0));
t2 = sin(pi/orientation*(n-1.0));
side = (int) (Gr->height-1)/2;
//CUDA
for (x=0;x<2*side+1;x++) {
for (y=0;y<2*side+1;y++) {
X = (double) (x-side)*t1+ (double) (y-side)*t2;
Y = (double) -(x-side)*t2+ (double) (y-side)*t1;
G = 1.0/(2.0*pi*Xvar*Yvar)*pow(a, (double) scale-s)*exp(-0.5*((X*X)/(Xvar*Xvar)+(Y*Y)/(Yvar*Yvar)));
Gr->data[x][y] = G*cos(2.0*pi*u0*X);
Gi->data[x][y] = G*sin(2.0*pi*u0*X);
}
}
/* if flag = 1, then remove the DC from the filter */
if (flag == 1) {
//CUDA - logn
m = 0;
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
m += Gr->data[x][y];
m /= pow((double) 2.0*side+1, 2.0);
//CUDA
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
Gr->data[x][y] -= m;
}
}
int main(int argc, char **argv){
int hei, wid, side, scale, orientation, flag;//, s, n;
//Matrix *Gabor_r, *Gabor_i, *Gr, *Gi, *img, *F_r, *F_i;
Matrix *img , *F_r , *F_i;
FILE *fp;
unsigned char *tmp;
//float *output;
double Ul, Uh;
/* --------------------------- Example --------------------------------
scale = 3,
orientation = 4,
Uh (highest spatial frequency) = 0.4,
Ul (lowest spatial frequency) = 0.1,
flag (removing the DC term) = 0 (False),
side (filter dimension = (2*side+1)*(2*side+1)) = 60
----------------------------------------------------------------------- */
scale = 3;
orientation = 4;
Ul = 0.1;
Uh = 0.4;
flag = 0;
side = 60;
if (argc != 4) {
printf("usage: %s <image_name> <height> <width>\n",argv[0]);
exit(0);
}
hei = atoi(argv[2]);
wid = atoi(argv[3]);
tmp = (unsigned char *) calloc(hei*wid, sizeof(unsigned char));
if ((fp = fopen(argv[1],"r")) == NULL) {
printf("%s can not be open!\n", argv[1]);
exit(0);
}
fread(tmp, sizeof(unsigned char), hei*wid, fp);
fclose(fp);
CreateMatrix(&img, hei, wid);
for(int i = 0 ; i < hei ; i++)
for(int j = 0 ; j < wid ; j++)
img->data[i][j] = (double) (tmp[i*wid+j]);
free(tmp);
CreateMatrix(&F_r, hei*scale, wid*orientation);
CreateMatrix(&F_i, hei*scale, wid*orientation);
GaborFilteredImg(F_r, F_i, img, side, Ul, Uh, scale, orientation, flag);
FreeMatrix(F_r);
FreeMatrix(F_i);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<bits/stdc++.h>
using namespace std;
#define pi (2.0*acos(0.0))
#define eps 1e-6
#define ll long long
#define inf (1<<29)
#define vi vector<int>
#define vll vector<ll>
#define sc(x) scanf("%d",&x)
#define scl(x) scanf("%lld",&x)
#define all(v) v.begin() , v.end()
#define me(a,val) memset( a , val ,sizeof(a) )
#define pb(x) push_back(x)
#define pii pair<int,int>
#define mp(a,b) make_pair(a,b)
#define Q(x) (x) * (x)
#define L(x) ((x<<1) + 1)
#define R(x) ((x<<1) + 2)
#define M(x,y) ((x+y)>>1)
#define fi first
#define se second
#define MOD 1000000007
#define ios ios::sync_with_stdio(0)
#define TRADITIONAL 1
#define N 1024
typedef struct MatrixStruct {
double **data;
int height, width;
} Matrix;
void nrerror(string s){
printf("Numerical Recipes run-time error...\n");
printf("%s\n",s.c_str());
printf("...now exiting to system...\n");
exit(1);
}
double *dvector(int nl, int nh){
double *v;
v = (double *) calloc((unsigned) (nh-nl+1), sizeof(double));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
float *vector(int nl, int nh){
float *v;
v = (float *) calloc((unsigned) (nh-nl+1), sizeof(float));
if (!v) nrerror("allocation failure in dvector()");
return v-nl;
}
void free_dvector(double *v, int nl, int nh){
free((char*) (v+nl));
}
void free_vector(float *v, int nl, int nh){
free((char*) (v+nl));
}
float **matrix(int nrl,int nrh,int ncl,int nch){
float **m;
m = (float **) malloc((unsigned) (nrh-nrl+1)*sizeof(float*));
if (!m) nrerror("allocation failure 1 in matrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i]=(float *) malloc((unsigned) (nch-ncl+1)*sizeof(float));
if (!m[i]) nrerror("allocation failure 2 in matrix()");
m[i] -= ncl;
}
return m;
}
void free_matrix(float **m,int nrl,int nrh,int ncl,int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
double **dmatrix(int nrl, int nrh, int ncl, int nch){
double **m;
m = (double **) calloc((unsigned) (nrh-nrl+1), sizeof(double*));
if (!m) nrerror("allocation failure 1 in dmatrix()");
m -= nrl;
for(int i = nrl ; i <= nrh ; i++){
m[i] = (double *) calloc((unsigned) (nch-ncl+1), sizeof(double));
if (!m[i]) nrerror("allocation failure 2 in dmatrix()");
m[i] -= ncl;
}
return m;
}
void free_dmatrix(double **m, int nrl, int nrh, int ncl, int nch){
for(int i = nrh ; i >= nrl ; i--) free((char*) (m[i]+ncl));
free((char*) (m+nrl));
}
/*
double log2(double x){
return log10(x) / log10( 2.0 );
}
*/
void CreateMatrix(Matrix **M, int hei, int wid){
Matrix *tmp;
tmp = (Matrix *) calloc(1, sizeof(Matrix));
tmp->data = (double **) calloc(hei, sizeof(double *));
if (!(tmp->data)) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
for (int h = 0 ; h < hei ; h++) {
tmp->data[h] = (double *) calloc(wid, sizeof(double));
if (!(tmp->data[h])) {
nrerror("allocation failure in CreateMatrix()");
exit(1);
}
}
tmp->height = hei;
tmp->width = wid;
*M = tmp;
}
void FreeMatrix(Matrix *M){
int hei = M->height;
for(int h = 0 ; h < hei ; h++){
free(M->data[h]);
}
free(M->data);
free(M);
}
void four1(double *data, int nn, int isign){
int n, mmax, m, j, istep, i;
double wtemp, wr, wpr, wpi, wi, theta;
double tempr, tempi;
n = nn << 1;
j = 1;
for (i=1;i<n;i+=2) {
if (j > i) {
swap(data[j],data[i]);
swap(data[j+1],data[i+1]);
}
m = n >> 1;
while (m >= 2 && j > m) {
j -= m;
m >>= 1;
}
j += m;
}
mmax = 2;
while (n > mmax) {
istep = 2*mmax;
theta = 6.28318530717959/(isign*mmax);
wtemp = sin(0.5*theta);
wpr = -2.0*wtemp*wtemp;
wpi = sin(theta);
wr = 1.0;
wi = 0.0;
for (m=1;m<mmax;m+=2) {
for (i=m;i<=n;i+=istep) {
j = i+mmax;
tempr = wr*data[j]-wi*data[j+1];
tempi = wr*data[j+1]+wi*data[j];
data[j] = data[i]-tempr;
data[j+1] = data[i+1]-tempi;
data[i] += tempr;
data[i+1] += tempi;
}
wr = (wtemp=wr)*wpr-wi*wpi+wr;
wi = wi*wpr+wtemp*wpi+wi;
}
mmax = istep;
}
}
void four2(double **fftr, double **ffti, double **rdata, double **idata, int rs, int cs, int isign){
/************************************************************
2-D fourier transform of data with real part stored in
"rdata" and imaginary part in "idata" with size "rs" x
"cs". The result is in "fftr" and "ffti". The isign is
"isign" = 1 forward, and "isign" = -1 inverse
*************************************************************/
double **T, *tmp1, *tmp2;
int i, j;
tmp1 = dvector(1,2*cs);
tmp2 = dvector(1,2*rs);
T = dmatrix(1,2*rs,1,cs);
for (i=1;i<=rs;i++) {
for (j=1;j<=cs;j++) {
tmp1[j*2-1] = rdata[i][j];
tmp1[j*2] = idata[i][j];
}
four1(tmp1, cs, isign);
for (j=1;j<=cs;j++) {
T[i*2-1][j] = tmp1[j*2-1];
T[i*2][j] = tmp1[j*2];
}
}
for (i=1;i<=cs;i++) {
for (j=1;j<=rs;j++) {
tmp2[j*2-1] = T[j*2-1][i];
tmp2[j*2] = T[j*2][i];
}
four1(tmp2,rs,isign);
for (j=1;j<=rs;j++) {
fftr[j][i] = tmp2[j*2-1];
ffti[j][i] = tmp2[j*2];
}
}
free_dvector(tmp1, 1, 2*cs);
free_dvector(tmp2, 1, 2*rs);
free_dmatrix(T, 1, 2*rs, 1, cs);
}
void Mat_FFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, 1); /* 2-D FFT */
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j];
Output_imag->data[i-1][j-1] = Fi[i][j];
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_IFFT2(Matrix *Output_real, Matrix *Output_imag, Matrix *Input_real, Matrix *Input_imag){
int xs, ys, i, j;
double **R, **I, **Fr, **Fi, NN;
xs = Input_real->height;
ys = Input_real->width;
R = dmatrix(1,xs,1,ys);
I = dmatrix(1,xs,1,ys);
Fr = dmatrix(1,xs,1,ys);
Fi = dmatrix(1,xs,1,ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
R[i][j] = Input_real->data[i-1][j-1];
I[i][j] = Input_imag->data[i-1][j-1];
}
four2(Fr, Fi, R, I, xs, ys, -1); /* 2-D IFFT */
NN = (double) (xs*ys);
for (i=1;i<=Input_real->height;i++)
for (j=1;j<=Input_real->width;j++) {
Output_real->data[i-1][j-1] = Fr[i][j]/NN;
Output_imag->data[i-1][j-1] = Fi[i][j]/NN;
}
free_dmatrix(R,1,xs,1,ys);
free_dmatrix(I,1,xs,1,ys);
free_dmatrix(Fr,1,xs,1,ys);
free_dmatrix(Fi,1,xs,1,ys);
}
void Mat_Copy(Matrix *A, Matrix *B, int h_target, int w_target, int h_begin, int w_begin, int h_end, int w_end){
int i, j, h, w, h_done, w_done;
if ((h_target >= 0)&&(h_target < A->height)&&(w_target >= 0)&&(w_target < A->width)) {
if ((h_begin >= 0)&&(h_begin < B->height)&&(w_begin >= 0)&&(w_begin < B->width)) {
h = h_end-h_begin+1;
w = w_end-w_begin+1;
if ((h >= 1)&&(w >= 1)) {
h_done = h_target+h-1;
w_done = w_target+w-1;
if ((h_done < A->height)&&(w_done < A->width)) {
for (i=0;i<h;i++) {
for (j=0;j<w;j++) {
A->data[i+h_target][j+w_target] = B->data[i+h_begin][j+w_begin];
}
}
}
}
}
}
else {
printf("matrix dimension error!\n");
exit(1);
}
}
void Mat_Product(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]*C->data[h][w];
}
void Mat_Sum(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A-> height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]+C->data[h][w];
}
void Mat_Substract(Matrix *A, Matrix *B, Matrix *C){
for(int h = 0 ; h < A->height ; h++)
for(int w = 0 ; w < A->width ; w++)
A->data[h][w] = B->data[h][w]-C->data[h][w];
}
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag);
void GaborFilteredImg(Matrix *FilteredImg_real, Matrix *FilteredImg_imag, Matrix *img, int side, double Ul, double Uh, int scale, int orientation, int flag){
int h, w, xs, ys, border, r1, r2, r3, r4, hei, wid, s, n, base;
Matrix *IMG, *IMG_imag, *Gr, *Gi, *Tmp_1, *Tmp_2, *F_1, *F_2, *G_real, *G_imag, *F_real, *F_imag,*F;
double m, v;
base = scale*orientation;
double *features; //exact memory
features = (double *)malloc( 2 * scale * orientation * sizeof(double) );
border = side;
hei = img->height;
wid = img->width;
/* FFT2 */
xs = (int) pow(2.0, ceil(log2((double)(img->height+2.0*border))));
ys = (int) pow(2.0, ceil(log2((double)(img->width+2.0*border))));
CreateMatrix(&IMG, xs, ys);
r1 = img->width+border;
r2 = img->width+2*border;
for (h=0;h<border;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[border-1-h][border-1-w];
for (w=border;w<r1;w++)
IMG->data[h][w] = img->data[border-1-h][w-border];
for (w=r1;w<r2;w++)
IMG->data[h][w] = img->data[border-1-h][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->width+border;
r3 = img->width+2*border;
for (h=border;h<r1;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[h-border][border-1-w];
for (w=border;w<r2;w++)
IMG->data[h][w] = img->data[h-border][w-border];
for (w=r2;w<r3;w++)
IMG->data[h][w] = img->data[h-border][2*img->width-w+border-1];
}
r1 = img->height+border;
r2 = img->height+2*border;
r3 = img->width+border;
r4 = img->width+2*border;
for (h=r1;h<r2;h++) {
for (w=0;w<border;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][border-1-w];
for (w=border;w<r3;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][w-border];
for (w=r3;w<r4;w++)
IMG->data[h][w] = img->data[2*img->height-h+border-1][2*img->width-w+border-1];
}
CreateMatrix(&F_real, xs, ys);
CreateMatrix(&F_imag, xs, ys);
CreateMatrix(&IMG_imag, xs, ys);
Mat_FFT2(F_real, F_imag, IMG, IMG_imag);
/* ----------- compute the Gabor filtered output ------------- */
CreateMatrix(&Gr, 2*side+1, 2*side+1);
CreateMatrix(&Gi, 2*side+1, 2*side+1);
CreateMatrix(&Tmp_1, xs, ys);
CreateMatrix(&Tmp_2, xs, ys);
CreateMatrix(&F_1, xs, ys);
CreateMatrix(&F_2, xs, ys);
CreateMatrix(&G_real, xs, ys);
CreateMatrix(&G_imag, xs, ys);
CreateMatrix(&F, hei, wid);
for (s=0;s<scale;s++){
for (n=0;n<orientation;n++) {
Gabor(Gr, Gi, s+1, n+1, Ul, Uh, scale, orientation, flag);//CUDA- 2 normales y logn
Mat_Copy(F_1, Gr, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_Copy(F_2, Gi, 0, 0, 0, 0, 2*side, 2*side);//CUDA
Mat_FFT2(G_real, G_imag, F_1, F_2);//CUDA-no definido
Mat_Product(Tmp_1, G_real, F_real);//CUDA
Mat_Product(Tmp_2, G_imag, F_imag);//CUDA
Mat_Substract(IMG, Tmp_1, Tmp_2);//CUDA
Mat_Product(Tmp_1, G_real, F_imag);//CUDA
Mat_Product(Tmp_2, G_imag, F_real);//CUDA
Mat_Sum(IMG_imag, Tmp_1, Tmp_2);//CUDA
Mat_IFFT2(Tmp_1, Tmp_2, IMG, IMG_imag);//CUDA-no definido
//CUDA - logn
m = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++) {
F->data[h][w] = sqrt(pow(IMG->data[h][w], 2.0)+pow(IMG_imag->data[h][w], 2.0));
m += F->data[h][w];
}
m /= (double) (hei*wid);
features[s*orientation+n] = (float) m;
//CUDA - logn
v = 0;
for (h=0;h<hei;h++)
for (w=0;w<wid;w++)
v += (F->data[h][w]-m)*(F->data[h][w]-m);
v /= (double) (hei*wid);
features[base+s*orientation+n] = (float) sqrt(v);
Mat_Copy(FilteredImg_real, Tmp_1, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
Mat_Copy(FilteredImg_imag, Tmp_2, s*hei, n*wid, 2*side, 2*side, hei+2*side-1, wid+2*side-1);//CUDA
}
}
for(int i = 0 ; i < (2 * scale * orientation) ; i++)
printf("%.8lf ",features[i]);
printf("\n");
cout << 2 * scale * orientation << endl;
FreeMatrix(Gr);
FreeMatrix(Gi);
FreeMatrix(Tmp_1);
FreeMatrix(Tmp_2);
FreeMatrix(F_1);
FreeMatrix(F_2);
FreeMatrix(G_real);
FreeMatrix(G_imag);
FreeMatrix(F_real);
FreeMatrix(F_imag);
FreeMatrix(IMG);
FreeMatrix(IMG_imag);
}
/* ------------------------------------------------------------------------------------------------------
The Gabor function generates a Gabor filter with the selected index 's' and 'n' (scale and orientation,
respectively) from a Gabor filter bank. This filter bank is designed by giving the range of spatial
frequency (Uh and Ul) and the total number of scales and orientations used to partition the spectrum.
The returned filter is stored in 'Gr' (real part) and 'Gi' (imaginary part).
--------------------------------------------------------------------------------------------------------*/
void Gabor(Matrix *Gr, Matrix *Gi, int s, int n, double Ul, double Uh, int scale, int orientation, int flag){
double base, a, u0, z, Uvar, Vvar, Xvar, Yvar, X, Y, G, t1, t2, m;
int x, y, side;
base = Uh/Ul;
a = pow(base, 1.0/(double)(scale-1));
u0 = Uh/pow(a, (double) scale-s);
Uvar = (a-1.0)*u0/((a+1.0)*sqrt(2.0*log(2.0)));
z = -2.0*log(2.0)*(Uvar*Uvar)/u0;
Vvar = tan(pi/(2*orientation))*(u0+z)/sqrt(2.0*log(2.0)-z*z/(Uvar*Uvar));
Xvar = 1.0/(2.0*pi*Uvar);
Yvar = 1.0/(2.0*pi*Vvar);
t1 = cos(pi/orientation*(n-1.0));
t2 = sin(pi/orientation*(n-1.0));
side = (int) (Gr->height-1)/2;
//CUDA
for (x=0;x<2*side+1;x++) {
for (y=0;y<2*side+1;y++) {
X = (double) (x-side)*t1+ (double) (y-side)*t2;
Y = (double) -(x-side)*t2+ (double) (y-side)*t1;
G = 1.0/(2.0*pi*Xvar*Yvar)*pow(a, (double) scale-s)*exp(-0.5*((X*X)/(Xvar*Xvar)+(Y*Y)/(Yvar*Yvar)));
Gr->data[x][y] = G*cos(2.0*pi*u0*X);
Gi->data[x][y] = G*sin(2.0*pi*u0*X);
}
}
/* if flag = 1, then remove the DC from the filter */
if (flag == 1) {
//CUDA - logn
m = 0;
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
m += Gr->data[x][y];
m /= pow((double) 2.0*side+1, 2.0);
//CUDA
for (x=0;x<2*side+1;x++)
for (y=0;y<2*side+1;y++)
Gr->data[x][y] -= m;
}
}
int main(int argc, char **argv){
int hei, wid, side, scale, orientation, flag;//, s, n;
//Matrix *Gabor_r, *Gabor_i, *Gr, *Gi, *img, *F_r, *F_i;
Matrix *img , *F_r , *F_i;
FILE *fp;
unsigned char *tmp;
//float *output;
double Ul, Uh;
/* --------------------------- Example --------------------------------
scale = 3,
orientation = 4,
Uh (highest spatial frequency) = 0.4,
Ul (lowest spatial frequency) = 0.1,
flag (removing the DC term) = 0 (False),
side (filter dimension = (2*side+1)*(2*side+1)) = 60
----------------------------------------------------------------------- */
scale = 3;
orientation = 4;
Ul = 0.1;
Uh = 0.4;
flag = 0;
side = 60;
if (argc != 4) {
printf("usage: %s <image_name> <height> <width>\n",argv[0]);
exit(0);
}
hei = atoi(argv[2]);
wid = atoi(argv[3]);
tmp = (unsigned char *) calloc(hei*wid, sizeof(unsigned char));
if ((fp = fopen(argv[1],"r")) == NULL) {
printf("%s can not be open!\n", argv[1]);
exit(0);
}
fread(tmp, sizeof(unsigned char), hei*wid, fp);
fclose(fp);
CreateMatrix(&img, hei, wid);
for(int i = 0 ; i < hei ; i++)
for(int j = 0 ; j < wid ; j++)
img->data[i][j] = (double) (tmp[i*wid+j]);
free(tmp);
CreateMatrix(&F_r, hei*scale, wid*orientation);
CreateMatrix(&F_i, hei*scale, wid*orientation);
GaborFilteredImg(F_r, F_i, img, side, Ul, Uh, scale, orientation, flag);
FreeMatrix(F_r);
FreeMatrix(F_i);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#include<stdio.h>
__global__ void ac_velocity(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dszz_dz, float *d_mem_dsxx_dx, float *d_Lambda, \
float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b, float *d_K_z, \
float *d_a_z, float *d_b_z, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, bool isFor){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dszz_dz = 0.0;
float dsxx_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (isFor) {
if(gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// if(gidz>=2 && gidz<=nz-nPad-2) {
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dszz_dz(gidz,gidx) = d_b_z[gidz]*d_mem_dszz_dz(gidz,gidx) + d_a_z[gidz]*dszz_dz;
}
d_vz(gidz,gidx) += (dszz_dz/d_K_z[gidz] + d_mem_dszz_dz(gidz,gidx)) * d_ave_Byc_a(gidz, gidx) * dt;
// }
// if(gidx>=1 && gidx<=nx-3) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dsxx_dx(gidz,gidx) = d_b_x_half[gidx]*d_mem_dsxx_dx(gidz,gidx) + d_a_x_half[gidx]*dsxx_dx;
}
d_vx(gidz,gidx) += (dsxx_dx/d_K_x_half[gidx] + d_mem_dsxx_dx(gidz,gidx)) * d_ave_Byc_b(gidz, gidx) * dt;
// }
}
else {
return;
}
}
else {
if(gidz>=nPml+2 && gidz<=nz-nPad-3-nPml && gidx>=nPml+2 && gidx<=nx-3-nPml) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
d_vx(gidz,gidx) -= dsxx_dx * d_ave_Byc_b(gidz, gidx) * dt;
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
d_vz(gidz,gidx) -= dszz_dz * d_ave_Byc_a(gidz, gidx) * dt;
}
else {
return;
}
}
} | .file "tmpxft_001a73ec_00000000-6_ac_velocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.type _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, @function
_Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.LFB2081:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq 416(%rsp), %rax
movq %rax, 88(%rsp)
movq 424(%rsp), %rax
movq %rax, 80(%rsp)
movq 432(%rsp), %rax
movq %rax, 72(%rsp)
movq 440(%rsp), %rax
movq %rax, 64(%rsp)
movq 448(%rsp), %rax
movq %rax, 56(%rsp)
movq 456(%rsp), %rax
movq %rax, 48(%rsp)
movq 464(%rsp), %rax
movq %rax, 40(%rsp)
movq 472(%rsp), %rax
movq %rax, 32(%rsp)
movq 480(%rsp), %rax
movq %rax, 24(%rsp)
movl 520(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 20(%rsp), %rax
movq %rax, 344(%rsp)
leaq 16(%rsp), %rax
movq %rax, 352(%rsp)
leaq 12(%rsp), %rax
movq %rax, 360(%rsp)
leaq 504(%rsp), %rax
movq %rax, 368(%rsp)
leaq 512(%rsp), %rax
movq %rax, 376(%rsp)
leaq 8(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
leaq 152(%rsp), %rcx
leaq 144(%rsp), %rdx
leaq 172(%rsp), %rsi
leaq 160(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 152(%rsp)
.cfi_def_cfa_offset 424
pushq 152(%rsp)
.cfi_def_cfa_offset 432
leaq 224(%rsp), %r9
movq 188(%rsp), %rcx
movl 196(%rsp), %r8d
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
leaq _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .-_Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.globl _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.type _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, @function
_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .-_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#include<stdio.h>
__global__ void ac_velocity(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dszz_dz, float *d_mem_dsxx_dx, float *d_Lambda, \
float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b, float *d_K_z, \
float *d_a_z, float *d_b_z, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, bool isFor){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dszz_dz = 0.0;
float dsxx_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (isFor) {
if(gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// if(gidz>=2 && gidz<=nz-nPad-2) {
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dszz_dz(gidz,gidx) = d_b_z[gidz]*d_mem_dszz_dz(gidz,gidx) + d_a_z[gidz]*dszz_dz;
}
d_vz(gidz,gidx) += (dszz_dz/d_K_z[gidz] + d_mem_dszz_dz(gidz,gidx)) * d_ave_Byc_a(gidz, gidx) * dt;
// }
// if(gidx>=1 && gidx<=nx-3) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dsxx_dx(gidz,gidx) = d_b_x_half[gidx]*d_mem_dsxx_dx(gidz,gidx) + d_a_x_half[gidx]*dsxx_dx;
}
d_vx(gidz,gidx) += (dsxx_dx/d_K_x_half[gidx] + d_mem_dsxx_dx(gidz,gidx)) * d_ave_Byc_b(gidz, gidx) * dt;
// }
}
else {
return;
}
}
else {
if(gidz>=nPml+2 && gidz<=nz-nPad-3-nPml && gidx>=nPml+2 && gidx<=nx-3-nPml) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
d_vx(gidz,gidx) -= dsxx_dx * d_ave_Byc_b(gidz, gidx) * dt;
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
d_vz(gidz,gidx) -= dszz_dz * d_ave_Byc_a(gidz, gidx) * dt;
}
else {
return;
}
}
} | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void ac_velocity(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dszz_dz, float *d_mem_dsxx_dx, float *d_Lambda, \
float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b, float *d_K_z, \
float *d_a_z, float *d_b_z, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, bool isFor){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dszz_dz = 0.0;
float dsxx_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (isFor) {
if(gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// if(gidz>=2 && gidz<=nz-nPad-2) {
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dszz_dz(gidz,gidx) = d_b_z[gidz]*d_mem_dszz_dz(gidz,gidx) + d_a_z[gidz]*dszz_dz;
}
d_vz(gidz,gidx) += (dszz_dz/d_K_z[gidz] + d_mem_dszz_dz(gidz,gidx)) * d_ave_Byc_a(gidz, gidx) * dt;
// }
// if(gidx>=1 && gidx<=nx-3) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dsxx_dx(gidz,gidx) = d_b_x_half[gidx]*d_mem_dsxx_dx(gidz,gidx) + d_a_x_half[gidx]*dsxx_dx;
}
d_vx(gidz,gidx) += (dsxx_dx/d_K_x_half[gidx] + d_mem_dsxx_dx(gidz,gidx)) * d_ave_Byc_b(gidz, gidx) * dt;
// }
}
else {
return;
}
}
else {
if(gidz>=nPml+2 && gidz<=nz-nPad-3-nPml && gidx>=nPml+2 && gidx<=nx-3-nPml) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
d_vx(gidz,gidx) -= dsxx_dx * d_ave_Byc_b(gidz, gidx) * dt;
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
d_vz(gidz,gidx) -= dszz_dz * d_ave_Byc_a(gidz, gidx) * dt;
}
else {
return;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void ac_velocity(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dszz_dz, float *d_mem_dsxx_dx, float *d_Lambda, \
float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b, float *d_K_z, \
float *d_a_z, float *d_b_z, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, bool isFor){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dszz_dz = 0.0;
float dsxx_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (isFor) {
if(gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// if(gidz>=2 && gidz<=nz-nPad-2) {
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dszz_dz(gidz,gidx) = d_b_z[gidz]*d_mem_dszz_dz(gidz,gidx) + d_a_z[gidz]*dszz_dz;
}
d_vz(gidz,gidx) += (dszz_dz/d_K_z[gidz] + d_mem_dszz_dz(gidz,gidx)) * d_ave_Byc_a(gidz, gidx) * dt;
// }
// if(gidx>=1 && gidx<=nx-3) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dsxx_dx(gidz,gidx) = d_b_x_half[gidx]*d_mem_dsxx_dx(gidz,gidx) + d_a_x_half[gidx]*dsxx_dx;
}
d_vx(gidz,gidx) += (dsxx_dx/d_K_x_half[gidx] + d_mem_dsxx_dx(gidz,gidx)) * d_ave_Byc_b(gidz, gidx) * dt;
// }
}
else {
return;
}
}
else {
if(gidz>=nPml+2 && gidz<=nz-nPad-3-nPml && gidx>=nPml+2 && gidx<=nx-3-nPml) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
d_vx(gidz,gidx) -= dsxx_dx * d_ave_Byc_b(gidz, gidx) * dt;
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
d_vz(gidz,gidx) -= dszz_dz * d_ave_Byc_a(gidz, gidx) * dt;
}
else {
return;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.globl _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.p2align 8
.type _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib,@function
_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
s_clause 0x4
s_load_b32 s2, s[0:1], 0xa4
s_load_b256 s[4:11], s[0:1], 0x78
s_load_b128 s[16:19], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x10
s_load_b128 s[20:23], s[0:1], 0x38
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_and_b32 s2, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_mov_b32 s2, -1
s_cbranch_scc0 .LBB0_6
s_add_i32 s2, s9, 2
s_mov_b32 s3, exec_lo
v_cmpx_le_i32_e64 s2, v2
s_cbranch_execz .LBB0_5
s_add_i32 s11, s9, s10
v_cmp_le_i32_e64 s2, s2, v0
s_sub_i32 s11, s4, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s11, -3
v_cmp_ge_i32_e32 vcc_lo, s11, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
s_sub_i32 s2, s5, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, -3
v_cmp_ge_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mad_u64_u32 v[3:4], null, v0, s4, v[2:3]
v_add_nc_u32_e32 v1, 2, v0
v_add_nc_u32_e32 v4, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, v1, s4, v[2:3]
v_add_nc_u32_e32 v7, s4, v3
v_mad_u64_u32 v[9:10], null, v4, s4, v[2:3]
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v15, -2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v6, vcc_lo, s12, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v8, vcc_lo
v_add_co_u32 v4, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
v_add_co_u32 v8, vcc_lo, s12, v9
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v10, vcc_lo
v_add_co_u32 v13, vcc_lo, s12, v11
v_add_co_ci_u32_e32 v14, vcc_lo, s13, v12, vcc_lo
s_clause 0x3
global_load_b32 v1, v[4:5], off
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[6:7], off
global_load_b32 v10, v[13:14], off
v_add_co_u32 v4, vcc_lo, s22, v11
v_add_co_ci_u32_e32 v5, vcc_lo, s23, v12, vcc_lo
v_add_co_u32 v6, vcc_lo, s18, v11
v_add_co_ci_u32_e32 v7, vcc_lo, s19, v12, vcc_lo
global_load_b32 v17, v[4:5], off
global_load_b32 v18, v[6:7], off
s_waitcnt vmcnt(4)
v_dual_sub_f32 v1, v1, v8 :: v_dual_add_nc_u32 v8, 1, v3
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v4, v9, v10 :: v_dual_mul_f32 v1, 0x3d2aaaab, v1
v_fma_f32 v1, v4, 0x3f900000, -v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, s8, s8, v1
v_div_scale_f32 v16, vcc_lo, v1, s8, v1
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v9, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v4, v10
v_dual_mul_f32 v19, v16, v10 :: v_dual_add_nc_u32 v4, -1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v9, v19, v16
v_fmac_f32_e32 v19, v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_fma_f32 v3, -v9, v19, v16
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v10, v3, v10, v19
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_div_fixup_f32 v1, v10, s8, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v17, v1
v_add_co_u32 v15, vcc_lo, s12, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s13, v16, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3)
v_fma_f32 v1, -v1, s6, v18
v_add_co_u32 v3, vcc_lo, s12, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_store_b32 v[6:7], v1, off
s_clause 0x3
global_load_b32 v1, v[8:9], off
global_load_b32 v7, v[15:16], off
global_load_b32 v8, v[13:14], off
global_load_b32 v9, v[3:4], off
v_add_co_u32 v3, vcc_lo, s20, v11
v_add_co_ci_u32_e32 v4, vcc_lo, s21, v12, vcc_lo
v_add_co_u32 v5, vcc_lo, s16, v11
v_add_co_ci_u32_e32 v6, vcc_lo, s17, v12, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
s_waitcnt vmcnt(4)
v_sub_f32_e32 v1, v1, v7
s_waitcnt vmcnt(2)
v_sub_f32_e32 v7, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x3d2aaaab, v1
v_fma_f32 v1, v7, 0x3f900000, -v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v7, null, s7, s7, v1
v_rcp_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v7, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v1, s7, v1
v_mul_f32_e32 v10, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v7, v10, v9
v_fmac_f32_e32 v10, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v7, v10, v9
v_div_fmas_f32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v7, s7, v1
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, v3, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v1, -v1, s6, v4
global_store_b32 v[5:6], v1, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s2, 0
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_18
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 1, v2
s_cbranch_execz .LBB0_18
s_sub_i32 s2, s4, s10
s_add_i32 s3, s5, -3
s_add_i32 s2, s2, -3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e32 vcc_lo, s2, v2
v_cmp_ge_i32_e64 s2, s3, v0
v_cmp_lt_i32_e64 s3, 1, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_18
v_mad_u64_u32 v[4:5], null, v0, s4, v[2:3]
s_load_b64 s[2:3], s[0:1], 0x18
v_cmp_ge_i32_e64 s11, s9, v2
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v6, -1, v4
v_add_nc_u32_e32 v8, 1, v4
v_add_nc_u32_e32 v10, -2, v4
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s12, v6
v_add_co_ci_u32_e32 v15, vcc_lo, s13, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s13, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s12, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
v_add_co_u32 v6, vcc_lo, s12, v12
v_add_co_ci_u32_e32 v7, vcc_lo, s13, v13, vcc_lo
s_clause 0x3
global_load_b32 v1, v[8:9], off
global_load_b32 v3, v[10:11], off
global_load_b32 v8, v[14:15], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v1, v1, v3
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v9, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0xbd2aaaab, v1
v_fmamk_f32 v1, v3, 0x3f900000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, s7, s7, v1
v_div_scale_f32 v10, vcc_lo, v1, s7, v1
v_rcp_f32_e32 v8, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v3, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, v9, v8
v_mul_f32_e32 v9, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, -v3, v9, v10
v_fmac_f32_e32 v9, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v9, v10
v_div_fmas_f32 v3, v3, v8, v9
v_cmpx_lt_i32_e64 s9, v2
s_add_i32 s10, s10, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_not_b32 s10, s10
s_add_i32 s10, s10, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s10, v2
s_and_not1_b32 s10, s11, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
s_or_b32 s11, s10, s11
s_or_b32 exec_lo, exec_lo, s14
v_div_fixup_f32 v1, v3, s7, v1
s_and_saveexec_b32 s7, s11
s_cbranch_execz .LBB0_13
s_load_b128 s[24:27], s[0:1], 0x50
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[10:11], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v12, vcc_lo, s26, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s27, v9, vcc_lo
v_add_co_u32 v8, vcc_lo, s24, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s25, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
global_load_b32 v3, v[8:9], off
global_load_b32 v8, v[12:13], off
global_load_b32 v9, v[10:11], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v3, v1, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v8, v9
global_store_b32 v[10:11], v3, off
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s7
s_load_b64 s[10:11], s[0:1], 0x48
v_mov_b32_e32 v3, 0
v_mul_lo_u32 v20, s4, v0
v_add_nc_u32_e32 v21, -1, v0
v_cmp_ge_i32_e64 s7, s9, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s10, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_load_b32 v14, v[8:9], off
v_lshlrev_b64 v[8:9], 2, v[4:5]
v_add_co_u32 v10, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v12, vcc_lo, s20, v8
v_add_co_ci_u32_e32 v13, vcc_lo, s21, v9, vcc_lo
global_load_b32 v15, v[10:11], off
v_add_co_u32 v8, vcc_lo, s16, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
global_load_b32 v16, v[12:13], off
global_load_b32 v17, v[8:9], off
v_add_nc_u32_e32 v13, 2, v0
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt vmcnt(3)
v_div_scale_f32 v3, null, v14, v14, v1
v_div_scale_f32 v12, vcc_lo, v1, v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v18, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v3, v18, 1.0
v_fmac_f32_e32 v18, v10, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v19, v12, v18
v_fma_f32 v10, -v3, v19, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v19, v10, v18
v_mad_u64_u32 v[10:11], null, v13, s4, v[2:3]
v_fma_f32 v3, -v3, v19, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v11, 31, v10
v_mad_u64_u32 v[12:13], null, v21, s4, v[2:3]
v_add3_u32 v2, v20, s4, v2
v_div_fmas_f32 v18, v3, v18, v19
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_mov_b32 s4, exec_lo
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v14, v18, v14, v1
v_ashrrev_i32_e32 v13, 31, v12
v_add_co_u32 v10, vcc_lo, s12, v10
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_waitcnt vmcnt(2)
v_add_f32_e32 v3, v14, v15
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s13, v11, vcc_lo
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, v3, v16
v_add_co_u32 v12, vcc_lo, s12, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v17, s6, v3
v_add_co_u32 v1, vcc_lo, s12, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
global_store_b32 v[8:9], v17, off
s_clause 0x3
global_load_b32 v3, v[10:11], off
global_load_b32 v8, v[12:13], off
global_load_b32 v1, v[1:2], off
global_load_b32 v2, v[6:7], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v3, v3, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0xbd2aaaab, v3
v_fmamk_f32 v1, v1, 0x3f900000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, s8, s8, v1
v_div_scale_f32 v7, vcc_lo, v1, s8, v1
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v3
v_mul_f32_e32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v2, v6, v7
v_fmac_f32_e32 v6, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v6, v7
v_div_fmas_f32 v2, v2, v3, v6
v_cmpx_lt_i32_e64 s9, v0
s_not_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s5
s_and_not1_b32 s5, s7, exec_lo
v_cmp_le_i32_e32 vcc_lo, s9, v0
s_and_b32 s7, vcc_lo, exec_lo
s_or_b32 s7, s5, s7
s_or_b32 exec_lo, exec_lo, s4
v_div_fixup_f32 v2, v2, s8, v1
s_and_saveexec_b32 s4, s7
s_cbranch_execz .LBB0_17
s_load_b128 s[8:11], s[0:1], 0x68
v_mov_b32_e32 v1, 0
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[6:7], off
global_load_b32 v3, v[10:11], off
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v1, v2, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v1, v3, v6
global_store_b32 v[8:9], v1, off
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x60
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v7, v[0:1], off
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_add_co_u32 v3, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v5, vcc_lo, s22, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s23, v1, vcc_lo
global_load_b32 v3, v[3:4], off
v_add_co_u32 v0, vcc_lo, s18, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
global_load_b32 v4, v[5:6], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(3)
v_div_scale_f32 v6, null, v7, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v6, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v2, v7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v6, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v8, v10
v_div_fixup_f32 v2, v6, v7, v2
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
s_waitcnt vmcnt(1)
v_mul_f32_e32 v2, v2, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s6, v2
global_store_b32 v[0:1], v5, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 408
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .Lfunc_end0-_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .offset: 120
.size: 4
.value_kind: by_value
- .offset: 124
.size: 4
.value_kind: by_value
- .offset: 128
.size: 4
.value_kind: by_value
- .offset: 132
.size: 4
.value_kind: by_value
- .offset: 136
.size: 4
.value_kind: by_value
- .offset: 140
.size: 4
.value_kind: by_value
- .offset: 144
.size: 4
.value_kind: by_value
- .offset: 148
.size: 1
.value_kind: by_value
- .offset: 152
.size: 4
.value_kind: hidden_block_count_x
- .offset: 156
.size: 4
.value_kind: hidden_block_count_y
- .offset: 160
.size: 4
.value_kind: hidden_block_count_z
- .offset: 164
.size: 2
.value_kind: hidden_group_size_x
- .offset: 166
.size: 2
.value_kind: hidden_group_size_y
- .offset: 168
.size: 2
.value_kind: hidden_group_size_z
- .offset: 170
.size: 2
.value_kind: hidden_remainder_x
- .offset: 172
.size: 2
.value_kind: hidden_remainder_y
- .offset: 174
.size: 2
.value_kind: hidden_remainder_z
- .offset: 192
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 200
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 208
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 216
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 408
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dszz_dz(z,x) d_mem_dszz_dz[(x)*(nz)+(z)]
#define d_mem_dsxx_dx(z,x) d_mem_dsxx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define d_Den(z,x) d_Den[(x)*(nz)+(z)]
#define d_ave_Byc_a(z,x) d_ave_Byc_a[(x)*(nz)+(z)]
#define d_ave_Byc_b(z,x) d_ave_Byc_b[(x)*(nz)+(z)]
#include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void ac_velocity(float *d_vz, float *d_vx, float *d_szz, \
float *d_mem_dszz_dz, float *d_mem_dsxx_dx, float *d_Lambda, \
float *d_Den, float *d_ave_Byc_a, float *d_ave_Byc_b, float *d_K_z, \
float *d_a_z, float *d_b_z, \
float *d_K_x_half, float *d_a_x_half, float *d_b_x_half, \
int nz, int nx, float dt, float dz, float dx, int nPml, int nPad, bool isFor){
int gidz = blockIdx.x*blockDim.x + threadIdx.x;
int gidx = blockIdx.y*blockDim.y + threadIdx.y;
float dszz_dz = 0.0;
float dsxx_dx = 0.0;
float c1 = 9.0/8.0;
float c2 = 1.0/24.0;
if (isFor) {
if(gidz>=2 && gidz<=nz-nPad-3 && gidx>=2 && gidx<=nx-3) {
// if(gidz>=2 && gidz<=nz-nPad-2) {
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
if(gidz<=nPml || (gidz>=nz-nPml-nPad-1)){
d_mem_dszz_dz(gidz,gidx) = d_b_z[gidz]*d_mem_dszz_dz(gidz,gidx) + d_a_z[gidz]*dszz_dz;
}
d_vz(gidz,gidx) += (dszz_dz/d_K_z[gidz] + d_mem_dszz_dz(gidz,gidx)) * d_ave_Byc_a(gidz, gidx) * dt;
// }
// if(gidx>=1 && gidx<=nx-3) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
if(gidx<=nPml || gidx>=nx-nPml-1){
d_mem_dsxx_dx(gidz,gidx) = d_b_x_half[gidx]*d_mem_dsxx_dx(gidz,gidx) + d_a_x_half[gidx]*dsxx_dx;
}
d_vx(gidz,gidx) += (dsxx_dx/d_K_x_half[gidx] + d_mem_dsxx_dx(gidz,gidx)) * d_ave_Byc_b(gidz, gidx) * dt;
// }
}
else {
return;
}
}
else {
if(gidz>=nPml+2 && gidz<=nz-nPad-3-nPml && gidx>=nPml+2 && gidx<=nx-3-nPml) {
// update vx
dsxx_dx = (c1*(d_szz(gidz,gidx+1)-d_szz(gidz,gidx)) - c2*(d_szz(gidz,gidx+2)-d_szz(gidz,gidx-1)))/dx;
d_vx(gidz,gidx) -= dsxx_dx * d_ave_Byc_b(gidz, gidx) * dt;
// update vz
dszz_dz = (c1*(d_szz(gidz,gidx)-d_szz(gidz-1,gidx)) - c2*(d_szz(gidz+1,gidx)-d_szz(gidz-2,gidx)))/dz;
d_vz(gidz,gidx) -= dszz_dz * d_ave_Byc_a(gidz, gidx) * dt;
}
else {
return;
}
}
} | .text
.file "ac_velocity.hip"
.globl _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib # -- Begin function _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.p2align 4, 0x90
.type _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib,@function
_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib: # @_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movzbl 408(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movb %al, 3(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 12(%rsp), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rax
movq %rax, 256(%rsp)
leaq 4(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 3(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .Lfunc_end0-_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib,@object # @_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.section .rodata,"a",@progbits
.globl _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.p2align 3, 0x0
_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.quad _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.size _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a73ec_00000000-6_ac_velocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.type _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, @function
_Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.LFB2081:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rcx, 112(%rsp)
movq %r8, 104(%rsp)
movq %r9, 96(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movq 416(%rsp), %rax
movq %rax, 88(%rsp)
movq 424(%rsp), %rax
movq %rax, 80(%rsp)
movq 432(%rsp), %rax
movq %rax, 72(%rsp)
movq 440(%rsp), %rax
movq %rax, 64(%rsp)
movq 448(%rsp), %rax
movq %rax, 56(%rsp)
movq 456(%rsp), %rax
movq %rax, 48(%rsp)
movq 464(%rsp), %rax
movq %rax, 40(%rsp)
movq 472(%rsp), %rax
movq %rax, 32(%rsp)
movq 480(%rsp), %rax
movq %rax, 24(%rsp)
movl 520(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 136(%rsp), %rax
movq %rax, 208(%rsp)
leaq 128(%rsp), %rax
movq %rax, 216(%rsp)
leaq 120(%rsp), %rax
movq %rax, 224(%rsp)
leaq 112(%rsp), %rax
movq %rax, 232(%rsp)
leaq 104(%rsp), %rax
movq %rax, 240(%rsp)
leaq 96(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 80(%rsp), %rax
movq %rax, 264(%rsp)
leaq 72(%rsp), %rax
movq %rax, 272(%rsp)
leaq 64(%rsp), %rax
movq %rax, 280(%rsp)
leaq 56(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rax
movq %rax, 296(%rsp)
leaq 40(%rsp), %rax
movq %rax, 304(%rsp)
leaq 32(%rsp), %rax
movq %rax, 312(%rsp)
leaq 24(%rsp), %rax
movq %rax, 320(%rsp)
leaq 488(%rsp), %rax
movq %rax, 328(%rsp)
leaq 496(%rsp), %rax
movq %rax, 336(%rsp)
leaq 20(%rsp), %rax
movq %rax, 344(%rsp)
leaq 16(%rsp), %rax
movq %rax, 352(%rsp)
leaq 12(%rsp), %rax
movq %rax, 360(%rsp)
leaq 504(%rsp), %rax
movq %rax, 368(%rsp)
leaq 512(%rsp), %rax
movq %rax, 376(%rsp)
leaq 8(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $1, 176(%rsp)
movl $1, 180(%rsp)
leaq 152(%rsp), %rcx
leaq 144(%rsp), %rdx
leaq 172(%rsp), %rsi
leaq 160(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 152(%rsp)
.cfi_def_cfa_offset 424
pushq 152(%rsp)
.cfi_def_cfa_offset 432
leaq 224(%rsp), %r9
movq 188(%rsp), %rcx
movl 196(%rsp), %r8d
movq 176(%rsp), %rsi
movl 184(%rsp), %edx
leaq _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .-_Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.globl _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.type _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, @function
_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 120(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
pushq 120(%rsp)
.cfi_def_cfa_offset 64
pushq 120(%rsp)
.cfi_def_cfa_offset 72
pushq 120(%rsp)
.cfi_def_cfa_offset 80
pushq 120(%rsp)
.cfi_def_cfa_offset 88
pushq 120(%rsp)
.cfi_def_cfa_offset 96
pushq 120(%rsp)
.cfi_def_cfa_offset 104
pushq 120(%rsp)
.cfi_def_cfa_offset 112
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
call _Z67__device_stub__Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiibPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .-_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ac_velocity.hip"
.globl _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib # -- Begin function _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.p2align 4, 0x90
.type _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib,@function
_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib: # @_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movzbl 408(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movb %al, 3(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 304(%rsp), %rax
movq %rax, 160(%rsp)
leaq 312(%rsp), %rax
movq %rax, 168(%rsp)
leaq 320(%rsp), %rax
movq %rax, 176(%rsp)
leaq 328(%rsp), %rax
movq %rax, 184(%rsp)
leaq 336(%rsp), %rax
movq %rax, 192(%rsp)
leaq 344(%rsp), %rax
movq %rax, 200(%rsp)
leaq 352(%rsp), %rax
movq %rax, 208(%rsp)
leaq 360(%rsp), %rax
movq %rax, 216(%rsp)
leaq 368(%rsp), %rax
movq %rax, 224(%rsp)
leaq 376(%rsp), %rax
movq %rax, 232(%rsp)
leaq 384(%rsp), %rax
movq %rax, 240(%rsp)
leaq 12(%rsp), %rax
movq %rax, 248(%rsp)
leaq 8(%rsp), %rax
movq %rax, 256(%rsp)
leaq 4(%rsp), %rax
movq %rax, 264(%rsp)
leaq 392(%rsp), %rax
movq %rax, 272(%rsp)
leaq 400(%rsp), %rax
movq %rax, 280(%rsp)
leaq 3(%rsp), %rax
movq %rax, 288(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, .Lfunc_end0-_Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib,@object # @_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.section .rodata,"a",@progbits
.globl _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.p2align 3, 0x0
_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib:
.quad _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.size _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11ac_velocityPfS_S_S_S_S_S_S_S_S_S_S_S_S_S_iifffiib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} | code for sm_80
Function : _Z12saxpy_kernelfPKfS0_Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} | .file "tmpxft_00100ebe_00000000-6_saxpy_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
.type _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj, @function
_Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12saxpy_kernelfPKfS0_Pfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj, .-_Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
.globl _Z12saxpy_kernelfPKfS0_Pfj
.type _Z12saxpy_kernelfPKfS0_Pfj, @function
_Z12saxpy_kernelfPKfS0_Pfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12saxpy_kernelfPKfS0_Pfj, .-_Z12saxpy_kernelfPKfS0_Pfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12saxpy_kernelfPKfS0_Pfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12saxpy_kernelfPKfS0_Pfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12saxpy_kernelfPKfS0_Pfj
.globl _Z12saxpy_kernelfPKfS0_Pfj
.p2align 8
.type _Z12saxpy_kernelfPKfS0_Pfj,@function
_Z12saxpy_kernelfPKfS0_Pfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12saxpy_kernelfPKfS0_Pfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12saxpy_kernelfPKfS0_Pfj, .Lfunc_end0-_Z12saxpy_kernelfPKfS0_Pfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12saxpy_kernelfPKfS0_Pfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12saxpy_kernelfPKfS0_Pfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void saxpy_kernel(const float a, const float* x, const float* y, float* result, unsigned int len) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) result[idx] = a * x[idx] + y[idx];
} | .text
.file "saxpy_kernel.hip"
.globl _Z27__device_stub__saxpy_kernelfPKfS0_Pfj # -- Begin function _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.p2align 4, 0x90
.type _Z27__device_stub__saxpy_kernelfPKfS0_Pfj,@function
_Z27__device_stub__saxpy_kernelfPKfS0_Pfj: # @_Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12saxpy_kernelfPKfS0_Pfj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__saxpy_kernelfPKfS0_Pfj, .Lfunc_end0-_Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12saxpy_kernelfPKfS0_Pfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12saxpy_kernelfPKfS0_Pfj,@object # @_Z12saxpy_kernelfPKfS0_Pfj
.section .rodata,"a",@progbits
.globl _Z12saxpy_kernelfPKfS0_Pfj
.p2align 3, 0x0
_Z12saxpy_kernelfPKfS0_Pfj:
.quad _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.size _Z12saxpy_kernelfPKfS0_Pfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12saxpy_kernelfPKfS0_Pfj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12saxpy_kernelfPKfS0_Pfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12saxpy_kernelfPKfS0_Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0007 */
/*00d0*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12saxpy_kernelfPKfS0_Pfj
.globl _Z12saxpy_kernelfPKfS0_Pfj
.p2align 8
.type _Z12saxpy_kernelfPKfS0_Pfj,@function
_Z12saxpy_kernelfPKfS0_Pfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12saxpy_kernelfPKfS0_Pfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12saxpy_kernelfPKfS0_Pfj, .Lfunc_end0-_Z12saxpy_kernelfPKfS0_Pfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12saxpy_kernelfPKfS0_Pfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12saxpy_kernelfPKfS0_Pfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00100ebe_00000000-6_saxpy_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
.type _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj, @function
_Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12saxpy_kernelfPKfS0_Pfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj, .-_Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
.globl _Z12saxpy_kernelfPKfS0_Pfj
.type _Z12saxpy_kernelfPKfS0_Pfj, @function
_Z12saxpy_kernelfPKfS0_Pfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12saxpy_kernelfPKfS0_PfjfPKfS0_Pfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12saxpy_kernelfPKfS0_Pfj, .-_Z12saxpy_kernelfPKfS0_Pfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12saxpy_kernelfPKfS0_Pfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12saxpy_kernelfPKfS0_Pfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy_kernel.hip"
.globl _Z27__device_stub__saxpy_kernelfPKfS0_Pfj # -- Begin function _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.p2align 4, 0x90
.type _Z27__device_stub__saxpy_kernelfPKfS0_Pfj,@function
_Z27__device_stub__saxpy_kernelfPKfS0_Pfj: # @_Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12saxpy_kernelfPKfS0_Pfj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__saxpy_kernelfPKfS0_Pfj, .Lfunc_end0-_Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12saxpy_kernelfPKfS0_Pfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12saxpy_kernelfPKfS0_Pfj,@object # @_Z12saxpy_kernelfPKfS0_Pfj
.section .rodata,"a",@progbits
.globl _Z12saxpy_kernelfPKfS0_Pfj
.p2align 3, 0x0
_Z12saxpy_kernelfPKfS0_Pfj:
.quad _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.size _Z12saxpy_kernelfPKfS0_Pfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12saxpy_kernelfPKfS0_Pfj"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__saxpy_kernelfPKfS0_Pfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12saxpy_kernelfPKfS0_Pfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
const float * __restrict__ matA,
const float * __restrict__ matB,
float * __restrict__ matC,
int dim0,
int dim1A, int dim2A,
int dim1B, int dim2B,
int dim1C, int dim2C){
extern __shared__ float smem[];
const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
const unsigned long
len_A = dim0*dim1A*dim2A,
len_B = dim0*dim1B*dim2B,
len_C = dim0*dim1C*dim2C;
const unsigned long
len_A_signleBatch = dim1A*dim2A,
len_B_signleBatch = dim1B*dim2B,
len_C_signleBatch = dim1C*dim2C;
const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;
//smemA = smem + 0;
//smemB = smem + len_subA;
// Block index
unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
unsigned int bz = blockIdx.z; // batch index
// Thread index
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int c_pos_x, c_pos_y;
c_pos_x = bx*BLOCK_SIZE_X + tx;
c_pos_y = by*BLOCK_SIZE_Y + ty;
unsigned long gidx1,gidx2;
unsigned int _d1,_d2;
//printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);
unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)
// Load sub matrices from global memory into shared memory
unsigned long idxA, idxB;
idxA = ty* BLOCK_SIZE_X + tx;
idxB = ty* BLOCK_SIZE_X + tx;
//printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);
while(idxA < len_subA){//Block-stride loop
gidx1 = offsetA + idxA;
if(idxA < len_subA && gidx1 < len_A) {
smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
/*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
}else{
smem[idxA] = 0;
}
idxA += BLOCKSIZE_P2;
}
///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
/// But then we might get shared memory write conflict. (?)
while(idxB < len_subB ){//Block-stride loop
//gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
_d2 = idxB%BLOCK_SIZE_X;
_d1 = (idxB/BLOCK_SIZE_X);
gidx2 = offsetB + _d1*dim2B + _d2;
if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
/*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
}else{
smem[len_subA+idxB] = 0;
}
idxB += BLOCKSIZE_P2;
}
__syncthreads();
// Multiply and add each result to produce output element of current thread in the thread block.
if(c_pos_x<dim2C && c_pos_y<dim1C){
float output_element = 0.0f;
//dim2A=dim1B is common equal dimension of 2 matrices --- block-stride loop
for (int k = 0; k < dim2A; k++) {
output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
/*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
bz,c_pos_x,c_pos_y,
ty*dim2A+k,smem[ty*dim2A+k],
len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
}
///TODO: Check matC index to not to exceed the len of matC!
matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;
}
}
void batch_matmul(
const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A, dim1A , *dim2A* )
const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* , dim2B )
float * matC, //row-major device ptr (batch, hB, wB) == (dim0B, dim1A , dim2B )
int dim0A, int dim1A, int dim2A,
int dim0B, int dim1B, int dim2B){
if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}
const int BLOCK_DIM_X = 4;
const int BLOCK_DIM_Y = 4;
dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
dim3 gridsize(0,0,0);
gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
gridsize.z = (dim0A);
unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
//printf("@batched_matmul:\n");
//printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
//printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
//printf("\t SHARED: %d Bytes\n",sharedmemsize);
if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
matA,
matB,
matC,
dim0A,
dim1A, //hA
dim2A, //wA
dim1B, //hA
dim2B, //wA
dim1A,
dim2B);
CudaCheckError();
}else{
printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
}
} | .file "tmpxft_001850e3_00000000-6_mamul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, @function
_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii:
.LFB3737:
.cfi_startproc
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3737:
.size _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, .-_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
.section .text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.type _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, @function
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
.LFB4040:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4040:
.size _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .-_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3715:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERR@batched_matmul: BAD SHAPE.\n"
.align 8
.LC1:
.string "ERR@batched_matmul: BAD BATCH SIZES.\n"
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.cu"
.align 8
.LC3:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC4:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.text
.globl _Z12batch_matmulPKfS0_Pfiiiiii
.type _Z12batch_matmulPKfS0_Pfiiiiii, @function
_Z12batch_matmulPKfS0_Pfiiiiii:
.LFB3712:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl 120(%rsp), %r15d
cmpl %r15d, %r9d
jne .L19
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %r12d
movl %r8d, %ebp
movl %r9d, %ebx
cmpl %ecx, 112(%rsp)
je .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L14:
movl $4, 24(%rsp)
movl $4, 28(%rsp)
movl 128(%rsp), %eax
addl $6, %eax
movl 128(%rsp), %edx
addl $3, %edx
cmovns %edx, %eax
sarl $2, %eax
movl %eax, 36(%rsp)
leal 6(%r8), %eax
movl %r8d, %edx
addl $3, %edx
cmovns %edx, %eax
sarl $2, %eax
movl %eax, 40(%rsp)
leal (%r9,%r15), %eax
sall $2, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl %r12d, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $212, %r8d
leaq .LC2(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl 128(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
pushq %rbp
.cfi_def_cfa_offset 128
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl %ebp, %r8d
movl %r12d, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $212, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3712:
.size _Z12batch_matmulPKfS0_Pfiiiiii, .-_Z12batch_matmulPKfS0_Pfiiiiii
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3740:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3740:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( cudaError err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
cudaError err = cudaGetLastError();
if ( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = cudaDeviceSynchronize();
if( cudaSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, cudaGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
const float * __restrict__ matA,
const float * __restrict__ matB,
float * __restrict__ matC,
int dim0,
int dim1A, int dim2A,
int dim1B, int dim2B,
int dim1C, int dim2C){
extern __shared__ float smem[];
const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
const unsigned long
len_A = dim0*dim1A*dim2A,
len_B = dim0*dim1B*dim2B,
len_C = dim0*dim1C*dim2C;
const unsigned long
len_A_signleBatch = dim1A*dim2A,
len_B_signleBatch = dim1B*dim2B,
len_C_signleBatch = dim1C*dim2C;
const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;
//smemA = smem + 0;
//smemB = smem + len_subA;
// Block index
unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
unsigned int bz = blockIdx.z; // batch index
// Thread index
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int c_pos_x, c_pos_y;
c_pos_x = bx*BLOCK_SIZE_X + tx;
c_pos_y = by*BLOCK_SIZE_Y + ty;
unsigned long gidx1,gidx2;
unsigned int _d1,_d2;
//printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);
unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)
// Load sub matrices from global memory into shared memory
unsigned long idxA, idxB;
idxA = ty* BLOCK_SIZE_X + tx;
idxB = ty* BLOCK_SIZE_X + tx;
//printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);
while(idxA < len_subA){//Block-stride loop
gidx1 = offsetA + idxA;
if(idxA < len_subA && gidx1 < len_A) {
smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
/*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
}else{
smem[idxA] = 0;
}
idxA += BLOCKSIZE_P2;
}
///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
/// But then we might get shared memory write conflict. (?)
while(idxB < len_subB ){//Block-stride loop
//gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
_d2 = idxB%BLOCK_SIZE_X;
_d1 = (idxB/BLOCK_SIZE_X);
gidx2 = offsetB + _d1*dim2B + _d2;
if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
/*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
}else{
smem[len_subA+idxB] = 0;
}
idxB += BLOCKSIZE_P2;
}
__syncthreads();
// Multiply and add each result to produce output element of current thread in the thread block.
if(c_pos_x<dim2C && c_pos_y<dim1C){
float output_element = 0.0f;
//dim2A=dim1B is common equal dimension of 2 matrices --- block-stride loop
for (int k = 0; k < dim2A; k++) {
output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
/*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
bz,c_pos_x,c_pos_y,
ty*dim2A+k,smem[ty*dim2A+k],
len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
}
///TODO: Check matC index to not to exceed the len of matC!
matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;
}
}
void batch_matmul(
const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A, dim1A , *dim2A* )
const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* , dim2B )
float * matC, //row-major device ptr (batch, hB, wB) == (dim0B, dim1A , dim2B )
int dim0A, int dim1A, int dim2A,
int dim0B, int dim1B, int dim2B){
if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}
const int BLOCK_DIM_X = 4;
const int BLOCK_DIM_Y = 4;
dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
dim3 gridsize(0,0,0);
gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
gridsize.z = (dim0A);
unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
//printf("@batched_matmul:\n");
//printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
//printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
//printf("\t SHARED: %d Bytes\n",sharedmemsize);
if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
matA,
matB,
matC,
dim0A,
dim1A, //hA
dim2A, //wA
dim1B, //hA
dim2B, //wA
dim1A,
dim2B);
CudaCheckError();
}else{
printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
}
} | // System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
const float * __restrict__ matA,
const float * __restrict__ matB,
float * __restrict__ matC,
int dim0,
int dim1A, int dim2A,
int dim1B, int dim2B,
int dim1C, int dim2C){
extern __shared__ float smem[];
const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
const unsigned long
len_A = dim0*dim1A*dim2A,
len_B = dim0*dim1B*dim2B,
len_C = dim0*dim1C*dim2C;
const unsigned long
len_A_signleBatch = dim1A*dim2A,
len_B_signleBatch = dim1B*dim2B,
len_C_signleBatch = dim1C*dim2C;
const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;
//smemA = smem + 0;
//smemB = smem + len_subA;
// Block index
unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
unsigned int bz = blockIdx.z; // batch index
// Thread index
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int c_pos_x, c_pos_y;
c_pos_x = bx*BLOCK_SIZE_X + tx;
c_pos_y = by*BLOCK_SIZE_Y + ty;
unsigned long gidx1,gidx2;
unsigned int _d1,_d2;
//printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);
unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)
// Load sub matrices from global memory into shared memory
unsigned long idxA, idxB;
idxA = ty* BLOCK_SIZE_X + tx;
idxB = ty* BLOCK_SIZE_X + tx;
//printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);
while(idxA < len_subA){//Block-stride loop
gidx1 = offsetA + idxA;
if(idxA < len_subA && gidx1 < len_A) {
smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
/*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
}else{
smem[idxA] = 0;
}
idxA += BLOCKSIZE_P2;
}
///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
/// But then we might get shared memory write conflict. (?)
while(idxB < len_subB ){//Block-stride loop
//gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
_d2 = idxB%BLOCK_SIZE_X;
_d1 = (idxB/BLOCK_SIZE_X);
gidx2 = offsetB + _d1*dim2B + _d2;
if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
/*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
}else{
smem[len_subA+idxB] = 0;
}
idxB += BLOCKSIZE_P2;
}
__syncthreads();
// Multiply and add each result to produce output element of current thread in the thread block.
if(c_pos_x<dim2C && c_pos_y<dim1C){
float output_element = 0.0f;
//dim2A=dim1B is common equal dimension of 2 matrices --- block-stride loop
for (int k = 0; k < dim2A; k++) {
output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
/*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
bz,c_pos_x,c_pos_y,
ty*dim2A+k,smem[ty*dim2A+k],
len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
}
///TODO: Check matC index to not to exceed the len of matC!
matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;
}
}
void batch_matmul(
const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A, dim1A , *dim2A* )
const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* , dim2B )
float * matC, //row-major device ptr (batch, hB, wB) == (dim0B, dim1A , dim2B )
int dim0A, int dim1A, int dim2A,
int dim0B, int dim1B, int dim2B){
if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}
const int BLOCK_DIM_X = 4;
const int BLOCK_DIM_Y = 4;
dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
dim3 gridsize(0,0,0);
gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
gridsize.z = (dim0A);
unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
//printf("@batched_matmul:\n");
//printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
//printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
//printf("\t SHARED: %d Bytes\n",sharedmemsize);
if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
matA,
matB,
matC,
dim0A,
dim1A, //hA
dim2A, //wA
dim1B, //hA
dim2B, //wA
dim1A,
dim2B);
CudaCheckError();
}else{
printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
const float * __restrict__ matA,
const float * __restrict__ matB,
float * __restrict__ matC,
int dim0,
int dim1A, int dim2A,
int dim1B, int dim2B,
int dim1C, int dim2C){
extern __shared__ float smem[];
const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
const unsigned long
len_A = dim0*dim1A*dim2A,
len_B = dim0*dim1B*dim2B,
len_C = dim0*dim1C*dim2C;
const unsigned long
len_A_signleBatch = dim1A*dim2A,
len_B_signleBatch = dim1B*dim2B,
len_C_signleBatch = dim1C*dim2C;
const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;
//smemA = smem + 0;
//smemB = smem + len_subA;
// Block index
unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
unsigned int bz = blockIdx.z; // batch index
// Thread index
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int c_pos_x, c_pos_y;
c_pos_x = bx*BLOCK_SIZE_X + tx;
c_pos_y = by*BLOCK_SIZE_Y + ty;
unsigned long gidx1,gidx2;
unsigned int _d1,_d2;
//printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);
unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)
// Load sub matrices from global memory into shared memory
unsigned long idxA, idxB;
idxA = ty* BLOCK_SIZE_X + tx;
idxB = ty* BLOCK_SIZE_X + tx;
//printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);
while(idxA < len_subA){//Block-stride loop
gidx1 = offsetA + idxA;
if(idxA < len_subA && gidx1 < len_A) {
smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
/*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
}else{
smem[idxA] = 0;
}
idxA += BLOCKSIZE_P2;
}
///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
/// But then we might get shared memory write conflict. (?)
while(idxB < len_subB ){//Block-stride loop
//gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
_d2 = idxB%BLOCK_SIZE_X;
_d1 = (idxB/BLOCK_SIZE_X);
gidx2 = offsetB + _d1*dim2B + _d2;
if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
/*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
}else{
smem[len_subA+idxB] = 0;
}
idxB += BLOCKSIZE_P2;
}
__syncthreads();
// Multiply and add each result to produce output element of current thread in the thread block.
if(c_pos_x<dim2C && c_pos_y<dim1C){
float output_element = 0.0f;
//dim2A=dim1B is common equal dimension of 2 matrices --- block-stride loop
for (int k = 0; k < dim2A; k++) {
output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
/*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
bz,c_pos_x,c_pos_y,
ty*dim2A+k,smem[ty*dim2A+k],
len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
}
///TODO: Check matC index to not to exceed the len of matC!
matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;
}
}
void batch_matmul(
const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A, dim1A , *dim2A* )
const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* , dim2B )
float * matC, //row-major device ptr (batch, hB, wB) == (dim0B, dim1A , dim2B )
int dim0A, int dim1A, int dim2A,
int dim0B, int dim1B, int dim2B){
if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}
const int BLOCK_DIM_X = 4;
const int BLOCK_DIM_Y = 4;
dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
dim3 gridsize(0,0,0);
gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
gridsize.z = (dim0A);
unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
//printf("@batched_matmul:\n");
//printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
//printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
//printf("\t SHARED: %d Bytes\n",sharedmemsize);
if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
matA,
matB,
matC,
dim0A,
dim1A, //hA
dim2A, //wA
dim1B, //hA
dim2B, //wA
dim1A,
dim2B);
CudaCheckError();
}else{
printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.protected _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.globl _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.p2align 8
.type _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@function
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
s_clause 0x1
s_load_b32 s16, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x8
v_bfe_u32 v7, v0, 10, 10
v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v6, 0x3ff, v0
s_lshl_b32 s14, s14, 2
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 2, v7
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v0, v8, v6
s_waitcnt lgkmcnt(0)
s_lshl_b32 s8, s16, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x18
s_load_b64 s[18:19], s[0:1], 0x0
v_add_co_u32 v2, s2, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, null, 0, 0, s2
s_mul_i32 s12, s14, s16
v_lshlrev_b32_e32 v4, 4, v7
v_add_co_u32 v2, vcc_lo, v2, s12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_lshlrev_b32_e32 v5, 2, v6
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add3_u32 v9, v4, v5, 0
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s16, s11
s_ashr_i32 s11, s2, 31
s_mul_hi_u32 s17, s2, s15
s_mul_i32 s11, s11, s15
s_mul_i32 s20, s2, s15
s_add_i32 s21, s17, s11
s_mul_i32 s10, s2, s10
s_lshl_b64 s[20:21], s[20:21], 2
s_ashr_i32 s11, s10, 31
s_add_u32 s2, s18, s20
s_addc_u32 s17, s19, s21
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
s_mov_b32 s17, s9
s_mov_b32 s18, s9
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_co_u32 v4, vcc_lo, v4, 16
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v2, s2, v2, 64
s_waitcnt vmcnt(0)
ds_store_b32 v9, v10
v_cmp_le_u64_e32 vcc_lo, s[8:9], v[4:5]
v_add_nc_u32_e32 v9, 64, v9
v_add_co_ci_u32_e64 v3, s2, 0, v3, s2
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_5
.LBB0_3:
v_add_co_u32 v10, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v11, vcc_lo, s17, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[10:11]
v_mov_b32_e32 v10, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
global_load_b32 v10, v[2:3], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x24
s_lshl_b32 s10, s13, 2
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_lshl_b32 s12, s3, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_gt_u32_e64 s12, v0
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[0:1], 0x28
s_mov_b32 s13, 0
v_add3_u32 v3, v6, v8, s8
s_mov_b32 s11, s13
v_and_b32_e32 v2, 3, v6
s_lshl_b64 s[18:19], s[10:11], 2
v_lshrrev_b32_e32 v4, 2, v0
v_lshl_add_u32 v5, v3, 2, 0
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v8, 2, v2
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s2, s3
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_ashr_i32 s11, s8, 31
s_mul_hi_u32 s17, s8, s15
s_mul_i32 s11, s11, s15
s_mul_i32 s20, s8, s15
s_add_u32 s8, s4, s18
s_addc_u32 s18, s5, s19
s_add_i32 s21, s17, s11
v_mul_lo_u32 v2, s2, v4
s_lshl_b64 s[4:5], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_add_u32 s4, s8, s4
s_addc_u32 s5, s18, s5
v_add_co_u32 v8, s4, s4, v8
v_add_co_ci_u32_e64 v9, null, s5, 0, s4
s_lshl_b32 s4, s2, 2
s_mov_b32 s5, s13
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s8
v_add_co_u32 v0, s2, v0, 16
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, s2, 0, v1, s2
s_waitcnt vmcnt(0)
ds_store_b32 v5, v10
v_add_nc_u32_e32 v5, 64, v5
v_add_nc_u32_e32 v2, s4, v2
v_cmp_le_u64_e64 s2, s[12:13], v[0:1]
v_add_nc_u32_e32 v4, 4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s2, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_10
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v4
v_mov_b32_e32 v10, 0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s8, s2
s_cbranch_execz .LBB0_7
v_lshlrev_b64 v[10:11], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s2, v8, v10
v_add_co_ci_u32_e64 v11, s2, v9, v11, s2
global_load_b32 v10, v[10:11], off
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
s_load_b64 s[2:3], s[0:1], 0x2c
v_add_nc_u32_e32 v0, s10, v6
v_add_nc_u32_e32 v1, s14, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_u32_e32 vcc_lo, s3, v0
v_cmp_gt_u32_e64 s0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s0, vcc_lo
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
s_cmp_lt_i32 s16, 1
s_cbranch_scc1 .LBB0_14
v_mul_lo_u32 v2, v7, s16
v_lshlrev_b32_e32 v3, 2, v6
s_lshl_b32 s0, s16, 4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshl_add_u32 v4, v2, 2, 0
v_mov_b32_e32 v2, 0
v_add3_u32 v3, 0, s0, v3
.LBB0_13:
ds_load_b32 v5, v4
ds_load_b32 v6, v3
v_add_nc_u32_e32 v4, 4, v4
v_add_nc_u32_e32 v3, 16, v3
s_add_i32 s16, s16, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s16, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v5, v6
s_cbranch_scc0 .LBB0_13
s_branch .LBB0_15
.LBB0_14:
v_mov_b32_e32 v2, 0
.LBB0_15:
v_mul_lo_u32 v3, v1, s3
s_mul_i32 s0, s3, s2
v_mov_b32_e32 v4, 0
s_ashr_i32 s1, s0, 31
s_mul_hi_u32 s2, s0, s15
s_mul_i32 s1, s1, s15
s_mul_i32 s0, s0, s15
s_add_i32 s1, s2, s1
v_mov_b32_e32 v1, v4
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_u32 s0, s6, s0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_addc_u32 s1, s7, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, v3, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 52
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.Lfunc_end0:
.size _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .Lfunc_end0-_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: read_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 52
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // System includes
#include <stdio.h>
#include <assert.h>
#include <iostream>
#include <numeric>
#include <stdlib.h>
// CUDA runtime
#include <hip/hip_runtime.h>
#define CUDA_ERROR_CHECK
#define CudaSafeCall( err ) __cudaSafeCall( err, __FILE__, __LINE__ )
#define CudaCheckError() __cudaCheckError( __FILE__, __LINE__ )
inline void __cudaSafeCall( hipError_t err, const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
if ( hipSuccess != err )
{
fprintf( stderr, "cudaSafeCall() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
inline void __cudaCheckError( const char *file, const int line )
{
#ifdef CUDA_ERROR_CHECK
hipError_t err = hipGetLastError();
if ( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
// More careful checking. However, this will affect performance.
// Comment away if needed.
err = hipDeviceSynchronize();
if( hipSuccess != err )
{
fprintf( stderr, "cudaCheckError() with sync failed at %s:%i : %s\n",
file, line, hipGetErrorString( err ) );
exit( -1 );
}
#endif
return;
}
// C = AB
template <int BLOCK_SIZE_X, int BLOCK_SIZE_Y>
__global__ void kernel_batch_matmul(
const float * __restrict__ matA,
const float * __restrict__ matB,
float * __restrict__ matC,
int dim0,
int dim1A, int dim2A,
int dim1B, int dim2B,
int dim1C, int dim2C){
extern __shared__ float smem[];
const unsigned int len_subA = BLOCK_SIZE_Y * dim2A, len_subB = BLOCK_SIZE_X * dim1B; //len of sub matrices of A and B.
const unsigned long
len_A = dim0*dim1A*dim2A,
len_B = dim0*dim1B*dim2B,
len_C = dim0*dim1C*dim2C;
const unsigned long
len_A_signleBatch = dim1A*dim2A,
len_B_signleBatch = dim1B*dim2B,
len_C_signleBatch = dim1C*dim2C;
const unsigned int BLOCKSIZE_P2 = BLOCK_SIZE_X*BLOCK_SIZE_Y;
//smemA = smem + 0;
//smemB = smem + len_subA;
// Block index
unsigned int bx = blockIdx.x; // mapped to the sub-matrices of output
unsigned int by = blockIdx.y; // mapped to the sub-matrices of output
unsigned int bz = blockIdx.z; // batch index
// Thread index
unsigned int tx = threadIdx.x;
unsigned int ty = threadIdx.y;
unsigned int c_pos_x, c_pos_y;
c_pos_x = bx*BLOCK_SIZE_X + tx;
c_pos_y = by*BLOCK_SIZE_Y + ty;
unsigned long gidx1,gidx2;
unsigned int _d1,_d2;
//printf("## bx:%u, by:%u, tx:%u, ty:%u, c_pos_x:%u, c_pos_y:%u\n",bx,by,tx,ty,c_pos_x,c_pos_y);
unsigned long offsetA = (by * BLOCK_SIZE_Y) * dim2A;
unsigned long offsetB = (bx * BLOCK_SIZE_X); //first row (d1=0)
// Load sub matrices from global memory into shared memory
unsigned long idxA, idxB;
idxA = ty* BLOCK_SIZE_X + tx;
idxB = ty* BLOCK_SIZE_X + tx;
//printf("*** bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, idxB:%ld\n",bx,by,tx,ty,idxA,idxB);
while(idxA < len_subA){//Block-stride loop
gidx1 = offsetA + idxA;
if(idxA < len_subA && gidx1 < len_A) {
smem[idxA] = matA[bz * len_A_signleBatch + gidx1];
/*printf("bx:%u, by:%u, tx:%u, ty:%u ,idxA:%ld, gidx1:%ld\n",bx,by,tx,ty,idxA,gidx1);*/
}else{
smem[idxA] = 0;
}
idxA += BLOCKSIZE_P2;
}
///TODO: It might be better to store transposed subMatB in shared memory to avoid shared memory read conflict.
/// But then we might get shared memory write conflict. (?)
while(idxB < len_subB ){//Block-stride loop
//gidx2 = offsetB + (bx*BLOCK_SIZE)*dim2B + (idxB % dim2B);
_d2 = idxB%BLOCK_SIZE_X;
_d1 = (idxB/BLOCK_SIZE_X);
gidx2 = offsetB + _d1*dim2B + _d2;
if(idxB < len_subB && _d1<dim1B && _d2<dim2B){
smem[len_subA+idxB] = matB[bz * len_B_signleBatch +gidx2];
/*printf("* bx:%u, by:%u ,tx:%u, ty:%u ,idxB:%ld, _d1:%d, _d2:%d, gidx2:%ld\n",bx,by,tx,ty,idxB,_d1,_d2,gidx2);*/
}else{
smem[len_subA+idxB] = 0;
}
idxB += BLOCKSIZE_P2;
}
__syncthreads();
// Multiply and add each result to produce output element of current thread in the thread block.
if(c_pos_x<dim2C && c_pos_y<dim1C){
float output_element = 0.0f;
//dim2A=dim1B is common equal dimension of 2 matrices --- block-stride loop
for (int k = 0; k < dim2A; k++) {
output_element += smem[ty*dim2A+k] * smem[len_subA+ k*BLOCK_SIZE_X + tx];
/*printf("###bz:%d, c_pos_x:%d, c_pos_y:%d, smem[%d]=%f, smem[%d]=%f\n",
bz,c_pos_x,c_pos_y,
ty*dim2A+k,smem[ty*dim2A+k],
len_subA+ k*BLOCK_SIZE+tx,smem[len_subA+ k*BLOCK_SIZE+tx]);*/
}
///TODO: Check matC index to not to exceed the len of matC!
matC[bz * len_C_signleBatch + c_pos_y*dim2C + c_pos_x] = output_element;
}
}
void batch_matmul(
const float * matA, //row-major device ptr (batch, hA, wA) == (dim0A, dim1A , *dim2A* )
const float * matB, //row-major device ptr (batch, hB, wB) == (dim0B, *dim1B* , dim2B )
float * matC, //row-major device ptr (batch, hB, wB) == (dim0B, dim1A , dim2B )
int dim0A, int dim1A, int dim2A,
int dim0B, int dim1B, int dim2B){
if(dim2A != dim1B){printf("ERR@batched_matmul: BAD SHAPE.\n"); return;}
if(dim0B != dim0A){printf("ERR@batched_matmul: BAD BATCH SIZES.\n"); return;}
const int BLOCK_DIM_X = 4;
const int BLOCK_DIM_Y = 4;
dim3 blocksize(BLOCK_DIM_X,BLOCK_DIM_Y,1);
dim3 gridsize(0,0,0);
gridsize.x = (dim2B + BLOCK_DIM_X-1)/BLOCK_DIM_X;
gridsize.y = (dim1A + BLOCK_DIM_Y-1)/BLOCK_DIM_Y;
gridsize.z = (dim0A);
unsigned long sharedmemsize = (BLOCK_DIM_Y*dim2A + BLOCK_DIM_X* dim1B)*sizeof(float);
//printf("@batched_matmul:\n");
//printf("\tBLOCK:(%d, %d)\n",blocksize.x,blocksize.y);
//printf("\t GRID:(%d, %d, %d)\n",gridsize.x,gridsize.y,gridsize.z);
//printf("\t SHARED: %d Bytes\n",sharedmemsize);
if(BLOCK_DIM_X==4 && BLOCK_DIM_Y==4){
kernel_batch_matmul<4,4> <<<gridsize, blocksize, sharedmemsize>>>(
matA,
matB,
matC,
dim0A,
dim1A, //hA
dim2A, //wA
dim1B, //hA
dim2B, //wA
dim1A,
dim2B);
CudaCheckError();
}else{
printf("ERR@batched_matmul: UNDEFINED BLOCK_DIM.\n"); return;
}
} | .text
.file "mamul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12batch_matmulPKfS0_Pfiiiiii # -- Begin function _Z12batch_matmulPKfS0_Pfiiiiii
.p2align 4, 0x90
.type _Z12batch_matmulPKfS0_Pfiiiiii,@function
_Z12batch_matmulPKfS0_Pfiiiiii: # @_Z12batch_matmulPKfS0_Pfiiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 280(%rsp), %r15d
movl $.Lstr.1, %eax
cmpl %r15d, %r9d
jne .LBB0_9
# %bb.1:
movl $.Lstr, %eax
cmpl %ecx, 272(%rsp)
jne .LBB0_9
# %bb.2:
movl %r9d, %r14d
movl %r8d, %ebx
movq %rdi, %r13
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdx, 48(%rsp) # 8-byte Spill
movl 288(%rsp), %r12d
leal 3(%r12), %eax
leal 6(%r12), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $2, %edx
leal 3(%rbx), %eax
leal 6(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $2, %edi
shlq $32, %rdi
orq %rdx, %rdi
leal (%r15,%r14), %eax
shll $2, %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $17179869188, %rdx # imm = 0x400000004
movl %ecx, %ebp
movl %ecx, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq %r13, 120(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 112(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movl %ebp, 36(%rsp)
movl %ebx, 32(%rsp)
movl %r14d, 28(%rsp)
movl %r15d, 24(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB0_5
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_8
# %bb.10: # %_Z16__cudaCheckErrorPKci.exit
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_9: # %_Z16__cudaCheckErrorPKci.exit.sink.split
.cfi_def_cfa_offset 272
movq %rax, %rdi
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_5:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB0_6
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB0_6:
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $212, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z12batch_matmulPKfS0_Pfiiiiii, .Lfunc_end0-_Z12batch_matmulPKfS0_Pfiiiiii
.cfi_endproc
# -- End function
.section .text._Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii # -- Begin function _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@function
_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii: # @_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .Lfunc_end1-_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@object # @_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.section .rodata._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"aG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.p2align 3, 0x0
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
.quad _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.size _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.hip"
.size .L.str.2, 107
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.4, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERR@batched_matmul: BAD BATCH SIZES."
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "ERR@batched_matmul: BAD SHAPE."
.size .Lstr.1, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001850e3_00000000-6_mamul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, @function
_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii:
.LFB3737:
.cfi_startproc
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3737:
.size _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii, .-_ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
.section .text._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.type _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, @function
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
.LFB4040:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4040:
.size _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .-_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3715:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3715:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "ERR@batched_matmul: BAD SHAPE.\n"
.align 8
.LC1:
.string "ERR@batched_matmul: BAD BATCH SIZES.\n"
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.cu"
.align 8
.LC3:
.string "cudaCheckError() failed at %s:%i : %s\n"
.align 8
.LC4:
.string "cudaCheckError() with sync failed at %s:%i : %s\n"
.text
.globl _Z12batch_matmulPKfS0_Pfiiiiii
.type _Z12batch_matmulPKfS0_Pfiiiiii, @function
_Z12batch_matmulPKfS0_Pfiiiiii:
.LFB3712:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl 120(%rsp), %r15d
cmpl %r15d, %r9d
jne .L19
movq %rsi, %r13
movq %rdx, %r14
movl %ecx, %r12d
movl %r8d, %ebp
movl %r9d, %ebx
cmpl %ecx, 112(%rsp)
je .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L14:
movl $4, 24(%rsp)
movl $4, 28(%rsp)
movl 128(%rsp), %eax
addl $6, %eax
movl 128(%rsp), %edx
addl $3, %edx
cmovns %edx, %eax
sarl $2, %eax
movl %eax, 36(%rsp)
leal 6(%r8), %eax
movl %r8d, %edx
addl $3, %edx
cmovns %edx, %eax
sarl $2, %eax
movl %eax, 40(%rsp)
leal (%r9,%r15), %eax
sall $2, %eax
cltq
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl %r12d, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L15:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L21
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L11
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $212, %r8d
leaq .LC2(%rip), %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L20:
movl 128(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 120
pushq %rbp
.cfi_def_cfa_offset 128
movl 144(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 136
pushq %r15
.cfi_def_cfa_offset 144
movl %ebx, %r9d
movl %ebp, %r8d
movl %r12d, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq 40(%rsp), %rdi
call _ZL63__device_stub__Z19kernel_batch_matmulILi4ELi4EEvPKfS1_PfiiiiiiiPKfS0_Pfiiiiiii
addq $32, %rsp
.cfi_def_cfa_offset 112
jmp .L15
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $212, %r8d
leaq .LC2(%rip), %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3712:
.size _Z12batch_matmulPKfS0_Pfiiiiii, .-_Z12batch_matmulPKfS0_Pfiiiiii
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3740:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3740:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mamul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12batch_matmulPKfS0_Pfiiiiii # -- Begin function _Z12batch_matmulPKfS0_Pfiiiiii
.p2align 4, 0x90
.type _Z12batch_matmulPKfS0_Pfiiiiii,@function
_Z12batch_matmulPKfS0_Pfiiiiii: # @_Z12batch_matmulPKfS0_Pfiiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 280(%rsp), %r15d
movl $.Lstr.1, %eax
cmpl %r15d, %r9d
jne .LBB0_9
# %bb.1:
movl $.Lstr, %eax
cmpl %ecx, 272(%rsp)
jne .LBB0_9
# %bb.2:
movl %r9d, %r14d
movl %r8d, %ebx
movq %rdi, %r13
movq %rsi, 40(%rsp) # 8-byte Spill
movq %rdx, 48(%rsp) # 8-byte Spill
movl 288(%rsp), %r12d
leal 3(%r12), %eax
leal 6(%r12), %edx
testl %eax, %eax
cmovnsl %eax, %edx
sarl $2, %edx
leal 3(%rbx), %eax
leal 6(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $2, %edi
shlq $32, %rdi
orq %rdx, %rdi
leal (%r15,%r14), %eax
shll $2, %eax
movslq %eax, %r8
shlq $2, %r8
movabsq $17179869188, %rdx # imm = 0x400000004
movl %ecx, %ebp
movl %ecx, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq %r13, 120(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 112(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movl %ebp, 36(%rsp)
movl %ebx, 32(%rsp)
movl %r14d, 28(%rsp)
movl %r15d, 24(%rsp)
movl %r12d, 20(%rsp)
movl %ebx, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
callq hipGetLastError
testl %eax, %eax
jne .LBB0_5
# %bb.7:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_8
# %bb.10: # %_Z16__cudaCheckErrorPKci.exit
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_9: # %_Z16__cudaCheckErrorPKci.exit.sink.split
.cfi_def_cfa_offset 272
movq %rax, %rdi
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB0_5:
.cfi_def_cfa_offset 272
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB0_6
.LBB0_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
.LBB0_6:
movl $.L.str.2, %edx
movq %rbx, %rdi
movl $212, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z12batch_matmulPKfS0_Pfiiiiii, .Lfunc_end0-_Z12batch_matmulPKfS0_Pfiiiiii
.cfi_endproc
# -- End function
.section .text._Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"axG",@progbits,_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii # -- Begin function _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@function
_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii: # @_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end1:
.size _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, .Lfunc_end1-_Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,@object # @_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.section .rodata._Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,"aG",@progbits,_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii,comdat
.weak _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.p2align 3, 0x0
_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii:
.quad _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.size _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/salehjg/DGCNN-GPGPU/master/kernels/cuda/mamul.hip"
.size .L.str.2, 107
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cudaCheckError() failed at %s:%i : %s\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "cudaCheckError() with sync failed at %s:%i : %s\n"
.size .L.str.4, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii"
.size .L__unnamed_1, 50
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERR@batched_matmul: BAD BATCH SIZES."
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "ERR@batched_matmul: BAD SHAPE."
.size .Lstr.1, 31
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19kernel_batch_matmulILi4ELi4EEvPKfS1_Pfiiiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* \file TestExceptions.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for unstructured control
flow mimicking exceptions.
*/
#include <cstdlib>
const unsigned int threads = 512;
const unsigned int iterations = 100;
__device__ unsigned int output[threads];
__device__ unsigned int input[threads];
extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
if(threadIdx.x == id)
{
goto Function_1_Begin;
}
else
{
goto Function_2_Begin;
}
Function_1_Begin:
if(input[threadIdx.x] != id) goto Catch_Label;
result = input[threadIdx.x];
goto Function_Return;
Function_2_Begin:
if(input[threadIdx.x] == id) goto Catch_Label;
result = threadIdx.x;
goto Function_Return;
Function_Return:
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_loop(int iterations)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
for(unsigned int i = 0; i < threadIdx.x; ++i)
{
if(input[i] > blockDim.x) goto Catch_Label;
result += input[i];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_conditional()
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
if(input[threadIdx.x] > 0)
{
if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
result = input[threadIdx.x];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) + threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
int main(int argc, char** argv)
{
unsigned int* in;
srand(0);
cudaGetSymbolAddress((void**)&in, "input");
unsigned int refIn[threads];
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = i;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_divergent_call<<<1, threads>>>(0);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() % threads;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_loop<<<1, threads>>>(iterations);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() & 1;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_conditional<<<1, threads>>>();
} | .file "tmpxft_0009bfbf_00000000-6_TestExceptions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z27exception_in_divergent_calljj
.type _Z46__device_stub__Z27exception_in_divergent_calljj, @function
_Z46__device_stub__Z27exception_in_divergent_calljj:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq exception_in_divergent_call(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z27exception_in_divergent_calljj, .-_Z46__device_stub__Z27exception_in_divergent_calljj
.globl exception_in_divergent_call
.type exception_in_divergent_call, @function
exception_in_divergent_call:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z27exception_in_divergent_calljj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size exception_in_divergent_call, .-exception_in_divergent_call
.globl _Z36__device_stub__Z17exception_in_loopii
.type _Z36__device_stub__Z17exception_in_loopii, @function
_Z36__device_stub__Z17exception_in_loopii:
.LFB2054:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq exception_in_loop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z17exception_in_loopii, .-_Z36__device_stub__Z17exception_in_loopii
.globl exception_in_loop
.type exception_in_loop, @function
exception_in_loop:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17exception_in_loopii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size exception_in_loop, .-exception_in_loop
.globl _Z43__device_stub__Z24exception_in_conditionalvv
.type _Z43__device_stub__Z24exception_in_conditionalvv, @function
_Z43__device_stub__Z24exception_in_conditionalvv:
.LFB2056:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq exception_in_conditional(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z43__device_stub__Z24exception_in_conditionalvv, .-_Z43__device_stub__Z24exception_in_conditionalvv
.globl exception_in_conditional
.type exception_in_conditional, @function
exception_in_conditional:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24exception_in_conditionalvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size exception_in_conditional, .-exception_in_conditional
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "input"
.text
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $2096, %rsp
.cfi_def_cfa_offset 2128
movq %fs:40, %rax
movq %rax, 2088(%rsp)
xorl %eax, %eax
movl $0, %edi
call srand@PLT
movq %rsp, %rdi
leaq .LC0(%rip), %rsi
call cudaGetSymbolAddress@PLT
movl $0, %eax
.L28:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L28
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L29:
leaq 32(%rsp), %rbx
leaq 2080(%rsp), %r12
movq %rbx, %rbp
.L30:
call rand@PLT
andl $511, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L30
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
call rand@PLT
andl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L32
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L33:
movq 2088(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $2096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $0, %edi
call _Z46__device_stub__Z27exception_in_divergent_calljj
jmp .L29
.L40:
movl $100, %edi
call _Z36__device_stub__Z17exception_in_loopii
jmp .L32
.L41:
call _Z43__device_stub__Z24exception_in_conditionalvv
jmp .L33
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "exception_in_conditional"
.LC2:
.string "exception_in_loop"
.LC3:
.string "exception_in_divergent_call"
.LC4:
.string "output"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_conditional(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_loop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_divergent_call(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2048, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6output(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2048, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5input(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5input
.comm _ZL5input,2048,32
.local _ZL6output
.comm _ZL6output,2048,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* \file TestExceptions.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for unstructured control
flow mimicking exceptions.
*/
#include <cstdlib>
const unsigned int threads = 512;
const unsigned int iterations = 100;
__device__ unsigned int output[threads];
__device__ unsigned int input[threads];
extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
if(threadIdx.x == id)
{
goto Function_1_Begin;
}
else
{
goto Function_2_Begin;
}
Function_1_Begin:
if(input[threadIdx.x] != id) goto Catch_Label;
result = input[threadIdx.x];
goto Function_Return;
Function_2_Begin:
if(input[threadIdx.x] == id) goto Catch_Label;
result = threadIdx.x;
goto Function_Return;
Function_Return:
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_loop(int iterations)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
for(unsigned int i = 0; i < threadIdx.x; ++i)
{
if(input[i] > blockDim.x) goto Catch_Label;
result += input[i];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_conditional()
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
if(input[threadIdx.x] > 0)
{
if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
result = input[threadIdx.x];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) + threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
int main(int argc, char** argv)
{
unsigned int* in;
srand(0);
cudaGetSymbolAddress((void**)&in, "input");
unsigned int refIn[threads];
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = i;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_divergent_call<<<1, threads>>>(0);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() % threads;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_loop<<<1, threads>>>(iterations);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() & 1;
}
cudaMemcpy(in, refIn, threads * sizeof(unsigned int),
cudaMemcpyHostToDevice);
exception_in_conditional<<<1, threads>>>();
} | /* \file TestExceptions.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for unstructured control
flow mimicking exceptions.
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
const unsigned int threads = 512;
const unsigned int iterations = 100;
__device__ unsigned int output[threads];
__device__ unsigned int input[threads];
extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
if(threadIdx.x == id)
{
goto Function_1_Begin;
}
else
{
goto Function_2_Begin;
}
Function_1_Begin:
if(input[threadIdx.x] != id) goto Catch_Label;
result = input[threadIdx.x];
goto Function_Return;
Function_2_Begin:
if(input[threadIdx.x] == id) goto Catch_Label;
result = threadIdx.x;
goto Function_Return;
Function_Return:
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_loop(int iterations)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
for(unsigned int i = 0; i < threadIdx.x; ++i)
{
if(input[i] > blockDim.x) goto Catch_Label;
result += input[i];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_conditional()
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
if(input[threadIdx.x] > 0)
{
if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
result = input[threadIdx.x];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) + threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
int main(int argc, char** argv)
{
unsigned int* in;
srand(0);
hipGetSymbolAddress((void**)&in, HIP_SYMBOL("input"));
unsigned int refIn[threads];
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = i;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_divergent_call<<<1, threads>>>(0);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() % threads;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_loop<<<1, threads>>>(iterations);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() & 1;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_conditional<<<1, threads>>>();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* \file TestExceptions.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for unstructured control
flow mimicking exceptions.
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
const unsigned int threads = 512;
const unsigned int iterations = 100;
__device__ unsigned int output[threads];
__device__ unsigned int input[threads];
extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
if(threadIdx.x == id)
{
goto Function_1_Begin;
}
else
{
goto Function_2_Begin;
}
Function_1_Begin:
if(input[threadIdx.x] != id) goto Catch_Label;
result = input[threadIdx.x];
goto Function_Return;
Function_2_Begin:
if(input[threadIdx.x] == id) goto Catch_Label;
result = threadIdx.x;
goto Function_Return;
Function_Return:
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_loop(int iterations)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
for(unsigned int i = 0; i < threadIdx.x; ++i)
{
if(input[i] > blockDim.x) goto Catch_Label;
result += input[i];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_conditional()
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
if(input[threadIdx.x] > 0)
{
if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
result = input[threadIdx.x];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) + threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
int main(int argc, char** argv)
{
unsigned int* in;
srand(0);
hipGetSymbolAddress((void**)&in, HIP_SYMBOL("input"));
unsigned int refIn[threads];
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = i;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_divergent_call<<<1, threads>>>(0);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() % threads;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_loop<<<1, threads>>>(iterations);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() & 1;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_conditional<<<1, threads>>>();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected exception_in_divergent_call
.globl exception_in_divergent_call
.p2align 8
.type exception_in_divergent_call,@function
exception_in_divergent_call:
v_lshlrev_b32_e32 v1, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, input@rel32@lo+4
s_addc_u32 s3, s3, input@rel32@hi+12
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v1, v1, s[2:3]
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e64 s1, s0, v0
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, s0, v1
v_cmp_ne_u32_e64 s0, s0, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s1
s_xor_b32 s1, exec_lo, s4
v_mov_b32_e32 v1, v0
s_mov_b32 s3, -1
s_and_b32 s2, s0, exec_lo
s_or_saveexec_b32 s0, s1
v_mov_b32_e32 v2, s3
s_xor_b32 exec_lo, exec_lo, s0
v_mov_b32_e32 v2, -1
s_and_not1_b32 s1, s2, exec_lo
s_and_b32 s2, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s1, s2
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_8
s_movk_i32 s1, 0x64
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshrrev_b32_e32 v1, 1, v1
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v0
s_cbranch_scc1 .LBB0_6
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v0, 2, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, output@rel32@lo+4
s_addc_u32 s1, s1, output@rel32@hi+12
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel exception_in_divergent_call
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 4
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size exception_in_divergent_call, .Lfunc_end0-exception_in_divergent_call
.section .AMDGPU.csdata,"",@progbits
.text
.protected exception_in_loop
.globl exception_in_loop
.p2align 8
.type exception_in_loop,@function
exception_in_loop:
v_mov_b32_e32 v3, 4
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB1_7
s_load_b32 s6, s[0:1], 0x14
v_mov_b32_e32 v2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, input@rel32@lo+4
s_addc_u32 s3, s3, input@rel32@hi+12
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_branch .LBB1_4
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v2, -1, v2
s_add_i32 s7, s9, s7
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_and_not1_b32 s8, s8, exec_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_mov_b32 s9, 4
s_and_b32 s10, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s8, s8, s10
.LBB1_3:
v_mov_b32_e32 v3, s9
v_mov_b32_e32 v1, s7
s_and_b32 s10, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s5, s10, s5
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_6
.LBB1_4:
s_load_b32 s9, s[2:3], 0x0
s_or_b32 s8, s8, exec_lo
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s9, s6
s_cbranch_scc0 .LBB1_2
s_mov_b32 s9, 7
s_branch .LBB1_3
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
.LBB1_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v2, -1
s_mov_b32 s3, -1
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 7, v3
s_cbranch_execz .LBB1_13
v_mov_b32_e32 v2, -1
s_mov_b32 s4, 0
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 4, v3
s_cbranch_execz .LBB1_12
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s0, 0
s_cbranch_scc1 .LBB1_11
.LBB1_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshrrev_b32_e32 v1, 1, v1
s_add_i32 s0, s0, -1
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v0
s_cbranch_scc1 .LBB1_10
.LBB1_11:
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
s_mov_b32 s4, exec_lo
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s3, s4, exec_lo
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB1_15
v_lshlrev_b32_e32 v0, 2, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, output@rel32@lo+4
s_addc_u32 s1, s1, output@rel32@hi+12
global_store_b32 v0, v2, s[0:1]
.LBB1_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel exception_in_loop
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 11
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size exception_in_loop, .Lfunc_end1-exception_in_loop
.section .AMDGPU.csdata,"",@progbits
.text
.protected exception_in_conditional
.globl exception_in_conditional
.p2align 8
.type exception_in_conditional,@function
exception_in_conditional:
v_lshlrev_b32_e32 v1, 2, v0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, input@rel32@lo+4
s_addc_u32 s3, s3, input@rel32@hi+12
global_load_b32 v2, v1, s[2:3]
v_mov_b32_e32 v1, 0
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s2, 0, v2
v_cmpx_ne_u32_e32 0, v2
s_cbranch_execz .LBB2_2
s_load_b32 s0, s[0:1], 0xc
v_mov_b32_e32 v1, v2
s_mov_b32 s4, -1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ge_u32_e32 vcc_lo, s0, v2
s_and_not1_b32 s0, s2, exec_lo
s_and_b32 s1, vcc_lo, exec_lo
s_or_b32 s2, s0, s1
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v2, s4
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB2_6
s_movk_i32 s1, 0x64
.LBB2_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_lshrrev_b32_e32 v1, 1, v1
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v0
s_cbranch_scc1 .LBB2_4
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v1
.LBB2_6:
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v0, 2, v0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, output@rel32@lo+4
s_addc_u32 s1, s1, output@rel32@hi+12
global_store_b32 v0, v2, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel exception_in_conditional
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size exception_in_conditional, .Lfunc_end2-exception_in_conditional
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected output
.type output,@object
.section .bss,"aw",@nobits
.globl output
.p2align 4, 0x0
output:
.zero 2048
.size output, 2048
.protected input
.type input,@object
.globl input
.p2align 4, 0x0
input:
.zero 2048
.size input, 2048
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym output
.addrsig_sym input
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 4
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: exception_in_divergent_call
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: exception_in_divergent_call.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: exception_in_loop
.private_segment_fixed_size: 0
.sgpr_count: 13
.sgpr_spill_count: 0
.symbol: exception_in_loop.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: exception_in_conditional
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: exception_in_conditional.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* \file TestExceptions.cu
\author Gregory Diamos <gregory.diamos@gatech.edu>
\date Tuesday November 9, 2010
\brief A CUDA assembly test for unstructured control
flow mimicking exceptions.
*/
#include <hip/hip_runtime.h>
#include <cstdlib>
const unsigned int threads = 512;
const unsigned int iterations = 100;
__device__ unsigned int output[threads];
__device__ unsigned int input[threads];
extern "C" __global__ void exception_in_divergent_call(unsigned int id)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
if(threadIdx.x == id)
{
goto Function_1_Begin;
}
else
{
goto Function_2_Begin;
}
Function_1_Begin:
if(input[threadIdx.x] != id) goto Catch_Label;
result = input[threadIdx.x];
goto Function_Return;
Function_2_Begin:
if(input[threadIdx.x] == id) goto Catch_Label;
result = threadIdx.x;
goto Function_Return;
Function_Return:
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_loop(int iterations)
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
for(unsigned int i = 0; i < threadIdx.x; ++i)
{
if(input[i] > blockDim.x) goto Catch_Label;
result += input[i];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) ^ threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
extern "C" __global__ void exception_in_conditional()
{
goto Try_Label;
Try_Label:
unsigned int result = 0;
goto Function_Begin;
Function_Begin:
if(input[threadIdx.x] > 0)
{
if(input[threadIdx.x] > blockDim.x) goto Catch_Label;
result = input[threadIdx.x];
}
for(unsigned int i = 0; i < iterations; ++i)
{
result = (result >> 1) + threadIdx.x;
}
goto Function_Return;
Function_Return:
output[threadIdx.x] = result;
return;
Catch_Label:
output[threadIdx.x] = (unsigned int)-1; // error occurred
return;
}
int main(int argc, char** argv)
{
unsigned int* in;
srand(0);
hipGetSymbolAddress((void**)&in, HIP_SYMBOL("input"));
unsigned int refIn[threads];
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = i;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_divergent_call<<<1, threads>>>(0);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() % threads;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_loop<<<1, threads>>>(iterations);
for(unsigned int i = 0; i < threads; i++)
{
refIn[i] = std::rand() & 1;
}
hipMemcpy(in, refIn, threads * sizeof(unsigned int),
hipMemcpyHostToDevice);
exception_in_conditional<<<1, threads>>>();
} | .text
.file "TestExceptions.hip"
.globl __device_stub__exception_in_divergent_call # -- Begin function __device_stub__exception_in_divergent_call
.p2align 4, 0x90
.type __device_stub__exception_in_divergent_call,@function
__device_stub__exception_in_divergent_call: # @__device_stub__exception_in_divergent_call
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $exception_in_divergent_call, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__exception_in_divergent_call, .Lfunc_end0-__device_stub__exception_in_divergent_call
.cfi_endproc
# -- End function
.globl __device_stub__exception_in_loop # -- Begin function __device_stub__exception_in_loop
.p2align 4, 0x90
.type __device_stub__exception_in_loop,@function
__device_stub__exception_in_loop: # @__device_stub__exception_in_loop
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $exception_in_loop, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__exception_in_loop, .Lfunc_end1-__device_stub__exception_in_loop
.cfi_endproc
# -- End function
.globl __device_stub__exception_in_conditional # -- Begin function __device_stub__exception_in_conditional
.p2align 4, 0x90
.type __device_stub__exception_in_conditional,@function
__device_stub__exception_in_conditional: # @__device_stub__exception_in_conditional
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $exception_in_conditional, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size __device_stub__exception_in_conditional, .Lfunc_end2-__device_stub__exception_in_conditional
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
leaq 72(%rsp), %rdi
movl $.L.str, %esi
callq hipGetSymbolAddress
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
incq %rbx
cmpq $512, %rbx # imm = 0x200
jne .LBB3_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
leaq 511(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.11:
movl $0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_divergent_call, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3: # %.preheader64
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
callq rand
andl $511, %eax # imm = 0x1FF
movl %eax, 80(%rsp,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB3_4
# %bb.5:
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.12:
movl $100, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_loop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # %.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
callq rand
andl $1, %eax
movl %eax, 80(%rsp,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB3_7
# %bb.8:
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_conditional, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_divergent_call, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_loop, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_conditional, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $output, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $2048, %r9d # imm = 0x800
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $input, %esi
movl $.L.str, %edx
movl $.L.str, %ecx
movl $2048, %r9d # imm = 0x800
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type output,@object # @output
.local output
.comm output,2048,16
.type input,@object # @input
.local input
.comm input,2048,16
.type exception_in_divergent_call,@object # @exception_in_divergent_call
.section .rodata,"a",@progbits
.globl exception_in_divergent_call
.p2align 3, 0x0
exception_in_divergent_call:
.quad __device_stub__exception_in_divergent_call
.size exception_in_divergent_call, 8
.type exception_in_loop,@object # @exception_in_loop
.globl exception_in_loop
.p2align 3, 0x0
exception_in_loop:
.quad __device_stub__exception_in_loop
.size exception_in_loop, 8
.type exception_in_conditional,@object # @exception_in_conditional
.globl exception_in_conditional
.p2align 3, 0x0
exception_in_conditional:
.quad __device_stub__exception_in_conditional
.size exception_in_conditional, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "input"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "exception_in_divergent_call"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "exception_in_loop"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "exception_in_conditional"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "output"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__exception_in_divergent_call
.addrsig_sym __device_stub__exception_in_loop
.addrsig_sym __device_stub__exception_in_conditional
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym output
.addrsig_sym input
.addrsig_sym exception_in_divergent_call
.addrsig_sym exception_in_loop
.addrsig_sym exception_in_conditional
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009bfbf_00000000-6_TestExceptions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z27exception_in_divergent_calljj
.type _Z46__device_stub__Z27exception_in_divergent_calljj, @function
_Z46__device_stub__Z27exception_in_divergent_calljj:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq exception_in_divergent_call(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z46__device_stub__Z27exception_in_divergent_calljj, .-_Z46__device_stub__Z27exception_in_divergent_calljj
.globl exception_in_divergent_call
.type exception_in_divergent_call, @function
exception_in_divergent_call:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z27exception_in_divergent_calljj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size exception_in_divergent_call, .-exception_in_divergent_call
.globl _Z36__device_stub__Z17exception_in_loopii
.type _Z36__device_stub__Z17exception_in_loopii, @function
_Z36__device_stub__Z17exception_in_loopii:
.LFB2054:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq exception_in_loop(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z17exception_in_loopii, .-_Z36__device_stub__Z17exception_in_loopii
.globl exception_in_loop
.type exception_in_loop, @function
exception_in_loop:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17exception_in_loopii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size exception_in_loop, .-exception_in_loop
.globl _Z43__device_stub__Z24exception_in_conditionalvv
.type _Z43__device_stub__Z24exception_in_conditionalvv, @function
_Z43__device_stub__Z24exception_in_conditionalvv:
.LFB2056:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq exception_in_conditional(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z43__device_stub__Z24exception_in_conditionalvv, .-_Z43__device_stub__Z24exception_in_conditionalvv
.globl exception_in_conditional
.type exception_in_conditional, @function
exception_in_conditional:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z24exception_in_conditionalvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size exception_in_conditional, .-exception_in_conditional
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "input"
.text
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $2096, %rsp
.cfi_def_cfa_offset 2128
movq %fs:40, %rax
movq %rax, 2088(%rsp)
xorl %eax, %eax
movl $0, %edi
call srand@PLT
movq %rsp, %rdi
leaq .LC0(%rip), %rsi
call cudaGetSymbolAddress@PLT
movl $0, %eax
.L28:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L28
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L29:
leaq 32(%rsp), %rbx
leaq 2080(%rsp), %r12
movq %rbx, %rbp
.L30:
call rand@PLT
andl $511, %eax
movl %eax, 0(%rbp)
addq $4, %rbp
cmpq %r12, %rbp
jne .L30
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L32:
call rand@PLT
andl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L32
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $2048, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L33:
movq 2088(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $2096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $0, %edi
call _Z46__device_stub__Z27exception_in_divergent_calljj
jmp .L29
.L40:
movl $100, %edi
call _Z36__device_stub__Z17exception_in_loopii
jmp .L32
.L41:
call _Z43__device_stub__Z24exception_in_conditionalvv
jmp .L33
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "exception_in_conditional"
.LC2:
.string "exception_in_loop"
.LC3:
.string "exception_in_divergent_call"
.LC4:
.string "output"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_conditional(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_loop(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq exception_in_divergent_call(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2048, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6output(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2048, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL5input(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL5input
.comm _ZL5input,2048,32
.local _ZL6output
.comm _ZL6output,2048,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TestExceptions.hip"
.globl __device_stub__exception_in_divergent_call # -- Begin function __device_stub__exception_in_divergent_call
.p2align 4, 0x90
.type __device_stub__exception_in_divergent_call,@function
__device_stub__exception_in_divergent_call: # @__device_stub__exception_in_divergent_call
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $exception_in_divergent_call, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size __device_stub__exception_in_divergent_call, .Lfunc_end0-__device_stub__exception_in_divergent_call
.cfi_endproc
# -- End function
.globl __device_stub__exception_in_loop # -- Begin function __device_stub__exception_in_loop
.p2align 4, 0x90
.type __device_stub__exception_in_loop,@function
__device_stub__exception_in_loop: # @__device_stub__exception_in_loop
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $exception_in_loop, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size __device_stub__exception_in_loop, .Lfunc_end1-__device_stub__exception_in_loop
.cfi_endproc
# -- End function
.globl __device_stub__exception_in_conditional # -- Begin function __device_stub__exception_in_conditional
.p2align 4, 0x90
.type __device_stub__exception_in_conditional,@function
__device_stub__exception_in_conditional: # @__device_stub__exception_in_conditional
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $exception_in_conditional, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end2:
.size __device_stub__exception_in_conditional, .Lfunc_end2-__device_stub__exception_in_conditional
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq srand
leaq 72(%rsp), %rdi
movl $.L.str, %esi
callq hipGetSymbolAddress
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 80(%rsp,%rbx,4)
incq %rbx
cmpq $512, %rbx # imm = 0x200
jne .LBB3_1
# %bb.2:
movabsq $4294967297, %rbx # imm = 0x100000001
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
leaq 511(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_3
# %bb.11:
movl $0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_divergent_call, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_3: # %.preheader64
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # =>This Inner Loop Header: Depth=1
callq rand
andl $511, %eax # imm = 0x1FF
movl %eax, 80(%rsp,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB3_4
# %bb.5:
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.12:
movl $100, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_loop, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6: # %.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
callq rand
andl $1, %eax
movl %eax, 80(%rsp,%r15,4)
incq %r15
cmpq $512, %r15 # imm = 0x200
jne .LBB3_7
# %bb.8:
movq 72(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $exception_in_conditional, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_divergent_call, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_loop, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $exception_in_conditional, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $output, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $2048, %r9d # imm = 0x800
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $input, %esi
movl $.L.str, %edx
movl $.L.str, %ecx
movl $2048, %r9d # imm = 0x800
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type output,@object # @output
.local output
.comm output,2048,16
.type input,@object # @input
.local input
.comm input,2048,16
.type exception_in_divergent_call,@object # @exception_in_divergent_call
.section .rodata,"a",@progbits
.globl exception_in_divergent_call
.p2align 3, 0x0
exception_in_divergent_call:
.quad __device_stub__exception_in_divergent_call
.size exception_in_divergent_call, 8
.type exception_in_loop,@object # @exception_in_loop
.globl exception_in_loop
.p2align 3, 0x0
exception_in_loop:
.quad __device_stub__exception_in_loop
.size exception_in_loop, 8
.type exception_in_conditional,@object # @exception_in_conditional
.globl exception_in_conditional
.p2align 3, 0x0
exception_in_conditional:
.quad __device_stub__exception_in_conditional
.size exception_in_conditional, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "input"
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "exception_in_divergent_call"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "exception_in_loop"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "exception_in_conditional"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "output"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__exception_in_divergent_call
.addrsig_sym __device_stub__exception_in_loop
.addrsig_sym __device_stub__exception_in_conditional
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym output
.addrsig_sym input
.addrsig_sym exception_in_divergent_call
.addrsig_sym exception_in_loop
.addrsig_sym exception_in_conditional
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} | code for sm_80
Function : _Z19collateSegments_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B0, 0x3e0 ; /* 0x0000032000007945 */
/* 0x000fe60003800000 */
/*00c0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.IADD R2, R0, 0x1, R5 ; /* 0x0000000100027824 */
/* 0x000fe200078e0205 */
/*00e0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fc40007ffe0ff */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*0100*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fe200078e33ff */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0160*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x001fc800078e02ff */
/*0170*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fcc00078e0002 */
/*0180*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R7, R0, R3, R7 ; /* 0x0000000300077224 */
/* 0x000fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0230*/ LOP3.LUT P1, R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fe4000782c0ff */
/*0240*/ IADD3 R2, R6, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0208 */
/*0260*/ @!P1 BRA 0x3d0 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.WIDE R6, R5, R8, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0208 */
/*0280*/ IMAD.WIDE R8, R5, R8, c[0x0][0x160] ; /* 0x0000580005087625 */
/* 0x000fca00078e0208 */
/*0290*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ ISETP.NE.AND P1, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x004fda0003f25270 */
/*02c0*/ @!P1 LDG.E R15, [R6.64] ; /* 0x00000004060f9981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a9424 */
/* 0x000fc800078e00ff */
/*02e0*/ @!P1 IMAD.WIDE R10, R13, R10, c[0x0][0x170] ; /* 0x00005c000d0a9625 */
/* 0x000fca00078e020a */
/*02f0*/ @!P1 STG.E [R10.64], R15 ; /* 0x0000000f0a009986 */
/* 0x0041e8000c101904 */
/*0300*/ @!P1 LDG.E R13, [R8.64] ; /* 0x00000004080d9981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000404080c7981 */
/* 0x000ea4000c1e1900 */
/*0320*/ ISETP.NE.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720c */
/* 0x004fda0003f25270 */
/*0330*/ @P1 LDG.E R17, [R6.64] ; /* 0x0000000406111981 */
/* 0x0002a2000c1e1900 */
/*0340*/ @P1 MOV R12, 0x4 ; /* 0x00000004000c1802 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fe200078e0205 */
/*0360*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x000fc800078e0208 */
/*0380*/ @P1 IMAD.WIDE R12, R13, R12, c[0x0][0x170] ; /* 0x00005c000d0c1625 */
/* 0x000fc800078e020c */
/*0390*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fe200078e0206 */
/*03a0*/ @P1 STG.E [R12.64], R17 ; /* 0x000000110c001986 */
/* 0x0041e2000c101904 */
/*03b0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*03c0*/ @P1 BRA 0x290 ; /* 0xfffffec000001947 */
/* 0x001fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0400*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x001eb2000c1e1900 */
/*0410*/ IMAD.WIDE R12, R5, R4, c[0x0][0x160] ; /* 0x00005800050c7625 */
/* 0x000fca00078e0204 */
/*0420*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R14, R5, R4, c[0x0][0x168] ; /* 0x00005a00050e7625 */
/* 0x000fe200078e0204 */
/*0440*/ ISETP.NE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f05270 */
/*0450*/ @!P0 LDG.E R17, [R14.64] ; /* 0x000000040e118981 */
/* 0x000ea2000c1e1900 */
/*0460*/ @!P0 IMAD.WIDE R8, R11, R4, c[0x0][0x170] ; /* 0x00005c000b088625 */
/* 0x000fca00078e0204 */
/*0470*/ @!P0 STG.E [R8.64], R17 ; /* 0x0000001108008986 */
/* 0x0041e8000c101904 */
/*0480*/ @!P0 LDG.E R11, [R12.64] ; /* 0x000000040c0b8981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ ISETP.NE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 LDG.E R19, [R14.64] ; /* 0x000000040e130981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ @P0 IMAD.WIDE R10, R11, R4, c[0x0][0x170] ; /* 0x00005c000b0a0625 */
/* 0x000fc800078e0204 */
/*04d0*/ IMAD.WIDE R6, R0.reuse, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x040fe200078e020c */
/*04e0*/ @P0 STG.E [R10.64], R19 ; /* 0x000000130a000986 */
/* 0x0043e8000c101904 */
/*04f0*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IADD3 R23, R0, R5, RZ ; /* 0x0000000500177210 */
/* 0x000fc40007ffe0ff */
/*0520*/ ISETP.NE.AND P0, PT, R21, R16, PT ; /* 0x000000101500720c */
/* 0x004fc60003f05270 */
/*0530*/ IMAD.WIDE R16, R23, R4, c[0x0][0x168] ; /* 0x00005a0017107625 */
/* 0x001fd400078e0204 */
/*0540*/ @!P0 LDG.E R5, [R16.64] ; /* 0x0000000410058981 */
/* 0x000ea2000c1e1900 */
/*0550*/ @!P0 IMAD.WIDE R12, R21, R4, c[0x0][0x170] ; /* 0x00005c00150c8625 */
/* 0x000fca00078e0204 */
/*0560*/ @!P0 STG.E [R12.64], R5 ; /* 0x000000050c008986 */
/* 0x0041e8000c101904 */
/*0570*/ @!P0 LDG.E R21, [R6.64] ; /* 0x0000000406158981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea4000c1e1900 */
/*0590*/ ISETP.NE.AND P0, PT, R21, R8, PT ; /* 0x000000081500720c */
/* 0x004fda0003f05270 */
/*05a0*/ @P0 LDG.E R15, [R16.64] ; /* 0x00000004100f0981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ @P0 IMAD.WIDE R10, R21, R4, c[0x0][0x170] ; /* 0x00005c00150a0625 */
/* 0x002fc800078e0204 */
/*05c0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe200078e0206 */
/*05d0*/ @P0 STG.E [R10.64], R15 ; /* 0x0000000f0a000986 */
/* 0x0043e8000c101904 */
/*05e0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fc800078e0217 */
/*0610*/ IMAD.WIDE R12, R23, R4, c[0x0][0x168] ; /* 0x00005a00170c7625 */
/* 0x001fe200078e0204 */
/*0620*/ ISETP.NE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x004fda0003f05270 */
/*0630*/ @!P0 LDG.E R5, [R12.64] ; /* 0x000000040c058981 */
/* 0x000ea2000c1e1900 */
/*0640*/ @!P0 IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013068625 */
/* 0x000fca00078e0204 */
/*0650*/ @!P0 STG.E [R6.64], R5 ; /* 0x0000000506008986 */
/* 0x0041e8000c101904 */
/*0660*/ @!P0 LDG.E R19, [R8.64] ; /* 0x0000000408138981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea4000c1e1900 */
/*0680*/ ISETP.NE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x004fda0003f05270 */
/*0690*/ @P0 LDG.E R21, [R12.64] ; /* 0x000000040c150981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ @P0 IMAD.WIDE R10, R19, R4, c[0x0][0x170] ; /* 0x00005c00130a0625 */
/* 0x002fc800078e0204 */
/*06b0*/ IMAD.WIDE R14, R0.reuse, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x040fe200078e0208 */
/*06c0*/ @P0 STG.E [R10.64], R21 ; /* 0x000000150a000986 */
/* 0x0043e8000c101904 */
/*06d0*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R5, R0, R23, RZ ; /* 0x0000001700057210 */
/* 0x001fc40007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R19, R16, PT ; /* 0x000000101300720c */
/* 0x004fc60003f05270 */
/*0710*/ IMAD.WIDE R16, R5, R4, c[0x0][0x168] ; /* 0x00005a0005107625 */
/* 0x000fd400078e0204 */
/*0720*/ @!P0 LDG.E R9, [R16.64] ; /* 0x0000000410098981 */
/* 0x000ea2000c1e1900 */
/*0730*/ @!P0 IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013068625 */
/* 0x000fca00078e0204 */
/*0740*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0043e8000c101904 */
/*0750*/ @!P0 LDG.E R19, [R14.64] ; /* 0x000000040e138981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R8, [R14.64+0x4] ; /* 0x000004040e087981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fe20007ffe0ff */
/*0780*/ BSSY B0, 0x800 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0790*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc40003f26270 */
/*07a0*/ ISETP.NE.AND P0, PT, R19, R8, PT ; /* 0x000000081300720c */
/* 0x004fda0003f05270 */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x002ea2000c1e1900 */
/*07d0*/ IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013067625 */
/* 0x000fca00078e0204 */
/*07e0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e4000c101904 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0800*/ @!P1 BRA 0x3f0 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} | .file "tmpxft_001b3130_00000000-6_collateSegments.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
.type _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, @function
_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, .-_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
.globl _Z19collateSegments_gpuPiS_S_i
.type _Z19collateSegments_gpuPiS_S_i, @function
_Z19collateSegments_gpuPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z19collateSegments_gpuPiS_S_i, .-_Z19collateSegments_gpuPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19collateSegments_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19collateSegments_gpuPiS_S_i
.globl _Z19collateSegments_gpuPiS_S_i
.p2align 8
.type _Z19collateSegments_gpuPiS_S_i,@function
_Z19collateSegments_gpuPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_7
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s11, s10
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_u32 s12, s0, -4
s_addc_u32 s13, s1, -1
s_ashr_i32 s11, s10, 31
s_mov_b32 s1, 0
s_lshl_b64 s[14:15], s[10:11], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v2, s0, v2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s15, v3, s0
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_7
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v6, v[4:5], off
global_load_b32 v7, v0, s[12:13]
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v6, v7
s_cbranch_execz .LBB0_5
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
global_load_b32 v8, v[7:8], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off offset:4
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v4, v5
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
global_load_b32 v6, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19collateSegments_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z19collateSegments_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19collateSegments_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19collateSegments_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
**********************************************
* CS314 Principles of Programming Languages *
* Spring 2020 *
**********************************************
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Collates results of segment scan (or segment prefix sum), putting last value from each segment into an array
* Note that behavior for empty segments is undefined. E.g. if there's no segment with source node 2, then output[2] might contain garbage data.
* @param src The segment ID for each edge in the scan result
* @param scanResult The scan result or prefix sum result that we're collating
* @param output The output
* @param numEdges The size of the src and scanResult arrays.
*/
__global__ void collateSegments_gpu(int * src, int * scanResult, int * output, int numEdges) {
int totalThreads = blockDim.x * gridDim.x; //the total amount of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x; //the thread ID
int i;
for (i = tid; i < numEdges; i+= totalThreads) {
//compares src[i] with src[i+1], if they are not equal, then the i-th data element is the last one in its own segment
//if the very last element of the input, just store it
if(src[i] == src[numEdges-1]) {
output[src[i]] = scanResult[i];
}
//check if the last element of the segment represented by the src value -> if it is, assign the output as the scanresult
if (src[i] != src[i+1]) {
output[src[i]] = scanResult[i];
}
}
} | .text
.file "collateSegments.hip"
.globl _Z34__device_stub__collateSegments_gpuPiS_S_i # -- Begin function _Z34__device_stub__collateSegments_gpuPiS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__collateSegments_gpuPiS_S_i,@function
_Z34__device_stub__collateSegments_gpuPiS_S_i: # @_Z34__device_stub__collateSegments_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19collateSegments_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z34__device_stub__collateSegments_gpuPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19collateSegments_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19collateSegments_gpuPiS_S_i,@object # @_Z19collateSegments_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z19collateSegments_gpuPiS_S_i
.p2align 3, 0x0
_Z19collateSegments_gpuPiS_S_i:
.quad _Z34__device_stub__collateSegments_gpuPiS_S_i
.size _Z19collateSegments_gpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19collateSegments_gpuPiS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__collateSegments_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19collateSegments_gpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19collateSegments_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fe200078e02ff */
/*00b0*/ BSSY B0, 0x3e0 ; /* 0x0000032000007945 */
/* 0x000fe60003800000 */
/*00c0*/ I2F.U32.RP R4, R0 ; /* 0x0000000000047306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.IADD R2, R0, 0x1, R5 ; /* 0x0000000100027824 */
/* 0x000fe200078e0205 */
/*00e0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fc40007ffe0ff */
/*00f0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*0100*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fe200078e33ff */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fc600000001ff */
/*0120*/ IADD3 R7, R7, c[0x0][0x178], R0 ; /* 0x00005e0007077a10 */
/* 0x000fe20007ffe000 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R3, R4, 0xffffffe, RZ ; /* 0x0ffffffe04037810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e24000021f000 */
/*0160*/ IMAD R9, R9, R3, RZ ; /* 0x0000000309097224 */
/* 0x001fc800078e02ff */
/*0170*/ IMAD.HI.U32 R2, R3, R9, R2 ; /* 0x0000000903027227 */
/* 0x000fcc00078e0002 */
/*0180*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R3, RZ, RZ, -R2 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a02 */
/*01a0*/ IMAD R7, R0, R3, R7 ; /* 0x0000000300077224 */
/* 0x000fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R3, R2.reuse, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x040fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0230*/ LOP3.LUT P1, R4, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303047812 */
/* 0x000fe4000782c0ff */
/*0240*/ IADD3 R2, R6, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.WIDE R2, R2, R8, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0208 */
/*0260*/ @!P1 BRA 0x3d0 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.WIDE R6, R5, R8, c[0x0][0x168] ; /* 0x00005a0005067625 */
/* 0x000fc800078e0208 */
/*0280*/ IMAD.WIDE R8, R5, R8, c[0x0][0x160] ; /* 0x0000580005087625 */
/* 0x000fca00078e0208 */
/*0290*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ ISETP.NE.AND P1, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x004fda0003f25270 */
/*02c0*/ @!P1 LDG.E R15, [R6.64] ; /* 0x00000004060f9981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a9424 */
/* 0x000fc800078e00ff */
/*02e0*/ @!P1 IMAD.WIDE R10, R13, R10, c[0x0][0x170] ; /* 0x00005c000d0a9625 */
/* 0x000fca00078e020a */
/*02f0*/ @!P1 STG.E [R10.64], R15 ; /* 0x0000000f0a009986 */
/* 0x0041e8000c101904 */
/*0300*/ @!P1 LDG.E R13, [R8.64] ; /* 0x00000004080d9981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000404080c7981 */
/* 0x000ea4000c1e1900 */
/*0320*/ ISETP.NE.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720c */
/* 0x004fda0003f25270 */
/*0330*/ @P1 LDG.E R17, [R6.64] ; /* 0x0000000406111981 */
/* 0x0002a2000c1e1900 */
/*0340*/ @P1 MOV R12, 0x4 ; /* 0x00000004000c1802 */
/* 0x000fe20000000f00 */
/*0350*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fe200078e0205 */
/*0360*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x000fc800078e0208 */
/*0380*/ @P1 IMAD.WIDE R12, R13, R12, c[0x0][0x170] ; /* 0x00005c000d0c1625 */
/* 0x000fc800078e020c */
/*0390*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fe200078e0206 */
/*03a0*/ @P1 STG.E [R12.64], R17 ; /* 0x000000110c001986 */
/* 0x0041e2000c101904 */
/*03b0*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*03c0*/ @P1 BRA 0x290 ; /* 0xfffffec000001947 */
/* 0x001fea000383ffff */
/*03d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03f0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*0400*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x001eb2000c1e1900 */
/*0410*/ IMAD.WIDE R12, R5, R4, c[0x0][0x160] ; /* 0x00005800050c7625 */
/* 0x000fca00078e0204 */
/*0420*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IMAD.WIDE R14, R5, R4, c[0x0][0x168] ; /* 0x00005a00050e7625 */
/* 0x000fe200078e0204 */
/*0440*/ ISETP.NE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f05270 */
/*0450*/ @!P0 LDG.E R17, [R14.64] ; /* 0x000000040e118981 */
/* 0x000ea2000c1e1900 */
/*0460*/ @!P0 IMAD.WIDE R8, R11, R4, c[0x0][0x170] ; /* 0x00005c000b088625 */
/* 0x000fca00078e0204 */
/*0470*/ @!P0 STG.E [R8.64], R17 ; /* 0x0000001108008986 */
/* 0x0041e8000c101904 */
/*0480*/ @!P0 LDG.E R11, [R12.64] ; /* 0x000000040c0b8981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R6, [R12.64+0x4] ; /* 0x000004040c067981 */
/* 0x000ea4000c1e1900 */
/*04a0*/ ISETP.NE.AND P0, PT, R11, R6, PT ; /* 0x000000060b00720c */
/* 0x004fda0003f05270 */
/*04b0*/ @P0 LDG.E R19, [R14.64] ; /* 0x000000040e130981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ @P0 IMAD.WIDE R10, R11, R4, c[0x0][0x170] ; /* 0x00005c000b0a0625 */
/* 0x000fc800078e0204 */
/*04d0*/ IMAD.WIDE R6, R0.reuse, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x040fe200078e020c */
/*04e0*/ @P0 STG.E [R10.64], R19 ; /* 0x000000130a000986 */
/* 0x0043e8000c101904 */
/*04f0*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000ea8000c1e1900 */
/*0500*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1900 */
/*0510*/ IADD3 R23, R0, R5, RZ ; /* 0x0000000500177210 */
/* 0x000fc40007ffe0ff */
/*0520*/ ISETP.NE.AND P0, PT, R21, R16, PT ; /* 0x000000101500720c */
/* 0x004fc60003f05270 */
/*0530*/ IMAD.WIDE R16, R23, R4, c[0x0][0x168] ; /* 0x00005a0017107625 */
/* 0x001fd400078e0204 */
/*0540*/ @!P0 LDG.E R5, [R16.64] ; /* 0x0000000410058981 */
/* 0x000ea2000c1e1900 */
/*0550*/ @!P0 IMAD.WIDE R12, R21, R4, c[0x0][0x170] ; /* 0x00005c00150c8625 */
/* 0x000fca00078e0204 */
/*0560*/ @!P0 STG.E [R12.64], R5 ; /* 0x000000050c008986 */
/* 0x0041e8000c101904 */
/*0570*/ @!P0 LDG.E R21, [R6.64] ; /* 0x0000000406158981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R8, [R6.64+0x4] ; /* 0x0000040406087981 */
/* 0x000ea4000c1e1900 */
/*0590*/ ISETP.NE.AND P0, PT, R21, R8, PT ; /* 0x000000081500720c */
/* 0x004fda0003f05270 */
/*05a0*/ @P0 LDG.E R15, [R16.64] ; /* 0x00000004100f0981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ @P0 IMAD.WIDE R10, R21, R4, c[0x0][0x170] ; /* 0x00005c00150a0625 */
/* 0x002fc800078e0204 */
/*05c0*/ IMAD.WIDE R8, R0.reuse, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x040fe200078e0206 */
/*05d0*/ @P0 STG.E [R10.64], R15 ; /* 0x0000000f0a000986 */
/* 0x0043e8000c101904 */
/*05e0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea8000c1e1900 */
/*05f0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.IADD R23, R0, 0x1, R23 ; /* 0x0000000100177824 */
/* 0x000fc800078e0217 */
/*0610*/ IMAD.WIDE R12, R23, R4, c[0x0][0x168] ; /* 0x00005a00170c7625 */
/* 0x001fe200078e0204 */
/*0620*/ ISETP.NE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x004fda0003f05270 */
/*0630*/ @!P0 LDG.E R5, [R12.64] ; /* 0x000000040c058981 */
/* 0x000ea2000c1e1900 */
/*0640*/ @!P0 IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013068625 */
/* 0x000fca00078e0204 */
/*0650*/ @!P0 STG.E [R6.64], R5 ; /* 0x0000000506008986 */
/* 0x0041e8000c101904 */
/*0660*/ @!P0 LDG.E R19, [R8.64] ; /* 0x0000000408138981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R14, [R8.64+0x4] ; /* 0x00000404080e7981 */
/* 0x000ea4000c1e1900 */
/*0680*/ ISETP.NE.AND P0, PT, R19, R14, PT ; /* 0x0000000e1300720c */
/* 0x004fda0003f05270 */
/*0690*/ @P0 LDG.E R21, [R12.64] ; /* 0x000000040c150981 */
/* 0x000ea2000c1e1900 */
/*06a0*/ @P0 IMAD.WIDE R10, R19, R4, c[0x0][0x170] ; /* 0x00005c00130a0625 */
/* 0x002fc800078e0204 */
/*06b0*/ IMAD.WIDE R14, R0.reuse, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x040fe200078e0208 */
/*06c0*/ @P0 STG.E [R10.64], R21 ; /* 0x000000150a000986 */
/* 0x0043e8000c101904 */
/*06d0*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R5, R0, R23, RZ ; /* 0x0000001700057210 */
/* 0x001fc40007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R19, R16, PT ; /* 0x000000101300720c */
/* 0x004fc60003f05270 */
/*0710*/ IMAD.WIDE R16, R5, R4, c[0x0][0x168] ; /* 0x00005a0005107625 */
/* 0x000fd400078e0204 */
/*0720*/ @!P0 LDG.E R9, [R16.64] ; /* 0x0000000410098981 */
/* 0x000ea2000c1e1900 */
/*0730*/ @!P0 IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013068625 */
/* 0x000fca00078e0204 */
/*0740*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0043e8000c101904 */
/*0750*/ @!P0 LDG.E R19, [R14.64] ; /* 0x000000040e138981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R8, [R14.64+0x4] ; /* 0x000004040e087981 */
/* 0x000ea2000c1e1900 */
/*0770*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fe20007ffe0ff */
/*0780*/ BSSY B0, 0x800 ; /* 0x0000007000007945 */
/* 0x000fe60003800000 */
/*0790*/ ISETP.GE.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fc40003f26270 */
/*07a0*/ ISETP.NE.AND P0, PT, R19, R8, PT ; /* 0x000000081300720c */
/* 0x004fda0003f05270 */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*07c0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x002ea2000c1e1900 */
/*07d0*/ IMAD.WIDE R6, R19, R4, c[0x0][0x170] ; /* 0x00005c0013067625 */
/* 0x000fca00078e0204 */
/*07e0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e4000c101904 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0800*/ @!P1 BRA 0x3f0 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19collateSegments_gpuPiS_S_i
.globl _Z19collateSegments_gpuPiS_S_i
.p2align 8
.type _Z19collateSegments_gpuPiS_S_i,@function
_Z19collateSegments_gpuPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s3, 0xffff
s_mov_b32 s3, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_7
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s11, s10
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_u32 s12, s0, -4
s_addc_u32 s13, s1, -1
s_ashr_i32 s11, s10, 31
s_mov_b32 s1, 0
s_lshl_b64 s[14:15], s[10:11], 2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s10, v1
v_add_co_u32 v2, s0, v2, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s15, v3, s0
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_7
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v6, v[4:5], off
global_load_b32 v7, v0, s[12:13]
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v6, v7
s_cbranch_execz .LBB0_5
v_add_co_u32 v7, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v3, vcc_lo
global_load_b32 v8, v[7:8], off
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v8, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
s_mov_b32 s0, exec_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off offset:4
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v4, v5
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
global_load_b32 v6, v[5:6], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v6, off
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19collateSegments_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z19collateSegments_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19collateSegments_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19collateSegments_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b3130_00000000-6_collateSegments.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
.type _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, @function
_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i, .-_Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
.globl _Z19collateSegments_gpuPiS_S_i
.type _Z19collateSegments_gpuPiS_S_i, @function
_Z19collateSegments_gpuPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19collateSegments_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z19collateSegments_gpuPiS_S_i, .-_Z19collateSegments_gpuPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19collateSegments_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19collateSegments_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "collateSegments.hip"
.globl _Z34__device_stub__collateSegments_gpuPiS_S_i # -- Begin function _Z34__device_stub__collateSegments_gpuPiS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__collateSegments_gpuPiS_S_i,@function
_Z34__device_stub__collateSegments_gpuPiS_S_i: # @_Z34__device_stub__collateSegments_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19collateSegments_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__collateSegments_gpuPiS_S_i, .Lfunc_end0-_Z34__device_stub__collateSegments_gpuPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19collateSegments_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19collateSegments_gpuPiS_S_i,@object # @_Z19collateSegments_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z19collateSegments_gpuPiS_S_i
.p2align 3, 0x0
_Z19collateSegments_gpuPiS_S_i:
.quad _Z34__device_stub__collateSegments_gpuPiS_S_i
.size _Z19collateSegments_gpuPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19collateSegments_gpuPiS_S_i"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__collateSegments_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19collateSegments_gpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} | code for sm_80
Function : _Z13kernel_jacobiPlS_l
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x960 ; /* 0x0000092000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, 0x80, R3 ; /* 0x0000008000007824 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0080*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06300 */
/*0090*/ @P0 BRA 0x950 ; /* 0x000008b000000947 */
/* 0x000fea0003800000 */
/*00a0*/ LEA R10, P1, R0, c[0x0][0x160], 0x3 ; /* 0x00005800000a7a11 */
/* 0x000fc800078218ff */
/*00b0*/ LEA.HI.X R11, R0, c[0x0][0x164], R3, 0x3, P1 ; /* 0x00005900000b7a11 */
/* 0x000fcc00008f1c03 */
/*00c0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x5 ; /* 0x00000005ff027424 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0110*/ IMAD R6, R7, R2.reuse, RZ ; /* 0x0000000207067224 */
/* 0x080fe200078e02ff */
/*0120*/ BSSY B1, 0x330 ; /* 0x0000020000017945 */
/* 0x000fe20003800000 */
/*0130*/ IMAD.WIDE.U32 R12, R5, R2, RZ ; /* 0x00000002050c7225 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R9, R4, R5, R6 ; /* 0x0000000504097224 */
/* 0x000fc800078e0206 */
/*0150*/ IMAD.IADD R9, R13, 0x1, R9 ; /* 0x000000010d097824 */
/* 0x000fca00078e0209 */
/*0160*/ LOP3.LUT R6, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b09067212 */
/* 0x020fc800078efcff */
/*0170*/ ISETP.NE.U32.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f25070 */
/*0180*/ @!P1 BRA 0x200 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R24, RZ, RZ, R12 ; /* 0x000000ffff187224 */
/* 0x000fe200078e000c */
/*01a0*/ MOV R6, 0x1f0 ; /* 0x000001f000067802 */
/* 0x000fe20000000f00 */
/*01b0*/ IMAD.MOV.U32 R25, RZ, RZ, R9 ; /* 0x000000ffff197224 */
/* 0x000fe400078e0009 */
/*01c0*/ IMAD.MOV.U32 R23, RZ, RZ, R10 ; /* 0x000000ffff177224 */
/* 0x000fe400078e000a */
/*01d0*/ IMAD.MOV.U32 R22, RZ, RZ, R11 ; /* 0x000000ffff167224 */
/* 0x000fe400078e000b */
/*01e0*/ CALL.REL.NOINC 0x9d0 ; /* 0x000007e000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BRA 0x320 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0200*/ I2F.U32.RP R6, R10 ; /* 0x0000000a00067306 */
/* 0x000e220000209000 */
/*0210*/ IMAD.MOV R17, RZ, RZ, -R10 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0a0a */
/*0220*/ ISETP.NE.U32.AND P2, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f45070 */
/*0230*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fca00078e00ff */
/*0240*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0250*/ IADD3 R14, R6, 0xffffffe, RZ ; /* 0x0ffffffe060e7810 */
/* 0x001fcc0007ffe0ff */
/*0260*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x000064000021f000 */
/*0270*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0280*/ IMAD R17, R17, R15, RZ ; /* 0x0000000f11117224 */
/* 0x002fc800078e02ff */
/*0290*/ IMAD.HI.U32 R15, R15, R17, R14 ; /* 0x000000110f0f7227 */
/* 0x000fcc00078e000e */
/*02a0*/ IMAD.HI.U32 R15, R15, R12, RZ ; /* 0x0000000c0f0f7227 */
/* 0x000fc800078e00ff */
/*02b0*/ IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0f */
/*02c0*/ IMAD R23, R10, R15, R12 ; /* 0x0000000f0a177224 */
/* 0x000fca00078e020c */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R23, R10, PT ; /* 0x0000000a1700720c */
/* 0x000fda0003f26070 */
/*02e0*/ @P1 IMAD.IADD R23, R23, 0x1, -R10 ; /* 0x0000000117171824 */
/* 0x000fca00078e0a0a */
/*02f0*/ ISETP.GE.U32.AND P1, PT, R23, R10, PT ; /* 0x0000000a1700720c */
/* 0x000fda0003f26070 */
/*0300*/ @P1 IMAD.IADD R23, R23, 0x1, -R10 ; /* 0x0000000117171824 */
/* 0x000fe200078e0a0a */
/*0310*/ @!P2 LOP3.LUT R23, RZ, R10, RZ, 0x33, !PT ; /* 0x0000000aff17a212 */
/* 0x000fe400078e33ff */
/*0320*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0330*/ ISETP.NE.U32.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f25070 */
/*0340*/ BSSY B1, 0x8d0 ; /* 0x0000058000017945 */
/* 0x000fe20003800000 */
/*0350*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe400078e00ff */
/*0360*/ ISETP.NE.AND.EX P1, PT, R22, RZ, PT, P1 ; /* 0x000000ff1600720c */
/* 0x000fe20003f25310 */
/*0370*/ IMAD.MOV.U32 R24, RZ, RZ, R10 ; /* 0x000000ffff187224 */
/* 0x000fe400078e000a */
/*0380*/ IMAD.MOV.U32 R25, RZ, RZ, R11 ; /* 0x000000ffff197224 */
/* 0x000fd400078e000b */
/*0390*/ @!P1 BRA 0x8c0 ; /* 0x0000052000009947 */
/* 0x000fea0003800000 */
/*03a0*/ LOP3.LUT R16, R23, 0x1, RZ, 0xc0, !PT ; /* 0x0000000117107812 */
/* 0x000fe200078ec0ff */
/*03b0*/ BSSY B2, 0x5d0 ; /* 0x0000021000027945 */
/* 0x000fe20003800000 */
/*03c0*/ SHF.R.S32.HI R15, RZ, 0x1f, R25.reuse ; /* 0x0000001fff0f7819 */
/* 0x100fe40000011419 */
/*03d0*/ ISETP.NE.U32.AND P3, PT, R16, 0x1, PT ; /* 0x000000011000780c */
/* 0x000fe40003f65070 */
/*03e0*/ LEA.HI R15, P1, R15, R24, RZ, 0x2 ; /* 0x000000180f0f7211 */
/* 0x000fe400078310ff */
/*03f0*/ ISETP.NE.U32.AND.EX P3, PT, RZ, RZ, PT, P3 ; /* 0x000000ffff00720c */
/* 0x000fe40003f65130 */
/*0400*/ LOP3.LUT R15, R15, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc0f0f7812 */
/* 0x000fe200078ec0ff */
/*0410*/ IMAD.X R14, RZ, RZ, R25, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fc600008e0619 */
/*0420*/ IADD3 R6, P2, R24, -R15, RZ ; /* 0x8000000f18067210 */
/* 0x000fc80007f5e0ff */
/*0430*/ ISETP.NE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f25070 */
/*0440*/ IMAD.X R6, R25, 0x1, ~R14, P2 ; /* 0x0000000119067824 */
/* 0x000fe200010e0e0e */
/*0450*/ PLOP3.LUT P2, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f4e170 */
/*0460*/ ISETP.NE.AND.EX P1, PT, R6, RZ, PT, P1 ; /* 0x000000ff0600720c */
/* 0x000fe20003f25310 */
/*0470*/ @!P3 BRA 0x5c0 ; /* 0x000001400000b947 */
/* 0x000fee0003800000 */
/*0480*/ SHF.R.S32.HI R15, RZ, 0x1f, R25 ; /* 0x0000001fff0f7819 */
/* 0x000fc80000011419 */
/*0490*/ LEA.HI R15, P3, R15, R24, RZ, 0x3 ; /* 0x000000180f0f7211 */
/* 0x000fc800078718ff */
/*04a0*/ LOP3.LUT R15, R15, 0xfffffff8, RZ, 0xc0, !PT ; /* 0xfffffff80f0f7812 */
/* 0x000fe200078ec0ff */
/*04b0*/ IMAD.X R6, RZ, RZ, R25, P3 ; /* 0x000000ffff067224 */
/* 0x000fc600018e0619 */
/*04c0*/ IADD3 R15, P4, R24, -R15, RZ ; /* 0x8000000f180f7210 */
/* 0x000fc80007f9e0ff */
/*04d0*/ ISETP.NE.U32.AND P3, PT, R15, 0x5, PT ; /* 0x000000050f00780c */
/* 0x000fe20003f65070 */
/*04e0*/ IMAD.X R6, R25, 0x1, ~R6, P4 ; /* 0x0000000119067824 */
/* 0x000fe200020e0e06 */
/*04f0*/ ISETP.NE.U32.AND P4, PT, R15, 0x3, PT ; /* 0x000000030f00780c */
/* 0x000fc80003f85070 */
/*0500*/ ISETP.NE.AND.EX P5, PT, R6.reuse, RZ, PT, P3 ; /* 0x000000ff0600720c */
/* 0x040fe40003fa5330 */
/*0510*/ ISETP.NE.AND.EX P3, PT, R6, RZ, PT, P4 ; /* 0x000000ff0600720c */
/* 0x000fc80003f65340 */
/*0520*/ PLOP3.LUT P3, PT, P5, P3, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd80002f67070 */
/*0530*/ LEA.HI R23, P4, R22, R23, RZ, 0x1 ; /* 0x0000001716177211 */
/* 0x000fe200078908ff */
/*0540*/ @!P3 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08b224 */
/* 0x000fc800078e0a08 */
/*0550*/ IMAD.X R22, RZ, RZ, R22, P4 ; /* 0x000000ffff167224 */
/* 0x000fca00020e0616 */
/*0560*/ SHF.R.S64 R23, R23, 0x1, R22.reuse ; /* 0x0000000117177819 */
/* 0x100fe40000001016 */
/*0570*/ SHF.R.S32.HI R22, RZ, 0x1, R22 ; /* 0x00000001ff167819 */
/* 0x000fe40000011416 */
/*0580*/ LOP3.LUT R6, R23, 0x1, RZ, 0xc0, !PT ; /* 0x0000000117067812 */
/* 0x000fc800078ec0ff */
/*0590*/ ISETP.NE.U32.AND P4, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc80003f85070 */
/*05a0*/ ISETP.NE.U32.AND.EX P4, PT, RZ, RZ, PT, P4 ; /* 0x000000ffff00720c */
/* 0x000fda0003f85140 */
/*05b0*/ @P4 BRA 0x530 ; /* 0xffffff7000004947 */
/* 0x000fea000383ffff */
/*05c0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05d0*/ BSSY B2, 0x690 ; /* 0x000000b000027945 */
/* 0x000fe20003800000 */
/*05e0*/ @P1 BRA 0x680 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*05f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R22 ; /* 0x0000001fff067819 */
/* 0x000fc80000011416 */
/*0600*/ LEA.HI R6, P1, R6, R23, RZ, 0x2 ; /* 0x0000001706067211 */
/* 0x000fc800078310ff */
/*0610*/ LOP3.LUT R6, R6, 0xfffffffc, RZ, 0xc0, !PT ; /* 0xfffffffc06067812 */
/* 0x000fe200078ec0ff */
/*0620*/ IMAD.X R15, RZ, RZ, R22, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fc600008e0616 */
/*0630*/ IADD3 R6, P3, R23, -R6, RZ ; /* 0x8000000617067210 */
/* 0x000fc80007f7e0ff */
/*0640*/ ISETP.NE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f45070 */
/*0650*/ IMAD.X R6, R22, 0x1, ~R15, P3 ; /* 0x0000000116067824 */
/* 0x000fca00018e0e0f */
/*0660*/ ISETP.NE.AND.EX P2, PT, R6, RZ, PT, P2 ; /* 0x000000ff0600720c */
/* 0x000fc80003f45320 */
/*0670*/ PLOP3.LUT P2, PT, P2, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fd0000174e170 */
/*0680*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0690*/ LOP3.LUT R6, R25, R22, RZ, 0xfc, !PT ; /* 0x0000001619067212 */
/* 0x000fe200078efcff */
/*06a0*/ BSSY B2, 0x870 ; /* 0x000001c000027945 */
/* 0x000fe20003800000 */
/*06b0*/ @P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff082224 */
/* 0x000fe400078e0a08 */
/*06c0*/ ISETP.NE.U32.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25070 */
/*06d0*/ IMAD.MOV.U32 R20, RZ, RZ, R23 ; /* 0x000000ffff147224 */
/* 0x000fe400078e0017 */
/*06e0*/ IMAD.MOV.U32 R21, RZ, RZ, R22 ; /* 0x000000ffff157224 */
/* 0x000fd400078e0016 */
/*06f0*/ @!P1 BRA 0x730 ; /* 0x0000003000009947 */
/* 0x000fea0003800000 */
/*0700*/ MOV R6, 0x720 ; /* 0x0000072000067802 */
/* 0x000fe40000000f00 */
/*0710*/ CALL.REL.NOINC 0x9d0 ; /* 0x000002b000007944 */
/* 0x000fea0003c00000 */
/*0720*/ BRA 0x860 ; /* 0x0000013000007947 */
/* 0x000fea0003800000 */
/*0730*/ I2F.U32.RP R6, R23 ; /* 0x0000001700067306 */
/* 0x000e220000209000 */
/*0740*/ ISETP.NE.U32.AND P2, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f45070 */
/*0750*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fcc00078e00ff */
/*0760*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0770*/ IADD3 R14, R6, 0xffffffe, RZ ; /* 0x0ffffffe060e7810 */
/* 0x001fcc0007ffe0ff */
/*0780*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x000064000021f000 */
/*0790*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*07a0*/ IMAD.MOV R16, RZ, RZ, -R15 ; /* 0x000000ffff107224 */
/* 0x002fc800078e0a0f */
/*07b0*/ IMAD R17, R16, R23, RZ ; /* 0x0000001710117224 */
/* 0x000fc800078e02ff */
/*07c0*/ IMAD.HI.U32 R15, R15, R17, R14 ; /* 0x000000110f0f7227 */
/* 0x000fcc00078e000e */
/*07d0*/ IMAD.HI.U32 R15, R15, R24, RZ ; /* 0x000000180f0f7227 */
/* 0x000fc800078e00ff */
/*07e0*/ IMAD.MOV R15, RZ, RZ, -R15 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0a0f */
/*07f0*/ IMAD R16, R23, R15, R24 ; /* 0x0000000f17107224 */
/* 0x000fca00078e0218 */
/*0800*/ ISETP.GE.U32.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fda0003f26070 */
/*0810*/ @P1 IMAD.IADD R16, R16, 0x1, -R23 ; /* 0x0000000110101824 */
/* 0x000fca00078e0a17 */
/*0820*/ ISETP.GE.U32.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fda0003f26070 */
/*0830*/ @P1 IMAD.IADD R16, R16, 0x1, -R23 ; /* 0x0000000110101824 */
/* 0x000fe200078e0a17 */
/*0840*/ @!P2 LOP3.LUT R16, RZ, R23, RZ, 0x33, !PT ; /* 0x00000017ff10a212 */
/* 0x000fca00078e33ff */
/*0850*/ IMAD.MOV.U32 R23, RZ, RZ, R16 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0010 */
/*0860*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0870*/ ISETP.NE.U32.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f25070 */
/*0880*/ IMAD.MOV.U32 R24, RZ, RZ, R20 ; /* 0x000000ffff187224 */
/* 0x000fe400078e0014 */
/*0890*/ IMAD.MOV.U32 R25, RZ, RZ, R21 ; /* 0x000000ffff197224 */
/* 0x000fe200078e0015 */
/*08a0*/ ISETP.NE.AND.EX P1, PT, R22, RZ, PT, P1 ; /* 0x000000ff1600720c */
/* 0x000fda0003f25310 */
/*08b0*/ @P1 BRA 0x3a0 ; /* 0xfffffae000001947 */
/* 0x000fea000383ffff */
/*08c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08d0*/ ISETP.NE.AND P1, PT, R8, -0x1, PT ; /* 0xffffffff0800780c */
/* 0x000fe40003f25270 */
/*08e0*/ ISETP.NE.U32.AND P2, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fe40003f45070 */
/*08f0*/ IADD3 R2, P3, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x000fe40007f7e0ff */
/*0900*/ ISETP.NE.OR.EX P1, PT, R25, RZ, P1, P2 ; /* 0x000000ff1900720c */
/* 0x000fe40000f25720 */
/*0910*/ IADD3 R5, P4, RZ, -R5, RZ ; /* 0x80000005ff057210 */
/* 0x000fe20007f9e0ff */
/*0920*/ IMAD.X R4, RZ, RZ, R4, P3 ; /* 0x000000ffff047224 */
/* 0x000fc800018e0604 */
/*0930*/ IMAD.X R7, RZ, RZ, ~R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fcc00020e0e07 */
/*0940*/ @P1 BRA 0x110 ; /* 0xfffff7c000001947 */
/* 0x000fea000383ffff */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0970*/ @!P0 LEA R2, P1, R0, c[0x0][0x168], 0x3 ; /* 0x00005a0000028a11 */
/* 0x000fe200078218ff */
/*0980*/ @!P0 IMAD.MOV.U32 R8, RZ, RZ, R12 ; /* 0x000000ffff088224 */
/* 0x000fc600078e000c */
/*0990*/ @!P0 LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x3, P1 ; /* 0x00005b0000038a11 */
/* 0x000fca00008f1c03 */
/*09a0*/ @!P0 STG.E.64 [R2.64], R8 ; /* 0x0000000802008986 */
/* 0x000fe8000c101b04 */
/*09b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ IADD3 R14, P2, RZ, -R23, RZ ; /* 0x80000017ff0e7210 */
/* 0x000fe40007f5e0ff */
/*09e0*/ ISETP.GE.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc60003f26270 */
/*09f0*/ IMAD.X R15, RZ, RZ, ~R22, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e0e16 */
/*0a00*/ SEL R14, R14, R23, !P1 ; /* 0x000000170e0e7207 */
/* 0x000fc80004800000 */
/*0a10*/ SEL R15, R15, R22, !P1 ; /* 0x000000160f0f7207 */
/* 0x000fc80004800000 */
/*0a20*/ I2F.U64.RP R26, R14 ; /* 0x0000000e001a7312 */
/* 0x000e300000309000 */
/*0a30*/ MUFU.RCP R26, R26 ; /* 0x0000001a001a7308 */
/* 0x001e240000001000 */
/*0a40*/ IADD3 R16, R26, 0x1ffffffe, RZ ; /* 0x1ffffffe1a107810 */
/* 0x001fcc0007ffe0ff */
/*0a50*/ F2I.U64.TRUNC R16, R16 ; /* 0x0000001000107311 */
/* 0x000e24000020d800 */
/*0a60*/ IMAD.WIDE.U32 R18, R16, R14, RZ ; /* 0x0000000e10127225 */
/* 0x001fc800078e00ff */
/*0a70*/ IMAD R19, R16, R15, R19 ; /* 0x0000000f10137224 */
/* 0x000fe200078e0213 */
/*0a80*/ IADD3 R29, P1, RZ, -R18, RZ ; /* 0x80000012ff1d7210 */
/* 0x000fc60007f3e0ff */
/*0a90*/ IMAD R19, R17, R14, R19 ; /* 0x0000000e11137224 */
/* 0x000fe400078e0213 */
/*0aa0*/ IMAD.HI.U32 R18, R16, R29, RZ ; /* 0x0000001d10127227 */
/* 0x000fc800078e00ff */
/*0ab0*/ IMAD.X R27, RZ, RZ, ~R19, P1 ; /* 0x000000ffff1b7224 */
/* 0x000fe400008e0e13 */
/*0ac0*/ IMAD.MOV.U32 R19, RZ, RZ, R16 ; /* 0x000000ffff137224 */
/* 0x000fc800078e0010 */
/*0ad0*/ IMAD.WIDE.U32 R18, P1, R16, R27, R18 ; /* 0x0000001b10127225 */
/* 0x000fcc0007820012 */
/*0ae0*/ IMAD.HI.U32 R18, P2, R17, R29, R18 ; /* 0x0000001d11127227 */
/* 0x000fc80007840012 */
/*0af0*/ IMAD R19, R17.reuse, R27.reuse, RZ ; /* 0x0000001b11137224 */
/* 0x0c0fe400078e02ff */
/*0b00*/ IMAD.HI.U32 R27, R17, R27, RZ ; /* 0x0000001b111b7227 */
/* 0x000fc600078e00ff */
/*0b10*/ IADD3 R19, P3, R19, R18, RZ ; /* 0x0000001213137210 */
/* 0x000fe20007f7e0ff */
/*0b20*/ IMAD.X R27, R27, 0x1, R17, P1 ; /* 0x000000011b1b7824 */
/* 0x000fc800008e0611 */
/*0b30*/ IMAD.WIDE.U32 R16, R19, R14, RZ ; /* 0x0000000e13107225 */
/* 0x000fe200078e00ff */
/*0b40*/ IADD3.X R27, RZ, RZ, R27, P3, P2 ; /* 0x000000ffff1b7210 */
/* 0x000fe40001fe441b */
/*0b50*/ ISETP.GE.AND P2, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe20003f46270 */
/*0b60*/ IMAD R18, R19, R15, R17 ; /* 0x0000000f13127224 */
/* 0x000fe200078e0211 */
/*0b70*/ IADD3 R17, P1, RZ, -R16, RZ ; /* 0x80000010ff117210 */
/* 0x000fc60007f3e0ff */
/*0b80*/ IMAD R16, R27, R14, R18 ; /* 0x0000000e1b107224 */
/* 0x000fe400078e0212 */
/*0b90*/ IMAD.HI.U32 R18, R19, R17, RZ ; /* 0x0000001113127227 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.X R16, RZ, RZ, ~R16, P1 ; /* 0x000000ffff107224 */
/* 0x000fc800008e0e10 */
/*0bb0*/ IMAD.WIDE.U32 R18, P1, R19, R16, R18 ; /* 0x0000001013127225 */
/* 0x000fcc0007820012 */
/*0bc0*/ IMAD.HI.U32 R18, P3, R27, R17, R18 ; /* 0x000000111b127227 */
/* 0x000fe20007860012 */
/*0bd0*/ IADD3 R19, P5, RZ, -R24, RZ ; /* 0x80000018ff137210 */
/* 0x000fc60007fbe0ff */
/*0be0*/ IMAD R17, R27, R16, RZ ; /* 0x000000101b117224 */
/* 0x000fe200078e02ff */
/*0bf0*/ SEL R19, R19, R24, !P2 ; /* 0x0000001813137207 */
/* 0x000fe20005000000 */
/*0c00*/ IMAD.HI.U32 R16, R27, R16, RZ ; /* 0x000000101b107227 */
/* 0x000fc600078e00ff */
/*0c10*/ IADD3 R18, P4, R17, R18, RZ ; /* 0x0000001211127210 */
/* 0x000fe20007f9e0ff */
/*0c20*/ IMAD.X R24, RZ, RZ, ~R25, P5 ; /* 0x000000ffff187224 */
/* 0x000fe400028e0e19 */
/*0c30*/ IMAD.X R27, R16, 0x1, R27, P1 ; /* 0x00000001101b7824 */
/* 0x000fe400008e061b */
/*0c40*/ IMAD.HI.U32 R16, R18, R19, RZ ; /* 0x0000001312107227 */
/* 0x000fe200078e00ff */
/*0c50*/ SEL R25, R24, R25, !P2 ; /* 0x0000001918197207 */
/* 0x000fe40005000000 */
/*0c60*/ IADD3.X R24, RZ, RZ, R27, P4, P3 ; /* 0x000000ffff187210 */
/* 0x000fe200027e641b */
/*0c70*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fc800078e00ff */
/*0c80*/ IMAD.WIDE.U32 R16, R18, R25, R16 ; /* 0x0000001912107225 */
/* 0x000fc800078e0010 */
/*0c90*/ IMAD R27, R24.reuse, R25, RZ ; /* 0x00000019181b7224 */
/* 0x040fe400078e02ff */
/*0ca0*/ IMAD.HI.U32 R16, P1, R24, R19, R16 ; /* 0x0000001318107227 */
/* 0x000fc80007820010 */
/*0cb0*/ IMAD.HI.U32 R18, R24, R25, RZ ; /* 0x0000001918127227 */
/* 0x000fe200078e00ff */
/*0cc0*/ IADD3 R27, P3, R27, R16, RZ ; /* 0x000000101b1b7210 */
/* 0x000fc60007f7e0ff */
/*0cd0*/ IMAD.X R18, RZ, RZ, R18, P1 ; /* 0x000000ffff127224 */
/* 0x000fe400008e0612 */
/*0ce0*/ IMAD.WIDE.U32 R16, R27, R14, RZ ; /* 0x0000000e1b107225 */
/* 0x000fc800078e00ff */
/*0cf0*/ IMAD.X R29, RZ, RZ, R18, P3 ; /* 0x000000ffff1d7224 */
/* 0x000fe200018e0612 */
/*0d00*/ IADD3 R18, P3, -R16, R19, RZ ; /* 0x0000001310127210 */
/* 0x000fe20007f7e1ff */
/*0d10*/ IMAD R27, R27, R15, R17 ; /* 0x0000000f1b1b7224 */
/* 0x000fc600078e0211 */
/*0d20*/ ISETP.GE.U32.AND P1, PT, R18, R14.reuse, PT ; /* 0x0000000e1200720c */
/* 0x080fe20003f26070 */
/*0d30*/ IMAD R16, R29, R14, R27 ; /* 0x0000000e1d107224 */
/* 0x000fc800078e021b */
/*0d40*/ IMAD.X R25, R25, 0x1, ~R16, P3 ; /* 0x0000000119197824 */
/* 0x000fe200018e0e10 */
/*0d50*/ IADD3 R17, P3, R18, -R14, RZ ; /* 0x8000000e12117210 */
/* 0x000fc80007f7e0ff */
/*0d60*/ ISETP.GE.U32.AND.EX P1, PT, R25.reuse, R15, PT, P1 ; /* 0x0000000f1900720c */
/* 0x040fe20003f26110 */
/*0d70*/ IMAD.X R19, R25, 0x1, ~R15, P3 ; /* 0x0000000119137824 */
/* 0x000fc600018e0e0f */
/*0d80*/ SEL R17, R17, R18, P1 ; /* 0x0000001211117207 */
/* 0x000fe40000800000 */
/*0d90*/ SEL R19, R19, R25, P1 ; /* 0x0000001913137207 */
/* 0x000fe40000800000 */
/*0da0*/ ISETP.GE.U32.AND P1, PT, R17.reuse, R14.reuse, PT ; /* 0x0000000e1100720c */
/* 0x0c0fe40003f26070 */
/*0db0*/ IADD3 R14, P3, R17, -R14, RZ ; /* 0x8000000e110e7210 */
/* 0x000fe40007f7e0ff */
/*0dc0*/ ISETP.GE.U32.AND.EX P1, PT, R19, R15, PT, P1 ; /* 0x0000000f1300720c */
/* 0x000fc60003f26110 */
/*0dd0*/ IMAD.X R15, R19, 0x1, ~R15, P3 ; /* 0x00000001130f7824 */
/* 0x000fe200018e0e0f */
/*0de0*/ SEL R14, R14, R17, P1 ; /* 0x000000110e0e7207 */
/* 0x000fc80000800000 */
/*0df0*/ SEL R15, R15, R19, P1 ; /* 0x000000130f0f7207 */
/* 0x000fe40000800000 */
/*0e00*/ IADD3 R17, P3, RZ, -R14.reuse, RZ ; /* 0x8000000eff117210 */
/* 0x080fe40007f7e0ff */
/*0e10*/ ISETP.NE.U32.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f25070 */
/*0e20*/ SEL R23, R17, R14, !P2 ; /* 0x0000000e11177207 */
/* 0x000fe20005000000 */
/*0e30*/ IMAD.X R16, RZ, RZ, ~R15, P3 ; /* 0x000000ffff107224 */
/* 0x000fe200018e0e0f */
/*0e40*/ ISETP.NE.AND.EX P1, PT, R22, RZ, PT, P1 ; /* 0x000000ff1600720c */
/* 0x000fe20003f25310 */
/*0e50*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0006 */
/*0e60*/ SEL R22, R16, R15, !P2 ; /* 0x0000000f10167207 */
/* 0x000fe20005000000 */
/*0e70*/ IMAD.MOV.U32 R15, RZ, RZ, 0x0 ; /* 0x00000000ff0f7424 */
/* 0x000fe200078e00ff */
/*0e80*/ SEL R23, R23, 0xffffffff, P1 ; /* 0xffffffff17177807 */
/* 0x000fe40000800000 */
/*0e90*/ SEL R22, R22, 0xffffffff, P1 ; /* 0xffffffff16167807 */
/* 0x000fe20000800000 */
/*0ea0*/ RET.REL.NODEC R14 0x0 ; /* 0xfffff1500e007950 */
/* 0x000fec0003c3ffff */
/*0eb0*/ BRA 0xeb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} | .file "tmpxft_0008be6a_00000000-6_kernel_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
.type _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l, @function
_Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_jacobiPlS_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l, .-_Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
.globl _Z13kernel_jacobiPlS_l
.type _Z13kernel_jacobiPlS_l, @function
_Z13kernel_jacobiPlS_l:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_jacobiPlS_l, .-_Z13kernel_jacobiPlS_l
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernel_jacobiPlS_l"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_jacobiPlS_l(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kernel_jacobiPlS_l
.globl _Z13kernel_jacobiPlS_l
.p2align 8
.type _Z13kernel_jacobiPlS_l,@function
_Z13kernel_jacobiPlS_l:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshl_add_u32 v0, s15, 7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i64_e64 s2, s[2:3], v[0:1]
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_25
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[2:3], 3, v[0:1]
v_mov_b32_e32 v5, 0
s_mov_b64 s[8:9], 1
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b64 s[6:7], 5
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v3
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s14
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_cmp_eq_u64_e32 vcc_lo, 1, v[8:9]
v_cmp_eq_u32_e64 s3, -1, v13
s_add_u32 s6, s6, 2
s_addc_u32 s7, s7, 0
s_sub_u32 s8, 0, s8
s_subb_u32 s9, 0, s9
s_and_b32 s3, vcc_lo, s3
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_and_b32 s3, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s12, s3, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_24
.LBB0_4:
s_mul_i32 s3, s8, s7
s_mul_hi_u32 s4, s8, s6
s_mul_i32 s10, s9, s6
s_add_i32 s3, s4, s3
v_mov_b32_e32 v6, v5
s_add_i32 s11, s3, s10
s_mul_i32 s10, s8, s6
v_or_b32_e32 v7, s11, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u64_e32 0, v[6:7]
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_6
v_add_co_u32 v4, vcc_lo, v2, v12
v_add_co_ci_u32_e32 v6, vcc_lo, v3, v12, vcc_lo
s_ashr_i32 s14, s11, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v12
s_add_u32 s16, s10, s14
v_xor_b32_e32 v15, v6, v12
s_mov_b32 s15, s14
s_addc_u32 s17, s11, s14
v_cvt_f32_u32_e32 v6, v4
v_sub_co_u32 v11, vcc_lo, 0, v4
v_cvt_f32_u32_e32 v7, v15
v_sub_co_ci_u32_e32 v16, vcc_lo, 0, v15, vcc_lo
s_xor_b64 s[16:17], s[16:17], s[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, 0x4f800000, v7
v_rcp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x5f7ffffc, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x2f800000, v6
v_trunc_f32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v6, 0xcf800000, v7
v_cvt_u32_f32_e32 v17, v7
v_cvt_u32_f32_e32 v18, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v8, v11, v17
v_mul_lo_u32 v9, v16, v18
v_mad_u64_u32 v[6:7], null, v11, v18, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v19, v7, v8, v9
v_mul_hi_u32 v20, v18, v6
v_mad_u64_u32 v[9:10], null, v17, v6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v18, v19, 0
v_mad_u64_u32 v[13:14], null, v17, v19, 0
v_add_co_u32 v6, vcc_lo, v20, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v18, vcc_lo, v18, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v17, v7, vcc_lo
v_mul_lo_u32 v8, v16, v18
v_mad_u64_u32 v[6:7], null, v11, v18, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, v11, v17
v_mul_hi_u32 v16, v18, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v11, v7, v9, v8
v_mad_u64_u32 v[9:10], null, v17, v6, 0
v_mad_u64_u32 v[7:8], null, v18, v11, 0
v_mad_u64_u32 v[13:14], null, v17, v11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v16, v7
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v9
v_add_co_ci_u32_e32 v6, vcc_lo, v7, v10, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v13
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v18, v6
v_add_co_ci_u32_e32 v13, vcc_lo, v17, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v14, s16, v10
v_mad_u64_u32 v[8:9], null, s17, v10, 0
v_mad_u64_u32 v[6:7], null, s16, v13, 0
v_mad_u64_u32 v[10:11], null, s17, v13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v14, v6
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, v6, v8
v_add_co_ci_u32_e32 v6, vcc_lo, v7, v9, vcc_lo
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, v10
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v10, v15, v8
v_mad_u64_u32 v[6:7], null, v4, v8, 0
v_mul_lo_u32 v8, v4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v6, vcc_lo, s16, v6
v_add3_u32 v7, v7, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, s17, v7
v_sub_co_ci_u32_e64 v8, s3, v8, v15, vcc_lo
v_sub_co_ci_u32_e32 v7, vcc_lo, s17, v7, vcc_lo
v_sub_co_u32 v9, vcc_lo, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v10, s3, 0, v8, vcc_lo
v_cmp_ge_u32_e64 s3, v6, v4
v_sub_co_ci_u32_e32 v8, vcc_lo, v8, v15, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v7, v15
v_cndmask_b32_e64 v11, 0, -1, s3
v_cmp_ge_u32_e64 s3, v9, v4
v_cndmask_b32_e64 v16, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v10, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, 0, -1, s3
v_cmp_ge_u32_e64 s3, v10, v15
v_cndmask_b32_e64 v14, 0, -1, s3
v_cmp_eq_u32_e64 s3, v7, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
v_sub_co_u32 v4, vcc_lo, v9, v4
v_subrev_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v11, v16, v11, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
v_cndmask_b32_e32 v4, v9, v4, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v6, v4, vcc_lo
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, s14, v4
v_xor_b32_e32 v6, s14, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v10, vcc_lo, v4, s14
v_subrev_co_ci_u32_e32 v11, vcc_lo, s14, v6, vcc_lo
.LBB0_6:
s_and_not1_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v4, v2
v_sub_nc_u32_e32 v6, 0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v6, v4
v_mul_hi_u32 v6, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v6
v_mul_hi_u32 v4, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, v2
v_sub_nc_u32_e32 v4, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v4, v2
v_cmp_ge_u32_e32 vcc_lo, v4, v2
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v6, v4, v2
v_cmp_ge_u32_e32 vcc_lo, v4, v2
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v7, v3
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
v_dual_mov_b32 v13, 1 :: v_dual_mov_b32 v6, v2
s_mov_b32 s14, 0
s_mov_b32 s13, exec_lo
v_cmpx_ne_u64_e32 0, v[10:11]
s_cbranch_execnz .LBB0_10
s_branch .LBB0_3
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
v_and_b32_e32 v7, 0x80000000, v7
v_sub_nc_u32_e32 v4, 0, v13
v_and_b32_e32 v6, 3, v6
v_and_b32_e32 v15, 0x80000000, v9
v_and_b32_e32 v14, 3, v8
v_cmp_eq_u64_e64 s4, 0, v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_eq_u64_e32 vcc_lo, 3, v[6:7]
v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
v_cmp_eq_u64_e64 s3, 3, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
s_and_b32 vcc_lo, vcc_lo, s3
s_or_b32 s14, s4, s14
v_cndmask_b32_e32 v13, v13, v4, vcc_lo
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_2
.LBB0_10:
v_and_b32_e32 v4, 1, v10
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u64_e32 0, v[4:5]
s_cbranch_execz .LBB0_20
v_ashrrev_i32_e32 v4, 31, v7
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 29, v4
v_add_co_u32 v4, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, -8, v4
v_sub_co_u32 v8, vcc_lo, v6, v4
s_delay_alu instid0(VALU_DEP_3)
v_sub_co_ci_u32_e32 v9, vcc_lo, v7, v9, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s16
v_and_b32_e32 v4, 2, v10
v_ashrrev_i64 v[10:11], 1, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_or_b32 s4, vcc_lo, s4
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_19
.LBB0_13:
s_mov_b32 s15, 0
s_mov_b32 s16, exec_lo
v_cmpx_lt_i64_e32 4, v[8:9]
s_xor_b32 s16, exec_lo, s16
v_cmp_eq_u64_e32 vcc_lo, 5, v[8:9]
s_and_b32 s15, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s16, s16
v_cmp_eq_u64_e32 vcc_lo, 3, v[8:9]
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s17, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s15, s17
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_12
v_sub_nc_u32_e32 v13, 0, v13
s_branch .LBB0_12
.LBB0_19:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_20:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s3
v_dual_mov_b32 v8, v10 :: v_dual_mov_b32 v9, v11
v_mov_b32_e32 v10, v5
v_or_b32_e32 v11, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[10:11]
s_and_saveexec_b32 s3, vcc_lo
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_22
v_ashrrev_i32_e32 v4, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v8, v4
v_add_co_ci_u32_e32 v11, vcc_lo, v9, v4, vcc_lo
v_xor_b32_e32 v18, v10, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v11, v4
v_cvt_f32_u32_e32 v10, v18
v_sub_co_u32 v19, vcc_lo, 0, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v11, v4
v_sub_co_ci_u32_e32 v20, vcc_lo, 0, v4, vcc_lo
v_fmac_f32_e32 v10, 0x4f800000, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, 0x5f7ffffc, v10
v_mul_f32_e32 v11, 0x2f800000, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v11, v11
v_fmac_f32_e32 v10, 0xcf800000, v11
v_cvt_u32_f32_e32 v21, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v22, v10
v_mul_lo_u32 v14, v19, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v15, v20, v22
v_mad_u64_u32 v[10:11], null, v19, v22, 0
v_add3_u32 v23, v11, v14, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v24, v22, v10
v_mad_u64_u32 v[16:17], null, v21, v10, 0
v_mad_u64_u32 v[14:15], null, v22, v23, 0
v_mad_u64_u32 v[10:11], null, v21, v23, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v14, vcc_lo, v24, v14
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v14, vcc_lo, v14, v16
v_add_co_ci_u32_e32 v14, vcc_lo, v15, v17, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v14, v10
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v22, vcc_lo, v22, v10
v_add_co_ci_u32_e32 v21, vcc_lo, v21, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v14, v20, v22
v_mad_u64_u32 v[10:11], null, v19, v22, 0
v_mul_lo_u32 v15, v19, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v20, v22, v10
v_mad_u64_u32 v[16:17], null, v21, v10, 0
v_add3_u32 v19, v11, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[14:15], null, v22, v19, 0
v_mad_u64_u32 v[10:11], null, v21, v19, 0
v_ashrrev_i32_e32 v19, 31, v7
v_add_co_u32 v14, vcc_lo, v20, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v15, vcc_lo
v_add_co_u32 v14, vcc_lo, v14, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v14, vcc_lo, v15, v17, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v15, vcc_lo, v6, v19
v_add_co_ci_u32_e32 v16, vcc_lo, v7, v19, vcc_lo
v_add_co_u32 v10, vcc_lo, v14, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_xor_b32_e32 v20, v15, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v17, vcc_lo, v22, v10
v_add_co_ci_u32_e32 v21, vcc_lo, v21, v11, vcc_lo
v_xor_b32_e32 v22, v16, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v23, v20, v17
v_mad_u64_u32 v[10:11], null, v20, v21, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[14:15], null, v22, v17, 0
v_mad_u64_u32 v[16:17], null, v22, v21, 0
v_add_co_u32 v10, vcc_lo, v23, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
v_add_co_u32 v10, vcc_lo, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, v11, v15, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v17, vcc_lo
v_add_co_u32 v14, vcc_lo, v10, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v15, vcc_lo, 0, v11, vcc_lo
v_mul_lo_u32 v16, v4, v14
v_mad_u64_u32 v[10:11], null, v18, v14, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v14, v18, v15
v_sub_co_u32 v10, vcc_lo, v20, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v11, v11, v14, v16
v_sub_nc_u32_e32 v14, v22, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_co_ci_u32_e64 v14, s3, v14, v4, vcc_lo
v_sub_co_ci_u32_e32 v11, vcc_lo, v22, v11, vcc_lo
v_sub_co_u32 v15, vcc_lo, v10, v18
v_subrev_co_ci_u32_e64 v16, s3, 0, v14, vcc_lo
v_cmp_ge_u32_e64 s3, v10, v18
v_sub_co_ci_u32_e32 v14, vcc_lo, v14, v4, vcc_lo
v_cmp_ge_u32_e32 vcc_lo, v11, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v17, 0, -1, s3
v_cmp_ge_u32_e64 s3, v15, v18
v_cndmask_b32_e64 v22, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, v16, v4
v_cndmask_b32_e64 v20, 0, -1, s3
v_cmp_ge_u32_e64 s3, v16, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v21, 0, -1, s3
v_cmp_eq_u32_e64 s3, v11, v4
v_cndmask_b32_e32 v20, v21, v20, vcc_lo
v_sub_co_u32 v18, vcc_lo, v15, v18
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, 0, v20
v_cndmask_b32_e64 v4, v22, v17, s3
v_cndmask_b32_e32 v14, v16, v14, vcc_lo
v_cndmask_b32_e32 v15, v15, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e32 v10, v10, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v11, v14, vcc_lo
v_xor_b32_e32 v10, v10, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v19
v_sub_co_u32 v10, vcc_lo, v10, v19
s_delay_alu instid0(VALU_DEP_2)
v_sub_co_ci_u32_e32 v11, vcc_lo, v4, v19, vcc_lo
.LBB0_22:
s_and_not1_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_9
v_cvt_f32_u32_e32 v4, v8
v_sub_nc_u32_e32 v10, 0, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, v10, v4
v_mul_hi_u32 v10, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v10
v_mul_hi_u32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, v8
v_sub_nc_u32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v4, v8
v_cmp_ge_u32_e32 vcc_lo, v4, v8
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v4, v8
v_cmp_ge_u32_e32 vcc_lo, v4, v8
v_cndmask_b32_e32 v4, v4, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v10, v4
s_branch .LBB0_9
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_27
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[6:7], off
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kernel_jacobiPlS_l
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kernel_jacobiPlS_l, .Lfunc_end0-_Z13kernel_jacobiPlS_l
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kernel_jacobiPlS_l
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13kernel_jacobiPlS_l.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*****************************************************************************/
// nvcc -O1 -o bpsw bpsw.cu -lrt -lm
// Assertion to check for errors
__global__ void kernel_jacobi(long* nArray, long* dArray, long len) {
int bx = blockIdx.x; // ID thread
int tx = threadIdx.x;
int result, t;
long d, dAbs, sign, temp, n1, d1;
// Identify the row and column of the Pd element to work on
long memIndex = bx*TILE_WIDTH + tx;
if (memIndex < len) //out of bounds checking - some threads will be doing nothing
{
result = 0;
dAbs = 5;
sign = 1;
while (result != -1) //if result != -1, increment d and try again
{
n1 = nArray[memIndex]; //reinitialize n1 to n
d = dAbs*sign;
t = 1;
d1 = d; //reinitialize d1 to d
d1 = d1 % n1;
while (d1 != 0)
{
while (d1 % 2 == 0) //while d is even
{
d1 = d1 / 2;
if (n1 % 8 == 3 || n1 % 8 == 5) t = -t;
}
temp = d1;
d1 = n1;
n1 = temp;
if ((d1 % 4 == 3) && (n1 % 4 == 3)) t = -t;
d1 = d1 % n1;
}
if (n1 == 1) result = t;
else result = 0;
dAbs = dAbs + 2;
sign = sign * -1;
}
}
__syncthreads();
if (memIndex < len)
dArray[memIndex] = d;
__syncthreads();
} | .text
.file "kernel_jacobi.hip"
.globl _Z28__device_stub__kernel_jacobiPlS_l # -- Begin function _Z28__device_stub__kernel_jacobiPlS_l
.p2align 4, 0x90
.type _Z28__device_stub__kernel_jacobiPlS_l,@function
_Z28__device_stub__kernel_jacobiPlS_l: # @_Z28__device_stub__kernel_jacobiPlS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_jacobiPlS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_jacobiPlS_l, .Lfunc_end0-_Z28__device_stub__kernel_jacobiPlS_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_jacobiPlS_l, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_jacobiPlS_l,@object # @_Z13kernel_jacobiPlS_l
.section .rodata,"a",@progbits
.globl _Z13kernel_jacobiPlS_l
.p2align 3, 0x0
_Z13kernel_jacobiPlS_l:
.quad _Z28__device_stub__kernel_jacobiPlS_l
.size _Z13kernel_jacobiPlS_l, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_jacobiPlS_l"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_jacobiPlS_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_jacobiPlS_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008be6a_00000000-6_kernel_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
.type _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l, @function
_Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kernel_jacobiPlS_l(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l, .-_Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
.globl _Z13kernel_jacobiPlS_l
.type _Z13kernel_jacobiPlS_l, @function
_Z13kernel_jacobiPlS_l:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kernel_jacobiPlS_lPlS_l
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13kernel_jacobiPlS_l, .-_Z13kernel_jacobiPlS_l
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kernel_jacobiPlS_l"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_jacobiPlS_l(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_jacobi.hip"
.globl _Z28__device_stub__kernel_jacobiPlS_l # -- Begin function _Z28__device_stub__kernel_jacobiPlS_l
.p2align 4, 0x90
.type _Z28__device_stub__kernel_jacobiPlS_l,@function
_Z28__device_stub__kernel_jacobiPlS_l: # @_Z28__device_stub__kernel_jacobiPlS_l
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kernel_jacobiPlS_l, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_jacobiPlS_l, .Lfunc_end0-_Z28__device_stub__kernel_jacobiPlS_l
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_jacobiPlS_l, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_jacobiPlS_l,@object # @_Z13kernel_jacobiPlS_l
.section .rodata,"a",@progbits
.globl _Z13kernel_jacobiPlS_l
.p2align 3, 0x0
_Z13kernel_jacobiPlS_l:
.quad _Z28__device_stub__kernel_jacobiPlS_l
.size _Z13kernel_jacobiPlS_l, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kernel_jacobiPlS_l"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_jacobiPlS_l
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_jacobiPlS_l
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(cudaSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(CUBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(CUDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(cudaGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
cudaStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(cudaSetDevice(0));
CUDA_CHECK(cudaStreamCreate(&stream));
CUDA_CHECK(cudaMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(cudaMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(cudaStreamSynchronize(stream));
CUDA_CHECK(cudaDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(cudaSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(cudaMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
cudaMemcpyDeviceToHost,
stream));
CUDA_CHECK(cudaStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(cudaSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(CUBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(CUDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(cudaGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
cudaStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(cudaSetDevice(0));
CUDA_CHECK(cudaStreamCreate(&stream));
CUDA_CHECK(cudaMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(cudaMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(cudaStreamSynchronize(stream));
CUDA_CHECK(cudaDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(cudaSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(cudaMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
cudaMemcpyDeviceToHost,
stream));
CUDA_CHECK(cudaStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} | .file "tmpxft_00064230_00000000-6_check_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "num devices: "
.LC2:
.string "running: reduce"
.LC4:
.string "DEBUG: x_h[0]: before: "
.LC5:
.string "DEBUG: x_h[0]: after: "
.LC10:
.string " avg wallclock: "
.LC11:
.string " ms"
.LC12:
.string " avg bandwidth: "
.LC13:
.string " GB/s"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
leaq .LC1(%rip), %rsi
leaq _ZSt4clog(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $0, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $100, %r15d
movq $0x000000000, 8(%rsp)
movl .LC3(%rip), %ebx
leaq _ZSt4clog(%rip), %r13
jmp .L4
.L15:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L16:
call _ZSt16__throw_bad_castv@PLT
.L10:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L11:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq 24(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
subl $1, %r15d
je .L12
.L4:
movq %r14, %rax
leaq 128(%r14), %rdx
.L5:
movl %ebx, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L5
movl $23, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm2, %xmm2
cvtss2sd (%r14), %xmm2
movsd %xmm2, 16(%rsp)
movapd %xmm2, %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L15
cmpb $0, 56(%r12)
je .L7
movzbl 67(%r12), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, 24(%rsp)
movl $23, %edx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L16
cmpb $0, 56(%r12)
je .L10
movzbl 67(%r12), %esi
jmp .L11
.L12:
movsd 8(%rsp), %xmm4
divsd .LC7(%rip), %xmm4
movq %xmm4, %rbx
movapd %xmm4, %xmm0
mulsd .LC8(%rip), %xmm0
movsd .LC9(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbp
leaq .LC10(%rip), %rsi
leaq _ZSt4clog(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1109917696
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC7:
.long 0
.long 1079574528
.align 8
.LC8:
.long -755914244
.long 1062232653
.align 8
.LC9:
.long -400107883
.long 1048653323
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(cudaSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(CUBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(CUDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(cudaGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
cudaStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(cudaSetDevice(0));
CUDA_CHECK(cudaStreamCreate(&stream));
CUDA_CHECK(cudaMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(cudaMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(cudaStreamSynchronize(stream));
CUDA_CHECK(cudaDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(cudaSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(cudaMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
cudaMemcpyDeviceToHost,
stream));
CUDA_CHECK(cudaStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(hipSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(HIPBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(HIPDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(hipGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
hipStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(hipSetDevice(0));
CUDA_CHECK(hipStreamCreate(&stream));
CUDA_CHECK(hipMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(hipMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(hipStreamSynchronize(stream));
CUDA_CHECK(hipDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(hipSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(hipMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
hipMemcpyDeviceToHost,
stream));
CUDA_CHECK(hipStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(hipSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(HIPBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(HIPDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(hipGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
hipStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(hipSetDevice(0));
CUDA_CHECK(hipStreamCreate(&stream));
CUDA_CHECK(hipMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(hipMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(hipStreamSynchronize(stream));
CUDA_CHECK(hipDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(hipSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(hipMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
hipMemcpyDeviceToHost,
stream));
CUDA_CHECK(hipStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <cublas_v2.h>
//#include <cublasXt.h>
//#include <cudnn.h>
//#include <nccl.h>
#include <cassert>
#include <chrono>
#include <iostream>
#define CUDA_CHECK(e) (assert(hipSuccess == (e)))
#define CUBLAS_CHECK(e) (assert(HIPBLAS_STATUS_SUCCESS == (e)))
#define CUDNN_CHECK(e) (assert(HIPDNN_STATUS_SUCCESS == (e)))
int main(int argc, const char** argv) {
int num_devices = 0;
CUDA_CHECK(hipGetDeviceCount(&num_devices));
std::clog << "num devices: " << num_devices << std::endl;
num_devices = 1;
const size_t buf_size = 32UL;
hipStream_t stream = NULL;
float* x_h = NULL;
float* x = NULL;
float* y = NULL;
x_h = (float*)malloc(buf_size * sizeof(float));
CUDA_CHECK(hipSetDevice(0));
CUDA_CHECK(hipStreamCreate(&stream));
CUDA_CHECK(hipMalloc((void**)&x, buf_size * sizeof(float)));
CUDA_CHECK(hipMalloc((void**)&y, buf_size * sizeof(float)));
CUDA_CHECK(hipStreamSynchronize(stream));
CUDA_CHECK(hipDeviceSynchronize());
const int num_trials = 100;
double avg_elapsed_ms = 0.0;
std::clog << "running: reduce" << std::endl;
for (int t = 0; t < num_trials; ++t) {
for (size_t i = 0; i < buf_size; ++i) {
x_h[i] = 42.0f;
}
std::clog << "DEBUG: x_h[0]: before: " << x_h[0] << std::endl;
auto start = std::chrono::steady_clock::now();
CUDA_CHECK(hipSetDevice(0));
//reduce<float, AtomicReduceMap><<<(buf_size+1024-1)/1024, 1024, 0, stream>>>(
// buf_size, x, y);
CUDA_CHECK(hipMemcpyAsync(
x_h,
x,
buf_size * sizeof(float),
hipMemcpyDeviceToHost,
stream));
CUDA_CHECK(hipStreamSynchronize(stream));
std::clog << "DEBUG: x_h[0]: after: " << x_h[0] << std::endl;
auto lap = std::chrono::steady_clock::now();
auto diff = lap - start;
avg_elapsed_ms += std::chrono::duration<double, std::milli>(diff).count();
}
avg_elapsed_ms /= num_trials;
double avg_bandwidth = ((double)(buf_size * sizeof(float)) * 1.0e-9) / (avg_elapsed_ms * 1.0e-3);
std::clog << " avg wallclock: " << avg_elapsed_ms << " ms" << std::endl;
std::clog << " avg bandwidth: " << avg_bandwidth << " GB/s" << std::endl;
return 0;
} | .text
.file "check_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x4059000000000000 # double 100
.LCPI0_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI0_3:
.quad 0x3e812e0be826d695 # double 1.2800000000000001E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4clog, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_29
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $_ZSt4clog, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4clog(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4clog+240(%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4clog, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorpd %xmm1, %xmm1
xorl %r12d, %r12d
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_9 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB0_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
# in Loop: Header=BB0_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
incl %r12d
cmpl $100, %r12d
je .LBB0_14
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movsd %xmm1, (%rsp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $1109917696, (%rbx,%rax,4) # imm = 0x42280000
incq %rax
cmpq $32, %rax
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $_ZSt4clog, %edi
movl $.L.str.2, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4clog, %edi
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_29
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB0_9 Depth=1
cmpb $0, 56(%r14)
je .LBB0_23
# %bb.13: # in Loop: Header=BB0_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_23: # in Loop: Header=BB0_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB0_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4clog, %edi
movl $.L.str.3, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_29
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
# in Loop: Header=BB0_9 Depth=1
cmpb $0, 56(%r15)
je .LBB0_27
# %bb.26: # in Loop: Header=BB0_9 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_28
.LBB0_14:
divsd .LCPI0_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $_ZSt4clog, %edi
movl $.L.str.4, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI0_2(%rip), %xmm1
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
je .LBB0_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB0_18
.LBB0_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4clog, %edi
movl $.L.str.6, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.7, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r14)
je .LBB0_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB0_22
.LBB0_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_29:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "num devices: "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "running: reduce"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "DEBUG: x_h[0]: before: "
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "DEBUG: x_h[0]: after: "
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " avg wallclock: "
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " ms"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " avg bandwidth: "
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " GB/s"
.size .L.str.7, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4clog
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00064230_00000000-6_check_mem.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3780:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3780:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "num devices: "
.LC2:
.string "running: reduce"
.LC4:
.string "DEBUG: x_h[0]: before: "
.LC5:
.string "DEBUG: x_h[0]: after: "
.LC10:
.string " avg wallclock: "
.LC11:
.string " ms"
.LC12:
.string " avg bandwidth: "
.LC13:
.string " GB/s"
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
leaq .LC1(%rip), %rsi
leaq _ZSt4clog(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $0, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r14
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $100, %r15d
movq $0x000000000, 8(%rsp)
movl .LC3(%rip), %ebx
leaq _ZSt4clog(%rip), %r13
jmp .L4
.L15:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L16:
call _ZSt16__throw_bad_castv@PLT
.L10:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L11:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq 24(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
subl $1, %r15d
je .L12
.L4:
movq %r14, %rax
leaq 128(%r14), %rdx
.L5:
movl %ebx, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L5
movl $23, %edx
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm2, %xmm2
cvtss2sd (%r14), %xmm2
movsd %xmm2, 16(%rsp)
movapd %xmm2, %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L15
cmpb $0, 56(%r12)
je .L7
movzbl 67(%r12), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, 24(%rsp)
movl $23, %edx
leaq .LC5(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 16(%rsp), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L16
cmpb $0, 56(%r12)
je .L10
movzbl 67(%r12), %esi
jmp .L11
.L12:
movsd 8(%rsp), %xmm4
divsd .LC7(%rip), %xmm4
movq %xmm4, %rbx
movapd %xmm4, %xmm0
mulsd .LC8(%rip), %xmm0
movsd .LC9(%rip), %xmm1
divsd %xmm0, %xmm1
movq %xmm1, %rbp
leaq .LC10(%rip), %rsi
leaq _ZSt4clog(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC11(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC12(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC13(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3768:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1109917696
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.align 8
.LC7:
.long 0
.long 1079574528
.align 8
.LC8:
.long -755914244
.long 1062232653
.align 8
.LC9:
.long -400107883
.long 1048653323
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "check_mem.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI0_1:
.quad 0x4059000000000000 # double 100
.LCPI0_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.LCPI0_3:
.quad 0x3e812e0be826d695 # double 1.2800000000000001E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $_ZSt4clog, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_29
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $128, %edi
callq malloc
movq %rax, %rbx
movl $_ZSt4clog, %edi
movl $.L.str.1, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4clog(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4clog+240(%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r14)
je .LBB0_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB0_8
.LBB0_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %al, %esi
movl $_ZSt4clog, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorpd %xmm1, %xmm1
xorl %r12d, %r12d
jmp .LBB0_9
.p2align 4, 0x90
.LBB0_27: # in Loop: Header=BB0_9 Depth=1
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB0_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
# in Loop: Header=BB0_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
subq %r14, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
incl %r12d
cmpl $100, %r12d
je .LBB0_14
.LBB0_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_10 Depth 2
movsd %xmm1, (%rsp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_10: # Parent Loop BB0_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $1109917696, (%rbx,%rax,4) # imm = 0x42280000
incq %rax
cmpq $32, %rax
jne .LBB0_10
# %bb.11: # in Loop: Header=BB0_9 Depth=1
movl $_ZSt4clog, %edi
movl $.L.str.2, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4clog, %edi
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB0_29
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
# in Loop: Header=BB0_9 Depth=1
cmpb $0, 56(%r14)
je .LBB0_23
# %bb.13: # in Loop: Header=BB0_9 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_23: # in Loop: Header=BB0_9 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB0_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
# in Loop: Header=BB0_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212steady_clock3nowEv
movq %rax, %r14
movl $_ZSt4clog, %edi
movl $.L.str.3, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_29
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
# in Loop: Header=BB0_9 Depth=1
cmpb $0, 56(%r15)
je .LBB0_27
# %bb.26: # in Loop: Header=BB0_9 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_28
.LBB0_14:
divsd .LCPI0_1(%rip), %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $_ZSt4clog, %edi
movl $.L.str.4, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.5, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
mulsd .LCPI0_2(%rip), %xmm1
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
cmpb $0, 56(%r14)
je .LBB0_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB0_18
.LBB0_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4clog, %edi
movl $.L.str.6, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4clog, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.7, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_29
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r14)
je .LBB0_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB0_22
.LBB0_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_29:
.cfi_def_cfa_offset 64
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "num devices: "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "running: reduce"
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "DEBUG: x_h[0]: before: "
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "DEBUG: x_h[0]: after: "
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " avg wallclock: "
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " ms"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " avg bandwidth: "
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " GB/s"
.size .L.str.7, 6
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4clog
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <cstdlib>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
int main(void)
{
using namespace std;
int DIM = 1 << 24;
thrust::host_vector<double> x_h(DIM);
cout << "CUDA-C (Thrust) version\n";
cout << "Filling vector with random doubles (on host).\n";
for(int i=0; i<DIM; i++)
{
x_h[i] = (double) (rand()) / (double) (RAND_MAX);
}
cout << "Done.\n";
cout << "Allocate device vector and copy array to device.\n";
thrust::device_vector<double> x_d = x_h;
cout << "Sorting random array with " << DIM << " double elements using std::sort..."<<"\n";
thrust::sort(x_d.begin(), x_d.end());
cout << "Done.\n";
cout << "Copy array to host.\n";
thrust::copy(x_d.begin(), x_d.end(), x_h.begin());
cout << "Done.\n";
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <cstdlib>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/sort.h>
int main(void)
{
using namespace std;
int DIM = 1 << 24;
thrust::host_vector<double> x_h(DIM);
cout << "CUDA-C (Thrust) version\n";
cout << "Filling vector with random doubles (on host).\n";
for(int i=0; i<DIM; i++)
{
x_h[i] = (double) (rand()) / (double) (RAND_MAX);
}
cout << "Done.\n";
cout << "Allocate device vector and copy array to device.\n";
thrust::device_vector<double> x_d = x_h;
cout << "Sorting random array with " << DIM << " double elements using std::sort..."<<"\n";
thrust::sort(x_d.begin(), x_d.end());
cout << "Done.\n";
cout << "Copy array to host.\n";
thrust::copy(x_d.begin(), x_d.end(), x_h.begin());
cout << "Done.\n";
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
cudaMalloc((void**)&da_in, sizeof(double)*gSize);
cudaMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
cudaMemcpy(da_in, a_in, sizeof(double)*gSize, cudaMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
cudaMemcpy(a_out, da_out, sizeof(double)*gSize, cudaMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} | code for sm_80
Function : _Z16simple_transposePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R4 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4copyPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0090*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
cudaMalloc((void**)&da_in, sizeof(double)*gSize);
cudaMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
cudaMemcpy(da_in, a_in, sizeof(double)*gSize, cudaMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
cudaMemcpy(a_out, da_out, sizeof(double)*gSize, cudaMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} | .file "tmpxft_001827dc_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9transposePdS_ii
.type _Z9transposePdS_ii, @function
_Z9transposePdS_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r11
movl %edx, %ebx
movslq %edx, %r8
salq $3, %r8
movl $0, %r10d
movl $0, %r9d
movslq %ecx, %rbp
jmp .L5
.L7:
movslq %r10d, %rdx
leaq (%r11,%rdx,8), %rax
addq %rbp, %rdx
leaq (%r11,%rdx,8), %rsi
movq %rdi, %rdx
.L6:
movsd (%rdx), %xmm0
movsd %xmm0, (%rax)
addq %r8, %rdx
addq $8, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %r9d
addq $8, %rdi
addl %ecx, %r10d
cmpl %r9d, %ebx
je .L3
.L5:
testl %ecx, %ecx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z9transposePdS_ii, .-_Z9transposePdS_ii
.globl _Z11print_arrayPdii
.type _Z11print_arrayPdii, @function
_Z11print_arrayPdii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
testl %esi, %esi
jle .L14
movl %edx, %r12d
movl $0, (%rsp)
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
jmp .L16
.L18:
movl $9, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
.L17:
addq $1, %rbx
cmpq %r14, %rbx
je .L24
.L20:
movsd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leal -1(%r12), %eax
cmpl %ebx, %eax
je .L17
movb $9, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L18
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L17
.L24:
movb $10, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L21
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L22:
addl $1, %r15d
addl %r12d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L14
.L16:
testl %r12d, %r12d
jle .L24
movslq %r12d, %r14
movslq (%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,8), %r13
movl $0, %ebx
jmp .L20
.L21:
movl $10, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L22
.L14:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11print_arrayPdii, .-_Z11print_arrayPdii
.globl _Z25__device_stub__Z4copyPdS_PdS_
.type _Z25__device_stub__Z4copyPdS_PdS_, @function
_Z25__device_stub__Z4copyPdS_PdS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z25__device_stub__Z4copyPdS_PdS_, .-_Z25__device_stub__Z4copyPdS_PdS_
.globl _Z4copyPdS_
.type _Z4copyPdS_, @function
_Z4copyPdS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4copyPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z4copyPdS_, .-_Z4copyPdS_
.globl _Z38__device_stub__Z16simple_transposePdS_PdS_
.type _Z38__device_stub__Z16simple_transposePdS_PdS_, @function
_Z38__device_stub__Z16simple_transposePdS_PdS_:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16simple_transposePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z38__device_stub__Z16simple_transposePdS_PdS_, .-_Z38__device_stub__Z16simple_transposePdS_PdS_
.globl _Z16simple_transposePdS_
.type _Z16simple_transposePdS_, @function
_Z16simple_transposePdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16simple_transposePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16simple_transposePdS_, .-_Z16simple_transposePdS_
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $512, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $64, %rax
jne .L46
movl $1, %ecx
movl $512, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11print_arrayPdii
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
call _Z11print_arrayPdii
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z16simple_transposePdS_PdS_
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16simple_transposePdS_"
.LC1:
.string "_Z4copyPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16simple_transposePdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
cudaMalloc((void**)&da_in, sizeof(double)*gSize);
cudaMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
cudaMemcpy(da_in, a_in, sizeof(double)*gSize, cudaMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
cudaMemcpy(a_out, da_out, sizeof(double)*gSize, cudaMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} | #include <hip/hip_runtime.h>
#include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
hipMalloc((void**)&da_in, sizeof(double)*gSize);
hipMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
hipMemcpy(da_in, a_in, sizeof(double)*gSize, hipMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
hipMemcpy(a_out, da_out, sizeof(double)*gSize, hipMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
hipMalloc((void**)&da_in, sizeof(double)*gSize);
hipMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
hipMemcpy(da_in, a_in, sizeof(double)*gSize, hipMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
hipMemcpy(a_out, da_out, sizeof(double)*gSize, hipMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPdS_
.globl _Z4copyPdS_
.p2align 8
.type _Z4copyPdS_,@function
_Z4copyPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPdS_, .Lfunc_end0-_Z4copyPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16simple_transposePdS_
.globl _Z16simple_transposePdS_
.p2align 8
.type _Z16simple_transposePdS_,@function
_Z16simple_transposePdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v1, v0, s4, s15
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16simple_transposePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16simple_transposePdS_, .Lfunc_end1-_Z16simple_transposePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16simple_transposePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16simple_transposePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
__global__ void copy(double* a_in, double *a_out){
int gid = blockIdx.x*blockDim.x + threadIdx.x;
a_out[gid] = a_in[gid];
}
__global__ void simple_transpose(double* a_in, double *a_out){
int gid_in = blockIdx.x*blockDim.x + threadIdx.x;
int gid_out = threadIdx.x*blockDim.x + blockIdx.x;
a_out[gid_in] = a_in[gid_out];
}
void transpose(double* a_in, double*a_out, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index_in = j + i*yDim;
int index_out = i + j*xDim;
a_out[index_in] = a_in[index_out];
}
}
}
void print_array(double *a, int xDim, int yDim){
for (int i = 0; i < xDim; ++i){
for (int j = 0; j < yDim; ++j){
int index = j + i*yDim;
std::cout << a[index];
if (j != yDim - 1){
std::cout << '\t';
}
}
std::cout << '\n';
}
}
int main(){
double *a_in, *a_out;
double *da_in, *da_out;
unsigned int xDim = 8;
unsigned int yDim = 8;
unsigned int gSize = xDim*yDim;
dim3 grid = {yDim, 1, 1};
dim3 threads = {xDim, 1, 1};
a_in = (double *)malloc(sizeof(double)*gSize);
a_out = (double *)malloc(sizeof(double)*gSize);
hipMalloc((void**)&da_in, sizeof(double)*gSize);
hipMalloc((void**)&da_out, sizeof(double)*gSize);
for (int i = 0; i < gSize; ++i){
a_in[i] = i;
}
hipMemcpy(da_in, a_in, sizeof(double)*gSize, hipMemcpyHostToDevice);
print_array(a_in, xDim, yDim);
std::cout << '\n';
//transpose(a_in, a_out, xDim, yDim);
simple_transpose<<<grid, threads>>>(da_in, da_out);
hipMemcpy(a_out, da_out, sizeof(double)*gSize, hipMemcpyDeviceToHost);
print_array(a_out, xDim, yDim);
} | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__copyPdS_ # -- Begin function _Z19__device_stub__copyPdS_
.p2align 4, 0x90
.type _Z19__device_stub__copyPdS_,@function
_Z19__device_stub__copyPdS_: # @_Z19__device_stub__copyPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4copyPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPdS_, .Lfunc_end0-_Z19__device_stub__copyPdS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__simple_transposePdS_ # -- Begin function _Z31__device_stub__simple_transposePdS_
.p2align 4, 0x90
.type _Z31__device_stub__simple_transposePdS_,@function
_Z31__device_stub__simple_transposePdS_: # @_Z31__device_stub__simple_transposePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16simple_transposePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__simple_transposePdS_, .Lfunc_end1-_Z31__device_stub__simple_transposePdS_
.cfi_endproc
# -- End function
.globl _Z9transposePdS_ii # -- Begin function _Z9transposePdS_ii
.p2align 4, 0x90
.type _Z9transposePdS_ii,@function
_Z9transposePdS_ii: # @_Z9transposePdS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %eax
movl %ecx, %edx
leaq (,%rax,8), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
addq $8, %rdi
cmpq %rax, %r10
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ecx, %ecx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r9d, %r11d
leaq (%rsi,%r11,8), %r11
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11,%r14,8)
incq %r14
addq %r8, %rbx
cmpq %r14, %rdx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_7: # %._crit_edge20
retq
.Lfunc_end2:
.size _Z9transposePdS_ii, .Lfunc_end2-_Z9transposePdS_ii
.cfi_endproc
# -- End function
.globl _Z11print_arrayPdii # -- Begin function _Z11print_arrayPdii
.p2align 4, 0x90
.type _Z11print_arrayPdii,@function
_Z11print_arrayPdii: # @_Z11print_arrayPdii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_11
# %bb.1: # %.preheader.lr.ph
leal -1(%rdx), %r13d
movl %esi, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r14d, %r14d
xorl %ebp, %ebp
movq %rdx, 32(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movb $10, 14(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 14(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB3_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB3_2 Depth=1
incq %rbp
movq 32(%rsp), %rdx # 8-byte Reload
addl %edx, %r14d
cmpq 24(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_11
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %edx, %edx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r15d, %r15d
jmp .LBB3_4
.LBB3_12: # in Loop: Header=BB3_4 Depth=2
movl $_ZSt4cout, %edi
movl $9, %esi
callq _ZNSo3putEc
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_4 Depth=2
incq %r15
cmpq %r15, %r12
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
cmpq %r15, %r13
je .LBB3_13
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movb $9, 15(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB3_12
# %bb.6: # in Loop: Header=BB3_4 Depth=2
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 15(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB3_10
.LBB3_11: # %._crit_edge20
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11print_arrayPdii, .Lfunc_end3-_Z11print_arrayPdii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $64, %rax
jne .LBB4_1
# %bb.2:
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $8, %esi
movl $8, %edx
callq _Z11print_arrayPdii
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB4_4
# %bb.3:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_5
.LBB4_4:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB4_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16simple_transposePdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $8, %esi
movl $8, %edx
callq _Z11print_arrayPdii
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16simple_transposePdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPdS_,@object # @_Z4copyPdS_
.section .rodata,"a",@progbits
.globl _Z4copyPdS_
.p2align 3, 0x0
_Z4copyPdS_:
.quad _Z19__device_stub__copyPdS_
.size _Z4copyPdS_, 8
.type _Z16simple_transposePdS_,@object # @_Z16simple_transposePdS_
.globl _Z16simple_transposePdS_
.p2align 3, 0x0
_Z16simple_transposePdS_:
.quad _Z31__device_stub__simple_transposePdS_
.size _Z16simple_transposePdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPdS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16simple_transposePdS_"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPdS_
.addrsig_sym _Z31__device_stub__simple_transposePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPdS_
.addrsig_sym _Z16simple_transposePdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16simple_transposePdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R5, c[0x0][0x0], R4 ; /* 0x0000000005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z4copyPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0090*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPdS_
.globl _Z4copyPdS_
.p2align 8
.type _Z4copyPdS_,@function
_Z4copyPdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPdS_, .Lfunc_end0-_Z4copyPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16simple_transposePdS_
.globl _Z16simple_transposePdS_
.p2align 8
.type _Z16simple_transposePdS_,@function
_Z16simple_transposePdS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u32_u24 v1, v0, s4, s15
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16simple_transposePdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16simple_transposePdS_, .Lfunc_end1-_Z16simple_transposePdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4copyPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
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.size: 8
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.size: 4
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.size: 4
.value_kind: hidden_block_count_z
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.size: 2
.value_kind: hidden_group_size_x
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.size: 2
.value_kind: hidden_group_size_y
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.size: 2
.value_kind: hidden_group_size_z
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.size: 2
.value_kind: hidden_remainder_x
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.size: 2
.value_kind: hidden_remainder_z
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.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16simple_transposePdS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16simple_transposePdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001827dc_00000000-6_transpose.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9transposePdS_ii
.type _Z9transposePdS_ii, @function
_Z9transposePdS_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rsi, %r11
movl %edx, %ebx
movslq %edx, %r8
salq $3, %r8
movl $0, %r10d
movl $0, %r9d
movslq %ecx, %rbp
jmp .L5
.L7:
movslq %r10d, %rdx
leaq (%r11,%rdx,8), %rax
addq %rbp, %rdx
leaq (%r11,%rdx,8), %rsi
movq %rdi, %rdx
.L6:
movsd (%rdx), %xmm0
movsd %xmm0, (%rax)
addq %r8, %rdx
addq $8, %rax
cmpq %rsi, %rax
jne .L6
.L8:
addl $1, %r9d
addq $8, %rdi
addl %ecx, %r10d
cmpl %r9d, %ebx
je .L3
.L5:
testl %ecx, %ecx
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z9transposePdS_ii, .-_Z9transposePdS_ii
.globl _Z11print_arrayPdii
.type _Z11print_arrayPdii, @function
_Z11print_arrayPdii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
testl %esi, %esi
jle .L14
movl %edx, %r12d
movl $0, (%rsp)
movl $0, %r15d
leaq _ZSt4cout(%rip), %rbp
jmp .L16
.L18:
movl $9, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
.L17:
addq $1, %rbx
cmpq %r14, %rbx
je .L24
.L20:
movsd 0(%r13,%rbx,8), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
leal -1(%r12), %eax
cmpl %ebx, %eax
je .L17
movb $9, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L18
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L17
.L24:
movb $10, 23(%rsp)
movq 0(%rbp), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rbp,%rax)
je .L21
leaq 23(%rsp), %rsi
movl $1, %edx
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L22:
addl $1, %r15d
addl %r12d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L14
.L16:
testl %r12d, %r12d
jle .L24
movslq %r12d, %r14
movslq (%rsp), %rax
movq 8(%rsp), %rcx
leaq (%rcx,%rax,8), %r13
movl $0, %ebx
jmp .L20
.L21:
movl $10, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L22
.L14:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11print_arrayPdii, .-_Z11print_arrayPdii
.globl _Z25__device_stub__Z4copyPdS_PdS_
.type _Z25__device_stub__Z4copyPdS_PdS_, @function
_Z25__device_stub__Z4copyPdS_PdS_:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z25__device_stub__Z4copyPdS_PdS_, .-_Z25__device_stub__Z4copyPdS_PdS_
.globl _Z4copyPdS_
.type _Z4copyPdS_, @function
_Z4copyPdS_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4copyPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z4copyPdS_, .-_Z4copyPdS_
.globl _Z38__device_stub__Z16simple_transposePdS_PdS_
.type _Z38__device_stub__Z16simple_transposePdS_PdS_, @function
_Z38__device_stub__Z16simple_transposePdS_PdS_:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16simple_transposePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z38__device_stub__Z16simple_transposePdS_PdS_, .-_Z38__device_stub__Z16simple_transposePdS_PdS_
.globl _Z16simple_transposePdS_
.type _Z16simple_transposePdS_, @function
_Z16simple_transposePdS_:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z16simple_transposePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16simple_transposePdS_, .-_Z16simple_transposePdS_
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $8, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $8, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $512, %edi
call malloc@PLT
movq %rax, %rbx
movl $512, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $64, %rax
jne .L46
movl $1, %ecx
movl $512, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbx, %rdi
call _Z11print_arrayPdii
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $8, %edx
movl $8, %esi
movq %rbp, %rdi
call _Z11print_arrayPdii
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z38__device_stub__Z16simple_transposePdS_PdS_
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16simple_transposePdS_"
.LC1:
.string "_Z4copyPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16simple_transposePdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__copyPdS_ # -- Begin function _Z19__device_stub__copyPdS_
.p2align 4, 0x90
.type _Z19__device_stub__copyPdS_,@function
_Z19__device_stub__copyPdS_: # @_Z19__device_stub__copyPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4copyPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPdS_, .Lfunc_end0-_Z19__device_stub__copyPdS_
.cfi_endproc
# -- End function
.globl _Z31__device_stub__simple_transposePdS_ # -- Begin function _Z31__device_stub__simple_transposePdS_
.p2align 4, 0x90
.type _Z31__device_stub__simple_transposePdS_,@function
_Z31__device_stub__simple_transposePdS_: # @_Z31__device_stub__simple_transposePdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16simple_transposePdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z31__device_stub__simple_transposePdS_, .Lfunc_end1-_Z31__device_stub__simple_transposePdS_
.cfi_endproc
# -- End function
.globl _Z9transposePdS_ii # -- Begin function _Z9transposePdS_ii
.p2align 4, 0x90
.type _Z9transposePdS_ii,@function
_Z9transposePdS_ii: # @_Z9transposePdS_ii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edx, %eax
movl %ecx, %edx
leaq (,%rax,8), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r10
addl %ecx, %r9d
addq $8, %rdi
cmpq %rax, %r10
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ecx, %ecx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r9d, %r11d
leaq (%rsi,%r11,8), %r11
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, (%r11,%r14,8)
incq %r14
addq %r8, %rbx
cmpq %r14, %rdx
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB2_7: # %._crit_edge20
retq
.Lfunc_end2:
.size _Z9transposePdS_ii, .Lfunc_end2-_Z9transposePdS_ii
.cfi_endproc
# -- End function
.globl _Z11print_arrayPdii # -- Begin function _Z11print_arrayPdii
.p2align 4, 0x90
.type _Z11print_arrayPdii,@function
_Z11print_arrayPdii: # @_Z11print_arrayPdii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdi, 16(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_11
# %bb.1: # %.preheader.lr.ph
leal -1(%rdx), %r13d
movl %esi, %eax
movq %rax, 24(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r14d, %r14d
xorl %ebp, %ebp
movq %rdx, 32(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movb $10, 14(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 14(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB3_10: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
# in Loop: Header=BB3_2 Depth=1
incq %rbp
movq 32(%rsp), %rdx # 8-byte Reload
addl %edx, %r14d
cmpq 24(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_11
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %edx, %edx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r14d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %rbx
xorl %r15d, %r15d
jmp .LBB3_4
.LBB3_12: # in Loop: Header=BB3_4 Depth=2
movl $_ZSt4cout, %edi
movl $9, %esi
callq _ZNSo3putEc
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_4 Depth=2
incq %r15
cmpq %r15, %r12
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%r15,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
cmpq %r15, %r13
je .LBB3_13
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movb $9, 15(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB3_12
# %bb.6: # in Loop: Header=BB3_4 Depth=2
movl $_ZSt4cout, %edi
movl $1, %edx
leaq 15(%rsp), %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB3_10
.LBB3_11: # %._crit_edge20
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z11print_arrayPdii, .Lfunc_end3-_Z11print_arrayPdii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %r14
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $64, %rax
jne .LBB4_1
# %bb.2:
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $8, %esi
movl $8, %edx
callq _Z11print_arrayPdii
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB4_4
# %bb.3:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB4_5
.LBB4_4:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB4_5: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16simple_transposePdS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $8, %esi
movl $8, %edx
callq _Z11print_arrayPdii
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16simple_transposePdS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPdS_,@object # @_Z4copyPdS_
.section .rodata,"a",@progbits
.globl _Z4copyPdS_
.p2align 3, 0x0
_Z4copyPdS_:
.quad _Z19__device_stub__copyPdS_
.size _Z4copyPdS_, 8
.type _Z16simple_transposePdS_,@object # @_Z16simple_transposePdS_
.globl _Z16simple_transposePdS_
.p2align 3, 0x0
_Z16simple_transposePdS_:
.quad _Z31__device_stub__simple_transposePdS_
.size _Z16simple_transposePdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4copyPdS_"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16simple_transposePdS_"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPdS_
.addrsig_sym _Z31__device_stub__simple_transposePdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4copyPdS_
.addrsig_sym _Z16simple_transposePdS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
cudaHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), cudaHostAllocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
cudaMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
cudaMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), cudaMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
cudaMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} | code for sm_80
Function : _Z11timestepGPUP8Particleif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R6, [R2.64+0x14] ; /* 0x0000140402067981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000f68000c1e1900 */
/*00e0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f62000c1e1900 */
/*00f0*/ FMUL R5, R0, c[0x0][0x16c] ; /* 0x00005b0000057a20 */
/* 0x004fc40000400000 */
/*0100*/ FMUL R7, R4, c[0x0][0x16c] ; /* 0x00005b0004077a20 */
/* 0x008fc60000400000 */
/*0110*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe2000c101904 */
/*0120*/ FMUL R9, R6, c[0x0][0x16c] ; /* 0x00005b0006097a20 */
/* 0x010fc60000400000 */
/*0130*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x000fe2000c101904 */
/*0140*/ FADD R11, R5, R8 ; /* 0x00000008050b7221 */
/* 0x020fc60000000000 */
/*0150*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe2000c101904 */
/*0160*/ FADD R13, R7, R10 ; /* 0x0000000a070d7221 */
/* 0x000fc60000000000 */
/*0170*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0180*/ FADD R15, R9, R12 ; /* 0x0000000c090f7221 */
/* 0x000fc60000000000 */
/*0190*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
cudaHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), cudaHostAllocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
cudaMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
cudaMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), cudaMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
cudaMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} | .file "tmpxft_000c2d96_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11timestepCPUP8Particle
.type _Z11timestepCPUP8Particle, @function
_Z11timestepCPUP8Particle:
.LFB2057:
.cfi_startproc
endbr64
cmpl $0, MAX_PARTICLES(%rip)
jle .L3
movl $0, %eax
.L5:
movss DEC_FACTOR(%rip), %xmm0
movaps %xmm0, %xmm2
mulss 12(%rdi), %xmm2
movss %xmm2, 12(%rdi)
movaps %xmm0, %xmm1
mulss 16(%rdi), %xmm1
movss %xmm1, 16(%rdi)
mulss 20(%rdi), %xmm0
movss %xmm0, 20(%rdi)
addss (%rdi), %xmm2
movss %xmm2, (%rdi)
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
addl $1, %eax
addq $24, %rdi
cmpl %eax, MAX_PARTICLES(%rip)
jg .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11timestepCPUP8Particle, .-_Z11timestepCPUP8Particle
.globl _Z7compareP8ParticleS0_
.type _Z7compareP8ParticleS0_, @function
_Z7compareP8ParticleS0_:
.LFB2058:
.cfi_startproc
endbr64
movl MAX_PARTICLES(%rip), %r8d
testl %r8d, %r8d
jle .L11
movss TOLERANCE(%rip), %xmm0
movl $0, %edx
.L9:
movss (%rdi), %xmm1
subss (%rsi), %xmm1
comiss %xmm1, %xmm0
seta %al
movss 4(%rdi), %xmm1
subss 4(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 8(%rdi), %xmm1
subss 8(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 12(%rdi), %xmm1
subss 12(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 16(%rdi), %xmm1
subss 16(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 20(%rdi), %xmm1
subss 20(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
addl $1, %edx
addq $24, %rdi
addq $24, %rsi
cmpl %r8d, %edx
jge .L12
testb %al, %al
jne .L9
.L12:
movzbl %al, %eax
ret
.L11:
movl $1, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z7compareP8ParticleS0_, .-_Z7compareP8ParticleS0_
.globl _Z9initArrayP8Particle
.type _Z9initArrayP8Particle, @function
_Z9initArrayP8Particle:
.LFB2059:
.cfi_startproc
endbr64
cmpl $0, MAX_PARTICLES(%rip)
jle .L19
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl $0, %ebp
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 20(%rbx)
addl $1, %ebp
addq $24, %rbx
cmpl %ebp, MAX_PARTICLES(%rip)
jg .L16
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z9initArrayP8Particle, .-_Z9initArrayP8Particle
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z13setParametersiPPc
.type _Z13setParametersiPPc, @function
_Z13setParametersiPPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $4, %edi
je .L27
jg .L28
cmpl $2, %edi
je .L29
cmpl $3, %edi
je .L30
.L31:
movl $100000, MAX_PARTICLES(%rip)
movl $100, NUM_ITERATIONS(%rip)
movl $256, TPB(%rip)
movl $0x3f666666, DEC_FACTOR(%rip)
jmp .L26
.L28:
cmpl $5, %edi
jne .L31
movq 32(%rsi), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, DEC_FACTOR(%rip)
.L27:
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, TPB(%rip)
.L30:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, NUM_ITERATIONS(%rip)
.L29:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, MAX_PARTICLES(%rip)
.L26:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z13setParametersiPPc, .-_Z13setParametersiPPc
.globl _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
.type _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif, @function
_Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11timestepGPUP8Particleif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif, .-_Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
.globl _Z11timestepGPUP8Particleif
.type _Z11timestepGPUP8Particleif, @function
_Z11timestepGPUP8Particleif:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11timestepGPUP8Particleif, .-_Z11timestepGPUP8Particleif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nSize of the array: %d\nTPB: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time: %2f\nGPU time: %2f\n"
.LC5:
.string "Differences between arrays\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z13setParametersiPPc
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, %rdi
call _Z9initArrayP8Particle
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call memcpy@PLT
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rsi
salq $3, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
cmpl $0, NUM_ITERATIONS(%rip)
jle .L43
movl $0, %ebx
.L44:
movq %rbp, %rdi
call _Z11timestepCPUP8Particle
addl $1, %ebx
cmpl %ebx, NUM_ITERATIONS(%rip)
jg .L44
.L43:
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movq %xmm0, %r12
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
cmpl $0, NUM_ITERATIONS(%rip)
jle .L45
movl $0, %ebx
jmp .L47
.L46:
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %ebx, NUM_ITERATIONS(%rip)
jle .L45
.L47:
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl TPB(%rip), %ecx
movl %ecx, 44(%rsp)
movl $1, 48(%rsp)
movl %ecx, %eax
addl MAX_PARTICLES(%rip), %eax
subl $1, %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movss DEC_FACTOR(%rip), %xmm0
movl MAX_PARTICLES(%rip), %esi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
jmp .L46
.L45:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movq %xmm0, %rbx
movl TPB(%rip), %ecx
movl MAX_PARTICLES(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %xmm1
movq %r12, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq 16(%rsp), %rdi
call _Z7compareP8ParticleS0_
testl %eax, %eax
je .L53
.L48:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L48
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11timestepGPUP8Particleif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11timestepGPUP8Particleif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl TOLERANCE
.data
.align 4
.type TOLERANCE, @object
.size TOLERANCE, 4
TOLERANCE:
.long 897988541
.globl DEC_FACTOR
.bss
.align 4
.type DEC_FACTOR, @object
.size DEC_FACTOR, 4
DEC_FACTOR:
.zero 4
.globl TPB
.align 4
.type TPB, @object
.size TPB, 4
TPB:
.zero 4
.globl NUM_ITERATIONS
.align 4
.type NUM_ITERATIONS, @object
.size NUM_ITERATIONS, 4
NUM_ITERATIONS:
.zero 4
.globl MAX_PARTICLES
.align 4
.type MAX_PARTICLES, @object
.size MAX_PARTICLES, 4
MAX_PARTICLES:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
cudaHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), cudaHostAllocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
cudaMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
cudaMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), cudaMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
cudaMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), cudaMemcpyDeviceToHost);
}
cudaDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
hipHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), hipHostMallocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
hipMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
hipMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), hipMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
hipMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
hipHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), hipHostMallocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
hipMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
hipMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), hipMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
hipMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11timestepGPUP8Particleif
.globl _Z11timestepGPUP8Particleif
.p2align 8
.type _Z11timestepGPUP8Particleif,@function
_Z11timestepGPUP8Particleif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 24, s[2:3]
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(1)
v_fma_f32 v0, s0, v3, v0
s_waitcnt vmcnt(0)
v_fma_f32 v1, s0, v6, v1
v_fmac_f32_e32 v2, s0, v7
v_dual_mul_f32 v3, s0, v3 :: v_dual_mul_f32 v6, s0, v6
v_mul_f32_e32 v7, s0, v7
s_clause 0x1
global_store_b64 v[4:5], v[6:7], off offset:16
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11timestepGPUP8Particleif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11timestepGPUP8Particleif, .Lfunc_end0-_Z11timestepGPUP8Particleif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11timestepGPUP8Particleif
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11timestepGPUP8Particleif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
int MAX_PARTICLES;
int NUM_ITERATIONS;
int TPB;
float DEC_FACTOR;
float TOLERANCE = 1e-6;
typedef struct {
float3 position;
float3 velocity;
} Particle;
__global__ void timestepGPU(Particle* array, int nPart, float dec_fact)
{
int myId = blockIdx.x * blockDim.x + threadIdx.x;
if (myId < nPart)
{
array[myId].velocity.x = array[myId].velocity.x * dec_fact;
array[myId].velocity.y = array[myId].velocity.y * dec_fact;
array[myId].velocity.z = array[myId].velocity.z * dec_fact;
array[myId].position.x = array[myId].position.x + array[myId].velocity.x;
array[myId].position.y = array[myId].position.y + array[myId].velocity.y;
array[myId].position.z = array[myId].position.z + array[myId].velocity.z;
}
}
void timestepCPU(Particle* array)
{
for (int i = 0; i < MAX_PARTICLES; i++)
{
array[i].velocity.x = array[i].velocity.x * DEC_FACTOR;
array[i].velocity.y = array[i].velocity.y * DEC_FACTOR;
array[i].velocity.z = array[i].velocity.z * DEC_FACTOR;
array[i].position.x = array[i].position.x + array[i].velocity.x;
array[i].position.y = array[i].position.y + array[i].velocity.y;
array[i].position.z = array[i].position.z + array[i].velocity.z;
}
}
int compare(Particle* x, Particle* y)
{
int value = 1;
for(int i = 0; i < MAX_PARTICLES && value; i++)
{
value = value & (x[i].position.x - y[i].position.x < TOLERANCE);
value = value & (x[i].position.y - y[i].position.y < TOLERANCE);
value = value & (x[i].position.z - y[i].position.z < TOLERANCE);
value = value & (x[i].velocity.x - y[i].velocity.x < TOLERANCE);
value = value & (x[i].velocity.y - y[i].velocity.y < TOLERANCE);
value = value & (x[i].velocity.z - y[i].velocity.z < TOLERANCE);
}
return value;
}
void initArray(Particle* p)
{
for(int i = 0; i < MAX_PARTICLES; i++)
{
p[i].position.x = (float) rand() / RAND_MAX;
p[i].position.y = (float) rand() / RAND_MAX;
p[i].position.z = (float) rand() / RAND_MAX;
p[i].velocity.x = (float) rand() / RAND_MAX;
p[i].velocity.y = (float) rand() / RAND_MAX;
p[i].velocity.z = (float) rand() / RAND_MAX;
}
}
double cpuSecond() {
struct timeval tp;
gettimeofday(&tp,NULL);
return ((double)tp.tv_sec + (double)tp.tv_usec*1.e-6);
}
void setParameters(int argc, char** argv)
{
switch (argc)
{
case 5: DEC_FACTOR = atof(argv[4]);
case 4: TPB = atoi(argv[3]);
case 3: NUM_ITERATIONS = atoi(argv[2]);
case 2: MAX_PARTICLES = atoi(argv[1]); break;
default: MAX_PARTICLES = 100000; NUM_ITERATIONS = 100; TPB = 256; DEC_FACTOR = 0.9; break;
}
}
int main(int argc, char **argv)
{
setParameters(argc, argv);
//Input parametres:
//[1] : Number of particles
//[2] : Number of iterations
//[3] : Decreasing factor of velocity (optional)
double iStart, iElapsCPU, iElapsGPU;
//Initialization of pointers
Particle* pOriginal = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
initArray(pOriginal);
Particle* pCPU = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
memcpy(pCPU, pOriginal, MAX_PARTICLES * sizeof(Particle));
//Particle* pForeign = (Particle*) malloc(MAX_PARTICLES * sizeof(Particle));
Particle* pForeign;
hipHostAlloc(&pForeign, MAX_PARTICLES * sizeof(Particle), hipHostMallocDefault);
memcpy(pForeign, pOriginal, MAX_PARTICLES * sizeof(Particle));
Particle* pGPU;
hipMalloc(&pGPU, MAX_PARTICLES * sizeof(Particle));
//Computing by CPU
//printf("Computing by CPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
timestepCPU(pCPU);
}
iElapsCPU = cpuSecond() - iStart;
//printf("Done\n");
//Computing by GPU
//printf("Computing by GPU... ");
iStart = cpuSecond();
for (int i = 0; i < NUM_ITERATIONS; i++)
{
//Moving data to the device
hipMemcpy(pGPU, pForeign, MAX_PARTICLES * sizeof(Particle), hipMemcpyHostToDevice);
timestepGPU<<<(MAX_PARTICLES + TPB - 1)/TPB, TPB>>>(pGPU, MAX_PARTICLES, DEC_FACTOR);
hipMemcpy(pForeign, pGPU, MAX_PARTICLES*sizeof(Particle), hipMemcpyDeviceToHost);
}
hipDeviceSynchronize();
iElapsGPU = cpuSecond() - iStart;
//printf("Done\n");
//Sum up
printf("\nSize of the array: %d\nTPB: %d\n", MAX_PARTICLES, TPB);
printf("CPU time: %2f\nGPU time: %2f\n", iElapsCPU, iElapsGPU);
int comp = compare(pForeign, pCPU);
if (comp)
{
//printf("Both arrays are equal\n");
}
else
{
printf("Differences between arrays\n");
}
return 0;
} | .text
.file "exercise_2a.hip"
.globl _Z26__device_stub__timestepGPUP8Particleif # -- Begin function _Z26__device_stub__timestepGPUP8Particleif
.p2align 4, 0x90
.type _Z26__device_stub__timestepGPUP8Particleif,@function
_Z26__device_stub__timestepGPUP8Particleif: # @_Z26__device_stub__timestepGPUP8Particleif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11timestepGPUP8Particleif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__timestepGPUP8Particleif, .Lfunc_end0-_Z26__device_stub__timestepGPUP8Particleif
.cfi_endproc
# -- End function
.globl _Z11timestepCPUP8Particle # -- Begin function _Z11timestepCPUP8Particle
.p2align 4, 0x90
.type _Z11timestepCPUP8Particle,@function
_Z11timestepCPUP8Particle: # @_Z11timestepCPUP8Particle
.cfi_startproc
# %bb.0:
cmpl $0, MAX_PARTICLES(%rip)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
addq $20, %rdi
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss -8(%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss DEC_FACTOR(%rip), %xmm0
movss -4(%rdi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm0, -8(%rdi)
mulss DEC_FACTOR(%rip), %xmm1
movss %xmm1, -4(%rdi)
movss (%rdi), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss DEC_FACTOR(%rip), %xmm2
movss %xmm2, (%rdi)
addss -20(%rdi), %xmm0
movss %xmm0, -20(%rdi)
addss -16(%rdi), %xmm1
movss %xmm1, -16(%rdi)
addss -12(%rdi), %xmm2
movss %xmm2, -12(%rdi)
incq %rax
movslq MAX_PARTICLES(%rip), %rcx
addq $24, %rdi
cmpq %rcx, %rax
jl .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11timestepCPUP8Particle, .Lfunc_end1-_Z11timestepCPUP8Particle
.cfi_endproc
# -- End function
.globl _Z7compareP8ParticleS0_ # -- Begin function _Z7compareP8ParticleS0_
.p2align 4, 0x90
.type _Z7compareP8ParticleS0_,@function
_Z7compareP8ParticleS0_: # @_Z7compareP8ParticleS0_
.cfi_startproc
# %bb.0:
movl MAX_PARTICLES(%rip), %eax
testl %eax, %eax
jle .LBB2_1
# %bb.4: # %.lr.ph
movl $20, %ecx
movl $1, %edx
movss TOLERANCE(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss -12(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -12(%rsi,%rcx), %xmm1
movss -20(%rdi,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss -16(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -20(%rsi,%rcx), %xmm2
subss -16(%rsi,%rcx), %xmm1
cmpltps %xmm0, %xmm1
cmpltps %xmm0, %xmm2
seta %r8b
andps %xmm1, %xmm2
movss -8(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -8(%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r9b
andb %r8b, %r9b
movss -4(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -4(%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r10b
movd %xmm2, %r8d
andb %r9b, %r10b
andb %r8b, %r10b
movss (%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r8b
andb %r10b, %r8b
cmpq %rax, %rdx
jae .LBB2_2
# %bb.6: # in Loop: Header=BB2_5 Depth=1
addq $24, %rcx
incq %rdx
testb %r8b, %r8b
jne .LBB2_5
.LBB2_2: # %._crit_edge.loopexit
movzbl %r8b, %eax
retq
.LBB2_1:
movl $1, %eax
retq
.Lfunc_end2:
.size _Z7compareP8ParticleS0_, .Lfunc_end2-_Z7compareP8ParticleS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initArrayP8Particle
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z9initArrayP8Particle
.p2align 4, 0x90
.type _Z9initArrayP8Particle,@function
_Z9initArrayP8Particle: # @_Z9initArrayP8Particle
.cfi_startproc
# %bb.0:
cmpl $0, MAX_PARTICLES(%rip)
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
addq $20, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -20(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -16(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -12(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -8(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -4(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%rbx)
incq %r14
movslq MAX_PARTICLES(%rip), %rax
addq $24, %rbx
cmpq %rax, %r14
jl .LBB3_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z9initArrayP8Particle, .Lfunc_end3-_Z9initArrayP8Particle
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9cpuSecondv, .Lfunc_end4-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z13setParametersiPPc # -- Begin function _Z13setParametersiPPc
.p2align 4, 0x90
.type _Z13setParametersiPPc,@function
_Z13setParametersiPPc: # @_Z13setParametersiPPc
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
addl $-2, %edi
cmpl $3, %edi
ja .LBB5_6
# %bb.1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
jmpq *.LJTI5_0(,%rdi,8)
.LBB5_2:
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, DEC_FACTOR(%rip)
.LBB5_3:
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, TPB(%rip)
.LBB5_4:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, NUM_ITERATIONS(%rip)
.LBB5_5:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, MAX_PARTICLES(%rip)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB5_6:
movl $100000, MAX_PARTICLES(%rip) # imm = 0x186A0
movl $100, NUM_ITERATIONS(%rip)
movl $256, TPB(%rip) # imm = 0x100
movl $1063675494, DEC_FACTOR(%rip) # imm = 0x3F666666
retq
.Lfunc_end5:
.size _Z13setParametersiPPc, .Lfunc_end5-_Z13setParametersiPPc
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_5
.quad .LBB5_4
.quad .LBB5_3
.quad .LBB5_2
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z13setParametersiPPc
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r14
movq %rax, %rdi
callq _Z9initArrayP8Particle
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
leaq 24(%rsp), %rdi
xorl %r12d, %r12d
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
movq 24(%rsp), %rdi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movq %r14, %rsi
callq memcpy@PLT
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl NUM_ITERATIONS(%rip), %eax
testl %eax, %eax
jle .LBB6_6
# %bb.1: # %.lr.ph
movl MAX_PARTICLES(%rip), %ecx
movss DEC_FACTOR(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rcx, %rdx
shlq $3, %rdx
leaq (%rdx,%rdx,2), %rdx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %_Z11timestepCPUP8Particle.exit
# in Loop: Header=BB6_2 Depth=1
incl %r12d
cmpl %eax, %r12d
je .LBB6_6
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testl %ecx, %ecx
jle .LBB6_5
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB6_2 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_4: # %.lr.ph.i
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movss 12(%rbx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rbx,%rsi)
movss 16(%rbx,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm0, %xmm2
movss %xmm2, 16(%rbx,%rsi)
movss 20(%rbx,%rsi), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm0, %xmm3
movss %xmm3, 20(%rbx,%rsi)
addss (%rbx,%rsi), %xmm1
movss %xmm1, (%rbx,%rsi)
addss 4(%rbx,%rsi), %xmm2
movss %xmm2, 4(%rbx,%rsi)
addss 8(%rbx,%rsi), %xmm3
movss %xmm3, 8(%rbx,%rsi)
addq $24, %rsi
cmpq %rsi, %rdx
jne .LBB6_4
jmp .LBB6_5
.LBB6_6: # %._crit_edge
xorl %r14d, %r14d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 40(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 40(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
cmpl $0, NUM_ITERATIONS(%rip)
jle .LBB6_11
# %bb.7: # %.lr.ph29
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 72(%rsp), %r12
leaq 64(%rsp), %r13
movq %rsp, %rbp
jmp .LBB6_8
.p2align 4, 0x90
.LBB6_10: # in Loop: Header=BB6_8 Depth=1
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $2, %ecx
callq hipMemcpy
incl %r14d
cmpl NUM_ITERATIONS(%rip), %r14d
jge .LBB6_11
.LBB6_8: # =>This Inner Loop Header: Depth=1
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $1, %ecx
callq hipMemcpy
movl MAX_PARTICLES(%rip), %eax
movl TPB(%rip), %ecx
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
orq %r15, %rax
orq %r15, %rcx
movq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9: # in Loop: Header=BB6_8 Depth=1
movq 48(%rsp), %rax
movl MAX_PARTICLES(%rip), %ecx
movss DEC_FACTOR(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 112(%rsp)
movl %ecx, 60(%rsp)
movss %xmm0, 56(%rsp)
leaq 112(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z11timestepGPUP8Particleif, %edi
movq %rbp, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_10
.LBB6_11: # %._crit_edge30
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 32(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl MAX_PARTICLES(%rip), %esi
movl TPB(%rip), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $2, %al
callq printf
movl MAX_PARTICLES(%rip), %eax
testl %eax, %eax
jle .LBB6_17
# %bb.12: # %.lr.ph.i20
movq 24(%rsp), %rcx
movl $1, %edx
movl $20, %esi
movss TOLERANCE(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_13: # =>This Inner Loop Header: Depth=1
movss -12(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -12(%rbx,%rsi), %xmm1
movss -20(%rcx,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss -16(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -20(%rbx,%rsi), %xmm2
subss -16(%rbx,%rsi), %xmm1
cmpltps %xmm0, %xmm1
cmpltps %xmm0, %xmm2
seta %dil
andps %xmm1, %xmm2
movss -8(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -8(%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %r8b
andb %dil, %r8b
movss -4(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -4(%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %r9b
movd %xmm2, %edi
andb %r8b, %r9b
andb %dil, %r9b
movss (%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %dil
andb %r9b, %dil
cmpq %rax, %rdx
jae .LBB6_15
# %bb.14: # in Loop: Header=BB6_13 Depth=1
incq %rdx
addq $24, %rsi
testb %dil, %dil
jne .LBB6_13
.LBB6_15: # %._crit_edge.loopexit.i
testb %dil, %dil
jne .LBB6_17
# %bb.16:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_17: # %.critedge
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11timestepGPUP8Particleif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type MAX_PARTICLES,@object # @MAX_PARTICLES
.bss
.globl MAX_PARTICLES
.p2align 2, 0x0
MAX_PARTICLES:
.long 0 # 0x0
.size MAX_PARTICLES, 4
.type NUM_ITERATIONS,@object # @NUM_ITERATIONS
.globl NUM_ITERATIONS
.p2align 2, 0x0
NUM_ITERATIONS:
.long 0 # 0x0
.size NUM_ITERATIONS, 4
.type TPB,@object # @TPB
.globl TPB
.p2align 2, 0x0
TPB:
.long 0 # 0x0
.size TPB, 4
.type DEC_FACTOR,@object # @DEC_FACTOR
.globl DEC_FACTOR
.p2align 2, 0x0
DEC_FACTOR:
.long 0x00000000 # float 0
.size DEC_FACTOR, 4
.type TOLERANCE,@object # @TOLERANCE
.data
.globl TOLERANCE
.p2align 2, 0x0
TOLERANCE:
.long 0x358637bd # float 9.99999997E-7
.size TOLERANCE, 4
.type _Z11timestepGPUP8Particleif,@object # @_Z11timestepGPUP8Particleif
.section .rodata,"a",@progbits
.globl _Z11timestepGPUP8Particleif
.p2align 3, 0x0
_Z11timestepGPUP8Particleif:
.quad _Z26__device_stub__timestepGPUP8Particleif
.size _Z11timestepGPUP8Particleif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nSize of the array: %d\nTPB: %d\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time: %2f\nGPU time: %2f\n"
.size .L.str.1, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11timestepGPUP8Particleif"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Differences between arrays"
.size .Lstr, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__timestepGPUP8Particleif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11timestepGPUP8Particleif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11timestepGPUP8Particleif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64+0xc] ; /* 0x00000c0402007981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R4, [R2.64+0x10] ; /* 0x0000100402047981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R6, [R2.64+0x14] ; /* 0x0000140402067981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000f68000c1e1900 */
/*00d0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000f68000c1e1900 */
/*00e0*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f62000c1e1900 */
/*00f0*/ FMUL R5, R0, c[0x0][0x16c] ; /* 0x00005b0000057a20 */
/* 0x004fc40000400000 */
/*0100*/ FMUL R7, R4, c[0x0][0x16c] ; /* 0x00005b0004077a20 */
/* 0x008fc60000400000 */
/*0110*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe2000c101904 */
/*0120*/ FMUL R9, R6, c[0x0][0x16c] ; /* 0x00005b0006097a20 */
/* 0x010fc60000400000 */
/*0130*/ STG.E [R2.64+0x10], R7 ; /* 0x0000100702007986 */
/* 0x000fe2000c101904 */
/*0140*/ FADD R11, R5, R8 ; /* 0x00000008050b7221 */
/* 0x020fc60000000000 */
/*0150*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe2000c101904 */
/*0160*/ FADD R13, R7, R10 ; /* 0x0000000a070d7221 */
/* 0x000fc60000000000 */
/*0170*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0180*/ FADD R15, R9, R12 ; /* 0x0000000c090f7221 */
/* 0x000fc60000000000 */
/*0190*/ STG.E [R2.64+0x4], R13 ; /* 0x0000040d02007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+0x8], R15 ; /* 0x0000080f02007986 */
/* 0x000fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11timestepGPUP8Particleif
.globl _Z11timestepGPUP8Particleif
.p2align 8
.type _Z11timestepGPUP8Particleif,@function
_Z11timestepGPUP8Particleif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 24, s[2:3]
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(1)
v_fma_f32 v0, s0, v3, v0
s_waitcnt vmcnt(0)
v_fma_f32 v1, s0, v6, v1
v_fmac_f32_e32 v2, s0, v7
v_dual_mul_f32 v3, s0, v3 :: v_dual_mul_f32 v6, s0, v6
v_mul_f32_e32 v7, s0, v7
s_clause 0x1
global_store_b64 v[4:5], v[6:7], off offset:16
global_store_b128 v[4:5], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11timestepGPUP8Particleif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11timestepGPUP8Particleif, .Lfunc_end0-_Z11timestepGPUP8Particleif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11timestepGPUP8Particleif
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z11timestepGPUP8Particleif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c2d96_00000000-6_exercise_2a.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11timestepCPUP8Particle
.type _Z11timestepCPUP8Particle, @function
_Z11timestepCPUP8Particle:
.LFB2057:
.cfi_startproc
endbr64
cmpl $0, MAX_PARTICLES(%rip)
jle .L3
movl $0, %eax
.L5:
movss DEC_FACTOR(%rip), %xmm0
movaps %xmm0, %xmm2
mulss 12(%rdi), %xmm2
movss %xmm2, 12(%rdi)
movaps %xmm0, %xmm1
mulss 16(%rdi), %xmm1
movss %xmm1, 16(%rdi)
mulss 20(%rdi), %xmm0
movss %xmm0, 20(%rdi)
addss (%rdi), %xmm2
movss %xmm2, (%rdi)
addss 4(%rdi), %xmm1
movss %xmm1, 4(%rdi)
addss 8(%rdi), %xmm0
movss %xmm0, 8(%rdi)
addl $1, %eax
addq $24, %rdi
cmpl %eax, MAX_PARTICLES(%rip)
jg .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z11timestepCPUP8Particle, .-_Z11timestepCPUP8Particle
.globl _Z7compareP8ParticleS0_
.type _Z7compareP8ParticleS0_, @function
_Z7compareP8ParticleS0_:
.LFB2058:
.cfi_startproc
endbr64
movl MAX_PARTICLES(%rip), %r8d
testl %r8d, %r8d
jle .L11
movss TOLERANCE(%rip), %xmm0
movl $0, %edx
.L9:
movss (%rdi), %xmm1
subss (%rsi), %xmm1
comiss %xmm1, %xmm0
seta %al
movss 4(%rdi), %xmm1
subss 4(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 8(%rdi), %xmm1
subss 8(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 12(%rdi), %xmm1
subss 12(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 16(%rdi), %xmm1
subss 16(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
movss 20(%rdi), %xmm1
subss 20(%rsi), %xmm1
comiss %xmm1, %xmm0
seta %cl
andl %ecx, %eax
addl $1, %edx
addq $24, %rdi
addq $24, %rsi
cmpl %r8d, %edx
jge .L12
testb %al, %al
jne .L9
.L12:
movzbl %al, %eax
ret
.L11:
movl $1, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z7compareP8ParticleS0_, .-_Z7compareP8ParticleS0_
.globl _Z9initArrayP8Particle
.type _Z9initArrayP8Particle, @function
_Z9initArrayP8Particle:
.LFB2059:
.cfi_startproc
endbr64
cmpl $0, MAX_PARTICLES(%rip)
jle .L19
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl $0, %ebp
.L16:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 20(%rbx)
addl $1, %ebp
addq $24, %rbx
cmpl %ebp, MAX_PARTICLES(%rip)
jg .L16
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z9initArrayP8Particle, .-_Z9initArrayP8Particle
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z13setParametersiPPc
.type _Z13setParametersiPPc, @function
_Z13setParametersiPPc:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $4, %edi
je .L27
jg .L28
cmpl $2, %edi
je .L29
cmpl $3, %edi
je .L30
.L31:
movl $100000, MAX_PARTICLES(%rip)
movl $100, NUM_ITERATIONS(%rip)
movl $256, TPB(%rip)
movl $0x3f666666, DEC_FACTOR(%rip)
jmp .L26
.L28:
cmpl $5, %edi
jne .L31
movq 32(%rsi), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, DEC_FACTOR(%rip)
.L27:
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, TPB(%rip)
.L30:
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, NUM_ITERATIONS(%rip)
.L29:
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, MAX_PARTICLES(%rip)
.L26:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z13setParametersiPPc, .-_Z13setParametersiPPc
.globl _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
.type _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif, @function
_Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif:
.LFB2087:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11timestepGPUP8Particleif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif, .-_Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
.globl _Z11timestepGPUP8Particleif
.type _Z11timestepGPUP8Particleif, @function
_Z11timestepGPUP8Particleif:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z11timestepGPUP8Particleif, .-_Z11timestepGPUP8Particleif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "\nSize of the array: %d\nTPB: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "CPU time: %2f\nGPU time: %2f\n"
.LC5:
.string "Differences between arrays\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
call _Z13setParametersiPPc
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movq %rax, %rdi
call _Z9initArrayP8Particle
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rbx
salq $3, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rcx
movq %rbx, %rdx
movq %r12, %rsi
movq %rax, %rdi
call __memcpy_chk@PLT
leaq 16(%rsp), %rdi
movl $0, %edx
movq %rbx, %rsi
call cudaHostAlloc@PLT
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movq %r12, %rsi
movq 16(%rsp), %rdi
call memcpy@PLT
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rsi
salq $3, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
cmpl $0, NUM_ITERATIONS(%rip)
jle .L43
movl $0, %ebx
.L44:
movq %rbp, %rdi
call _Z11timestepCPUP8Particle
addl $1, %ebx
cmpl %ebx, NUM_ITERATIONS(%rip)
jg .L44
.L43:
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movq %xmm0, %r12
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
cmpl $0, NUM_ITERATIONS(%rip)
jle .L45
movl $0, %ebx
jmp .L47
.L46:
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
addl $1, %ebx
cmpl %ebx, NUM_ITERATIONS(%rip)
jle .L45
.L47:
movslq MAX_PARTICLES(%rip), %rax
leaq (%rax,%rax,2), %rdx
salq $3, %rdx
movl $1, %ecx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl TPB(%rip), %ecx
movl %ecx, 44(%rsp)
movl $1, 48(%rsp)
movl %ecx, %eax
addl MAX_PARTICLES(%rip), %eax
subl $1, %eax
cltd
idivl %ecx
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L46
movss DEC_FACTOR(%rip), %xmm0
movl MAX_PARTICLES(%rip), %esi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z11timestepGPUP8ParticleifP8Particleif
jmp .L46
.L45:
call cudaDeviceSynchronize@PLT
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
movq %xmm0, %rbx
movl TPB(%rip), %ecx
movl MAX_PARTICLES(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %xmm1
movq %r12, %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq 16(%rsp), %rdi
call _Z7compareP8ParticleS0_
testl %eax, %eax
je .L53
.L48:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
jmp .L48
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11timestepGPUP8Particleif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11timestepGPUP8Particleif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl TOLERANCE
.data
.align 4
.type TOLERANCE, @object
.size TOLERANCE, 4
TOLERANCE:
.long 897988541
.globl DEC_FACTOR
.bss
.align 4
.type DEC_FACTOR, @object
.size DEC_FACTOR, 4
DEC_FACTOR:
.zero 4
.globl TPB
.align 4
.type TPB, @object
.size TPB, 4
TPB:
.zero 4
.globl NUM_ITERATIONS
.align 4
.type NUM_ITERATIONS, @object
.size NUM_ITERATIONS, 4
NUM_ITERATIONS:
.zero 4
.globl MAX_PARTICLES
.align 4
.type MAX_PARTICLES, @object
.size MAX_PARTICLES, 4
MAX_PARTICLES:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_2a.hip"
.globl _Z26__device_stub__timestepGPUP8Particleif # -- Begin function _Z26__device_stub__timestepGPUP8Particleif
.p2align 4, 0x90
.type _Z26__device_stub__timestepGPUP8Particleif,@function
_Z26__device_stub__timestepGPUP8Particleif: # @_Z26__device_stub__timestepGPUP8Particleif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movss %xmm0, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11timestepGPUP8Particleif, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__timestepGPUP8Particleif, .Lfunc_end0-_Z26__device_stub__timestepGPUP8Particleif
.cfi_endproc
# -- End function
.globl _Z11timestepCPUP8Particle # -- Begin function _Z11timestepCPUP8Particle
.p2align 4, 0x90
.type _Z11timestepCPUP8Particle,@function
_Z11timestepCPUP8Particle: # @_Z11timestepCPUP8Particle
.cfi_startproc
# %bb.0:
cmpl $0, MAX_PARTICLES(%rip)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
addq $20, %rdi
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss -8(%rdi), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss DEC_FACTOR(%rip), %xmm0
movss -4(%rdi), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss %xmm0, -8(%rdi)
mulss DEC_FACTOR(%rip), %xmm1
movss %xmm1, -4(%rdi)
movss (%rdi), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss DEC_FACTOR(%rip), %xmm2
movss %xmm2, (%rdi)
addss -20(%rdi), %xmm0
movss %xmm0, -20(%rdi)
addss -16(%rdi), %xmm1
movss %xmm1, -16(%rdi)
addss -12(%rdi), %xmm2
movss %xmm2, -12(%rdi)
incq %rax
movslq MAX_PARTICLES(%rip), %rcx
addq $24, %rdi
cmpq %rcx, %rax
jl .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z11timestepCPUP8Particle, .Lfunc_end1-_Z11timestepCPUP8Particle
.cfi_endproc
# -- End function
.globl _Z7compareP8ParticleS0_ # -- Begin function _Z7compareP8ParticleS0_
.p2align 4, 0x90
.type _Z7compareP8ParticleS0_,@function
_Z7compareP8ParticleS0_: # @_Z7compareP8ParticleS0_
.cfi_startproc
# %bb.0:
movl MAX_PARTICLES(%rip), %eax
testl %eax, %eax
jle .LBB2_1
# %bb.4: # %.lr.ph
movl $20, %ecx
movl $1, %edx
movss TOLERANCE(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss -12(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -12(%rsi,%rcx), %xmm1
movss -20(%rdi,%rcx), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss -16(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -20(%rsi,%rcx), %xmm2
subss -16(%rsi,%rcx), %xmm1
cmpltps %xmm0, %xmm1
cmpltps %xmm0, %xmm2
seta %r8b
andps %xmm1, %xmm2
movss -8(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -8(%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r9b
andb %r8b, %r9b
movss -4(%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -4(%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r10b
movd %xmm2, %r8d
andb %r9b, %r10b
andb %r8b, %r10b
movss (%rdi,%rcx), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rsi,%rcx), %xmm1
ucomiss %xmm1, %xmm0
seta %r8b
andb %r10b, %r8b
cmpq %rax, %rdx
jae .LBB2_2
# %bb.6: # in Loop: Header=BB2_5 Depth=1
addq $24, %rcx
incq %rdx
testb %r8b, %r8b
jne .LBB2_5
.LBB2_2: # %._crit_edge.loopexit
movzbl %r8b, %eax
retq
.LBB2_1:
movl $1, %eax
retq
.Lfunc_end2:
.size _Z7compareP8ParticleS0_, .Lfunc_end2-_Z7compareP8ParticleS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9initArrayP8Particle
.LCPI3_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z9initArrayP8Particle
.p2align 4, 0x90
.type _Z9initArrayP8Particle,@function
_Z9initArrayP8Particle: # @_Z9initArrayP8Particle
.cfi_startproc
# %bb.0:
cmpl $0, MAX_PARTICLES(%rip)
jle .LBB3_4
# %bb.1: # %.lr.ph.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
addq $20, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -20(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -16(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -12(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -8(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, -4(%rbx)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI3_0(%rip), %xmm0
movss %xmm0, (%rbx)
incq %r14
movslq MAX_PARTICLES(%rip), %rax
addq $24, %rbx
cmpq %rax, %r14
jl .LBB3_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z9initArrayP8Particle, .Lfunc_end3-_Z9initArrayP8Particle
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9cpuSecondv, .Lfunc_end4-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z13setParametersiPPc # -- Begin function _Z13setParametersiPPc
.p2align 4, 0x90
.type _Z13setParametersiPPc,@function
_Z13setParametersiPPc: # @_Z13setParametersiPPc
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
addl $-2, %edi
cmpl $3, %edi
ja .LBB5_6
# %bb.1:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
jmpq *.LJTI5_0(,%rdi,8)
.LBB5_2:
movq 32(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, DEC_FACTOR(%rip)
.LBB5_3:
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, TPB(%rip)
.LBB5_4:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, NUM_ITERATIONS(%rip)
.LBB5_5:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, MAX_PARTICLES(%rip)
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
retq
.LBB5_6:
movl $100000, MAX_PARTICLES(%rip) # imm = 0x186A0
movl $100, NUM_ITERATIONS(%rip)
movl $256, TPB(%rip) # imm = 0x100
movl $1063675494, DEC_FACTOR(%rip) # imm = 0x3F666666
retq
.Lfunc_end5:
.size _Z13setParametersiPPc, .Lfunc_end5-_Z13setParametersiPPc
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI5_0:
.quad .LBB5_5
.quad .LBB5_4
.quad .LBB5_3
.quad .LBB5_2
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq _Z13setParametersiPPc
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r14
movq %rax, %rdi
callq _Z9initArrayP8Particle
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
leaq 24(%rsp), %rdi
xorl %r12d, %r12d
movq %r15, %rsi
xorl %edx, %edx
callq hipHostAlloc
movq 24(%rsp), %rdi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movq %r14, %rsi
callq memcpy@PLT
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl NUM_ITERATIONS(%rip), %eax
testl %eax, %eax
jle .LBB6_6
# %bb.1: # %.lr.ph
movl MAX_PARTICLES(%rip), %ecx
movss DEC_FACTOR(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rcx, %rdx
shlq $3, %rdx
leaq (%rdx,%rdx,2), %rdx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_5: # %_Z11timestepCPUP8Particle.exit
# in Loop: Header=BB6_2 Depth=1
incl %r12d
cmpl %eax, %r12d
je .LBB6_6
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
testl %ecx, %ecx
jle .LBB6_5
# %bb.3: # %.lr.ph.i.preheader
# in Loop: Header=BB6_2 Depth=1
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_4: # %.lr.ph.i
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movss 12(%rbx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
movss %xmm1, 12(%rbx,%rsi)
movss 16(%rbx,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
mulss %xmm0, %xmm2
movss %xmm2, 16(%rbx,%rsi)
movss 20(%rbx,%rsi), %xmm3 # xmm3 = mem[0],zero,zero,zero
mulss %xmm0, %xmm3
movss %xmm3, 20(%rbx,%rsi)
addss (%rbx,%rsi), %xmm1
movss %xmm1, (%rbx,%rsi)
addss 4(%rbx,%rsi), %xmm2
movss %xmm2, 4(%rbx,%rsi)
addss 8(%rbx,%rsi), %xmm3
movss %xmm3, 8(%rbx,%rsi)
addq $24, %rsi
cmpq %rsi, %rdx
jne .LBB6_4
jmp .LBB6_5
.LBB6_6: # %._crit_edge
xorl %r14d, %r14d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 40(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 40(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 32(%rsp) # 8-byte Spill
cmpl $0, NUM_ITERATIONS(%rip)
jle .LBB6_11
# %bb.7: # %.lr.ph29
movabsq $4294967296, %r15 # imm = 0x100000000
leaq 72(%rsp), %r12
leaq 64(%rsp), %r13
movq %rsp, %rbp
jmp .LBB6_8
.p2align 4, 0x90
.LBB6_10: # in Loop: Header=BB6_8 Depth=1
movq 24(%rsp), %rdi
movq 48(%rsp), %rsi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $2, %ecx
callq hipMemcpy
incl %r14d
cmpl NUM_ITERATIONS(%rip), %r14d
jge .LBB6_11
.LBB6_8: # =>This Inner Loop Header: Depth=1
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
movslq MAX_PARTICLES(%rip), %rax
shlq $3, %rax
leaq (%rax,%rax,2), %rdx
movl $1, %ecx
callq hipMemcpy
movl MAX_PARTICLES(%rip), %eax
movl TPB(%rip), %ecx
addl %ecx, %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
orq %r15, %rax
orq %r15, %rcx
movq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_10
# %bb.9: # in Loop: Header=BB6_8 Depth=1
movq 48(%rsp), %rax
movl MAX_PARTICLES(%rip), %ecx
movss DEC_FACTOR(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, 112(%rsp)
movl %ecx, 60(%rsp)
movss %xmm0, 56(%rsp)
leaq 112(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z11timestepGPUP8Particleif, %edi
movq %rbp, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_10
.LBB6_11: # %._crit_edge30
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
mulsd .LCPI6_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 32(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, 32(%rsp) # 8-byte Spill
movl MAX_PARTICLES(%rip), %esi
movl TPB(%rip), %edx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 32(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $2, %al
callq printf
movl MAX_PARTICLES(%rip), %eax
testl %eax, %eax
jle .LBB6_17
# %bb.12: # %.lr.ph.i20
movq 24(%rsp), %rcx
movl $1, %edx
movl $20, %esi
movss TOLERANCE(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB6_13: # =>This Inner Loop Header: Depth=1
movss -12(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -12(%rbx,%rsi), %xmm1
movss -20(%rcx,%rsi), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
movss -16(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -20(%rbx,%rsi), %xmm2
subss -16(%rbx,%rsi), %xmm1
cmpltps %xmm0, %xmm1
cmpltps %xmm0, %xmm2
seta %dil
andps %xmm1, %xmm2
movss -8(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -8(%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %r8b
andb %dil, %r8b
movss -4(%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss -4(%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %r9b
movd %xmm2, %edi
andb %r8b, %r9b
andb %dil, %r9b
movss (%rcx,%rsi), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss (%rbx,%rsi), %xmm1
ucomiss %xmm1, %xmm0
seta %dil
andb %r9b, %dil
cmpq %rax, %rdx
jae .LBB6_15
# %bb.14: # in Loop: Header=BB6_13 Depth=1
incq %rdx
addq $24, %rsi
testb %dil, %dil
jne .LBB6_13
.LBB6_15: # %._crit_edge.loopexit.i
testb %dil, %dil
jne .LBB6_17
# %bb.16:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_17: # %.critedge
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11timestepGPUP8Particleif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type MAX_PARTICLES,@object # @MAX_PARTICLES
.bss
.globl MAX_PARTICLES
.p2align 2, 0x0
MAX_PARTICLES:
.long 0 # 0x0
.size MAX_PARTICLES, 4
.type NUM_ITERATIONS,@object # @NUM_ITERATIONS
.globl NUM_ITERATIONS
.p2align 2, 0x0
NUM_ITERATIONS:
.long 0 # 0x0
.size NUM_ITERATIONS, 4
.type TPB,@object # @TPB
.globl TPB
.p2align 2, 0x0
TPB:
.long 0 # 0x0
.size TPB, 4
.type DEC_FACTOR,@object # @DEC_FACTOR
.globl DEC_FACTOR
.p2align 2, 0x0
DEC_FACTOR:
.long 0x00000000 # float 0
.size DEC_FACTOR, 4
.type TOLERANCE,@object # @TOLERANCE
.data
.globl TOLERANCE
.p2align 2, 0x0
TOLERANCE:
.long 0x358637bd # float 9.99999997E-7
.size TOLERANCE, 4
.type _Z11timestepGPUP8Particleif,@object # @_Z11timestepGPUP8Particleif
.section .rodata,"a",@progbits
.globl _Z11timestepGPUP8Particleif
.p2align 3, 0x0
_Z11timestepGPUP8Particleif:
.quad _Z26__device_stub__timestepGPUP8Particleif
.size _Z11timestepGPUP8Particleif, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nSize of the array: %d\nTPB: %d\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU time: %2f\nGPU time: %2f\n"
.size .L.str.1, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11timestepGPUP8Particleif"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Differences between arrays"
.size .Lstr, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__timestepGPUP8Particleif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11timestepGPUP8Particleif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
//#define NUM_BINS 64 // We are also going to use this for the number of threads in a block.
#define NUM_BINS 1024 // We are also going to use this for the number of threads in a block.
#define NUM_THREADS_PER_BLOCK 16
#define NUM_BLOCKS 16
////////////////////////////////////////////////////////////////////////////////
// Took this code from a Dr. Dobbs example.
////////////////////////////////////////////////////////////////////////////////
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
////////////////////////////////////////////////////////////////////////////////
// The kernel.
////////////////////////////////////////////////////////////////////////////////
__global__ void kernel (int *dev_hist)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// shared memory
__shared__ int shared_hist[NUM_BINS];
// access thread id
//const unsigned int tid = threadIdx.x;
// access number of threads in this block
const unsigned int num_threads = blockDim.x;
// Note that we only clear things out for the first thread on each block.
if(threadIdx.x==0)
{
for (int i=0;i<NUM_BINS;i++)
shared_hist[i] = 0;
}
__syncthreads();
////////////////////////////////////////////////////////////////////////
// FILL THE ARRAYS
shared_hist[tid] = blockIdx.x*1000 + tid;
//shared_hist[tid] = blockIdx.x;
__syncthreads();
if(threadIdx.x==0)
{
for(int i=0;i<NUM_BINS;i++)
{
dev_hist[i+(blockIdx.x*(NUM_BINS))]=shared_hist[i];
}
}
}
////////////////////////////////////////////////////////////////////////////////
// The main() program.
////////////////////////////////////////////////////////////////////////////////
int main()
{
int nbins = NUM_BINS;
int dimx = NUM_BLOCKS; // Number of blocks
int num_bytes = NUM_BINS*sizeof(int);
int num_bytes_on_gpu = dimx*NUM_BINS*sizeof(int);
int *d_a=0, *h_a=0, *h_hist=0; // device and host pointers
// Allocate memory on host (CPU)
h_a = (int*)malloc(num_bytes_on_gpu);
h_hist = (int*)malloc(num_bytes);
// Allocate memory on device (GPU)
cudaMalloc((void**)&d_a,num_bytes_on_gpu);
checkCUDAError("malloc");
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_a)
{
printf("Couldn't allocate host memory\n");
return 1;
}
if (0==d_a)
{
printf("Couldn't allocate device memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(d_a,0,num_bytes_on_gpu);
checkCUDAError("memset");
//-----------------------------------------------------------------------//
// Some explanatory code
/*
// This will give us 256 thread blocks, arranged in a 16x16 grid.
dim3 grid(16,16);
// This will give us 256 threads/block, arranged in a 16x16 grid.
dim3 block(16,16);
kernel<<<grid,block,0,0>>>(XXX);
// This is a shortcut for launching some thread blocks.
// It launches a grid of 32 thread blocks arranged in a 1x32 grid
// and 512 threads per block, arranged in a 1x512 array.
kernel<<<32,512>>>(YYY);
*/
//dim3 grid,block;
//block.x = 8;
//grid.x = dimx/block.x;
//kernel<<<grid,block>>>(d_a);
//kernel<<<4,16>>>(d_a);
dim3 grid, block;
grid.x = NUM_BLOCKS; // Number of blocks
block.x = NUM_BINS; // Number of threads per block.
kernel<<<grid,block>>>(d_a);
cudaThreadSynchronize();
checkCUDAError("kernel");
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes_on_gpu,cudaMemcpyDeviceToHost);
for (int i=0;i<dimx;i++)
{
for (int j=0;j<NUM_BINS;j++)
{
printf("%d ",h_a[i*NUM_BINS + j]);
}
printf("\n");
}
printf("\n");
free(h_a);
cudaFree(d_a);
return 0;
} | .file "tmpxft_0009d04b_00000000-6_testing_size_of_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1
.LC1:
.string "malloc"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Couldn't allocate host memory\n"
.align 8
.LC3:
.string "Couldn't allocate device memory\n"
.section .rodata.str1.1
.LC4:
.string "memset"
.LC5:
.string "kernel"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $65536, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
testq %r15, %r15
je .L26
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L27
movl $65536, %edx
movl $0, %esi
call cudaMemset@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, 20(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1024, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaThreadSynchronize@PLT
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 4096(%r15), %rbp
leaq 69632(%r15), %r14
leaq .LC6(%rip), %r12
leaq .LC7(%rip), %r13
.L20:
leaq -4096(%rbp), %rbx
.L21:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4096, %rbp
cmpq %r14, %rbp
jne .L20
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L15:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L28:
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L19
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
//#define NUM_BINS 64 // We are also going to use this for the number of threads in a block.
#define NUM_BINS 1024 // We are also going to use this for the number of threads in a block.
#define NUM_THREADS_PER_BLOCK 16
#define NUM_BLOCKS 16
////////////////////////////////////////////////////////////////////////////////
// Took this code from a Dr. Dobbs example.
////////////////////////////////////////////////////////////////////////////////
void checkCUDAError(const char *msg)
{
cudaError_t err = cudaGetLastError();
if( cudaSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
////////////////////////////////////////////////////////////////////////////////
// The kernel.
////////////////////////////////////////////////////////////////////////////////
__global__ void kernel (int *dev_hist)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// shared memory
__shared__ int shared_hist[NUM_BINS];
// access thread id
//const unsigned int tid = threadIdx.x;
// access number of threads in this block
const unsigned int num_threads = blockDim.x;
// Note that we only clear things out for the first thread on each block.
if(threadIdx.x==0)
{
for (int i=0;i<NUM_BINS;i++)
shared_hist[i] = 0;
}
__syncthreads();
////////////////////////////////////////////////////////////////////////
// FILL THE ARRAYS
shared_hist[tid] = blockIdx.x*1000 + tid;
//shared_hist[tid] = blockIdx.x;
__syncthreads();
if(threadIdx.x==0)
{
for(int i=0;i<NUM_BINS;i++)
{
dev_hist[i+(blockIdx.x*(NUM_BINS))]=shared_hist[i];
}
}
}
////////////////////////////////////////////////////////////////////////////////
// The main() program.
////////////////////////////////////////////////////////////////////////////////
int main()
{
int nbins = NUM_BINS;
int dimx = NUM_BLOCKS; // Number of blocks
int num_bytes = NUM_BINS*sizeof(int);
int num_bytes_on_gpu = dimx*NUM_BINS*sizeof(int);
int *d_a=0, *h_a=0, *h_hist=0; // device and host pointers
// Allocate memory on host (CPU)
h_a = (int*)malloc(num_bytes_on_gpu);
h_hist = (int*)malloc(num_bytes);
// Allocate memory on device (GPU)
cudaMalloc((void**)&d_a,num_bytes_on_gpu);
checkCUDAError("malloc");
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_a)
{
printf("Couldn't allocate host memory\n");
return 1;
}
if (0==d_a)
{
printf("Couldn't allocate device memory\n");
return 1;
}
// Initialize array to all 0's
cudaMemset(d_a,0,num_bytes_on_gpu);
checkCUDAError("memset");
//-----------------------------------------------------------------------//
// Some explanatory code
/*
// This will give us 256 thread blocks, arranged in a 16x16 grid.
dim3 grid(16,16);
// This will give us 256 threads/block, arranged in a 16x16 grid.
dim3 block(16,16);
kernel<<<grid,block,0,0>>>(XXX);
// This is a shortcut for launching some thread blocks.
// It launches a grid of 32 thread blocks arranged in a 1x32 grid
// and 512 threads per block, arranged in a 1x512 array.
kernel<<<32,512>>>(YYY);
*/
//dim3 grid,block;
//block.x = 8;
//grid.x = dimx/block.x;
//kernel<<<grid,block>>>(d_a);
//kernel<<<4,16>>>(d_a);
dim3 grid, block;
grid.x = NUM_BLOCKS; // Number of blocks
block.x = NUM_BINS; // Number of threads per block.
kernel<<<grid,block>>>(d_a);
cudaThreadSynchronize();
checkCUDAError("kernel");
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes_on_gpu,cudaMemcpyDeviceToHost);
for (int i=0;i<dimx;i++)
{
for (int j=0;j<NUM_BINS;j++)
{
printf("%d ",h_a[i*NUM_BINS + j]);
}
printf("\n");
}
printf("\n");
free(h_a);
cudaFree(d_a);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
//#define NUM_BINS 64 // We are also going to use this for the number of threads in a block.
#define NUM_BINS 1024 // We are also going to use this for the number of threads in a block.
#define NUM_THREADS_PER_BLOCK 16
#define NUM_BLOCKS 16
////////////////////////////////////////////////////////////////////////////////
// Took this code from a Dr. Dobbs example.
////////////////////////////////////////////////////////////////////////////////
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
////////////////////////////////////////////////////////////////////////////////
// The kernel.
////////////////////////////////////////////////////////////////////////////////
__global__ void kernel (int *dev_hist)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// shared memory
__shared__ int shared_hist[NUM_BINS];
// access thread id
//const unsigned int tid = threadIdx.x;
// access number of threads in this block
const unsigned int num_threads = blockDim.x;
// Note that we only clear things out for the first thread on each block.
if(threadIdx.x==0)
{
for (int i=0;i<NUM_BINS;i++)
shared_hist[i] = 0;
}
__syncthreads();
////////////////////////////////////////////////////////////////////////
// FILL THE ARRAYS
shared_hist[tid] = blockIdx.x*1000 + tid;
//shared_hist[tid] = blockIdx.x;
__syncthreads();
if(threadIdx.x==0)
{
for(int i=0;i<NUM_BINS;i++)
{
dev_hist[i+(blockIdx.x*(NUM_BINS))]=shared_hist[i];
}
}
}
////////////////////////////////////////////////////////////////////////////////
// The main() program.
////////////////////////////////////////////////////////////////////////////////
int main()
{
int nbins = NUM_BINS;
int dimx = NUM_BLOCKS; // Number of blocks
int num_bytes = NUM_BINS*sizeof(int);
int num_bytes_on_gpu = dimx*NUM_BINS*sizeof(int);
int *d_a=0, *h_a=0, *h_hist=0; // device and host pointers
// Allocate memory on host (CPU)
h_a = (int*)malloc(num_bytes_on_gpu);
h_hist = (int*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_a,num_bytes_on_gpu);
checkCUDAError("malloc");
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_a)
{
printf("Couldn't allocate host memory\n");
return 1;
}
if (0==d_a)
{
printf("Couldn't allocate device memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(d_a,0,num_bytes_on_gpu);
checkCUDAError("memset");
//-----------------------------------------------------------------------//
// Some explanatory code
/*
// This will give us 256 thread blocks, arranged in a 16x16 grid.
dim3 grid(16,16);
// This will give us 256 threads/block, arranged in a 16x16 grid.
dim3 block(16,16);
kernel<<<grid,block,0,0>>>(XXX);
// This is a shortcut for launching some thread blocks.
// It launches a grid of 32 thread blocks arranged in a 1x32 grid
// and 512 threads per block, arranged in a 1x512 array.
kernel<<<32,512>>>(YYY);
*/
//dim3 grid,block;
//block.x = 8;
//grid.x = dimx/block.x;
//kernel<<<grid,block>>>(d_a);
//kernel<<<4,16>>>(d_a);
dim3 grid, block;
grid.x = NUM_BLOCKS; // Number of blocks
block.x = NUM_BINS; // Number of threads per block.
kernel<<<grid,block>>>(d_a);
hipDeviceSynchronize();
checkCUDAError("kernel");
// Copy it back over
hipMemcpy(h_a,d_a,num_bytes_on_gpu,hipMemcpyDeviceToHost);
for (int i=0;i<dimx;i++)
{
for (int j=0;j<NUM_BINS;j++)
{
printf("%d ",h_a[i*NUM_BINS + j]);
}
printf("\n");
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//#define NUM_BINS 64 // We are also going to use this for the number of threads in a block.
#define NUM_BINS 1024 // We are also going to use this for the number of threads in a block.
#define NUM_THREADS_PER_BLOCK 16
#define NUM_BLOCKS 16
////////////////////////////////////////////////////////////////////////////////
// Took this code from a Dr. Dobbs example.
////////////////////////////////////////////////////////////////////////////////
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
////////////////////////////////////////////////////////////////////////////////
// The kernel.
////////////////////////////////////////////////////////////////////////////////
__global__ void kernel (int *dev_hist)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// shared memory
__shared__ int shared_hist[NUM_BINS];
// access thread id
//const unsigned int tid = threadIdx.x;
// access number of threads in this block
const unsigned int num_threads = blockDim.x;
// Note that we only clear things out for the first thread on each block.
if(threadIdx.x==0)
{
for (int i=0;i<NUM_BINS;i++)
shared_hist[i] = 0;
}
__syncthreads();
////////////////////////////////////////////////////////////////////////
// FILL THE ARRAYS
shared_hist[tid] = blockIdx.x*1000 + tid;
//shared_hist[tid] = blockIdx.x;
__syncthreads();
if(threadIdx.x==0)
{
for(int i=0;i<NUM_BINS;i++)
{
dev_hist[i+(blockIdx.x*(NUM_BINS))]=shared_hist[i];
}
}
}
////////////////////////////////////////////////////////////////////////////////
// The main() program.
////////////////////////////////////////////////////////////////////////////////
int main()
{
int nbins = NUM_BINS;
int dimx = NUM_BLOCKS; // Number of blocks
int num_bytes = NUM_BINS*sizeof(int);
int num_bytes_on_gpu = dimx*NUM_BINS*sizeof(int);
int *d_a=0, *h_a=0, *h_hist=0; // device and host pointers
// Allocate memory on host (CPU)
h_a = (int*)malloc(num_bytes_on_gpu);
h_hist = (int*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_a,num_bytes_on_gpu);
checkCUDAError("malloc");
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_a)
{
printf("Couldn't allocate host memory\n");
return 1;
}
if (0==d_a)
{
printf("Couldn't allocate device memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(d_a,0,num_bytes_on_gpu);
checkCUDAError("memset");
//-----------------------------------------------------------------------//
// Some explanatory code
/*
// This will give us 256 thread blocks, arranged in a 16x16 grid.
dim3 grid(16,16);
// This will give us 256 threads/block, arranged in a 16x16 grid.
dim3 block(16,16);
kernel<<<grid,block,0,0>>>(XXX);
// This is a shortcut for launching some thread blocks.
// It launches a grid of 32 thread blocks arranged in a 1x32 grid
// and 512 threads per block, arranged in a 1x512 array.
kernel<<<32,512>>>(YYY);
*/
//dim3 grid,block;
//block.x = 8;
//grid.x = dimx/block.x;
//kernel<<<grid,block>>>(d_a);
//kernel<<<4,16>>>(d_a);
dim3 grid, block;
grid.x = NUM_BLOCKS; // Number of blocks
block.x = NUM_BINS; // Number of threads per block.
kernel<<<grid,block>>>(d_a);
hipDeviceSynchronize();
checkCUDAError("kernel");
// Copy it back over
hipMemcpy(h_a,d_a,num_bytes_on_gpu,hipMemcpyDeviceToHost);
for (int i=0;i<dimx;i++)
{
for (int j=0;j<NUM_BINS;j++)
{
printf("%d ",h_a[i*NUM_BINS + j]);
}
printf("\n");
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s3, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
.LBB0_2:
v_mov_b32_e32 v2, s3
s_add_i32 s3, s3, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s3, 0x1000
ds_store_b32 v2, v1
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_mad_u64_u32 v[1:2], null, s15, 0x3e8, v[0:1]
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_store_b32 v0, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s15, 10
s_mov_b32 s1, 0
v_mov_b32_e32 v0, 0
s_lshl_b64 s[4:5], s[0:1], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
.LBB0_5:
v_mov_b32_e32 v1, s1
s_add_i32 s1, s1, 4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_lg_i32 s1, 0x1000
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPi, .Lfunc_end0-_Z6kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
//#define NUM_BINS 64 // We are also going to use this for the number of threads in a block.
#define NUM_BINS 1024 // We are also going to use this for the number of threads in a block.
#define NUM_THREADS_PER_BLOCK 16
#define NUM_BLOCKS 16
////////////////////////////////////////////////////////////////////////////////
// Took this code from a Dr. Dobbs example.
////////////////////////////////////////////////////////////////////////////////
void checkCUDAError(const char *msg)
{
hipError_t err = hipGetLastError();
if( hipSuccess != err)
{
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
////////////////////////////////////////////////////////////////////////////////
// The kernel.
////////////////////////////////////////////////////////////////////////////////
__global__ void kernel (int *dev_hist)
{
int tid = threadIdx.x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
// shared memory
__shared__ int shared_hist[NUM_BINS];
// access thread id
//const unsigned int tid = threadIdx.x;
// access number of threads in this block
const unsigned int num_threads = blockDim.x;
// Note that we only clear things out for the first thread on each block.
if(threadIdx.x==0)
{
for (int i=0;i<NUM_BINS;i++)
shared_hist[i] = 0;
}
__syncthreads();
////////////////////////////////////////////////////////////////////////
// FILL THE ARRAYS
shared_hist[tid] = blockIdx.x*1000 + tid;
//shared_hist[tid] = blockIdx.x;
__syncthreads();
if(threadIdx.x==0)
{
for(int i=0;i<NUM_BINS;i++)
{
dev_hist[i+(blockIdx.x*(NUM_BINS))]=shared_hist[i];
}
}
}
////////////////////////////////////////////////////////////////////////////////
// The main() program.
////////////////////////////////////////////////////////////////////////////////
int main()
{
int nbins = NUM_BINS;
int dimx = NUM_BLOCKS; // Number of blocks
int num_bytes = NUM_BINS*sizeof(int);
int num_bytes_on_gpu = dimx*NUM_BINS*sizeof(int);
int *d_a=0, *h_a=0, *h_hist=0; // device and host pointers
// Allocate memory on host (CPU)
h_a = (int*)malloc(num_bytes_on_gpu);
h_hist = (int*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_a,num_bytes_on_gpu);
checkCUDAError("malloc");
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_a)
{
printf("Couldn't allocate host memory\n");
return 1;
}
if (0==d_a)
{
printf("Couldn't allocate device memory\n");
return 1;
}
// Initialize array to all 0's
hipMemset(d_a,0,num_bytes_on_gpu);
checkCUDAError("memset");
//-----------------------------------------------------------------------//
// Some explanatory code
/*
// This will give us 256 thread blocks, arranged in a 16x16 grid.
dim3 grid(16,16);
// This will give us 256 threads/block, arranged in a 16x16 grid.
dim3 block(16,16);
kernel<<<grid,block,0,0>>>(XXX);
// This is a shortcut for launching some thread blocks.
// It launches a grid of 32 thread blocks arranged in a 1x32 grid
// and 512 threads per block, arranged in a 1x512 array.
kernel<<<32,512>>>(YYY);
*/
//dim3 grid,block;
//block.x = 8;
//grid.x = dimx/block.x;
//kernel<<<grid,block>>>(d_a);
//kernel<<<4,16>>>(d_a);
dim3 grid, block;
grid.x = NUM_BLOCKS; // Number of blocks
block.x = NUM_BINS; // Number of threads per block.
kernel<<<grid,block>>>(d_a);
hipDeviceSynchronize();
checkCUDAError("kernel");
// Copy it back over
hipMemcpy(h_a,d_a,num_bytes_on_gpu,hipMemcpyDeviceToHost);
for (int i=0;i<dimx;i++)
{
for (int j=0;j<NUM_BINS;j++)
{
printf("%d ",h_a[i*NUM_BINS + j]);
}
printf("\n");
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} | .text
.file "testing_size_of_shared_memory.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPi, .Lfunc_end1-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z14checkCUDAErrorPKc.exit
testq %rbx, %rbx
je .LBB2_4
# %bb.6:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_7
# %bb.8:
movl $65536, %edx # imm = 0x10000
xorl %esi, %esi
callq hipMemset
callq hipGetLastError
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_Z14checkCUDAErrorPKc.exit30
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 1008(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_13
# %bb.14: # %_Z14checkCUDAErrorPKc.exit32
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_16 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_16: # Parent Loop BB2_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB2_16
# %bb.17: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $16, %r15
jne .LBB2_15
# %bb.18:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB2_19
.LBB2_4:
movl $.Lstr.1, %edi
jmp .LBB2_5
.LBB2_7:
movl $.Lstr, %edi
.LBB2_5:
callq puts@PLT
movl $1, %eax
.LBB2_19:
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB2_2
.LBB2_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
jmp .LBB2_2
.LBB2_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "malloc"
.size .L.str.1, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memset"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Couldn't allocate device memory"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Couldn't allocate host memory"
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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