system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009d04b_00000000-6_testing_size_of_shared_memory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z25__device_stub__Z6kernelPiPi
.type _Z25__device_stub__Z6kernelPiPi, @function
_Z25__device_stub__Z6kernelPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z6kernelPiPi, .-_Z25__device_stub__Z6kernelPiPi
.globl _Z6kernelPi
.type _Z6kernelPi, @function
_Z6kernelPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPi, .-_Z6kernelPi
.section .rodata.str1.1
.LC1:
.string "malloc"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Couldn't allocate host memory\n"
.align 8
.LC3:
.string "Couldn't allocate device memory\n"
.section .rodata.str1.1
.LC4:
.string "memset"
.LC5:
.string "kernel"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movl $65536, %edi
call malloc@PLT
movq %rax, %r15
leaq 8(%rsp), %rdi
movl $65536, %esi
call cudaMalloc@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
testq %r15, %r15
je .L26
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .L27
movl $65536, %edx
movl $0, %esi
call cudaMemset@PLT
leaq .LC4(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, 20(%rsp)
movl $1, 32(%rsp)
movl $16, 16(%rsp)
movl $1024, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L19:
call cudaThreadSynchronize@PLT
leaq .LC5(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $65536, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq 4096(%r15), %rbp
leaq 69632(%r15), %r14
leaq .LC6(%rip), %r12
leaq .LC7(%rip), %r13
.L20:
leaq -4096(%rbp), %rbx
.L21:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L21
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4096, %rbp
cmpq %r14, %rbp
jne .L20
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L15:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L29
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L27:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L15
.L28:
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6kernelPiPi
jmp .L19
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "testing_size_of_shared_memory.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPi,@function
_Z21__device_stub__kernelPi: # @_Z21__device_stub__kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPi, .Lfunc_end1-_Z21__device_stub__kernelPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, 8(%rsp)
movl $65536, %edi # imm = 0x10000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $65536, %esi # imm = 0x10000
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z14checkCUDAErrorPKc.exit
testq %rbx, %rbx
je .LBB2_4
# %bb.6:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB2_7
# %bb.8:
movl $65536, %edx # imm = 0x10000
xorl %esi, %esi
callq hipMemset
callq hipGetLastError
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_Z14checkCUDAErrorPKc.exit30
movabsq $4294967312, %rdi # imm = 0x100000010
leaq 1008(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB2_13
# %bb.14: # %_Z14checkCUDAErrorPKc.exit32
movq 8(%rsp), %rsi
movl $65536, %edx # imm = 0x10000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_16 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_16: # Parent Loop BB2_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB2_16
# %bb.17: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addq $4096, %r14 # imm = 0x1000
cmpq $16, %r15
jne .LBB2_15
# %bb.18:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB2_19
.LBB2_4:
movl $.Lstr.1, %edi
jmp .LBB2_5
.LBB2_7:
movl $.Lstr, %edi
.LBB2_5:
callq puts@PLT
movl $1, %eax
.LBB2_19:
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB2_2
.LBB2_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.4, %edx
jmp .LBB2_2
.LBB2_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.5, %edx
.LBB2_2:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type _Z6kernelPi,@object # @_Z6kernelPi
.section .rodata,"a",@progbits
.globl _Z6kernelPi
.p2align 3, 0x0
_Z6kernelPi:
.quad _Z21__device_stub__kernelPi
.size _Z6kernelPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "malloc"
.size .L.str.1, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memset"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "kernel"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Couldn't allocate device memory"
.size .Lstr, 32
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Couldn't allocate host memory"
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
cudaMalloc((void**)&dev_a,N*sizeof(int));
cudaMalloc((void**)&dev_b,N*sizeof(int));
cudaMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
cudaEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z6addvecPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x3e7, PT ; /* 0x000003e70600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
cudaMalloc((void**)&dev_a,N*sizeof(int));
cudaMalloc((void**)&dev_b,N*sizeof(int));
cudaMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
cudaEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_001236da_00000000-6_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6addvecPiS_S_PiS_S_
.type _Z29__device_stub__Z6addvecPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addvecPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6addvecPiS_S_PiS_S_, .-_Z29__device_stub__Z6addvecPiS_S_PiS_S_
.globl _Z6addvecPiS_S_
.type _Z6addvecPiS_S_, @function
_Z6addvecPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addvecPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPiS_S_, .-_Z6addvecPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time : %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8200
orq $0, (%rsp)
subq $3896, %rsp
.cfi_def_cfa_offset 12096
movq %fs:40, %rax
movq %rax, 12072(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
leal 1(%rax), %edx
movl %edx, 4064(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4064(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 8064(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 12072(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $12088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6addvecPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addvecPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
cudaMalloc((void**)&dev_a,N*sizeof(int));
cudaMalloc((void**)&dev_b,N*sizeof(int));
cudaMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
cudaEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
cudaMemcpy(dev_a,a,N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b,b,N*sizeof(int),cudaMemcpyHostToDevice);
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
cudaMemcpy(c,dev_c,N*sizeof(int),cudaMemcpyDeviceToHost);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
hipMalloc((void**)&dev_a,N*sizeof(int));
hipMalloc((void**)&dev_b,N*sizeof(int));
hipMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
hipEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
hipMalloc((void**)&dev_a,N*sizeof(int));
hipMalloc((void**)&dev_b,N*sizeof(int));
hipMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
hipEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPiS_S_
.globl _Z6addvecPiS_S_
.p2align 8
.type _Z6addvecPiS_S_,@function
_Z6addvecPiS_S_:
s_cmpk_gt_i32 s15, 0x3e7
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPiS_S_, .Lfunc_end0-_Z6addvecPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6addvecPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N 1000
__global__ void addvec(int *a, int *b, int *c)
{
int tid=blockIdx.x; //manejar los datos a este índice
if(tid<N)
c[tid]=a[tid]+b[tid];
}
//función principal
int main(void){
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
//asignar memoria en la GPU
hipMalloc((void**)&dev_a,N*sizeof(int));
hipMalloc((void**)&dev_b,N*sizeof(int));
hipMalloc((void**)&dev_c,N*sizeof(int));
//Llenar datos a los arreglos 'a' y 'b' en la CPU
for(int i=0; i<N;i++){
a[i]=i;
b[i]=i+1;
}
//GPU Time
hipEvent_t start, stop;
float time;
//copiar el arreglo 'a' y 'b' en la GPU
hipMemcpy(dev_a,a,N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b,b,N*sizeof(int),hipMemcpyHostToDevice);
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//lanzar el kernel
addvec<<<N,1>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
//copiar el arreglo 'c' de la GPU a la CPU
hipMemcpy(c,dev_c,N*sizeof(int),hipMemcpyDeviceToHost);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "addition.hip"
.globl _Z21__device_stub__addvecPiS_S_ # -- Begin function _Z21__device_stub__addvecPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addvecPiS_S_,@function
_Z21__device_stub__addvecPiS_S_: # @_Z21__device_stub__addvecPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPiS_S_, .Lfunc_end0-_Z21__device_stub__addvecPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $12120, %rsp # imm = 0x2F58
.cfi_def_cfa_offset 12128
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 8112(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 4112(%rsp,%rax,4)
movq %rcx, %rax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
leaq 8112(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4112(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addvecPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12120, %rsp # imm = 0x2F58
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPiS_S_,@object # @_Z6addvecPiS_S_
.section .rodata,"a",@progbits
.globl _Z6addvecPiS_S_
.p2align 3, 0x0
_Z6addvecPiS_S_:
.quad _Z21__device_stub__addvecPiS_S_
.size _Z6addvecPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %f ms\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6addvecPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x3e7, PT ; /* 0x000003e70600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6addvecPiS_S_
.globl _Z6addvecPiS_S_
.p2align 8
.type _Z6addvecPiS_S_,@function
_Z6addvecPiS_S_:
s_cmpk_gt_i32 s15, 0x3e7
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addvecPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6addvecPiS_S_, .Lfunc_end0-_Z6addvecPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addvecPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z6addvecPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001236da_00000000-6_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6addvecPiS_S_PiS_S_
.type _Z29__device_stub__Z6addvecPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addvecPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addvecPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6addvecPiS_S_PiS_S_, .-_Z29__device_stub__Z6addvecPiS_S_PiS_S_
.globl _Z6addvecPiS_S_
.type _Z6addvecPiS_S_, @function
_Z6addvecPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addvecPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6addvecPiS_S_, .-_Z6addvecPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Time : %f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8200
orq $0, (%rsp)
subq $3896, %rsp
.cfi_def_cfa_offset 12096
movq %fs:40, %rax
movq %rax, 12072(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
leal 1(%rax), %edx
movl %edx, 4064(%rsp,%rax,4)
addq $1, %rax
cmpq $1000, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 4064(%rsp), %rsi
movl $1, %ecx
movl $4000, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1000, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 8064(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 12072(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $12088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6addvecPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6addvecPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addvecPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addition.hip"
.globl _Z21__device_stub__addvecPiS_S_ # -- Begin function _Z21__device_stub__addvecPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addvecPiS_S_,@function
_Z21__device_stub__addvecPiS_S_: # @_Z21__device_stub__addvecPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addvecPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__addvecPiS_S_, .Lfunc_end0-_Z21__device_stub__addvecPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $12120, %rsp # imm = 0x2F58
.cfi_def_cfa_offset 12128
leaq 24(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 8112(%rsp,%rax,4)
leaq 1(%rax), %rcx
movl %ecx, 4112(%rsp,%rax,4)
movq %rcx, %rax
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
leaq 8112(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 4112(%rsp), %rsi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 999(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addvecPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
leaq 112(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $12120, %rsp # imm = 0x2F58
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addvecPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6addvecPiS_S_,@object # @_Z6addvecPiS_S_
.section .rodata,"a",@progbits
.globl _Z6addvecPiS_S_
.p2align 3, 0x0
_Z6addvecPiS_S_:
.quad _Z21__device_stub__addvecPiS_S_
.size _Z6addvecPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %f ms\n"
.size .L.str, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6addvecPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__addvecPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6addvecPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} | code for sm_80
Function : _Z24kernelCalculateHistogramPjPhll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06070 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fca00078e00ff */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20003f06300 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fd800078e0203 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R9, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000097a10 */
/* 0x000fe40007f1e0ff */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*00d0*/ IADD3.X R11, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00020b7a10 */
/* 0x000fe400007fe4ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0100*/ BSSY B0, 0x1b0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0110*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06300 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R5, R2, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x000fca00007fe4ff */
/*0150*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1100 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x004fca00078e0003 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0001e4000c10e184 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*01d0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x001fc80000011400 */
/*01e0*/ ISETP.GT.AND.EX P0, PT, R11, R2, PT, P0 ; /* 0x000000020b00720c */
/* 0x000fda0003f04300 */
/*01f0*/ @P0 BRA 0xe0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} | .file "tmpxft_001b9132_00000000-6_kernelCalculateHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
.type _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll, @function
_Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24kernelCalculateHistogramPjPhll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll, .-_Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
.globl _Z24kernelCalculateHistogramPjPhll
.type _Z24kernelCalculateHistogramPjPhll, @function
_Z24kernelCalculateHistogramPjPhll:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24kernelCalculateHistogramPjPhll, .-_Z24kernelCalculateHistogramPjPhll
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24kernelCalculateHistogramPjPhll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kernelCalculateHistogramPjPhll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24kernelCalculateHistogramPjPhll
.globl _Z24kernelCalculateHistogramPjPhll
.p2align 8
.type _Z24kernelCalculateHistogramPjPhll,@function
_Z24kernelCalculateHistogramPjPhll:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v2, vcc_lo, v0, s2
s_mov_b32 s2, exec_lo
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 v[2:3], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v4, 1
s_mov_b32 s2, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_le_i64_e32 vcc_lo, v[2:3], v[0:1]
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
.LBB0_3:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i64_e64 s[0:1], v[0:1]
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
global_load_u8 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
global_atomic_add_u32 v1, v4, s[4:5]
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24kernelCalculateHistogramPjPhll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24kernelCalculateHistogramPjPhll, .Lfunc_end0-_Z24kernelCalculateHistogramPjPhll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24kernelCalculateHistogramPjPhll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24kernelCalculateHistogramPjPhll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelCalculateHistogram(unsigned int* histogram, unsigned char* rawPixels, long chunkSize, long totalPixels)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
int startPosition = id * chunkSize;
for (int i = startPosition; i < (startPosition + chunkSize); i++) {
if (i < totalPixels) {
int pixelValue = (int)rawPixels[i];
atomicAdd(&histogram[pixelValue], 1);
}
}
} | .text
.file "kernelCalculateHistogram.hip"
.globl _Z39__device_stub__kernelCalculateHistogramPjPhll # -- Begin function _Z39__device_stub__kernelCalculateHistogramPjPhll
.p2align 4, 0x90
.type _Z39__device_stub__kernelCalculateHistogramPjPhll,@function
_Z39__device_stub__kernelCalculateHistogramPjPhll: # @_Z39__device_stub__kernelCalculateHistogramPjPhll
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernelCalculateHistogramPjPhll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__kernelCalculateHistogramPjPhll, .Lfunc_end0-_Z39__device_stub__kernelCalculateHistogramPjPhll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kernelCalculateHistogramPjPhll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kernelCalculateHistogramPjPhll,@object # @_Z24kernelCalculateHistogramPjPhll
.section .rodata,"a",@progbits
.globl _Z24kernelCalculateHistogramPjPhll
.p2align 3, 0x0
_Z24kernelCalculateHistogramPjPhll:
.quad _Z39__device_stub__kernelCalculateHistogramPjPhll
.size _Z24kernelCalculateHistogramPjPhll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kernelCalculateHistogramPjPhll"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kernelCalculateHistogramPjPhll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kernelCalculateHistogramPjPhll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24kernelCalculateHistogramPjPhll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06070 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff027624 */
/* 0x000fca00078e00ff */
/*0060*/ ISETP.GE.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20003f06300 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fd800078e0203 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a24 */
/* 0x000fe200078e02ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00b0*/ IADD3 R9, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000097a10 */
/* 0x000fe40007f1e0ff */
/*00c0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*00d0*/ IADD3.X R11, R2, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00020b7a10 */
/* 0x000fe400007fe4ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0100*/ BSSY B0, 0x1b0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0110*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x17c], PT, P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0003f06300 */
/*0120*/ @P0 BRA 0x1a0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0140*/ IADD3.X R5, R2, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0002057a10 */
/* 0x000fca00007fe4ff */
/*0150*/ LDG.E.U8 R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1100 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x004fca00078e0003 */
/*0190*/ RED.E.ADD.STRONG.GPU [R2.64], R7 ; /* 0x000000070200798e */
/* 0x0001e4000c10e184 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*01d0*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x001fc80000011400 */
/*01e0*/ ISETP.GT.AND.EX P0, PT, R11, R2, PT, P0 ; /* 0x000000020b00720c */
/* 0x000fda0003f04300 */
/*01f0*/ @P0 BRA 0xe0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24kernelCalculateHistogramPjPhll
.globl _Z24kernelCalculateHistogramPjPhll
.p2align 8
.type _Z24kernelCalculateHistogramPjPhll,@function
_Z24kernelCalculateHistogramPjPhll:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mul_lo_u32 v0, v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v2, vcc_lo, v0, s2
s_mov_b32 s2, exec_lo
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i64_e64 v[2:3], v[0:1]
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v4, 1
s_mov_b32 s2, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_cmp_le_i64_e32 vcc_lo, v[2:3], v[0:1]
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
.LBB0_3:
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i64_e64 s[0:1], v[0:1]
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
global_load_u8 v1, v[5:6], off
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
global_atomic_add_u32 v1, v4, s[4:5]
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24kernelCalculateHistogramPjPhll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24kernelCalculateHistogramPjPhll, .Lfunc_end0-_Z24kernelCalculateHistogramPjPhll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24kernelCalculateHistogramPjPhll
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24kernelCalculateHistogramPjPhll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b9132_00000000-6_kernelCalculateHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
.type _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll, @function
_Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24kernelCalculateHistogramPjPhll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll, .-_Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
.globl _Z24kernelCalculateHistogramPjPhll
.type _Z24kernelCalculateHistogramPjPhll, @function
_Z24kernelCalculateHistogramPjPhll:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z24kernelCalculateHistogramPjPhllPjPhll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24kernelCalculateHistogramPjPhll, .-_Z24kernelCalculateHistogramPjPhll
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24kernelCalculateHistogramPjPhll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24kernelCalculateHistogramPjPhll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelCalculateHistogram.hip"
.globl _Z39__device_stub__kernelCalculateHistogramPjPhll # -- Begin function _Z39__device_stub__kernelCalculateHistogramPjPhll
.p2align 4, 0x90
.type _Z39__device_stub__kernelCalculateHistogramPjPhll,@function
_Z39__device_stub__kernelCalculateHistogramPjPhll: # @_Z39__device_stub__kernelCalculateHistogramPjPhll
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24kernelCalculateHistogramPjPhll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__kernelCalculateHistogramPjPhll, .Lfunc_end0-_Z39__device_stub__kernelCalculateHistogramPjPhll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24kernelCalculateHistogramPjPhll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24kernelCalculateHistogramPjPhll,@object # @_Z24kernelCalculateHistogramPjPhll
.section .rodata,"a",@progbits
.globl _Z24kernelCalculateHistogramPjPhll
.p2align 3, 0x0
_Z24kernelCalculateHistogramPjPhll:
.quad _Z39__device_stub__kernelCalculateHistogramPjPhll
.size _Z24kernelCalculateHistogramPjPhll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24kernelCalculateHistogramPjPhll"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__kernelCalculateHistogramPjPhll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24kernelCalculateHistogramPjPhll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} | code for sm_80
Function : _Z17initTempNodeArrayiiPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0050*/ UIADD3 UR4, UR4, UR7, URZ ; /* 0x0000000704047290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ ULEA UR5, UR4, 0x1, 0x1 ; /* 0x0000000104057891 */
/* 0x000fc8000f8e083f */
/*0080*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0100*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0170*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0180*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0190*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fe400078e0206 */
/*01e0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc600078e0209 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0210*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe20003f06070 */
/*0240*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fd800078e0209 */
/*0250*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0003 */
/*0270*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0209 */
/*0280*/ @!P1 IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0a9210 */
/* 0x000fe20007ffe1ff */
/*0290*/ IMAD.WIDE R8, R0, R9, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fe200078e0209 */
/*02a0*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff0aaa12 */
/* 0x000fc800078e33ff */
/*02b0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x000fda0003f04270 */
/*02c0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x7530 ; /* 0xffff8ad0ff0b8424 */
/* 0x000fca00078e00ff */
/*02d0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101906 */
/*02e0*/ @!P0 STG.E [R4.64], R11 ; /* 0x0000000b04008986 */
/* 0x0001e8000c101906 */
/*02f0*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101906 */
/*0300*/ @!P0 STG.E [R8.64], R11 ; /* 0x0000000b08008986 */
/* 0x0001e2000c101906 */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fda000bf05270 */
/*0330*/ @!P0 BRA 0x3d0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, -R10, UR4, RZ ; /* 0x000000040a007c10 */
/* 0x000fc8000fffe1ff */
/*0350*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0360*/ IADD3 R11, R0.reuse, -0x5, RZ ; /* 0xfffffffb000b7810 */
/* 0x041fe40007ffe0ff */
/*0370*/ IADD3 R13, R0, -0xa, RZ ; /* 0xfffffff6000d7810 */
/* 0x000fc60007ffe0ff */
/*0380*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101906 */
/*0390*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101906 */
/*03a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101906 */
/*03b0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R11, RZ, RZ, -0x5 ; /* 0xfffffffbff0b7424 */
/* 0x001fe200078e00ff */
/*03e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101906 */
/*03f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101906 */
/*0400*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101906 */
/*0410*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} | .file "tmpxft_000fe717_00000000-6_initTempNodeArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
.type _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_, @function
_Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17initTempNodeArrayiiPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_, .-_Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
.globl _Z17initTempNodeArrayiiPiS_S_S_
.type _Z17initTempNodeArrayiiPiS_S_S_, @function
_Z17initTempNodeArrayiiPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17initTempNodeArrayiiPiS_S_S_, .-_Z17initTempNodeArrayiiPiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17initTempNodeArrayiiPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17initTempNodeArrayiiPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17initTempNodeArrayiiPiS_S_S_
.globl _Z17initTempNodeArrayiiPiS_S_S_
.p2align 8
.type _Z17initTempNodeArrayiiPiS_S_S_,@function
_Z17initTempNodeArrayiiPiS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_add_i32 s6, s5, 1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_lshl_b32 s2, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, 1
s_mul_i32 s2, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v3
v_cmp_ge_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0xffff8ad0
s_movk_i32 s5, 0x8ad0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_3:
s_or_saveexec_b32 s4, s4
v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v0, s5
v_mov_b32_e32 v4, s5
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e64 s6, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_6
v_sub_nc_u32_e32 v0, s6, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_nc_u32_e32 v0, -5, v7
v_add_nc_u32_e32 v3, -10, v7
global_store_b32 v[5:6], v0, off
.LBB0_6:
s_or_saveexec_b32 s5, s5
v_mov_b32_e32 v4, s7
s_xor_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, -5
v_mov_b32_e32 v0, -5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[5:6], v4, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[5:6], v3, off
global_store_b32 v[7:8], v0, off
global_store_b32 v[1:2], v4, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17initTempNodeArrayiiPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17initTempNodeArrayiiPiS_S_S_, .Lfunc_end0-_Z17initTempNodeArrayiiPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17initTempNodeArrayiiPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17initTempNodeArrayiiPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initTempNodeArray( const int hitNum, const int allowableGap, int* tempNodeArray_score, int* tempNodeArray_vertical, int* tempNodeArray_horizontal, int* tempNodeArray_matchNum) {
const int bIdx = gridDim.x * blockIdx.y + blockIdx.x;
const int idx = blockDim.x * bIdx + threadIdx.x;
const int halfTempNodeWidth = allowableGap + MARGIN;
const int tempNodeWidth = 1 + 2 * halfTempNodeWidth;
if(idx < hitNum * tempNodeWidth) {
const int bandIdx = idx / hitNum;
if(bandIdx < halfTempNodeWidth) {
tempNodeArray_score [idx] = -30000;
tempNodeArray_vertical [idx] = -30000;
tempNodeArray_horizontal[idx] = -30000;
tempNodeArray_matchNum [idx] = -30000;
} else if(bandIdx == halfTempNodeWidth) {
tempNodeArray_score [idx] = 0;
tempNodeArray_vertical [idx] = GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = GAP_OPEN_POINT;
tempNodeArray_matchNum [idx] = 0;
} else {
const int i = bandIdx - halfTempNodeWidth;
const int tempScore = i * GAP_POINT + GAP_OPEN_POINT;
tempNodeArray_score [idx] = tempScore;
tempNodeArray_vertical [idx] = tempScore + GAP_OPEN_POINT;
tempNodeArray_horizontal[idx] = tempScore;
tempNodeArray_matchNum [idx] = 0;
}
}
} | .text
.file "initTempNodeArray.hip"
.globl _Z32__device_stub__initTempNodeArrayiiPiS_S_S_ # -- Begin function _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.p2align 4, 0x90
.type _Z32__device_stub__initTempNodeArrayiiPiS_S_S_,@function
_Z32__device_stub__initTempNodeArrayiiPiS_S_S_: # @_Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17initTempNodeArrayiiPiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__initTempNodeArrayiiPiS_S_S_, .Lfunc_end0-_Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17initTempNodeArrayiiPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17initTempNodeArrayiiPiS_S_S_,@object # @_Z17initTempNodeArrayiiPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z17initTempNodeArrayiiPiS_S_S_
.p2align 3, 0x0
_Z17initTempNodeArrayiiPiS_S_S_:
.quad _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.size _Z17initTempNodeArrayiiPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17initTempNodeArrayiiPiS_S_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17initTempNodeArrayiiPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17initTempNodeArrayiiPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0050*/ UIADD3 UR4, UR4, UR7, URZ ; /* 0x0000000704047290 */
/* 0x000fc6000fffe03f */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0070*/ ULEA UR5, UR4, 0x1, 0x1 ; /* 0x0000000104057891 */
/* 0x000fc8000f8e083f */
/*0080*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fe2000f8e023f */
/*0090*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IABS R5, c[0x0][0x160] ; /* 0x0000580000057a13 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0100*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0170*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0180*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0190*/ LOP3.LUT R2, R0, c[0x0][0x160], RZ, 0x3c, !PT ; /* 0x0000580000027a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fca00078e00ff */
/*01c0*/ IADD3 R4, -R3, RZ, RZ ; /* 0x000000ff03047210 */
/* 0x000fca0007ffe1ff */
/*01d0*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fe400078e0206 */
/*01e0*/ IMAD.WIDE R6, R0, R9, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fc600078e0209 */
/*01f0*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*0200*/ @!P2 IMAD.IADD R4, R4, 0x1, -R5 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a05 */
/*0210*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe20003f06070 */
/*0240*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fd800078e0209 */
/*0250*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0260*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0003 */
/*0270*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc600078e0209 */
/*0280*/ @!P1 IADD3 R10, -R10, RZ, RZ ; /* 0x000000ff0a0a9210 */
/* 0x000fe20007ffe1ff */
/*0290*/ IMAD.WIDE R8, R0, R9, c[0x0][0x180] ; /* 0x0000600000087625 */
/* 0x000fe200078e0209 */
/*02a0*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x160], RZ, 0x33, !PT ; /* 0x00005800ff0aaa12 */
/* 0x000fc800078e33ff */
/*02b0*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x164], PT ; /* 0x000059000a007a0c */
/* 0x000fda0003f04270 */
/*02c0*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, -0x7530 ; /* 0xffff8ad0ff0b8424 */
/* 0x000fca00078e00ff */
/*02d0*/ @!P0 STG.E [R2.64], R11 ; /* 0x0000000b02008986 */
/* 0x0001e8000c101906 */
/*02e0*/ @!P0 STG.E [R4.64], R11 ; /* 0x0000000b04008986 */
/* 0x0001e8000c101906 */
/*02f0*/ @!P0 STG.E [R6.64], R11 ; /* 0x0000000b06008986 */
/* 0x0001e8000c101906 */
/*0300*/ @!P0 STG.E [R8.64], R11 ; /* 0x0000000b08008986 */
/* 0x0001e2000c101906 */
/*0310*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0320*/ ISETP.NE.AND P0, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x000fda000bf05270 */
/*0330*/ @!P0 BRA 0x3d0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0340*/ IADD3 R0, -R10, UR4, RZ ; /* 0x000000040a007c10 */
/* 0x000fc8000fffe1ff */
/*0350*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0360*/ IADD3 R11, R0.reuse, -0x5, RZ ; /* 0xfffffffb000b7810 */
/* 0x041fe40007ffe0ff */
/*0370*/ IADD3 R13, R0, -0xa, RZ ; /* 0xfffffff6000d7810 */
/* 0x000fc60007ffe0ff */
/*0380*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101906 */
/*0390*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101906 */
/*03a0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101906 */
/*03b0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*03c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03d0*/ IMAD.MOV.U32 R11, RZ, RZ, -0x5 ; /* 0xfffffffbff0b7424 */
/* 0x001fe200078e00ff */
/*03e0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101906 */
/*03f0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101906 */
/*0400*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe8000c101906 */
/*0410*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x000fe2000c101906 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17initTempNodeArrayiiPiS_S_S_
.globl _Z17initTempNodeArrayiiPiS_S_S_
.p2align 8
.type _Z17initTempNodeArrayiiPiS_S_S_,@function
_Z17initTempNodeArrayiiPiS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_add_i32 s6, s5, 1
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_lshl_b32 s2, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, 1
s_mul_i32 s2, s2, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s3, s3, s2
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s3
s_sub_i32 s4, 0, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v0, v3
v_cmp_ge_i32_e32 vcc_lo, s5, v5
s_and_saveexec_b32 s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_mov_b32_e32 v0, 0xffff8ad0
s_movk_i32 s5, 0x8ad0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_3:
s_or_saveexec_b32 s4, s4
v_dual_mov_b32 v3, s5 :: v_dual_mov_b32 v0, s5
v_mov_b32_e32 v4, s5
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_9
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e64 s6, v5
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_6
v_sub_nc_u32_e32 v0, s6, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 1, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_nc_u32_e32 v0, -5, v7
v_add_nc_u32_e32 v3, -10, v7
global_store_b32 v[5:6], v0, off
.LBB0_6:
s_or_saveexec_b32 s5, s5
v_mov_b32_e32 v4, s7
s_xor_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_8
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, -5
v_mov_b32_e32 v0, -5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_store_b32 v[5:6], v4, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x20
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[5:6], v3, off
global_store_b32 v[7:8], v0, off
global_store_b32 v[1:2], v4, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17initTempNodeArrayiiPiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17initTempNodeArrayiiPiS_S_S_, .Lfunc_end0-_Z17initTempNodeArrayiiPiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17initTempNodeArrayiiPiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17initTempNodeArrayiiPiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fe717_00000000-6_initTempNodeArray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
.type _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_, @function
_Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17initTempNodeArrayiiPiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_, .-_Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
.globl _Z17initTempNodeArrayiiPiS_S_S_
.type _Z17initTempNodeArrayiiPiS_S_S_, @function
_Z17initTempNodeArrayiiPiS_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17initTempNodeArrayiiPiS_S_S_iiPiS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17initTempNodeArrayiiPiS_S_S_, .-_Z17initTempNodeArrayiiPiS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17initTempNodeArrayiiPiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17initTempNodeArrayiiPiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initTempNodeArray.hip"
.globl _Z32__device_stub__initTempNodeArrayiiPiS_S_S_ # -- Begin function _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.p2align 4, 0x90
.type _Z32__device_stub__initTempNodeArrayiiPiS_S_S_,@function
_Z32__device_stub__initTempNodeArrayiiPiS_S_S_: # @_Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17initTempNodeArrayiiPiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__initTempNodeArrayiiPiS_S_S_, .Lfunc_end0-_Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17initTempNodeArrayiiPiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17initTempNodeArrayiiPiS_S_S_,@object # @_Z17initTempNodeArrayiiPiS_S_S_
.section .rodata,"a",@progbits
.globl _Z17initTempNodeArrayiiPiS_S_S_
.p2align 3, 0x0
_Z17initTempNodeArrayiiPiS_S_S_:
.quad _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.size _Z17initTempNodeArrayiiPiS_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17initTempNodeArrayiiPiS_S_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__initTempNodeArrayiiPiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17initTempNodeArrayiiPiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22matproductsharedmemoryPxS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R29, SR_TID.X ; /* 0x00000000001d7919 */
/* 0x000e220000002100 */
/*0020*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000ea20000002600 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe400078e00ff */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, R29 ; /* 0x000000ffff047224 */
/* 0x001fe400078e001d */
/*0070*/ IMAD.U32 R2, RZ, RZ, UR4 ; /* 0x00000004ff027e24 */
/* 0x002fe2000f8e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.WIDE.U32 R10, R7, 0xa, R4 ; /* 0x0000000a070a7825 */
/* 0x004fc800078e0004 */
/*00a0*/ IMAD.WIDE.U32 R4, R7, 0xa, R2 ; /* 0x0000000a07047825 */
/* 0x000fe200078e0002 */
/*00b0*/ LEA R8, P1, R10, c[0x0][0x160], 0x3 ; /* 0x000058000a087a11 */
/* 0x000fc600078218ff */
/*00c0*/ IMAD.WIDE.U32 R6, R29, 0xa, R2 ; /* 0x0000000a1d067825 */
/* 0x000fe200078e0002 */
/*00d0*/ LEA R2, P0, R4, c[0x0][0x170], 0x3 ; /* 0x00005c0004027a11 */
/* 0x000fe400078018ff */
/*00e0*/ LEA.HI.X R9, R10, c[0x0][0x164], R11, 0x3, P1 ; /* 0x000059000a097a11 */
/* 0x000fe400008f1c0b */
/*00f0*/ LEA R12, P2, R6, c[0x0][0x168], 0x3 ; /* 0x00005a00060c7a11 */
/* 0x000fe400078418ff */
/*0100*/ LEA.HI.X R3, R4, c[0x0][0x174], R5, 0x3, P0 ; /* 0x00005d0004037a11 */
/* 0x000fe400000f1c05 */
/*0110*/ LEA.HI.X R13, R6, c[0x0][0x16c], R7, 0x3, P2 ; /* 0x00005b00060d7a11 */
/* 0x000fc600010f1c07 */
/*0120*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101b04 */
/*0130*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ LDG.E.64 R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x000ea4000c1e1b00 */
/*0150*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x004fc400078e02ff */
/*0160*/ IMAD.WIDE.U32 R10, R6, R4, RZ ; /* 0x00000004060a7225 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD R7, R5, R6, R7 ; /* 0x0000000605077224 */
/* 0x000fe400078e0207 */
/*0180*/ IMAD.MOV.U32 R26, RZ, RZ, R10 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e000a */
/*0190*/ IMAD.IADD R27, R11, 0x1, R7 ; /* 0x000000010b1b7824 */
/* 0x000fca00078e0207 */
/*01a0*/ STS.64 [R29.X8], R26 ; /* 0x0000001a1d007388 */
/* 0x000fe80000008a00 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01c0*/ LDG.E.64 R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000ea80000000c00 */
/*01e0*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e280000000c00 */
/*01f0*/ LDS.128 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000e680000000c00 */
/*0200*/ LDS.128 R16, [0x30] ; /* 0x00003000ff107984 */
/* 0x000ee80000000c00 */
/*0210*/ LDS.128 R20, [0x40] ; /* 0x00004000ff147984 */
/* 0x000f220000000c00 */
/*0220*/ IADD3 R0, P0, P1, R6, R4, R24 ; /* 0x0000000406007210 */
/* 0x004fc8000791e018 */
/*0230*/ IADD3.X R7, R7, R5, R25, P0, P1 ; /* 0x0000000507077210 */
/* 0x000fe400007e2419 */
/*0240*/ IADD3 R5, P0, P1, R10, R8, R0 ; /* 0x000000080a057210 */
/* 0x001fc8000791e000 */
/*0250*/ IADD3.X R9, R11, R9, R7, P0, P1 ; /* 0x000000090b097210 */
/* 0x000fe400007e2407 */
/*0260*/ IADD3 R5, P0, P1, R14, R12, R5 ; /* 0x0000000c0e057210 */
/* 0x002fc8000791e005 */
/*0270*/ IADD3.X R13, R15, R13, R9, P0, P1 ; /* 0x0000000d0f0d7210 */
/* 0x000fe400007e2409 */
/*0280*/ IADD3 R5, P0, P1, R18, R16, R5 ; /* 0x0000001012057210 */
/* 0x008fc8000791e005 */
/*0290*/ IADD3.X R17, R19, R17, R13, P0, P1 ; /* 0x0000001113117210 */
/* 0x000fe400007e240d */
/*02a0*/ IADD3 R4, P0, P1, R22, R20, R5 ; /* 0x0000001416047210 */
/* 0x010fc8000791e005 */
/*02b0*/ IADD3.X R5, R23, R21, R17, P0, P1 ; /* 0x0000001517057210 */
/* 0x000fca00007e2411 */
/*02c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22matproductsharedmemoryPxS_S_
.globl _Z22matproductsharedmemoryPxS_S_
.p2align 8
.type _Z22matproductsharedmemoryPxS_S_,@function
_Z22matproductsharedmemoryPxS_S_:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v6, 3, v0
s_mul_i32 s11, s2, 0x50
s_mov_b32 s15, 0
s_mul_hi_u32 s10, s2, 0x50
v_mul_u32_u24_e32 v3, 10, v0
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v3, 3, v3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s8, s11
s_addc_u32 s1, s9, s10
s_lshl_b64 s[2:3], s[14:15], 3
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_add_u32 s4, s4, s11
s_addc_u32 s5, s5, s10
s_add_u32 s2, s2, s6
global_store_b64 v5, v[1:2], s[0:1]
s_addc_u32 s3, s3, s7
global_load_b64 v[0:1], v6, s[4:5]
global_load_b64 v[2:3], v3, s[2:3]
s_mov_b64 s[2:3], 10
s_waitcnt vmcnt(0)
v_mul_lo_u32 v7, v3, v0
v_mul_lo_u32 v1, v2, v1
v_mad_u64_u32 v[3:4], null, v2, v0, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v4, v1, v7
ds_store_b64 v6, v[3:4]
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b64 v[0:1], v5, s[0:1]
.LBB0_1:
v_mov_b32_e32 v2, s15
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_add_i32 s15, s15, 8
s_cmp_lg_u64 s[2:3], 0
ds_load_b64 v[2:3], v2
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
s_cbranch_scc1 .LBB0_1
v_mov_b32_e32 v2, 0
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22matproductsharedmemoryPxS_S_
.amdhsa_group_segment_fixed_size 80
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22matproductsharedmemoryPxS_S_, .Lfunc_end0-_Z22matproductsharedmemoryPxS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 80
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22matproductsharedmemoryPxS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22matproductsharedmemoryPxS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00022211_00000000-6_matMatMul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_
.type _Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_, @function
_Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22matproductsharedmemoryPxS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_, .-_Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_
.globl _Z22matproductsharedmemoryPxS_S_
.type _Z22matproductsharedmemoryPxS_S_, @function
_Z22matproductsharedmemoryPxS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z22matproductsharedmemoryPxS_S_, .-_Z22matproductsharedmemoryPxS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n Product of two matrices:\n "
.LC1:
.string "%Ld\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $2464, %rsp
.cfi_def_cfa_offset 2512
movq %fs:40, %rax
movq %rax, 2456(%rsp)
xorl %eax, %eax
movl $10, %edx
.L12:
leaq -10(%rdx), %rax
.L13:
movq %rax, 48(%rsp,%rax,8)
addq $1, %rax
cmpq %rdx, %rax
jne .L13
addq $10, %rdx
cmpq $110, %rdx
jne .L12
movl $10, %edx
.L14:
leaq -10(%rdx), %rax
.L15:
movq %rax, 848(%rsp,%rax,8)
addq $1, %rax
cmpq %rdx, %rax
jne .L15
addq $10, %rdx
cmpq $110, %rdx
jne .L14
movq %rsp, %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $800, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 848(%rsp), %rsi
movl $1, %ecx
movl $800, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $10, 24(%rsp)
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
leaq 1648(%rsp), %rdi
movl $2, %ecx
movl $800, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1728(%rsp), %rbp
leaq 2528(%rsp), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L18:
leaq -80(%rbp), %rbx
.L19:
movq (%rbx), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L19
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $80, %rbp
cmpq %r14, %rbp
jne .L18
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 2456(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $2464, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z46__device_stub__Z22matproductsharedmemoryPxS_S_PxS_S_
jmp .L17
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z22matproductsharedmemoryPxS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22matproductsharedmemoryPxS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMatMul.hip"
.globl _Z37__device_stub__matproductsharedmemoryPxS_S_ # -- Begin function _Z37__device_stub__matproductsharedmemoryPxS_S_
.p2align 4, 0x90
.type _Z37__device_stub__matproductsharedmemoryPxS_S_,@function
_Z37__device_stub__matproductsharedmemoryPxS_S_: # @_Z37__device_stub__matproductsharedmemoryPxS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22matproductsharedmemoryPxS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z37__device_stub__matproductsharedmemoryPxS_S_, .Lfunc_end0-_Z37__device_stub__matproductsharedmemoryPxS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $2496, %rsp # imm = 0x9C0
.cfi_def_cfa_offset 2528
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $10, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %rsi, 1696(%rsp,%rsi,8)
incq %rsi
decq %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $10, %rax
cmpq $10, %rcx
jne .LBB1_1
# %bb.4: # %.preheader30.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_5: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
movl $10, %edx
movq %rax, %rsi
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_5 Depth=1
# => This Inner Loop Header: Depth=2
movq %rsi, 896(%rsp,%rsi,8)
incq %rsi
decq %rdx
jne .LBB1_6
# %bb.7: # in Loop: Header=BB1_5 Depth=1
incq %rcx
addq $10, %rax
cmpq $10, %rcx
jne .LBB1_5
# %bb.8:
leaq 16(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq %rsp, %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
movq 16(%rsp), %rdi
leaq 1696(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 896(%rsp), %rsi
movl $800, %edx # imm = 0x320
movl $1, %ecx
callq hipMemcpy
movabsq $42949672970, %rdi # imm = 0xA0000000A
movabsq $4294967306, %rdx # imm = 0x10000000A
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22matproductsharedmemoryPxS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
movq (%rsp), %rsi
leaq 96(%rsp), %rbx
movl $800, %edx # imm = 0x320
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_12: # Parent Loop BB1_11 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r15,8), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_12
# %bb.13: # in Loop: Header=BB1_11 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $80, %rbx
cmpq $10, %r14
jne .LBB1_11
# %bb.14:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $2496, %rsp # imm = 0x9C0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22matproductsharedmemoryPxS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22matproductsharedmemoryPxS_S_,@object # @_Z22matproductsharedmemoryPxS_S_
.section .rodata,"a",@progbits
.globl _Z22matproductsharedmemoryPxS_S_
.p2align 3, 0x0
_Z22matproductsharedmemoryPxS_S_:
.quad _Z37__device_stub__matproductsharedmemoryPxS_S_
.size _Z22matproductsharedmemoryPxS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n Product of two matrices:\n "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%Ld\t"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22matproductsharedmemoryPxS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__matproductsharedmemoryPxS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22matproductsharedmemoryPxS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <string>
#include <unordered_map>
#include <unordered_set>
#include <stdlib.h>
#include <vector>
#include <random>
using namespace std;
void printNeighbours(unordered_map<long, unordered_set<long>> neighbours) {
for (auto& n : neighbours) {
cout << n.first << ": ";
for (auto& s : n.second) {
cout << s << " ";
}
cout << endl;
}
}
void printWalks(long** walks, int numNodes, int walkPerNode, int walkLength) {
for (int i = 0; i < numNodes * walkPerNode; i++) {
for (int j = 0; j < walkLength; j++) {
cout << walks[i][j] << " ";
}
cout << endl;
}
}
long findNextNode(unordered_map<long, unordered_set<long>> neighbours, long curNode, long prevNode, double p, double q) {
default_random_engine generator;
vector<long> curNeighbours;
curNeighbours.insert(curNeighbours.end(), neighbours[curNode].begin(), neighbours[curNode].end());
if (prevNode == -1) {
return curNeighbours[rand() % curNeighbours.size()];
} else {
unordered_set<long> prevNeighbours = neighbours[prevNode];
vector<double> weights(curNeighbours.size());
for (int i = 0; i < weights.size(); i++) {
long nextNode = curNeighbours[i];
if (nextNode == prevNode) {
weights[i] = 1.0 / p;
} else if (prevNeighbours.find(nextNode) != prevNeighbours.end()) {
weights[i] = 1.0;
} else {
weights[i] = 1.0 / q;
}
}
discrete_distribution<int> dist(weights.begin(), weights.end());
return curNeighbours[dist(generator)];
}
}
long** generateWalks(unordered_map<long, unordered_set<long>> neighbours, int walkPerNode, int walkLength, double p, double q) {
long** walks = new long*[walkPerNode * neighbours.size()];
int counter = 0;
for (auto& neighbour : neighbours) {
long node = neighbour.first;
for (int i = 0; i < walkPerNode; i++) {
walks[counter + i] = new long[walkLength];
walks[counter + i][0] = node;
int curNode = node;
int prevNode = -1;
for (int j = 1; j < walkLength; j++) {
int nextNode = findNextNode(neighbours, curNode, prevNode, p, q);
walks[counter + i][j] = nextNode;
prevNode = curNode;
curNode = nextNode;
}
}
counter += walkPerNode;
}
return walks;
}
int main(int argc, char* argv[]) {
string fileName;
int walkPerNode = 1;
int walkLength = 10;
double p = 1;
double q = 2;
if (argc == 2) {
fileName = argv[1];
} else {
cerr << "Invalid argument, must provide path to edge list" << endl;
return 1;
}
unordered_map<long, unordered_set<long>> neighbours = {};
ifstream in(fileName);
long s, e;
while (in >> s >> e) {
if (s == e) {
cerr << "Loop edge is not supported" << endl;
return 1;
} else if (s <= 0 || e <= 0) {
cerr << "node must be greater than or equal to 0" << endl;
return 1;
}
if (neighbours.find(s) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[s] = emptySet;
}
if (neighbours.find(e) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[e] = emptySet;
}
neighbours[s].insert(e);
neighbours[e].insert(s);
}
long** cuNeighbours;
cudaMallocManaged(&cuNeighbours, neighbours.size() * sizeof(long*));
long** walks = generateWalks(neighbours, walkPerNode, walkLength, p, q);
printWalks(walks, neighbours.size(), walkPerNode, walkLength);
// clean up
for (int i = 0; i < walkPerNode * neighbours.size(); i++) {
delete[] walks[i];
}
delete[] walks;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <string>
#include <unordered_map>
#include <unordered_set>
#include <stdlib.h>
#include <vector>
#include <random>
using namespace std;
void printNeighbours(unordered_map<long, unordered_set<long>> neighbours) {
for (auto& n : neighbours) {
cout << n.first << ": ";
for (auto& s : n.second) {
cout << s << " ";
}
cout << endl;
}
}
void printWalks(long** walks, int numNodes, int walkPerNode, int walkLength) {
for (int i = 0; i < numNodes * walkPerNode; i++) {
for (int j = 0; j < walkLength; j++) {
cout << walks[i][j] << " ";
}
cout << endl;
}
}
long findNextNode(unordered_map<long, unordered_set<long>> neighbours, long curNode, long prevNode, double p, double q) {
default_random_engine generator;
vector<long> curNeighbours;
curNeighbours.insert(curNeighbours.end(), neighbours[curNode].begin(), neighbours[curNode].end());
if (prevNode == -1) {
return curNeighbours[rand() % curNeighbours.size()];
} else {
unordered_set<long> prevNeighbours = neighbours[prevNode];
vector<double> weights(curNeighbours.size());
for (int i = 0; i < weights.size(); i++) {
long nextNode = curNeighbours[i];
if (nextNode == prevNode) {
weights[i] = 1.0 / p;
} else if (prevNeighbours.find(nextNode) != prevNeighbours.end()) {
weights[i] = 1.0;
} else {
weights[i] = 1.0 / q;
}
}
discrete_distribution<int> dist(weights.begin(), weights.end());
return curNeighbours[dist(generator)];
}
}
long** generateWalks(unordered_map<long, unordered_set<long>> neighbours, int walkPerNode, int walkLength, double p, double q) {
long** walks = new long*[walkPerNode * neighbours.size()];
int counter = 0;
for (auto& neighbour : neighbours) {
long node = neighbour.first;
for (int i = 0; i < walkPerNode; i++) {
walks[counter + i] = new long[walkLength];
walks[counter + i][0] = node;
int curNode = node;
int prevNode = -1;
for (int j = 1; j < walkLength; j++) {
int nextNode = findNextNode(neighbours, curNode, prevNode, p, q);
walks[counter + i][j] = nextNode;
prevNode = curNode;
curNode = nextNode;
}
}
counter += walkPerNode;
}
return walks;
}
int main(int argc, char* argv[]) {
string fileName;
int walkPerNode = 1;
int walkLength = 10;
double p = 1;
double q = 2;
if (argc == 2) {
fileName = argv[1];
} else {
cerr << "Invalid argument, must provide path to edge list" << endl;
return 1;
}
unordered_map<long, unordered_set<long>> neighbours = {};
ifstream in(fileName);
long s, e;
while (in >> s >> e) {
if (s == e) {
cerr << "Loop edge is not supported" << endl;
return 1;
} else if (s <= 0 || e <= 0) {
cerr << "node must be greater than or equal to 0" << endl;
return 1;
}
if (neighbours.find(s) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[s] = emptySet;
}
if (neighbours.find(e) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[e] = emptySet;
}
neighbours[s].insert(e);
neighbours[e].insert(s);
}
long** cuNeighbours;
cudaMallocManaged(&cuNeighbours, neighbours.size() * sizeof(long*));
long** walks = generateWalks(neighbours, walkPerNode, walkLength, p, q);
printWalks(walks, neighbours.size(), walkPerNode, walkLength);
// clean up
for (int i = 0; i < walkPerNode * neighbours.size(); i++) {
delete[] walks[i];
}
delete[] walks;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <unordered_map>
#include <unordered_set>
#include <stdlib.h>
#include <vector>
#include <random>
using namespace std;
void printNeighbours(unordered_map<long, unordered_set<long>> neighbours) {
for (auto& n : neighbours) {
cout << n.first << ": ";
for (auto& s : n.second) {
cout << s << " ";
}
cout << endl;
}
}
void printWalks(long** walks, int numNodes, int walkPerNode, int walkLength) {
for (int i = 0; i < numNodes * walkPerNode; i++) {
for (int j = 0; j < walkLength; j++) {
cout << walks[i][j] << " ";
}
cout << endl;
}
}
long findNextNode(unordered_map<long, unordered_set<long>> neighbours, long curNode, long prevNode, double p, double q) {
default_random_engine generator;
vector<long> curNeighbours;
curNeighbours.insert(curNeighbours.end(), neighbours[curNode].begin(), neighbours[curNode].end());
if (prevNode == -1) {
return curNeighbours[rand() % curNeighbours.size()];
} else {
unordered_set<long> prevNeighbours = neighbours[prevNode];
vector<double> weights(curNeighbours.size());
for (int i = 0; i < weights.size(); i++) {
long nextNode = curNeighbours[i];
if (nextNode == prevNode) {
weights[i] = 1.0 / p;
} else if (prevNeighbours.find(nextNode) != prevNeighbours.end()) {
weights[i] = 1.0;
} else {
weights[i] = 1.0 / q;
}
}
discrete_distribution<int> dist(weights.begin(), weights.end());
return curNeighbours[dist(generator)];
}
}
long** generateWalks(unordered_map<long, unordered_set<long>> neighbours, int walkPerNode, int walkLength, double p, double q) {
long** walks = new long*[walkPerNode * neighbours.size()];
int counter = 0;
for (auto& neighbour : neighbours) {
long node = neighbour.first;
for (int i = 0; i < walkPerNode; i++) {
walks[counter + i] = new long[walkLength];
walks[counter + i][0] = node;
int curNode = node;
int prevNode = -1;
for (int j = 1; j < walkLength; j++) {
int nextNode = findNextNode(neighbours, curNode, prevNode, p, q);
walks[counter + i][j] = nextNode;
prevNode = curNode;
curNode = nextNode;
}
}
counter += walkPerNode;
}
return walks;
}
int main(int argc, char* argv[]) {
string fileName;
int walkPerNode = 1;
int walkLength = 10;
double p = 1;
double q = 2;
if (argc == 2) {
fileName = argv[1];
} else {
cerr << "Invalid argument, must provide path to edge list" << endl;
return 1;
}
unordered_map<long, unordered_set<long>> neighbours = {};
ifstream in(fileName);
long s, e;
while (in >> s >> e) {
if (s == e) {
cerr << "Loop edge is not supported" << endl;
return 1;
} else if (s <= 0 || e <= 0) {
cerr << "node must be greater than or equal to 0" << endl;
return 1;
}
if (neighbours.find(s) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[s] = emptySet;
}
if (neighbours.find(e) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[e] = emptySet;
}
neighbours[s].insert(e);
neighbours[e].insert(s);
}
long** cuNeighbours;
hipMallocManaged(&cuNeighbours, neighbours.size() * sizeof(long*));
long** walks = generateWalks(neighbours, walkPerNode, walkLength, p, q);
printWalks(walks, neighbours.size(), walkPerNode, walkLength);
// clean up
for (int i = 0; i < walkPerNode * neighbours.size(); i++) {
delete[] walks[i];
}
delete[] walks;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <string>
#include <unordered_map>
#include <unordered_set>
#include <stdlib.h>
#include <vector>
#include <random>
using namespace std;
void printNeighbours(unordered_map<long, unordered_set<long>> neighbours) {
for (auto& n : neighbours) {
cout << n.first << ": ";
for (auto& s : n.second) {
cout << s << " ";
}
cout << endl;
}
}
void printWalks(long** walks, int numNodes, int walkPerNode, int walkLength) {
for (int i = 0; i < numNodes * walkPerNode; i++) {
for (int j = 0; j < walkLength; j++) {
cout << walks[i][j] << " ";
}
cout << endl;
}
}
long findNextNode(unordered_map<long, unordered_set<long>> neighbours, long curNode, long prevNode, double p, double q) {
default_random_engine generator;
vector<long> curNeighbours;
curNeighbours.insert(curNeighbours.end(), neighbours[curNode].begin(), neighbours[curNode].end());
if (prevNode == -1) {
return curNeighbours[rand() % curNeighbours.size()];
} else {
unordered_set<long> prevNeighbours = neighbours[prevNode];
vector<double> weights(curNeighbours.size());
for (int i = 0; i < weights.size(); i++) {
long nextNode = curNeighbours[i];
if (nextNode == prevNode) {
weights[i] = 1.0 / p;
} else if (prevNeighbours.find(nextNode) != prevNeighbours.end()) {
weights[i] = 1.0;
} else {
weights[i] = 1.0 / q;
}
}
discrete_distribution<int> dist(weights.begin(), weights.end());
return curNeighbours[dist(generator)];
}
}
long** generateWalks(unordered_map<long, unordered_set<long>> neighbours, int walkPerNode, int walkLength, double p, double q) {
long** walks = new long*[walkPerNode * neighbours.size()];
int counter = 0;
for (auto& neighbour : neighbours) {
long node = neighbour.first;
for (int i = 0; i < walkPerNode; i++) {
walks[counter + i] = new long[walkLength];
walks[counter + i][0] = node;
int curNode = node;
int prevNode = -1;
for (int j = 1; j < walkLength; j++) {
int nextNode = findNextNode(neighbours, curNode, prevNode, p, q);
walks[counter + i][j] = nextNode;
prevNode = curNode;
curNode = nextNode;
}
}
counter += walkPerNode;
}
return walks;
}
int main(int argc, char* argv[]) {
string fileName;
int walkPerNode = 1;
int walkLength = 10;
double p = 1;
double q = 2;
if (argc == 2) {
fileName = argv[1];
} else {
cerr << "Invalid argument, must provide path to edge list" << endl;
return 1;
}
unordered_map<long, unordered_set<long>> neighbours = {};
ifstream in(fileName);
long s, e;
while (in >> s >> e) {
if (s == e) {
cerr << "Loop edge is not supported" << endl;
return 1;
} else if (s <= 0 || e <= 0) {
cerr << "node must be greater than or equal to 0" << endl;
return 1;
}
if (neighbours.find(s) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[s] = emptySet;
}
if (neighbours.find(e) == neighbours.end()) {
unordered_set<long> emptySet = {};
neighbours[e] = emptySet;
}
neighbours[s].insert(e);
neighbours[e].insert(s);
}
long** cuNeighbours;
hipMallocManaged(&cuNeighbours, neighbours.size() * sizeof(long*));
long** walks = generateWalks(neighbours, walkPerNode, walkLength, p, q);
printWalks(walks, neighbours.size(), walkPerNode, walkLength);
// clean up
for (int i = 0; i < walkPerNode * neighbours.size(); i++) {
delete[] walks[i];
}
delete[] walks;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
cudaFree(rnd);
return 0;
} | code for sm_80
Function : _Z6genranPid
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B1, 0x1150 ; /* 0x0000111000017945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x001fe200078e0205 */
/*0060*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fca0003f05270 */
/*0070*/ I2F.F64.U32 R2, R2 ; /* 0x0000000200027312 */
/* 0x000e300000201800 */
/*0080*/ @!P0 BRA 0x1140 ; /* 0x000010b000008947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff067624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fc600078e00ff */
/*00b0*/ LOP3.LUT R7, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06077812 */
/* 0x000fe200078ec0ff */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff067624 */
/* 0x000fcc00078e00ff */
/*00d0*/ DMUL R16, R6, 1.80143985094819840000e+16 ; /* 0x4350000006107828 */
/* 0x0002880000000000 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, -0x64c00000 ; /* 0x9b400000ff047424 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R7, 0x7fefffff, PT ; /* 0x7fefffff0700780c */
/* 0x000fe20003f04070 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x41d07193 ; /* 0x41d07193ff057424 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x10f0 ; /* 0x00000fd000007945 */
/* 0x000fea0003800000 */
/*0120*/ DFMA R4, R2, R4, 12345 ; /* 0x40c81c800204742b */
/* 0x001e140000000004 */
/*0130*/ LOP3.LUT R13, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff050d7812 */
/* 0x001fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0004 */
/*0150*/ ISETP.GT.U32.OR P0, PT, R13, 0x7fefffff, P0 ; /* 0x7fefffff0d00780c */
/* 0x000fda0000704470 */
/*0160*/ @P0 BRA 0x1080 ; /* 0x00000f1000000947 */
/* 0x000fea0003800000 */
/*0170*/ DSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600722a */
/* 0x000e220003f0d000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; /* 0xfff80000ff037424 */
/* 0x000fd600078e00ff */
/*01a0*/ @!P0 BRA 0x10e0 ; /* 0x00000f3000008947 */
/* 0x001fea0003800000 */
/*01b0*/ DSETP.GE.AND P0, PT, R12, R6, PT ; /* 0x000000060c00722a */
/* 0x000e220003f06000 */
/*01c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fd600078e0005 */
/*01e0*/ @!P0 BRA 0x10e0 ; /* 0x00000ef000008947 */
/* 0x001fea0003800000 */
/*01f0*/ SHF.R.U32.HI R18, RZ, 0x14, R13 ; /* 0x00000014ff127819 */
/* 0x000fe2000001160d */
/*0200*/ BSSY B2, 0x460 ; /* 0x0000025000027945 */
/* 0x000fe20003800000 */
/*0210*/ SHF.R.U32.HI R9, RZ, 0x14, R7 ; /* 0x00000014ff097819 */
/* 0x000fe40000011607 */
/*0220*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe40003f05270 */
/*0230*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fd60003f25270 */
/*0240*/ @!P0 DMUL R12, R12, 1.80143985094819840000e+16 ; /* 0x435000000c0c8828 */
/* 0x000e240000000000 */
/*0250*/ @!P1 LEA.HI R9, R17, 0xffffffca, RZ, 0xc ; /* 0xffffffca11099811 */
/* 0x004fd000078f60ff */
/*0260*/ @!P0 LEA.HI R18, R13.reuse, 0xffffffca, RZ, 0xc ; /* 0xffffffca0d128811 */
/* 0x041fe200078f60ff */
/*0270*/ IMAD.MOV.U32 R15, RZ, RZ, R12 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000c */
/*0280*/ LOP3.LUT R14, R13, 0xfffff, RZ, 0xc0, !PT ; /* 0x000fffff0d0e7812 */
/* 0x000fe400078ec0ff */
/*0290*/ LOP3.LUT R2, RZ, R18, RZ, 0x33, !PT ; /* 0x00000012ff027212 */
/* 0x000fe200078e33ff */
/*02a0*/ IMAD.IADD R12, R18, 0x1, -R9 ; /* 0x00000001120c7824 */
/* 0x000fe200078e0a09 */
/*02b0*/ LOP3.LUT R14, R14, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000e0e7812 */
/* 0x000fc600078efcff */
/*02c0*/ IMAD.IADD R2, R2, 0x1, R9 ; /* 0x0000000102027824 */
/* 0x000fca00078e0209 */
/*02d0*/ IMNMX R3, R2, -0x1, !PT ; /* 0xffffffff02037817 */
/* 0x000fe20007800200 */
/*02e0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0006 */
/*02f0*/ @!P1 IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff029224 */
/* 0x000fe400078e0010 */
/*0300*/ IMAD.IADD R20, R3, 0x1, R18 ; /* 0x0000000103147824 */
/* 0x000fe400078e0212 */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0007 */
/*0320*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0011 */
/*0330*/ IADD3 R11, R20, 0x2, -R9 ; /* 0x00000002140b7810 */
/* 0x000fc80007ffe809 */
/*0340*/ LOP3.LUT P0, R13, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0d7812 */
/* 0x000fe4000780c0ff */
/*0350*/ LOP3.LUT R11, R3, 0xfffff, RZ, 0xc0, !PT ; /* 0x000fffff030b7812 */
/* 0x000fc800078ec0ff */
/*0360*/ LOP3.LUT R11, R11, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000b0b7812 */
/* 0x000fce00078efcff */
/*0370*/ @!P0 BRA 0x450 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0380*/ BSSY B3, 0x450 ; /* 0x000000c000037945 */
/* 0x000fe40003800000 */
/*0390*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fe40007f1e1ff */
/*03a0*/ IADD3 R13, R13, -0x1, RZ ; /* 0xffffffff0d0d7810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fe20007ffe0ff */
/*03c0*/ IMAD.X R19, R14, 0x1, ~R11, P0 ; /* 0x000000010e137824 */
/* 0x000fe200000e0e0b */
/*03d0*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f25270 */
/*03e0*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc80003f06270 */
/*03f0*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*0400*/ SEL R8, R14, R19, !P0 ; /* 0x000000130e087207 */
/* 0x000fc60004000000 */
/*0410*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*0420*/ SHF.L.U64.HI R14, R10, 0x1, R8 ; /* 0x000000010a0e7819 */
/* 0x000fe20000010208 */
/*0430*/ @P1 BRA 0x390 ; /* 0xffffff5000001947 */
/* 0x000fea000383ffff */
/*0440*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0450*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0460*/ IADD3 R13, R20, 0x1, -R9 ; /* 0x00000001140d7810 */
/* 0x000fe20007ffe809 */
/*0470*/ BSSY B2, 0xee0 ; /* 0x00000a6000027945 */
/* 0x000fe60003800000 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R13, 0x3, PT ; /* 0x000000030d00780c */
/* 0x000fda0003f06070 */
/*0490*/ @!P0 BRA 0xed0 ; /* 0x00000a3000008947 */
/* 0x000fea0003800000 */
/*04a0*/ LOP3.LUT R13, RZ, R12, RZ, 0x33, !PT ; /* 0x0000000cff0d7212 */
/* 0x000fe200078e33ff */
/*04b0*/ BSSY B3, 0x760 ; /* 0x000002a000037945 */
/* 0x000fe60003800000 */
/*04c0*/ IMNMX R13, R13, -0x4, !PT ; /* 0xfffffffc0d0d7817 */
/* 0x000fc80007800200 */
/*04d0*/ IADD3 R13, R12, 0x4, R13 ; /* 0x000000040c0d7810 */
/* 0x000fc80007ffe00d */
/*04e0*/ LEA.HI R18, R13, 0x1, RZ, 0x1e ; /* 0x000000010d127811 */
/* 0x000fc800078ff0ff */
/*04f0*/ LOP3.LUT P0, R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fda000780c0ff */
/*0500*/ @!P0 BRA 0x750 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0510*/ BSSY B4, 0x740 ; /* 0x0000022000047945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R8, RZ, RZ, R18 ; /* 0x000000ffff087224 */
/* 0x000fc600078e0012 */
/*0530*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fe40007f1e1ff */
/*0540*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0550*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD.X R19, R14, 0x1, ~R11, P0 ; /* 0x000000010e137824 */
/* 0x000fe200000e0e0b */
/*0570*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f25270 */
/*0580*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc80003f06270 */
/*0590*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*05a0*/ SEL R19, R14, R19, !P0 ; /* 0x000000130e137207 */
/* 0x000fc60004000000 */
/*05b0*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*05c0*/ SHF.L.U64.HI R14, R10, 0x1, R19 ; /* 0x000000010a0e7819 */
/* 0x000fc80000010213 */
/*05d0*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fca0007f1e1ff */
/*05e0*/ IMAD.X R19, R14, 0x1, ~R11, P0 ; /* 0x000000010e137824 */
/* 0x000fca00000e0e0b */
/*05f0*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc80003f06270 */
/*0600*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*0610*/ SEL R19, R14, R19, !P0 ; /* 0x000000130e137207 */
/* 0x000fc60004000000 */
/*0620*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*0630*/ SHF.L.U64.HI R10, R10, 0x1, R19 ; /* 0x000000010a0a7819 */
/* 0x000fc80000010213 */
/*0640*/ IADD3 R14, P0, -R2, R15, RZ ; /* 0x0000000f020e7210 */
/* 0x000fca0007f1e1ff */
/*0650*/ IMAD.X R19, R10, 0x1, ~R11, P0 ; /* 0x000000010a137824 */
/* 0x000fca00000e0e0b */
/*0660*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc80003f06270 */
/*0670*/ SEL R14, R15, R14, !P0 ; /* 0x0000000e0f0e7207 */
/* 0x000fe40004000000 */
/*0680*/ SEL R19, R10, R19, !P0 ; /* 0x000000130a137207 */
/* 0x000fc60004000000 */
/*0690*/ IMAD.SHL.U32 R15, R14.reuse, 0x2, RZ ; /* 0x000000020e0f7824 */
/* 0x040fe200078e00ff */
/*06a0*/ SHF.L.U64.HI R14, R14, 0x1, R19 ; /* 0x000000010e0e7819 */
/* 0x000fc80000010213 */
/*06b0*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fca0007f1e1ff */
/*06c0*/ IMAD.X R19, R14, 0x1, ~R11, P0 ; /* 0x000000010e137824 */
/* 0x000fca00000e0e0b */
/*06d0*/ ISETP.GE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc80003f06270 */
/*06e0*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*06f0*/ SEL R19, R14, R19, !P0 ; /* 0x000000130e137207 */
/* 0x000fc60004000000 */
/*0700*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*0710*/ SHF.L.U64.HI R14, R10, 0x1, R19 ; /* 0x000000010a0e7819 */
/* 0x000fe20000010213 */
/*0720*/ @P1 BRA 0x530 ; /* 0xfffffe0000001947 */
/* 0x000fea000383ffff */
/*0730*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*0740*/ IMAD.MOV.U32 R8, RZ, RZ, R19 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0013 */
/*0750*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0760*/ ISETP.GE.U32.AND P0, PT, R13, 0xc, PT ; /* 0x0000000c0d00780c */
/* 0x000fda0003f06070 */
/*0770*/ @!P0 BRA 0xed0 ; /* 0x0000075000008947 */
/* 0x000fea0003800000 */
/*0780*/ BSSY B3, 0xed0 ; /* 0x0000074000037945 */
/* 0x000fe40003800000 */
/*0790*/ IADD3 R8, P0, -R2, R15, RZ ; /* 0x0000000f02087210 */
/* 0x000fe40007f1e1ff */
/*07a0*/ ISETP.GT.AND P1, PT, R12.reuse, 0xf, PT ; /* 0x0000000f0c00780c */
/* 0x040fe40003f24270 */
/*07b0*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD.X R13, R14, 0x1, ~R11, P0 ; /* 0x000000010e0d7824 */
/* 0x000fca00000e0e0b */
/*07d0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*07e0*/ SEL R8, R15, R8, !P0 ; /* 0x000000080f087207 */
/* 0x000fe40004000000 */
/*07f0*/ SEL R13, R14, R13, !P0 ; /* 0x0000000d0e0d7207 */
/* 0x000fc60004000000 */
/*0800*/ IMAD.SHL.U32 R15, R8.reuse, 0x2, RZ ; /* 0x00000002080f7824 */
/* 0x040fe200078e00ff */
/*0810*/ SHF.L.U64.HI R8, R8, 0x1, R13 ; /* 0x0000000108087819 */
/* 0x000fc8000001020d */
/*0820*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fca0007f1e1ff */
/*0830*/ IMAD.X R13, R8, 0x1, ~R11, P0 ; /* 0x00000001080d7824 */
/* 0x000fca00000e0e0b */
/*0840*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0850*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*0860*/ SEL R13, R8, R13, !P0 ; /* 0x0000000d080d7207 */
/* 0x000fc60004000000 */
/*0870*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*0880*/ SHF.L.U64.HI R10, R10, 0x1, R13 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020d */
/*0890*/ IADD3 R8, P0, -R2, R15, RZ ; /* 0x0000000f02087210 */
/* 0x000fca0007f1e1ff */
/*08a0*/ IMAD.X R13, R10, 0x1, ~R11, P0 ; /* 0x000000010a0d7824 */
/* 0x000fca00000e0e0b */
/*08b0*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*08c0*/ SEL R8, R15, R8, !P0 ; /* 0x000000080f087207 */
/* 0x000fe40004000000 */
/*08d0*/ SEL R13, R10, R13, !P0 ; /* 0x0000000d0a0d7207 */
/* 0x000fc60004000000 */
/*08e0*/ IMAD.SHL.U32 R15, R8.reuse, 0x2, RZ ; /* 0x00000002080f7824 */
/* 0x040fe200078e00ff */
/*08f0*/ SHF.L.U64.HI R8, R8, 0x1, R13 ; /* 0x0000000108087819 */
/* 0x000fc8000001020d */
/*0900*/ IADD3 R10, P0, -R2, R15, RZ ; /* 0x0000000f020a7210 */
/* 0x000fca0007f1e1ff */
/*0910*/ IMAD.X R13, R8, 0x1, ~R11, P0 ; /* 0x00000001080d7824 */
/* 0x000fca00000e0e0b */
/*0920*/ ISETP.GE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc80003f06270 */
/*0930*/ SEL R10, R15, R10, !P0 ; /* 0x0000000a0f0a7207 */
/* 0x000fe40004000000 */
/*0940*/ SEL R13, R8, R13, !P0 ; /* 0x0000000d080d7207 */
/* 0x000fc60004000000 */
/*0950*/ IMAD.SHL.U32 R19, R10.reuse, 0x2, RZ ; /* 0x000000020a137824 */
/* 0x040fe200078e00ff */
/*0960*/ SHF.L.U64.HI R8, R10, 0x1, R13 ; /* 0x000000010a087819 */
/* 0x000fc8000001020d */
/*0970*/ IADD3 R10, P0, -R2, R19, RZ ; /* 0x00000013020a7210 */
/* 0x000fca0007f1e1ff */
/*0980*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0990*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*09a0*/ SEL R10, R19, R10, !P0 ; /* 0x0000000a130a7207 */
/* 0x000fe40004000000 */
/*09b0*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*09c0*/ IMAD.SHL.U32 R13, R10.reuse, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x040fe200078e00ff */
/*09d0*/ SHF.L.U64.HI R10, R10, 0x1, R15 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020f */
/*09e0*/ IADD3 R8, P0, -R2, R13, RZ ; /* 0x0000000d02087210 */
/* 0x000fca0007f1e1ff */
/*09f0*/ IMAD.X R15, R10, 0x1, ~R11, P0 ; /* 0x000000010a0f7824 */
/* 0x000fca00000e0e0b */
/*0a00*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0a10*/ SEL R8, R13, R8, !P0 ; /* 0x000000080d087207 */
/* 0x000fe40004000000 */
/*0a20*/ SEL R15, R10, R15, !P0 ; /* 0x0000000f0a0f7207 */
/* 0x000fc60004000000 */
/*0a30*/ IMAD.SHL.U32 R13, R8.reuse, 0x2, RZ ; /* 0x00000002080d7824 */
/* 0x040fe200078e00ff */
/*0a40*/ SHF.L.U64.HI R8, R8, 0x1, R15 ; /* 0x0000000108087819 */
/* 0x000fc8000001020f */
/*0a50*/ IADD3 R10, P0, -R2, R13, RZ ; /* 0x0000000d020a7210 */
/* 0x000fca0007f1e1ff */
/*0a60*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0a70*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0a80*/ SEL R10, R13, R10, !P0 ; /* 0x0000000a0d0a7207 */
/* 0x000fe40004000000 */
/*0a90*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*0aa0*/ IMAD.SHL.U32 R13, R10.reuse, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x040fe200078e00ff */
/*0ab0*/ SHF.L.U64.HI R10, R10, 0x1, R15 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020f */
/*0ac0*/ IADD3 R8, P0, -R2, R13, RZ ; /* 0x0000000d02087210 */
/* 0x000fca0007f1e1ff */
/*0ad0*/ IMAD.X R15, R10, 0x1, ~R11, P0 ; /* 0x000000010a0f7824 */
/* 0x000fca00000e0e0b */
/*0ae0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0af0*/ SEL R8, R13, R8, !P0 ; /* 0x000000080d087207 */
/* 0x000fe40004000000 */
/*0b00*/ SEL R15, R10, R15, !P0 ; /* 0x0000000f0a0f7207 */
/* 0x000fc60004000000 */
/*0b10*/ IMAD.SHL.U32 R13, R8.reuse, 0x2, RZ ; /* 0x00000002080d7824 */
/* 0x040fe200078e00ff */
/*0b20*/ SHF.L.U64.HI R8, R8, 0x1, R15 ; /* 0x0000000108087819 */
/* 0x000fc8000001020f */
/*0b30*/ IADD3 R10, P0, -R2, R13, RZ ; /* 0x0000000d020a7210 */
/* 0x000fca0007f1e1ff */
/*0b40*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0b50*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0b60*/ SEL R10, R13, R10, !P0 ; /* 0x0000000a0d0a7207 */
/* 0x000fe40004000000 */
/*0b70*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*0b80*/ IMAD.SHL.U32 R13, R10.reuse, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x040fe200078e00ff */
/*0b90*/ SHF.L.U64.HI R10, R10, 0x1, R15 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020f */
/*0ba0*/ IADD3 R8, P0, -R2, R13, RZ ; /* 0x0000000d02087210 */
/* 0x000fca0007f1e1ff */
/*0bb0*/ IMAD.X R15, R10, 0x1, ~R11, P0 ; /* 0x000000010a0f7824 */
/* 0x000fca00000e0e0b */
/*0bc0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0bd0*/ SEL R8, R13, R8, !P0 ; /* 0x000000080d087207 */
/* 0x000fe40004000000 */
/*0be0*/ SEL R15, R10, R15, !P0 ; /* 0x0000000f0a0f7207 */
/* 0x000fc60004000000 */
/*0bf0*/ IMAD.SHL.U32 R13, R8.reuse, 0x2, RZ ; /* 0x00000002080d7824 */
/* 0x040fe200078e00ff */
/*0c00*/ SHF.L.U64.HI R8, R8, 0x1, R15 ; /* 0x0000000108087819 */
/* 0x000fc8000001020f */
/*0c10*/ IADD3 R10, P0, -R2, R13, RZ ; /* 0x0000000d020a7210 */
/* 0x000fca0007f1e1ff */
/*0c20*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0c30*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0c40*/ SEL R10, R13, R10, !P0 ; /* 0x0000000a0d0a7207 */
/* 0x000fe40004000000 */
/*0c50*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*0c60*/ IMAD.SHL.U32 R13, R10.reuse, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x040fe200078e00ff */
/*0c70*/ SHF.L.U64.HI R10, R10, 0x1, R15 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020f */
/*0c80*/ IADD3 R8, P0, -R2, R13, RZ ; /* 0x0000000d02087210 */
/* 0x000fca0007f1e1ff */
/*0c90*/ IMAD.X R15, R10, 0x1, ~R11, P0 ; /* 0x000000010a0f7824 */
/* 0x000fca00000e0e0b */
/*0ca0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0cb0*/ SEL R8, R13, R8, !P0 ; /* 0x000000080d087207 */
/* 0x000fe40004000000 */
/*0cc0*/ SEL R15, R10, R15, !P0 ; /* 0x0000000f0a0f7207 */
/* 0x000fc60004000000 */
/*0cd0*/ IMAD.SHL.U32 R13, R8.reuse, 0x2, RZ ; /* 0x00000002080d7824 */
/* 0x040fe200078e00ff */
/*0ce0*/ SHF.L.U64.HI R8, R8, 0x1, R15 ; /* 0x0000000108087819 */
/* 0x000fc8000001020f */
/*0cf0*/ IADD3 R10, P0, -R2, R13, RZ ; /* 0x0000000d020a7210 */
/* 0x000fca0007f1e1ff */
/*0d00*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0d10*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0d20*/ SEL R10, R13, R10, !P0 ; /* 0x0000000a0d0a7207 */
/* 0x000fe40004000000 */
/*0d30*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*0d40*/ IMAD.SHL.U32 R13, R10.reuse, 0x2, RZ ; /* 0x000000020a0d7824 */
/* 0x040fe200078e00ff */
/*0d50*/ SHF.L.U64.HI R10, R10, 0x1, R15 ; /* 0x000000010a0a7819 */
/* 0x000fc8000001020f */
/*0d60*/ IADD3 R8, P0, -R2, R13, RZ ; /* 0x0000000d02087210 */
/* 0x000fca0007f1e1ff */
/*0d70*/ IMAD.X R15, R10, 0x1, ~R11, P0 ; /* 0x000000010a0f7824 */
/* 0x000fca00000e0e0b */
/*0d80*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0d90*/ SEL R8, R13, R8, !P0 ; /* 0x000000080d087207 */
/* 0x000fe40004000000 */
/*0da0*/ SEL R15, R10, R15, !P0 ; /* 0x0000000f0a0f7207 */
/* 0x000fc60004000000 */
/*0db0*/ IMAD.SHL.U32 R13, R8.reuse, 0x2, RZ ; /* 0x00000002080d7824 */
/* 0x040fe200078e00ff */
/*0dc0*/ SHF.L.U64.HI R8, R8, 0x1, R15 ; /* 0x0000000108087819 */
/* 0x000fc8000001020f */
/*0dd0*/ IADD3 R14, P0, -R2, R13, RZ ; /* 0x0000000d020e7210 */
/* 0x000fca0007f1e1ff */
/*0de0*/ IMAD.X R15, R8, 0x1, ~R11, P0 ; /* 0x00000001080f7824 */
/* 0x000fca00000e0e0b */
/*0df0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f06270 */
/*0e00*/ SEL R14, R13, R14, !P0 ; /* 0x0000000e0d0e7207 */
/* 0x000fe40004000000 */
/*0e10*/ SEL R15, R8, R15, !P0 ; /* 0x0000000f080f7207 */
/* 0x000fc60004000000 */
/*0e20*/ IMAD.SHL.U32 R13, R14.reuse, 0x2, RZ ; /* 0x000000020e0d7824 */
/* 0x040fe200078e00ff */
/*0e30*/ SHF.L.U64.HI R14, R14, 0x1, R15 ; /* 0x000000010e0e7819 */
/* 0x000fc8000001020f */
/*0e40*/ IADD3 R10, P0, -R2, R13, RZ ; /* 0x0000000d020a7210 */
/* 0x000fca0007f1e1ff */
/*0e50*/ IMAD.X R8, R14, 0x1, ~R11, P0 ; /* 0x000000010e087824 */
/* 0x000fca00000e0e0b */
/*0e60*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f06270 */
/*0e70*/ SEL R10, R13, R10, !P0 ; /* 0x0000000a0d0a7207 */
/* 0x000fe40004000000 */
/*0e80*/ SEL R8, R14, R8, !P0 ; /* 0x000000080e087207 */
/* 0x000fc60004000000 */
/*0e90*/ IMAD.SHL.U32 R15, R10.reuse, 0x2, RZ ; /* 0x000000020a0f7824 */
/* 0x040fe200078e00ff */
/*0ea0*/ SHF.L.U64.HI R14, R10, 0x1, R8 ; /* 0x000000010a0e7819 */
/* 0x000fe20000010208 */
/*0eb0*/ @P1 BRA 0x790 ; /* 0xfffff8d000001947 */
/* 0x000fea000383ffff */
/*0ec0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0ed0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ee0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05070 */
/*0ef0*/ BSSY B2, 0x1040 ; /* 0x0000014000027945 */
/* 0x000fe20003800000 */
/*0f00*/ LOP3.LUT R13, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff080d7812 */
/* 0x000fe200078ec0ff */
/*0f10*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0f20*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0f30*/ ISETP.NE.AND.EX P0, PT, R13, RZ, PT, P0 ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05300 */
/*0f40*/ @!P0 BRA 0x1030 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0f50*/ IMAD.MOV.U32 R11, RZ, RZ, R13 ; /* 0x000000ffff0b7224 */
/* 0x000fcc00078e000d */
/*0f60*/ DMUL R2, R10, 1.80143985094819840000e+16 ; /* 0x435000000a027828 */
/* 0x000e140000000000 */
/*0f70*/ SHF.R.U32.HI R2, RZ, 0x14, R3 ; /* 0x00000014ff027819 */
/* 0x001fc80000011603 */
/*0f80*/ IADD3 R3, -R2, 0x37, RZ ; /* 0x0000003702037810 */
/* 0x000fc80007ffe1ff */
/*0f90*/ SHF.L.U32 R12, R10.reuse, R3.reuse, RZ ; /* 0x000000030a0c7219 */
/* 0x0c0fe200000006ff */
/*0fa0*/ IMAD.IADD R9, R9, 0x1, -R3 ; /* 0x0000000109097824 */
/* 0x000fe200078e0a03 */
/*0fb0*/ SHF.L.U64.HI R3, R10, R3, R13 ; /* 0x000000030a037219 */
/* 0x000fe4000001020d */
/*0fc0*/ IADD3 R11, P1, RZ, R12, RZ ; /* 0x0000000cff0b7210 */
/* 0x000fe40007f3e0ff */
/*0fd0*/ ISETP.GE.AND P0, PT, R9.reuse, 0x1, PT ; /* 0x000000010900780c */
/* 0x040fe40003f06270 */
/*0fe0*/ IADD3 R2, R9.reuse, -0x1, RZ ; /* 0xffffffff09027810 */
/* 0x040fe40007ffe0ff */
/*0ff0*/ IADD3 R9, -R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc60007ffe1ff */
/*1000*/ IMAD.U32.X R14, R2, 0x100000, R3, P1 ; /* 0x00100000020e7824 */
/* 0x000fcc00008e0403 */
/*1010*/ @!P0 SHF.R.U64 R11, R12, R9.reuse, R3.reuse ; /* 0x000000090c0b8219 */
/* 0x180fe40000001203 */
/*1020*/ @!P0 SHF.R.U32.HI R14, RZ, R9, R3 ; /* 0x00000009ff0e8219 */
/* 0x000fe40000011603 */
/*1030*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1040*/ IMAD.MOV.U32 R3, RZ, RZ, R14 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000e */
/*1050*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fc600078e000b */
/*1060*/ LOP3.LUT R3, R3, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef805 */
/*1070*/ BRA 0x10e0 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*1080*/ DSETP.GTU.AND P0, PT, R6, +INF , PT ; /* 0x7ff000000600742a */
/* 0x000e0c0003f0c000 */
/*1090*/ DSETP.LE.AND P0, PT, R12, +INF , !P0 ; /* 0x7ff000000c00742a */
/* 0x001e1c0004703000 */
/*10a0*/ @P0 DSETP.NEU.AND P1, PT, R12, +INF , PT ; /* 0x7ff000000c00042a */
/* 0x001e080003f2d000 */
/*10b0*/ @!P0 DADD R2, R4, c[0x0][0x168] ; /* 0x00005a0004028629 */
/* 0x00070c0000000000 */
/*10c0*/ @P0 FSEL R2, R4, RZ, P1 ; /* 0x000000ff04020208 */
/* 0x001fe40000800000 */
/*10d0*/ @P0 FSEL R3, R5, -QNAN , P1 ; /* 0xfff8000005030808 */
/* 0x000fe40000800000 */
/*10e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x018fea0003800000 */
/*10f0*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*1100*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fc80007ffe0ff */
/*1110*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x001fda0003f06070 */
/*1120*/ @P0 CALL.REL.NOINC 0x1140 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*1130*/ BRA 0xe0 ; /* 0xffffefa000007947 */
/* 0x000fea000383ffff */
/*1140*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1150*/ F2I.U64.F64.TRUNC R2, R2 ; /* 0x0000000200027311 */
/* 0x001e22000030d800 */
/*1160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*1170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x002fe200078e00ff */
/*1180*/ LEA R4, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002047a11 */
/* 0x001fc800078010ff */
/*1190*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f1403 */
/*11a0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x000fe2000c10e184 */
/*11b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*11c0*/ BRA 0x11c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
cudaFree(rnd);
return 0;
} | .file "tmpxft_0016f7e6_00000000-6_cuda10.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6genranPidPid
.type _Z26__device_stub__Z6genranPidPid, @function
_Z26__device_stub__Z6genranPidPid:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6genranPid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z6genranPidPid, .-_Z26__device_stub__Z6genranPidPid
.globl _Z6genranPid
.type _Z6genranPid, @function
_Z6genranPid:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6genranPidPid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6genranPid, .-_Z6genranPid
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "|"
.LC6:
.string "*"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
movl $1, %edx
movl $2147483648, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movl $2147483648, %ecx
.L12:
movq 40(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4194304, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
fldz
fld %st(0)
fstpt (%rsp)
jmp .L19
.L28:
movsd .LC1(%rip), %xmm0
movq 40(%rsp), %rdi
call _Z26__device_stub__Z6genranPidPid
jmp .L13
.L16:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldz
fld %st(0)
fstpt (%rsp)
.L14:
addq $4, %rbx
movl $2147483648, %eax
cmpq %rax, %rbx
je .L29
.L19:
movq 40(%rsp), %rax
fildl (%rax,%rbx)
fldt (%rsp)
faddp %st, %st(1)
fstpt (%rsp)
fld1
faddp %st, %st(1)
flds .LC3(%rip)
fxch %st(1)
fucomi %st(1), %st
fstp %st(1)
jp .L14
jne .L14
fstp %st(0)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldt (%rsp)
fmuls .LC5(%rip)
fld %st(0)
fstpt 16(%rsp)
movl $0, %ebp
leaq .LC6(%rip), %r12
fldz
fxch %st(1)
fcomip %st(1), %st
fstp %st(0)
jbe .L16
.L18:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl %ebp, (%rsp)
fildl (%rsp)
fldt 16(%rsp)
fcomip %st(1), %st
fstp %st(0)
ja .L18
jmp .L16
.L29:
fstp %st(0)
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z6genranPid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6genranPid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1103101952
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1266679808
.align 4
.LC5:
.long 905969664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
cudaFree(rnd);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
hipFree(rnd);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
hipFree(rnd);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6genranPid
.globl _Z6genranPid
.p2align 8
.type _Z6genranPid,@function
_Z6genranPid:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s8, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f64_u32_e32 v[5:6], v1
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_12
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s7, 0x41d07193
s_mov_b32 s6, 0x9b400000
s_mov_b32 s11, 0
s_waitcnt lgkmcnt(0)
v_frexp_mant_f64_e64 v[1:2], |s[4:5]|
v_cmp_eq_f64_e64 s9, s[4:5], 0
v_cmp_o_f64_e64 s10, s[4:5], s[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[1:2], v[1:2], 1
v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], 1.0
v_div_scale_f64 v[11:12], vcc_lo, 1.0, v[1:2], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[3:4]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], -v[3:4], v[7:8], 1.0
v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[11:12], v[7:8]
v_fma_f64 v[3:4], -v[3:4], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[3:4], v[3:4], v[7:8], v[9:10]
v_frexp_exp_i32_f64_e32 v9, s[4:5]
v_div_fixup_f64 v[3:4], v[3:4], v[1:2], 1.0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, -1, v9
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s12
v_subrev_nc_u32_e32 v11, 25, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], v11
v_mul_f64 v[11:12], v[3:4], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[11:12], v[11:12]
v_fma_f64 v[7:8], -v[11:12], v[1:2], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8]
v_cndmask_b32_e32 v12, 0x80000000, v2, vcc_lo
v_cndmask_b32_e32 v11, 0, v1, vcc_lo
v_add_f64 v[7:8], v[7:8], v[11:12]
v_and_b32_e32 v11, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], v10
v_xor_b32_e32 v8, v11, v8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_class_f64_e64 s2, v[5:6], 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v7, 0, s9
v_cndmask_b32_e64 v6, v8, 0x7ff80000, s9
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, s11, v0
s_and_b32 s2, s10, s2
s_or_b32 s8, vcc_lo, s8
v_cndmask_b32_e64 v6, 0x7ff80000, v6, s2
v_cndmask_b32_e64 v5, 0, v5, s2
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB0_11
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], s[6:7], 0x40c81c80
v_cmp_ngt_f64_e64 s2, |v[5:6]|, |s[4:5]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s12, s2
s_xor_b32 s2, exec_lo, s12
v_cmp_eq_f64_e64 vcc_lo, |v[5:6]|, |s[4:5]|
v_and_b32_e32 v7, 0x80000000, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, v6, v7, vcc_lo
v_cndmask_b32_e64 v7, v5, 0, vcc_lo
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_3
v_frexp_mant_f64_e64 v[7:8], |v[5:6]|
v_frexp_exp_i32_f64_e32 v11, v[5:6]
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[7:8], v[7:8], 26
v_sub_nc_u32_e32 v11, v11, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 26, v11
s_cbranch_execz .LBB0_2
s_mov_b32 s13, 0
.p2align 6
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[3:4], v[7:8]
v_rndne_f64_e32 v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[12:13], v[1:2], v[7:8]
v_cmp_gt_f64_e32 vcc_lo, 0, v[7:8]
v_cndmask_b32_e32 v13, 0x80000000, v2, vcc_lo
v_cndmask_b32_e32 v12, 0, v1, vcc_lo
v_cmp_gt_u32_e32 vcc_lo, 53, v11
v_subrev_nc_u32_e32 v11, 26, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], v[12:13]
s_or_b32 s13, vcc_lo, s13
v_ldexp_f64 v[7:8], v[7:8], 26
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_9
s_or_b32 exec_lo, exec_lo, s13
s_branch .LBB0_2
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s8
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
v_trunc_f64_e32 v[0:1], v[5:6]
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_ldexp_f64 v[2:3], v[0:1], 0xffffffe0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f64_e32 v[2:3], v[2:3]
v_fma_f64 v[0:1], v[2:3], 0xc1f00000, v[0:1]
v_cvt_u32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f64_e32 v1, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6genranPid
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6genranPid, .Lfunc_end0-_Z6genranPid
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6genranPid
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6genranPid.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Kernel function to generate random numbers
__global__
void genran(int *rnd,double m)
{
double n,a=1103515245, c=12345;
n=blockIdx.x*blockDim.x+threadIdx.x;
//n=threadIdx.x;
for(int i=0;i<threadIdx.x;i++)
n=fmod(((n*a)+c),m);
__syncthreads();
atomicAdd(&rnd[(unsigned long int)n],1);
}
int main(void)
{
int t=29;
long int m = pow(2,t);
int *rnd;
double val;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&rnd, m*sizeof(int));
// initialize
val = m;
for (int i = 0; i < m; i++) {
rnd[i] = 0;
}
//generate random numbers
int blockSize = 128;
int numblocks = (m+blockSize-1)/blockSize;
// Run kernel
genran<<<numblocks, blockSize>>>(rnd,val);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
//Generate Histrogram
long double count =0,j=0;
for(long int i=0;i<m;++i)
{
count+=rnd[i];
j++;
if(j==pow(2,t-5))
{
j=0;
printf("|");
count/=pow(2,t-10);
for(int k=0;k<count;++k)
printf("*");
printf("\n");
count=0;
}
}
// Free memory
hipFree(rnd);
return 0;
} | .text
.file "cuda10.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__genranPid # -- Begin function _Z21__device_stub__genranPid
.p2align 4, 0x90
.type _Z21__device_stub__genranPid,@function
_Z21__device_stub__genranPid: # @_Z21__device_stub__genranPid
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6genranPid, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__genranPid, .Lfunc_end0-_Z21__device_stub__genranPid
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4b800000 # float 16777216
.LCPI1_1:
.long 0x36000000 # float 1.90734863E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $2147483648, %esi # imm = 0x80000000
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
movl $2147483648, %edx # imm = 0x80000000
xorl %esi, %esi
callq memset@PLT
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 4194176(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movabsq $4737786807993761792, %rax # imm = 0x41C0000000000000
movq %rax, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6genranPid, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
fldz
xorl %ebx, %ebx
flds .LCPI1_0(%rip)
fstpt 100(%rsp) # 10-byte Folded Spill
fld %st(0)
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_3 Depth=1
fstp %st(0)
movl $10, %edi
callq putchar@PLT
fldz
fld %st(0)
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $536870912, %rbx # imm = 0x20000000
fxch %st(1)
je .LBB1_9
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
fld1
faddp %st, %st(1)
movq (%rsp), %rax
movl (%rax,%rbx,4), %eax
movl %eax, 16(%rsp)
fxch %st(1)
fiaddl 16(%rsp)
fldt 100(%rsp) # 10-byte Folded Reload
fxch %st(2)
fucomi %st(2), %st
fstp %st(2)
jne .LBB1_8
jp .LBB1_8
# %bb.4: # in Loop: Header=BB1_3 Depth=1
fstp %st(1)
movl $124, %edi
fstpt 20(%rsp) # 10-byte Folded Spill
callq putchar@PLT
fldt 20(%rsp) # 10-byte Folded Reload
fmuls .LCPI1_1(%rip)
fldz
fxch %st(1)
fucomi %st(1), %st
fstp %st(1)
jbe .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_3 Depth=1
movl $1, %ebp
fstpt 20(%rsp) # 10-byte Folded Spill
fldz
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
fstp %st(0)
movl $42, %edi
callq putchar@PLT
fldt 20(%rsp) # 10-byte Folded Reload
movl %ebp, 12(%rsp)
fildl 12(%rsp)
incl %ebp
fxch %st(1)
fucompi %st(1), %st
fstp %st(0)
fldz
ja .LBB1_6
jmp .LBB1_7
.LBB1_9:
fstp %st(0)
fstp %st(0)
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6genranPid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6genranPid,@object # @_Z6genranPid
.section .rodata,"a",@progbits
.globl _Z6genranPid
.p2align 3, 0x0
_Z6genranPid:
.quad _Z21__device_stub__genranPid
.size _Z6genranPid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6genranPid"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__genranPid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6genranPid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f7e6_00000000-6_cuda10.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6genranPidPid
.type _Z26__device_stub__Z6genranPidPid, @function
_Z26__device_stub__Z6genranPidPid:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6genranPid(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z6genranPidPid, .-_Z26__device_stub__Z6genranPidPid
.globl _Z6genranPid
.type _Z6genranPid, @function
_Z6genranPid:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6genranPidPid
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6genranPid, .-_Z6genranPid
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "|"
.LC6:
.string "*"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
movl $1, %edx
movl $2147483648, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movl $2147483648, %ecx
.L12:
movq 40(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L12
movl $128, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $4194304, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L13:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
fldz
fld %st(0)
fstpt (%rsp)
jmp .L19
.L28:
movsd .LC1(%rip), %xmm0
movq 40(%rsp), %rdi
call _Z26__device_stub__Z6genranPidPid
jmp .L13
.L16:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldz
fld %st(0)
fstpt (%rsp)
.L14:
addq $4, %rbx
movl $2147483648, %eax
cmpq %rax, %rbx
je .L29
.L19:
movq 40(%rsp), %rax
fildl (%rax,%rbx)
fldt (%rsp)
faddp %st, %st(1)
fstpt (%rsp)
fld1
faddp %st, %st(1)
flds .LC3(%rip)
fxch %st(1)
fucomi %st(1), %st
fstp %st(1)
jp .L14
jne .L14
fstp %st(0)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
fldt (%rsp)
fmuls .LC5(%rip)
fld %st(0)
fstpt 16(%rsp)
movl $0, %ebp
leaq .LC6(%rip), %r12
fldz
fxch %st(1)
fcomip %st(1), %st
fstp %st(0)
jbe .L16
.L18:
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl %ebp, (%rsp)
fildl (%rsp)
fldt 16(%rsp)
fcomip %st(1), %st
fstp %st(0)
ja .L18
jmp .L16
.L29:
fstp %st(0)
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z6genranPid"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z6genranPid(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1103101952
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1266679808
.align 4
.LC5:
.long 905969664
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda10.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__genranPid # -- Begin function _Z21__device_stub__genranPid
.p2align 4, 0x90
.type _Z21__device_stub__genranPid,@function
_Z21__device_stub__genranPid: # @_Z21__device_stub__genranPid
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6genranPid, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__genranPid, .Lfunc_end0-_Z21__device_stub__genranPid
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4b800000 # float 16777216
.LCPI1_1:
.long 0x36000000 # float 1.90734863E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $136, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsp, %rdi
movl $2147483648, %esi # imm = 0x80000000
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rdi
movl $2147483648, %edx # imm = 0x80000000
xorl %esi, %esi
callq memset@PLT
movabsq $4294967424, %rdx # imm = 0x100000080
leaq 4194176(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movabsq $4737786807993761792, %rax # imm = 0x41C0000000000000
movq %rax, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6genranPid, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
fldz
xorl %ebx, %ebx
flds .LCPI1_0(%rip)
fstpt 100(%rsp) # 10-byte Folded Spill
fld %st(0)
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_3 Depth=1
fstp %st(0)
movl $10, %edi
callq putchar@PLT
fldz
fld %st(0)
.LBB1_8: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $536870912, %rbx # imm = 0x20000000
fxch %st(1)
je .LBB1_9
.LBB1_3: # =>This Loop Header: Depth=1
# Child Loop BB1_6 Depth 2
fld1
faddp %st, %st(1)
movq (%rsp), %rax
movl (%rax,%rbx,4), %eax
movl %eax, 16(%rsp)
fxch %st(1)
fiaddl 16(%rsp)
fldt 100(%rsp) # 10-byte Folded Reload
fxch %st(2)
fucomi %st(2), %st
fstp %st(2)
jne .LBB1_8
jp .LBB1_8
# %bb.4: # in Loop: Header=BB1_3 Depth=1
fstp %st(1)
movl $124, %edi
fstpt 20(%rsp) # 10-byte Folded Spill
callq putchar@PLT
fldt 20(%rsp) # 10-byte Folded Reload
fmuls .LCPI1_1(%rip)
fldz
fxch %st(1)
fucomi %st(1), %st
fstp %st(1)
jbe .LBB1_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB1_3 Depth=1
movl $1, %ebp
fstpt 20(%rsp) # 10-byte Folded Spill
fldz
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
fstp %st(0)
movl $42, %edi
callq putchar@PLT
fldt 20(%rsp) # 10-byte Folded Reload
movl %ebp, 12(%rsp)
fildl 12(%rsp)
incl %ebp
fxch %st(1)
fucompi %st(1), %st
fstp %st(0)
fldz
ja .LBB1_6
jmp .LBB1_7
.LBB1_9:
fstp %st(0)
fstp %st(0)
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6genranPid, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6genranPid,@object # @_Z6genranPid
.section .rodata,"a",@progbits
.globl _Z6genranPid
.p2align 3, 0x0
_Z6genranPid:
.quad _Z21__device_stub__genranPid
.size _Z6genranPid, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6genranPid"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__genranPid
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6genranPid
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z16LeftRightBound2DPdS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0x230 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x002fe200000001ff */
/*00a0*/ IMAD R14, R0, c[0x0][0x188], RZ ; /* 0x00006200000e7a24 */
/* 0x000fd200078e02ff */
/*00b0*/ IMAD.WIDE R2, R14, R17, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fcc00078e0211 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IADD3 R16, R14.reuse, c[0x0][0x188], RZ ; /* 0x000062000e107a10 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.WIDE R6, R14, R17, c[0x0][0x160] ; /* 0x000058000e067625 */
/* 0x000fc600078e0211 */
/*00f0*/ IADD3 R12, R16, -0x1, RZ ; /* 0xffffffff100c7810 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R8, R12, R17, c[0x0][0x168] ; /* 0x00005a000c087625 */
/* 0x000fe200078e0211 */
/*0110*/ DADD R4, R2, c[0x3][0x0] ; /* 0x00c0000002047629 */
/* 0x004e0e0000000000 */
/*0120*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0011e8000c101b04 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0211 */
/*0150*/ IMAD.WIDE R14, R14, R17, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fe200078e0211 */
/*0160*/ DADD R10, R8, c[0x3][0x0] ; /* 0x00c00000080a7629 */
/* 0x004e4e0000000000 */
/*0170*/ STG.E.64 [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x0023e8000c101b04 */
/*0180*/ LDG.E.64 R2, [R14.64+0x8] ; /* 0x000008040e027981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ IADD3 R16, R16, -0x2, RZ ; /* 0xfffffffe10107810 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*01b0*/ STG.E.64 [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0043e8000c101b04 */
/*01c0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1b00 */
/*01d0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0200*/ STG.E.64 [R16.64+0x8], R18 ; /* 0x0000081210007986 */
/* 0x0043d8000c101b04 */
/*0210*/ @!P0 BRA 0x90 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x001fe200000001ff */
/*0240*/ IMAD R14, R0, c[0x0][0x188], RZ ; /* 0x00006200000e7a24 */
/* 0x000fd200078e02ff */
/*0250*/ IMAD.WIDE R12, R14, R17, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x000fca00078e0211 */
/*0260*/ LDG.E.64 R2, [R12.64+0x8] ; /* 0x000008040c027981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IADD3 R4, R14, c[0x0][0x188], RZ ; /* 0x000062000e047a10 */
/* 0x000fc80007ffe0ff */
/*0280*/ IADD3 R16, R4, -0x2, RZ ; /* 0xfffffffe04107810 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE R4, R16, R17.reuse, c[0x0][0x160] ; /* 0x0000580010047625 */
/* 0x080fe200078e0211 */
/*02a0*/ STG.E.64 [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0041e8000c101b04 */
/*02b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*02c0*/ IMAD.WIDE R14, R14, R17, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fc600078e0211 */
/*02d0*/ STG.E.64 [R4.64+0x8], R6 ; /* 0x0000080604007986 */
/* 0x0041e8000c101b04 */
/*02e0*/ LDG.E.64 R8, [R14.64+0x8] ; /* 0x000008040e087981 */
/* 0x000ea2000c1e1b00 */
/*02f0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*0300*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fe40000000f00 */
/*0310*/ STG.E.64 [R14.64], R8 ; /* 0x000000080e007986 */
/* 0x0041e8000c101b04 */
/*0320*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IMAD R0, R19, c[0x0][0xc], R0 ; /* 0x0000030013007a24 */
/* 0x000fca00078e0200 */
/*0340*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0350*/ STG.E.64 [R16.64+0x8], R10 ; /* 0x0000080a10007986 */
/* 0x0041d8000c101b04 */
/*0360*/ @!P0 BRA 0x230 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00021ec0_00000000-6_LeftRightBound2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
.type _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii, @function
_Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16LeftRightBound2DPdS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii, .-_Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
.globl _Z16LeftRightBound2DPdS_S_S_iii
.type _Z16LeftRightBound2DPdS_S_S_iii, @function
_Z16LeftRightBound2DPdS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16LeftRightBound2DPdS_S_S_iii, .-_Z16LeftRightBound2DPdS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16LeftRightBound2DPdS_S_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "hcri"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16LeftRightBound2DPdS_S_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4hcri(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4hcri
.comm _ZL4hcri,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16LeftRightBound2DPdS_S_S_iii
.globl _Z16LeftRightBound2DPdS_S_S_iii
.p2align 8
.type _Z16LeftRightBound2DPdS_S_S_iii,@function
_Z16LeftRightBound2DPdS_S_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x24
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s15, s15, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s15, v0
v_cmpx_gt_i32_e64 s10, v7
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s14, s[0:1], 0x28
s_load_b32 s13, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 0
v_mad_u64_u32 v[0:1], null, s14, v7, s[14:15]
s_cselect_b32 s11, -1, 0
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, hcri@rel32@lo+4
s_addc_u32 s9, s9, hcri@rel32@hi+12
s_load_b256 s[0:7], s[0:1], 0x0
s_load_b64 s[8:9], s[8:9], 0x0
v_mul_lo_u32 v8, s14, v7
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_mul_i32 s14, s12, s14
s_mov_b32 s15, 0
s_branch .LBB0_3
.LBB0_2:
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, s12, v7
s_add_i32 s15, s15, s14
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v5
global_load_b64 v[3:4], v[1:2], off offset:8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v7
s_or_b32 s13, vcc_lo, s13
s_waitcnt vmcnt(0)
global_store_b64 v[1:2], v[3:4], off
global_load_b64 v[1:2], v[5:6], off offset:-16
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[1:2], off offset:-8
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v8
s_and_b32 vcc_lo, exec_lo, s11
s_mov_b32 s16, -1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_cbranch_vccz .LBB0_5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add3_u32 v9, v0, s15, -1
v_add_co_u32 v11, vcc_lo, s0, v3
global_load_b64 v[5:6], v[5:6], off
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v4, vcc_lo
v_ashrrev_i32_e32 v10, 31, v9
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v13, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], s[8:9], v[5:6]
global_store_b64 v[11:12], v[5:6], off
global_load_b64 v[5:6], v[13:14], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], s[8:9], v[5:6]
global_store_b64 v[9:10], v[5:6], off
.LBB0_5:
v_add_nc_u32_e32 v5, s15, v0
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_ashrrev_i32_e32 v6, 31, v5
global_load_b64 v[9:10], v[3:4], off offset:8
v_lshlrev_b64 v[11:12], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[9:10], off
global_load_b64 v[3:4], v[11:12], off offset:-16
s_waitcnt vmcnt(0)
global_store_b64 v[11:12], v[3:4], off offset:-8
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16LeftRightBound2DPdS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16LeftRightBound2DPdS_S_S_iii, .Lfunc_end0-_Z16LeftRightBound2DPdS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected hcri
.type hcri,@object
.section .bss,"aw",@nobits
.globl hcri
.p2align 3, 0x0
hcri:
.quad 0x0000000000000000
.size hcri, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym hcri
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16LeftRightBound2DPdS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z16LeftRightBound2DPdS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void LeftRightBound2D(double *Hs, double *Ztopo, double *K2e, double *K2w, int BC2D, int M, int N) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < M) {
// no-flow BCs
if (BC2D == 0) {
Hs[tid*N] = Hs[tid*N+1];
Hs[(tid+1)*N-1] = Hs[(tid+1)*N-2];
} else { // Critical depth flow BCs
Hs[tid*N] = hcri + Ztopo[tid*N];
Hs[(tid+1)*N-1] = hcri + Ztopo[(tid+1)*N-1];
}
K2w[tid*N] = K2w[tid*N+1];
K2e[(tid+1)*N-1] = K2e[(tid+1)*N-2];
tid += blockDim.x * gridDim.x;
}
} | .text
.file "LeftRightBound2D.hip"
.globl _Z31__device_stub__LeftRightBound2DPdS_S_S_iii # -- Begin function _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__LeftRightBound2DPdS_S_S_iii,@function
_Z31__device_stub__LeftRightBound2DPdS_S_S_iii: # @_Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16LeftRightBound2DPdS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__LeftRightBound2DPdS_S_S_iii, .Lfunc_end0-_Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16LeftRightBound2DPdS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $hcri, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type hcri,@object # @hcri
.local hcri
.comm hcri,8,8
.type _Z16LeftRightBound2DPdS_S_S_iii,@object # @_Z16LeftRightBound2DPdS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z16LeftRightBound2DPdS_S_S_iii
.p2align 3, 0x0
_Z16LeftRightBound2DPdS_S_S_iii:
.quad _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.size _Z16LeftRightBound2DPdS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16LeftRightBound2DPdS_S_S_iii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "hcri"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hcri
.addrsig_sym _Z16LeftRightBound2DPdS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16LeftRightBound2DPdS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe20003f05270 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @!P0 BRA 0x230 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x002fe200000001ff */
/*00a0*/ IMAD R14, R0, c[0x0][0x188], RZ ; /* 0x00006200000e7a24 */
/* 0x000fd200078e02ff */
/*00b0*/ IMAD.WIDE R2, R14, R17, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fcc00078e0211 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ IADD3 R16, R14.reuse, c[0x0][0x188], RZ ; /* 0x000062000e107a10 */
/* 0x040fe20007ffe0ff */
/*00e0*/ IMAD.WIDE R6, R14, R17, c[0x0][0x160] ; /* 0x000058000e067625 */
/* 0x000fc600078e0211 */
/*00f0*/ IADD3 R12, R16, -0x1, RZ ; /* 0xffffffff100c7810 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE R8, R12, R17, c[0x0][0x168] ; /* 0x00005a000c087625 */
/* 0x000fe200078e0211 */
/*0110*/ DADD R4, R2, c[0x3][0x0] ; /* 0x00c0000002047629 */
/* 0x004e0e0000000000 */
/*0120*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x0011e8000c101b04 */
/*0130*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R12, R12, R17, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fc800078e0211 */
/*0150*/ IMAD.WIDE R14, R14, R17, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fe200078e0211 */
/*0160*/ DADD R10, R8, c[0x3][0x0] ; /* 0x00c00000080a7629 */
/* 0x004e4e0000000000 */
/*0170*/ STG.E.64 [R12.64], R10 ; /* 0x0000000a0c007986 */
/* 0x0023e8000c101b04 */
/*0180*/ LDG.E.64 R2, [R14.64+0x8] ; /* 0x000008040e027981 */
/* 0x000ea2000c1e1b00 */
/*0190*/ IADD3 R16, R16, -0x2, RZ ; /* 0xfffffffe10107810 */
/* 0x000fca0007ffe0ff */
/*01a0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*01b0*/ STG.E.64 [R14.64], R2 ; /* 0x000000020e007986 */
/* 0x0043e8000c101b04 */
/*01c0*/ LDG.E.64 R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1b00 */
/*01d0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x001fca0000000f00 */
/*01e0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fca00078e0200 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0200*/ STG.E.64 [R16.64+0x8], R18 ; /* 0x0000081210007986 */
/* 0x0043d8000c101b04 */
/*0210*/ @!P0 BRA 0x90 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ HFMA2.MMA R17, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff117435 */
/* 0x001fe200000001ff */
/*0240*/ IMAD R14, R0, c[0x0][0x188], RZ ; /* 0x00006200000e7a24 */
/* 0x000fd200078e02ff */
/*0250*/ IMAD.WIDE R12, R14, R17, c[0x0][0x160] ; /* 0x000058000e0c7625 */
/* 0x000fca00078e0211 */
/*0260*/ LDG.E.64 R2, [R12.64+0x8] ; /* 0x000008040c027981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IADD3 R4, R14, c[0x0][0x188], RZ ; /* 0x000062000e047a10 */
/* 0x000fc80007ffe0ff */
/*0280*/ IADD3 R16, R4, -0x2, RZ ; /* 0xfffffffe04107810 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE R4, R16, R17.reuse, c[0x0][0x160] ; /* 0x0000580010047625 */
/* 0x080fe200078e0211 */
/*02a0*/ STG.E.64 [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0041e8000c101b04 */
/*02b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea2000c1e1b00 */
/*02c0*/ IMAD.WIDE R14, R14, R17, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fc600078e0211 */
/*02d0*/ STG.E.64 [R4.64+0x8], R6 ; /* 0x0000080604007986 */
/* 0x0041e8000c101b04 */
/*02e0*/ LDG.E.64 R8, [R14.64+0x8] ; /* 0x000008040e087981 */
/* 0x000ea2000c1e1b00 */
/*02f0*/ IMAD.WIDE R16, R16, R17, c[0x0][0x170] ; /* 0x00005c0010107625 */
/* 0x000fe200078e0211 */
/*0300*/ MOV R19, c[0x0][0x0] ; /* 0x0000000000137a02 */
/* 0x000fe40000000f00 */
/*0310*/ STG.E.64 [R14.64], R8 ; /* 0x000000080e007986 */
/* 0x0041e8000c101b04 */
/*0320*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IMAD R0, R19, c[0x0][0xc], R0 ; /* 0x0000030013007a24 */
/* 0x000fca00078e0200 */
/*0340*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0350*/ STG.E.64 [R16.64+0x8], R10 ; /* 0x0000080a10007986 */
/* 0x0041d8000c101b04 */
/*0360*/ @!P0 BRA 0x230 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16LeftRightBound2DPdS_S_S_iii
.globl _Z16LeftRightBound2DPdS_S_S_iii
.p2align 8
.type _Z16LeftRightBound2DPdS_S_S_iii,@function
_Z16LeftRightBound2DPdS_S_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s10, s[0:1], 0x24
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s4, 0xffff
s_mov_b32 s4, exec_lo
s_mul_i32 s15, s15, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v7, s15, v0
v_cmpx_gt_i32_e64 s10, v7
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s4, s[0:1], 0x20
s_load_b32 s14, s[0:1], 0x28
s_load_b32 s13, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 0
v_mad_u64_u32 v[0:1], null, s14, v7, s[14:15]
s_cselect_b32 s11, -1, 0
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, hcri@rel32@lo+4
s_addc_u32 s9, s9, hcri@rel32@hi+12
s_load_b256 s[0:7], s[0:1], 0x0
s_load_b64 s[8:9], s[8:9], 0x0
v_mul_lo_u32 v8, s14, v7
s_mul_i32 s12, s13, s12
s_mov_b32 s13, 0
s_mul_i32 s14, s12, s14
s_mov_b32 s15, 0
s_branch .LBB0_3
.LBB0_2:
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v7, s12, v7
s_add_i32 s15, s15, s14
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v5
global_load_b64 v[3:4], v[1:2], off offset:8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s10, v7
s_or_b32 s13, vcc_lo, s13
s_waitcnt vmcnt(0)
global_store_b64 v[1:2], v[3:4], off
global_load_b64 v[1:2], v[5:6], off offset:-16
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[1:2], off offset:-8
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_7
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v8
s_and_b32 vcc_lo, exec_lo, s11
s_mov_b32 s16, -1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
s_cbranch_vccz .LBB0_5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add3_u32 v9, v0, s15, -1
v_add_co_u32 v11, vcc_lo, s0, v3
global_load_b64 v[5:6], v[5:6], off
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v4, vcc_lo
v_ashrrev_i32_e32 v10, 31, v9
s_mov_b32 s16, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v13, vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s1, v10, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], s[8:9], v[5:6]
global_store_b64 v[11:12], v[5:6], off
global_load_b64 v[5:6], v[13:14], off
s_waitcnt vmcnt(0)
v_add_f64 v[5:6], s[8:9], v[5:6]
global_store_b64 v[9:10], v[5:6], off
.LBB0_5:
v_add_nc_u32_e32 v5, s15, v0
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_ashrrev_i32_e32 v6, 31, v5
global_load_b64 v[9:10], v[3:4], off offset:8
v_lshlrev_b64 v[11:12], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s1, v12, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[9:10], off
global_load_b64 v[3:4], v[11:12], off offset:-16
s_waitcnt vmcnt(0)
global_store_b64 v[11:12], v[3:4], off offset:-8
s_branch .LBB0_2
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16LeftRightBound2DPdS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16LeftRightBound2DPdS_S_S_iii, .Lfunc_end0-_Z16LeftRightBound2DPdS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected hcri
.type hcri,@object
.section .bss,"aw",@nobits
.globl hcri
.p2align 3, 0x0
hcri:
.quad 0x0000000000000000
.size hcri, 8
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym hcri
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16LeftRightBound2DPdS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z16LeftRightBound2DPdS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021ec0_00000000-6_LeftRightBound2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
.type _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii, @function
_Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16LeftRightBound2DPdS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii, .-_Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
.globl _Z16LeftRightBound2DPdS_S_S_iii
.type _Z16LeftRightBound2DPdS_S_S_iii, @function
_Z16LeftRightBound2DPdS_S_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z16LeftRightBound2DPdS_S_S_iiiPdS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16LeftRightBound2DPdS_S_S_iii, .-_Z16LeftRightBound2DPdS_S_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16LeftRightBound2DPdS_S_S_iii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "hcri"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16LeftRightBound2DPdS_S_S_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4hcri(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4hcri
.comm _ZL4hcri,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LeftRightBound2D.hip"
.globl _Z31__device_stub__LeftRightBound2DPdS_S_S_iii # -- Begin function _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.p2align 4, 0x90
.type _Z31__device_stub__LeftRightBound2DPdS_S_S_iii,@function
_Z31__device_stub__LeftRightBound2DPdS_S_S_iii: # @_Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16LeftRightBound2DPdS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z31__device_stub__LeftRightBound2DPdS_S_S_iii, .Lfunc_end0-_Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16LeftRightBound2DPdS_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $hcri, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type hcri,@object # @hcri
.local hcri
.comm hcri,8,8
.type _Z16LeftRightBound2DPdS_S_S_iii,@object # @_Z16LeftRightBound2DPdS_S_S_iii
.section .rodata,"a",@progbits
.globl _Z16LeftRightBound2DPdS_S_S_iii
.p2align 3, 0x0
_Z16LeftRightBound2DPdS_S_S_iii:
.quad _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.size _Z16LeftRightBound2DPdS_S_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16LeftRightBound2DPdS_S_S_iii"
.size .L__unnamed_1, 32
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "hcri"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__LeftRightBound2DPdS_S_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym hcri
.addrsig_sym _Z16LeftRightBound2DPdS_S_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <ctype.h>
#include <vector>
#include <string>
typedef std::vector<double> double_vec;
int main()
{
double_vec aapl, msft;
std::string values;
std::string delimiter = " ";
while (true)
{
std::getline(std::cin, values);
if (!isdigit(values[0]))
{
break;
}
else
{
std::string first_val = values.substr(0, values.find(delimiter));
aapl.push_back(std::stod(first_val));
std::string second_val = values.erase(0, values.find(delimiter) + delimiter.length());
msft.push_back(std::stod(second_val));
}
}
thrust::host_vector<double> host_aapl(int(aapl.size())), host_msft(int(msft.size()));
host_aapl = aapl;
host_msft = msft;
thrust::device_vector<double> dev_aapl(host_aapl), dev_msft(host_msft), dev(int(aapl.size()), 0);
thrust::transform(
dev_aapl.begin(),
dev_aapl.end(),
dev_msft.begin(),
dev.begin(),
thrust::minus<double>());
double sumDiffs = thrust::reduce(dev.begin(), dev.end(), 0.0, thrust::plus<double>());
double avgDiffs = sumDiffs / int(aapl.size());
std::cout << "Diferença média entre AAPL e MSFT nos últimos 10 anos: US$ " << avgDiffs << std::endl;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <iostream>
#include <ctype.h>
#include <vector>
#include <string>
typedef std::vector<double> double_vec;
int main()
{
double_vec aapl, msft;
std::string values;
std::string delimiter = " ";
while (true)
{
std::getline(std::cin, values);
if (!isdigit(values[0]))
{
break;
}
else
{
std::string first_val = values.substr(0, values.find(delimiter));
aapl.push_back(std::stod(first_val));
std::string second_val = values.erase(0, values.find(delimiter) + delimiter.length());
msft.push_back(std::stod(second_val));
}
}
thrust::host_vector<double> host_aapl(int(aapl.size())), host_msft(int(msft.size()));
host_aapl = aapl;
host_msft = msft;
thrust::device_vector<double> dev_aapl(host_aapl), dev_msft(host_msft), dev(int(aapl.size()), 0);
thrust::transform(
dev_aapl.begin(),
dev_aapl.end(),
dev_msft.begin(),
dev.begin(),
thrust::minus<double>());
double sumDiffs = thrust::reduce(dev.begin(), dev.end(), 0.0, thrust::plus<double>());
double avgDiffs = sumDiffs / int(aapl.size());
std::cout << "Diferença média entre AAPL e MSFT nos últimos 10 anos: US$ " << avgDiffs << std::endl;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void lga_filter_backward (const int n, const float *bottom_data, const float *top_diff, const int height, const int width, const int channel, const int radius, float *filter_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int wsize = 2 * radius + 1;
int base =
index / (step * wsize * wsize * 3) * (step * channel) + index % step;
int location = index / step % (wsize * wsize * 3);
int d = location / (wsize * wsize) - 1;
int r = (location / wsize) % wsize - radius;
int c = location % wsize - radius;
int rr = index % step / width + r;
int cc = index % width + c;
for (int i = 0; i < channel; i++)
{
int dd = i + d;
if (rr >= 0 && cc >= 0 && dd >= 0 && rr < height && cc < width
&& dd < channel)
{
int shift = r * width + c + d * step;
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + shift + i * step];
}
else
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + i * step];
}
} | .file "tmpxft_000d69f3_00000000-6_lga_filter_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
.type _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf, @function
_Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19lga_filter_backwardiPKfS0_iiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf, .-_Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
.globl _Z19lga_filter_backwardiPKfS0_iiiiPf
.type _Z19lga_filter_backwardiPKfS0_iiiiPf, @function
_Z19lga_filter_backwardiPKfS0_iiiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19lga_filter_backwardiPKfS0_iiiiPf, .-_Z19lga_filter_backwardiPKfS0_iiiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19lga_filter_backwardiPKfS0_iiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19lga_filter_backwardiPKfS0_iiiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void lga_filter_backward (const int n, const float *bottom_data, const float *top_diff, const int height, const int width, const int channel, const int radius, float *filter_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int wsize = 2 * radius + 1;
int base =
index / (step * wsize * wsize * 3) * (step * channel) + index % step;
int location = index / step % (wsize * wsize * 3);
int d = location / (wsize * wsize) - 1;
int r = (location / wsize) % wsize - radius;
int c = location % wsize - radius;
int rr = index % step / width + r;
int cc = index % width + c;
for (int i = 0; i < channel; i++)
{
int dd = i + d;
if (rr >= 0 && cc >= 0 && dd >= 0 && rr < height && cc < width
&& dd < channel)
{
int shift = r * width + c + d * step;
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + shift + i * step];
}
else
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + i * step];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lga_filter_backward (const int n, const float *bottom_data, const float *top_diff, const int height, const int width, const int channel, const int radius, float *filter_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int wsize = 2 * radius + 1;
int base =
index / (step * wsize * wsize * 3) * (step * channel) + index % step;
int location = index / step % (wsize * wsize * 3);
int d = location / (wsize * wsize) - 1;
int r = (location / wsize) % wsize - radius;
int c = location % wsize - radius;
int rr = index % step / width + r;
int cc = index % width + c;
for (int i = 0; i < channel; i++)
{
int dd = i + d;
if (rr >= 0 && cc >= 0 && dd >= 0 && rr < height && cc < width
&& dd < channel)
{
int shift = r * width + c + d * step;
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + shift + i * step];
}
else
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + i * step];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lga_filter_backward (const int n, const float *bottom_data, const float *top_diff, const int height, const int width, const int channel, const int radius, float *filter_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int wsize = 2 * radius + 1;
int base =
index / (step * wsize * wsize * 3) * (step * channel) + index % step;
int location = index / step % (wsize * wsize * 3);
int d = location / (wsize * wsize) - 1;
int r = (location / wsize) % wsize - radius;
int c = location % wsize - radius;
int rr = index % step / width + r;
int cc = index % width + c;
for (int i = 0; i < channel; i++)
{
int dd = i + d;
if (rr >= 0 && cc >= 0 && dd >= 0 && rr < height && cc < width
&& dd < channel)
{
int shift = r * width + c + d * step;
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + shift + i * step];
}
else
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + i * step];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19lga_filter_backwardiPKfS0_iiiiPf
.globl _Z19lga_filter_backwardiPKfS0_iiiiPf
.p2align 8
.type _Z19lga_filter_backwardiPKfS0_iiiiPf,@function
_Z19lga_filter_backwardiPKfS0_iiiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x18
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s12, 31
s_add_i32 s3, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s3, s2
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s3, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v2, v0
v_ashrrev_i32_e32 v0, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v3, s3, v2
s_lshl_b32 s3, s7, 1
s_or_b32 s3, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s3, s3
s_mul_i32 s9, s8, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_cvt_f32_u32_e32 v5, s9
v_rcp_iflag_f32_e32 v5, v5
v_add_nc_u32_e32 v4, v1, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v5, 0x4f7ffffe, v5 :: v_dual_add_nc_u32 v2, v2, v3
v_xor_b32_e32 v4, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v4, v2
v_mul_lo_u32 v3, v2, s10
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v4, v3
v_subrev_nc_u32_e32 v7, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v3, v3, v7
v_xor_b32_e32 v7, s2, v0
s_sub_i32 s2, 0, s9
s_cmp_lt_i32 s6, 1
v_add_nc_u32_e32 v6, 1, v2
v_cmp_le_u32_e32 vcc_lo, s10, v3
v_cvt_u32_f32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
v_mul_lo_u32 v6, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v7
v_sub_nc_u32_e32 v5, v2, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v3, v6
v_ashrrev_i32_e32 v7, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
v_add_nc_u32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v6, v7
v_mul_hi_u32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, s9
v_sub_nc_u32_e32 v2, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s9, v2
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e32 v8, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s9, v8
s_cbranch_scc1 .LBB0_4
s_load_b64 s[10:11], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v10, s9, v8
v_cvt_f32_u32_e32 v13, s8
s_ashr_i32 s15, s5, 31
v_mul_lo_u32 v20, v5, s12
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v1, v20
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, s2, s10, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s2, s11, v3, s2
s_ashr_i32 s2, s3, 31
s_mul_i32 s11, s9, s12
s_add_i32 s10, s3, s2
global_load_b32 v6, v[2:3], off
s_xor_b32 s10, s10, s2
s_ashr_i32 s14, s11, 31
v_cvt_f32_u32_e32 v9, s10
s_add_i32 s11, s11, s14
v_xor_b32_e32 v22, s14, v0
s_xor_b32 s9, s11, s14
s_sub_i32 s11, 0, s10
v_rcp_iflag_f32_e32 v9, v9
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
v_cvt_f32_u32_e32 v11, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v10, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
v_xor_b32_e32 v8, v8, v7
v_cvt_u32_f32_e32 v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v8, v7
v_mul_lo_u32 v7, s11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
s_sub_i32 s11, 0, s9
v_xor_b32_e32 v19, s2, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_hi_u32 v7, v9, v7
v_mul_f32_e32 v8, 0x4f7ffffe, v10
v_add_nc_u32_e32 v10, v11, v12
v_xor_b32_e32 v15, v10, v12
v_rcp_iflag_f32_e32 v10, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v13, v9, v7
v_cvt_u32_f32_e32 v8, v8
v_mul_hi_u32 v9, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v14, s11, v8
s_sub_i32 s11, 0, s8
v_add_nc_u32_e32 v18, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v7, v8, v14
v_mul_lo_u32 v14, v9, s10
v_sub_nc_u32_e32 v14, v15, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s10, v14
v_dual_cndmask_b32 v9, v9, v18 :: v_dual_add_nc_u32 v16, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, v4, v16, 0
v_subrev_nc_u32_e32 v7, s10, v14
v_dual_mul_f32 v10, 0x4f7ffffe, v10 :: v_dual_cndmask_b32 v7, v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cvt_u32_f32_e32 v10, v10
v_add_nc_u32_e32 v14, 1, v9
v_mul_lo_u32 v18, v8, s9
v_cmp_le_u32_e32 vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v17, s11, v10
s_add_i32 s11, s5, s15
s_xor_b32 s11, s11, s15
v_cndmask_b32_e32 v7, v9, v14, vcc_lo
v_cvt_f32_u32_e32 v16, s11
s_sub_i32 s2, 0, s11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v17, v10, v17
v_xor_b32_e32 v7, v7, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v16, v16
v_add_nc_u32_e32 v14, v10, v17
v_sub_nc_u32_e32 v17, v4, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v18, v7, v19
v_mad_u64_u32 v[9:10], null, v15, v14, 0
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v14, 31, v18
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v16, 0x4f7ffffe, v16
v_add_nc_u32_e32 v7, 1, v8
v_cmp_le_u32_e32 vcc_lo, s9, v17
v_add_nc_u32_e32 v19, v18, v14
s_delay_alu instid0(VALU_DEP_4)
v_cvt_u32_f32_e32 v9, v16
v_mul_lo_u32 v21, v10, s8
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
v_subrev_nc_u32_e32 v8, s9, v17
v_xor_b32_e32 v19, v19, v14
v_mul_lo_u32 v16, s2, v9
v_mul_lo_u32 v18, v18, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v8, v17, v8 :: v_dual_add_nc_u32 v17, 1, v7
v_mul_hi_u32 v13, v19, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v16, v9, v16
v_cmp_le_u32_e32 vcc_lo, s9, v8
v_sub_nc_u32_e32 v8, v15, v21
v_add_nc_u32_e32 v15, 1, v10
v_mul_lo_u32 v13, v13, s10
v_add_nc_u32_e32 v9, v9, v16
v_ashrrev_i32_e32 v16, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v21, v4, v9
v_sub_nc_u32_e32 v13, v19, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v19, v21, s11
v_subrev_nc_u32_e32 v21, s10, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v19
v_subrev_nc_u32_e32 v19, s11, v4
v_cndmask_b32_e32 v7, v7, v17, vcc_lo
v_subrev_nc_u32_e32 v17, s8, v8
v_cmp_le_u32_e32 vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v7, v22
v_cndmask_b32_e32 v10, v10, v15, vcc_lo
v_dual_cndmask_b32 v8, v8, v17 :: v_dual_add_nc_u32 v15, v5, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, 1, v10
v_cmp_le_u32_e32 vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v15, v15, v16
v_xor_b32_e32 v16, s15, v16
v_cndmask_b32_e32 v8, v10, v17, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s10, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v9, v15, v9
v_xor_b32_e32 v17, v8, v12
v_cndmask_b32_e32 v10, v13, v21, vcc_lo
v_sub_nc_u32_e32 v13, v7, v22
v_not_b32_e32 v12, v12
v_mul_lo_u32 v8, v9, s11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s10, v10
v_cmp_le_u32_e32 vcc_lo, s10, v10
v_mul_lo_u32 v21, s6, v13
v_dual_cndmask_b32 v7, v10, v7 :: v_dual_add_nc_u32 v22, 1, v9
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_sub_nc_u32_e32 v15, v15, v8
v_cndmask_b32_e32 v10, v4, v19, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v7, v14
v_add3_u32 v19, v17, v21, v12
v_subrev_nc_u32_e32 v23, s11, v15
v_cmp_le_u32_e32 vcc_lo, s11, v15
v_subrev_nc_u32_e32 v21, s11, v10
v_cmp_le_u32_e64 s2, s11, v10
v_mad_u64_u32 v[7:8], null, s4, v19, v[4:5]
v_cndmask_b32_e32 v8, v9, v22, vcc_lo
v_sub_nc_u32_e32 v4, v4, v14
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v10, v21, s2
v_cndmask_b32_e32 v10, v15, v23, vcc_lo
v_sub_nc_u32_e32 v7, v7, v14
v_xor_b32_e32 v9, v9, v0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s11, v10
v_sub_nc_u32_e32 v10, v11, v18
v_subrev_nc_u32_e32 v4, s7, v4
v_subrev_nc_u32_e32 v7, s7, v7
v_sub_nc_u32_e32 v0, v9, v0
s_load_b128 s[8:11], s[0:1], 0x8
v_subrev_nc_u32_e32 v9, s7, v10
s_mul_i32 s0, s12, s6
v_mul_lo_u32 v7, s5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v1, v11, v1, v7
v_add_nc_u32_e32 v7, v0, v9
v_add_nc_u32_e32 v15, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s1, s5, v7
v_cndmask_b32_e32 v8, v8, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, v8, v16
v_sub_nc_u32_e32 v8, v8, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v8, v4
v_sub_nc_u32_e32 v8, v1, v18
v_or_b32_e32 v9, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v9
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, s0, v13, v[5:6]
v_sub_nc_u32_e32 v5, v8, v20
v_add_nc_u32_e32 v1, v12, v17
v_cmp_gt_i32_e64 s0, s4, v4
s_mov_b32 s4, s6
s_delay_alu instid0(VALU_DEP_3)
v_subrev_nc_u32_e32 v4, s7, v5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
v_cmp_lt_i32_e64 s2, -1, v1
v_add_nc_u32_e32 v7, s13, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v5, s13, v4
v_cmp_gt_i32_e64 s3, s6, v1
s_add_i32 s4, s4, -1
s_and_b32 s2, vcc_lo, s2
v_ashrrev_i32_e32 v8, 31, v7
s_and_b32 s2, s2, s0
v_ashrrev_i32_e32 v11, 31, v5
s_and_b32 s2, s2, s1
s_add_i32 s13, s13, s12
s_and_b32 s2, s2, s3
v_lshlrev_b64 v[9:10], 2, v[7:8]
v_cndmask_b32_e64 v8, v8, v11, s2
v_cndmask_b32_e64 v7, v7, v5, s2
s_cmp_lg_u32 s4, 0
v_add_nc_u32_e32 v1, 1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, s2, s10, v9
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e64 v10, s2, s11, v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v7, s2, s8, v7
v_add_co_ci_u32_e64 v8, s2, s9, v8, s2
global_load_b32 v5, v[9:10], off
global_load_b32 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19lga_filter_backwardiPKfS0_iiiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19lga_filter_backwardiPKfS0_iiiiPf, .Lfunc_end0-_Z19lga_filter_backwardiPKfS0_iiiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19lga_filter_backwardiPKfS0_iiiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19lga_filter_backwardiPKfS0_iiiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void lga_filter_backward (const int n, const float *bottom_data, const float *top_diff, const int height, const int width, const int channel, const int radius, float *filter_diff){
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= n)
{
return;
}
int step = height * width;
int wsize = 2 * radius + 1;
int base =
index / (step * wsize * wsize * 3) * (step * channel) + index % step;
int location = index / step % (wsize * wsize * 3);
int d = location / (wsize * wsize) - 1;
int r = (location / wsize) % wsize - radius;
int c = location % wsize - radius;
int rr = index % step / width + r;
int cc = index % width + c;
for (int i = 0; i < channel; i++)
{
int dd = i + d;
if (rr >= 0 && cc >= 0 && dd >= 0 && rr < height && cc < width
&& dd < channel)
{
int shift = r * width + c + d * step;
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + shift + i * step];
}
else
filter_diff[index] +=
top_diff[base + i * step] * bottom_data[base + i * step];
}
} | .text
.file "lga_filter_backward.hip"
.globl _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf # -- Begin function _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.p2align 4, 0x90
.type _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf,@function
_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf: # @_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19lga_filter_backwardiPKfS0_iiiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf, .Lfunc_end0-_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19lga_filter_backwardiPKfS0_iiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19lga_filter_backwardiPKfS0_iiiiPf,@object # @_Z19lga_filter_backwardiPKfS0_iiiiPf
.section .rodata,"a",@progbits
.globl _Z19lga_filter_backwardiPKfS0_iiiiPf
.p2align 3, 0x0
_Z19lga_filter_backwardiPKfS0_iiiiPf:
.quad _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.size _Z19lga_filter_backwardiPKfS0_iiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19lga_filter_backwardiPKfS0_iiiiPf"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19lga_filter_backwardiPKfS0_iiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d69f3_00000000-6_lga_filter_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
.type _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf, @function
_Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 20(%rsp)
movl %r9d, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19lga_filter_backwardiPKfS0_iiiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf, .-_Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
.globl _Z19lga_filter_backwardiPKfS0_iiiiPf
.type _Z19lga_filter_backwardiPKfS0_iiiiPf, @function
_Z19lga_filter_backwardiPKfS0_iiiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z50__device_stub__Z19lga_filter_backwardiPKfS0_iiiiPfiPKfS0_iiiiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19lga_filter_backwardiPKfS0_iiiiPf, .-_Z19lga_filter_backwardiPKfS0_iiiiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19lga_filter_backwardiPKfS0_iiiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19lga_filter_backwardiPKfS0_iiiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lga_filter_backward.hip"
.globl _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf # -- Begin function _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.p2align 4, 0x90
.type _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf,@function
_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf: # @_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19lga_filter_backwardiPKfS0_iiiiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf, .Lfunc_end0-_Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19lga_filter_backwardiPKfS0_iiiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19lga_filter_backwardiPKfS0_iiiiPf,@object # @_Z19lga_filter_backwardiPKfS0_iiiiPf
.section .rodata,"a",@progbits
.globl _Z19lga_filter_backwardiPKfS0_iiiiPf
.p2align 3, 0x0
_Z19lga_filter_backwardiPKfS0_iiiiPf:
.quad _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.size _Z19lga_filter_backwardiPKfS0_iiiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19lga_filter_backwardiPKfS0_iiiiPf"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__lga_filter_backwardiPKfS0_iiiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19lga_filter_backwardiPKfS0_iiiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} | code for sm_80
Function : _Z22BilinearResampleKernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R5 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*00b0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00c0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*00e0*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fce000fffe13f */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc60000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0170*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*0180*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0190*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*01a0*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R2, -R0, RZ, RZ ; /* 0x000000ff00027210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R2, R5.reuse, R2, R6 ; /* 0x0000000205027224 */
/* 0x040fe400078e0206 */
/*01d0*/ I2F R6, UR4 ; /* 0x0000000400067d06 */
/* 0x000fe60008201400 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fca0003f04070 */
/*01f0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x001e300000001000 */
/*0200*/ @!P0 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102028824 */
/* 0x000fe200078e0a05 */
/*0210*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc40003f05270 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f26070 */
/*0240*/ LOP3.LUT R2, R4, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0004027a12 */
/* 0x000fe200078e3cff */
/*0250*/ FFMA R3, -R7, R8, 1 ; /* 0x3f80000007037423 */
/* 0x001fc60000000108 */
/*0260*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0270*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fc80000000008 */
/*0280*/ FFMA R2, R6, R3, RZ ; /* 0x0000000306027223 */
/* 0x000fe400000000ff */
/*0290*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ FCHK P1, R6, R7 ; /* 0x0000000706007302 */
/* 0x000e220000020000 */
/*02b0*/ FFMA R5, -R7, R2, R6 ; /* 0x0000000207057223 */
/* 0x000fc80000000106 */
/*02c0*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*02d0*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff008a12 */
/* 0x000fe200078e33ff */
/*02e0*/ FFMA R5, R3, R5, R2 ; /* 0x0000000503057223 */
/* 0x000fc60000000002 */
/*02f0*/ IADD3 R9, -R0, RZ, RZ ; /* 0x000000ff00097210 */
/* 0x000fca0007ffe1ff */
/*0300*/ IMAD R3, R9, c[0x0][0x178], R4 ; /* 0x00005e0009037a24 */
/* 0x000fe200078e0204 */
/*0310*/ @!P1 BRA 0x360 ; /* 0x0000004000009947 */
/* 0x001fea0003800000 */
/*0320*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0330*/ MOV R2, 0x350 ; /* 0x0000035000027802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x780 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0350*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0004 */
/*0360*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0370*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0380*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fce0000000800 */
/*0390*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*03a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*03b0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fd2000fffe13f */
/*03c0*/ I2F R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000e620008201400 */
/*03d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*03e0*/ MUFU.RCP R4, R7 ; /* 0x0000000700047308 */
/* 0x001e300000001000 */
/*03f0*/ FCHK P0, R2, R7 ; /* 0x0000000702007302 */
/* 0x002e620000000000 */
/*0400*/ FFMA R9, -R7, R4, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000104 */
/*0410*/ FFMA R9, R4, R9, R4 ; /* 0x0000000904097223 */
/* 0x000fc80000000004 */
/*0420*/ FFMA R4, R2, R9, RZ ; /* 0x0000000902047223 */
/* 0x000fc800000000ff */
/*0430*/ FFMA R6, -R7, R4, R2 ; /* 0x0000000407067223 */
/* 0x000fc80000000102 */
/*0440*/ FFMA R4, R9, R6, R4 ; /* 0x0000000609047223 */
/* 0x000fe20000000004 */
/*0450*/ @!P0 BRA 0x490 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0460*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0470*/ MOV R2, 0x490 ; /* 0x0000049000027802 */
/* 0x000fe40000000f00 */
/*0480*/ CALL.REL.NOINC 0x780 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0490*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x000e700000201400 */
/*04a0*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x000ea20000201400 */
/*04b0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x002fc40000400000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fca00078e00ff */
/*04d0*/ F2I.FLOOR.NTZ R16, R5 ; /* 0x0000000500107305 */
/* 0x000fe20000207100 */
/*04e0*/ FMUL R4, R7, R4 ; /* 0x0000000407047220 */
/* 0x005fce0000400000 */
/*04f0*/ F2I.CEIL.NTZ R21, R5 ; /* 0x0000000500157305 */
/* 0x000e30000020b100 */
/*0500*/ F2I.CEIL.NTZ R6, R4 ; /* 0x0000000400067305 */
/* 0x000e62000020b100 */
/*0510*/ ISETP.NE.AND P0, PT, R16, R21, PT ; /* 0x000000151000720c */
/* 0x001fce0003f05270 */
/*0520*/ F2I.FLOOR.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000e220000207100 */
/*0530*/ IMAD R9, R6, c[0x0][0x170], R16 ; /* 0x00005c0006097a24 */
/* 0x002fc800078e0210 */
/*0540*/ IMAD.WIDE R8, R9, R2, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0202 */
/*0550*/ @P0 IMAD R15, R6, c[0x0][0x170], R21.reuse ; /* 0x00005c00060f0a24 */
/* 0x100fe400078e0215 */
/*0560*/ @P0 IMAD R11, R7, c[0x0][0x170], R21 ; /* 0x00005c00070b0a24 */
/* 0x001fe200078e0215 */
/*0570*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a2000c1e1900 */
/*0580*/ @P0 IMAD.WIDE R14, R15, R2, c[0x0][0x160] ; /* 0x000058000f0e0625 */
/* 0x000fc800078e0202 */
/*0590*/ IMAD R13, R7, c[0x0][0x170], R16 ; /* 0x00005c00070d7a24 */
/* 0x000fe400078e0210 */
/*05a0*/ @P0 IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x160] ; /* 0x000058000b0a0625 */
/* 0x080fe200078e0202 */
/*05b0*/ @P0 LDG.E R14, [R14.64] ; /* 0x000000040e0e0981 */
/* 0x0002e6000c1e1900 */
/*05c0*/ IMAD.WIDE R12, R13, R2, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e0202 */
/*05d0*/ @P0 LDG.E R10, [R10.64] ; /* 0x000000040a0a0981 */
/* 0x000f28000c1e1900 */
/*05e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*05f0*/ I2F R18, R21 ; /* 0x0000001500127306 */
/* 0x000e300000201400 */
/*0600*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e700000201400 */
/*0610*/ I2F R19, R6 ; /* 0x0000000600137306 */
/* 0x000e620000201400 */
/*0620*/ FADD R18, R5, -R18 ; /* 0x8000001205127221 */
/* 0x001fce0000000000 */
/*0630*/ I2F R17, R7 ; /* 0x0000000700117306 */
/* 0x000e220000201400 */
/*0640*/ FADD R5, -R5, R16 ; /* 0x0000001005057221 */
/* 0x002fe20000000100 */
/*0650*/ ISETP.NE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f25270 */
/*0660*/ FADD R15, R18, 1 ; /* 0x3f800000120f7421 */
/* 0x000fe40000000000 */
/*0670*/ FADD R9, R5, 1 ; /* 0x3f80000005097421 */
/* 0x000fe40000000000 */
/*0680*/ FADD R19, R4, -R19 ; /* 0x8000001304137221 */
/* 0x000fc80000000000 */
/*0690*/ FADD R19, R19, 1 ; /* 0x3f80000013137421 */
/* 0x000fe40000000000 */
/*06a0*/ FADD R17, -R4, R17 ; /* 0x0000001104117221 */
/* 0x001fe40000000100 */
/*06b0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fe400078e0203 */
/*06c0*/ FADD R17, R17, 1 ; /* 0x3f80000011117421 */
/* 0x000fe40000000000 */
/*06d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0202 */
/*06e0*/ @P0 FMUL R5, R15, R14 ; /* 0x0000000e0f050220 */
/* 0x008fc80000400000 */
/*06f0*/ @P0 FFMA R8, R9, R8, R5 ; /* 0x0000000809080223 */
/* 0x004fe40000000005 */
/*0700*/ @P0 FMUL R5, R15, R10 ; /* 0x0000000a0f050220 */
/* 0x010fe40000400000 */
/*0710*/ @P1 FMUL R7, R19, R8 ; /* 0x0000000813071220 */
/* 0x000fe40000400000 */
/*0720*/ @P0 FFMA R12, R9, R12, R5 ; /* 0x0000000c090c0223 */
/* 0x020fc80000000005 */
/*0730*/ @P1 FFMA R7, R17, R12, R7 ; /* 0x0000000c11071223 */
/* 0x000fca0000000007 */
/*0740*/ @P1 STG.E [R2.64], R7 ; /* 0x0000000702001986 */
/* 0x0001e2000c101904 */
/*0750*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0760*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ SHF.R.U32.HI R6, RZ, 0x17, R7 ; /* 0x00000017ff067819 */
/* 0x000fe40000011607 */
/*0790*/ SHF.R.U32.HI R4, RZ, 0x17, R8.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011608 */
/*07a0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe400078ec0ff */
/*07b0*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*07d0*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0800*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0810*/ @!P0 MOV R6, RZ ; /* 0x000000ff00068202 */
/* 0x000fe20000000f00 */
/*0820*/ @!P0 BRA 0x9a0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0830*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0840*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0850*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0860*/ @P0 BRA 0xd80 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c804 */
/*0880*/ @!P0 BRA 0xd60 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0890*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*08a0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*08b0*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*08c0*/ @!P1 BRA !P2, 0xd60 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*08d0*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*08e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*08f0*/ @P1 BRA 0xd40 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0910*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0920*/ @P0 BRA 0xd10 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0940*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0950*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0960*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0970*/ @!P0 FFMA R4, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008048823 */
/* 0x000fe400000000ff */
/*0980*/ @!P1 FFMA R7, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007079823 */
/* 0x000fe200000000ff */
/*0990*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ LEA R8, R12, 0xc0800000, 0x17 ; /* 0xc08000000c087811 */
/* 0x000fc800078eb8ff */
/*09b0*/ IADD3 R8, -R8, R7, RZ ; /* 0x0000000708087210 */
/* 0x000fe40007ffe1ff */
/*09c0*/ IADD3 R7, R10, -0x7f, RZ ; /* 0xffffff810a077810 */
/* 0x000fe40007ffe0ff */
/*09d0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e220000001000 */
/*09e0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*09f0*/ IMAD R4, R7, -0x800000, R4 ; /* 0xff80000007047824 */
/* 0x000fe400078e0204 */
/*0a00*/ FFMA R10, R9, R11, 1 ; /* 0x3f800000090a7423 */
/* 0x001fc8000000000b */
/*0a10*/ FFMA R13, R9, R10, R9 ; /* 0x0000000a090d7223 */
/* 0x000fc80000000009 */
/*0a20*/ FFMA R9, R4, R13, RZ ; /* 0x0000000d04097223 */
/* 0x000fc800000000ff */
/*0a30*/ FFMA R10, R11, R9, R4 ; /* 0x000000090b0a7223 */
/* 0x000fc80000000004 */
/*0a40*/ FFMA R10, R13, R10, R9 ; /* 0x0000000a0d0a7223 */
/* 0x000fe20000000009 */
/*0a50*/ IADD3 R9, R7, 0x7f, -R12 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80c */
/*0a60*/ FFMA R11, R11, R10, R4 ; /* 0x0000000a0b0b7223 */
/* 0x000fe40000000004 */
/*0a70*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x000fe400078e0206 */
/*0a80*/ FFMA R4, R13, R11, R10 ; /* 0x0000000b0d047223 */
/* 0x000fca000000000a */
/*0a90*/ SHF.R.U32.HI R7, RZ, 0x17, R4 ; /* 0x00000017ff077819 */
/* 0x000fc80000011604 */
/*0aa0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R12, R7, 0x1, R9 ; /* 0x00000001070c7824 */
/* 0x000fca00078e0209 */
/*0ac0*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fc80007ffe0ff */
/*0ad0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0ae0*/ @!P0 BRA 0xcf0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0b00*/ @P0 BRA 0xcc0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0b20*/ @P0 BRA 0xd90 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0b40*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0b50*/ @!P0 BRA 0xd90 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FFMA.RZ R6, R13.reuse, R11.reuse, R10.reuse ; /* 0x0000000b0d067223 */
/* 0x1c0fe2000000c00a */
/*0b70*/ IADD3 R9, R12.reuse, 0x20, RZ ; /* 0x000000200c097810 */
/* 0x040fe20007ffe0ff */
/*0b80*/ FFMA.RM R7, R13.reuse, R11.reuse, R10.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000400a */
/*0b90*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f45270 */
/*0ba0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0bb0*/ FFMA.RP R6, R13, R11, R10 ; /* 0x0000000b0d067223 */
/* 0x000fe2000000800a */
/*0bc0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*0bd0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0be0*/ IADD3 R10, -R12, RZ, RZ ; /* 0x000000ff0c0a7210 */
/* 0x000fc40007ffe1ff */
/*0bf0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0c00*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0c10*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0c20*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0c30*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0c40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0c50*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0c60*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0c70*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0c80*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0c90*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x000fca00078e0206 */
/*0ca0*/ LOP3.LUT R4, R9, R4, RZ, 0xfc, !PT ; /* 0x0000000409047212 */
/* 0x000fe200078efcff */
/*0cb0*/ BRA 0xd90 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0cd0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd90 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ IMAD R4, R9, 0x800000, R4 ; /* 0x0080000009047824 */
/* 0x000fe200078e0204 */
/*0d00*/ BRA 0xd90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d10*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fc800078e4804 */
/*0d20*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0d30*/ BRA 0xd90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fe200078e4804 */
/*0d50*/ BRA 0xd90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d60*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0d70*/ BRA 0xd90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d80*/ FADD.FTZ R4, R8, R7 ; /* 0x0000000708047221 */
/* 0x000fe40000010000 */
/*0d90*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0da0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0db0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff24006007950 */
/* 0x000fea0003c3ffff */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} | .file "tmpxft_000d3e34_00000000-6_BilinearResampleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
.type _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii, @function
_Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22BilinearResampleKernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii, .-_Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
.globl _Z22BilinearResampleKernelPfS_iiii
.type _Z22BilinearResampleKernelPfS_iiii, @function
_Z22BilinearResampleKernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22BilinearResampleKernelPfS_iiii, .-_Z22BilinearResampleKernelPfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22BilinearResampleKernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BilinearResampleKernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22BilinearResampleKernelPfS_iiii
.globl _Z22BilinearResampleKernelPfS_iiii
.p2align 8
.type _Z22BilinearResampleKernelPfS_iiii,@function
_Z22BilinearResampleKernelPfS_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_ashr_i32 s8, s4, 31
s_load_b64 s[6:7], s[0:1], 0x10
s_add_i32 s2, s4, s8
v_ashrrev_i32_e32 v3, 31, v1
s_xor_b32 s9, s2, s8
s_add_i32 s3, s5, -1
v_cvt_f32_u32_e32 v0, s9
v_cvt_f32_i32_e32 v6, s3
s_sub_i32 s2, 0, s9
s_mov_b32 s5, exec_lo
v_add_nc_u32_e32 v5, v1, v3
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v3
v_xor_b32_e32 v3, s8, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, s3
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, v6, v6, v8
v_mul_lo_u32 v2, s2, v0
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_rcp_f32_e32 v11, v9
v_cvt_f32_i32_e32 v4, s2
s_add_i32 s2, s6, -1
v_cvt_f32_i32_e32 v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
v_div_scale_f32 v13, vcc_lo, v7, v4, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v9, v11, 1.0
v_add_nc_u32_e32 v0, v0, v2
v_div_scale_f32 v2, null, v4, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v15, v11
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v2
v_mul_lo_u32 v12, v0, s9
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v2, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v10, v14, v10
v_sub_nc_u32_e32 v5, v5, v12
v_add_nc_u32_e32 v16, 1, v0
v_div_scale_f32 v12, s2, v8, v6, v8
v_mul_f32_e32 v15, v13, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v14, s9, v5
v_cmp_le_u32_e64 s3, s9, v5
v_fma_f32 v17, -v2, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v0, v16, s3
v_cndmask_b32_e64 v5, v5, v14, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v16, v12, v11 :: v_dual_fmac_f32 v15, v17, v10
v_add_nc_u32_e32 v14, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e64 s3, s9, v5
v_fma_f32 v18, -v9, v16, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v5, -v2, v15, v13
v_cndmask_b32_e64 v0, v0, v14, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v16, v18, v11
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v9, v16, v12
v_sub_nc_u32_e32 v2, v0, v3
v_div_fmas_f32 v3, v5, v10, v15
s_mov_b32 vcc_lo, s2
s_load_b64 s[2:3], s[0:1], 0x0
v_div_fmas_f32 v0, v9, v11, v16
v_mul_lo_u32 v5, v2, s4
v_div_fixup_f32 v3, v3, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v6, v0, v6, v8
v_cvt_f32_i32_e32 v8, v2
v_sub_nc_u32_e32 v0, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, v6, v8
v_cvt_f32_i32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v5, v1
v_mul_f32_e32 v7, v3, v4
v_ceil_f32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v5
v_floor_f32_e32 v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v4
v_mul_lo_u32 v9, v3, s6
v_ceil_f32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v8, v5
v_mul_lo_u32 v11, v4, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v10, v10
v_add_nc_u32_e32 v5, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v11, v8
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[12:13], off
v_cmpx_ne_u32_e64 v8, v10
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v11, v11, v10
v_add_nc_u32_e32 v13, v9, v10
v_cvt_f32_i32_e32 v10, v10
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v10, v7, v10 :: v_dual_sub_f32 v7, v8, v7
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_dual_add_f32 v8, 1.0, v10 :: v_dual_add_f32 v7, 1.0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v9, v[11:12], off
global_load_b32 v11, v[13:14], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v9, v8, v9
s_waitcnt vmcnt(0)
v_mul_f32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v6, v7
v_fmac_f32_e32 v8, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v5, v8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
v_cvt_f32_i32_e32 v7, v3
v_cvt_f32_i32_e32 v9, v4
s_load_b64 s[0:1], s[0:1], 0x8
v_cmp_eq_u32_e32 vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v7, v1
v_mad_u64_u32 v[7:8], null, v2, s4, v[0:1]
v_dual_sub_f32 v0, v1, v9 :: v_dual_add_f32 v1, 1.0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, 1.0, v0
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v1, v5
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v0, v6
v_lshlrev_b64 v[0:1], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22BilinearResampleKernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22BilinearResampleKernelPfS_iiii, .Lfunc_end0-_Z22BilinearResampleKernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22BilinearResampleKernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22BilinearResampleKernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void BilinearResampleKernel(float *input, float *output, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int size = outputWidth * outputHeight;
float iT, iB;
if (id < size)
{
//output point coordinates
int px = id % outputWidth;
int py = id / outputWidth;
float xRatio = (float)(inputWidth - 1) / (outputWidth - 1);
float yRatio = (float)(inputHeight - 1) / (outputHeight - 1);
//corresponding coordinates in the original image
float x = xRatio * px;
float y = yRatio * py;
//corresponding integer (pixel) coordinates in the original image
int xL = (int)floor(x);
int xR = (int)ceil(x);
int yT = (int)floor(y);
int yB = (int)ceil(y);
//inverse distances to these points
float dL = 1.0f - (x - xL);
float dR = 1.0f - (xR - x);
float dT = 1.0f - (y - yT);
float dB = 1.0f - (yB - y);
//values at those points
float topLeft = input[yT * inputWidth + xL];
float topRight = input[yT * inputWidth + xR];
float bottomLeft = input[yB * inputWidth + xL];
float bottomRight = input[yB * inputWidth + xR];
//linear interpolation in X (i.e., top and bottom pairs of points)
if (xL == xR) { //interpolated points corresponds exactly to one integer x-coordinate in the original image, choose any one of them
iT = topLeft;
iB = bottomLeft;
}
else {
iT = topLeft * dL + topRight * dR;
iB = bottomLeft * dL + bottomRight * dR;
}
//linear interpolation in Y (i.e., linear interpolation of those two points)
if (yT == yB) //interpolated points corresponds exactly to one integer ycoordinate in the original image, choose any one of them
{
output[py * outputWidth + px] = iT;
}
else {
output[py * outputWidth + px] = iT * dT + iB * dB;
}
}
} | .text
.file "BilinearResampleKernel.hip"
.globl _Z37__device_stub__BilinearResampleKernelPfS_iiii # -- Begin function _Z37__device_stub__BilinearResampleKernelPfS_iiii
.p2align 4, 0x90
.type _Z37__device_stub__BilinearResampleKernelPfS_iiii,@function
_Z37__device_stub__BilinearResampleKernelPfS_iiii: # @_Z37__device_stub__BilinearResampleKernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22BilinearResampleKernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z37__device_stub__BilinearResampleKernelPfS_iiii, .Lfunc_end0-_Z37__device_stub__BilinearResampleKernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BilinearResampleKernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22BilinearResampleKernelPfS_iiii,@object # @_Z22BilinearResampleKernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z22BilinearResampleKernelPfS_iiii
.p2align 3, 0x0
_Z22BilinearResampleKernelPfS_iiii:
.quad _Z37__device_stub__BilinearResampleKernelPfS_iiii
.size _Z22BilinearResampleKernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22BilinearResampleKernelPfS_iiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__BilinearResampleKernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22BilinearResampleKernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22BilinearResampleKernelPfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R4, R0, c[0x0][0x0], R5 ; /* 0x0000000000047a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R4, UR4, PT ; /* 0x0000000404007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*00b0*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*00c0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00d0*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e220000209400 */
/*00e0*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fce000fffe13f */
/*00f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0140*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0150*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc60000000000 */
/*0160*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*0170*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*0180*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0190*/ UIADD3 UR4, -UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe13f */
/*01a0*/ IMAD.HI.U32 R0, R3, R6, RZ ; /* 0x0000000603007227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R2, -R0, RZ, RZ ; /* 0x000000ff00027210 */
/* 0x000fca0007ffe1ff */
/*01c0*/ IMAD R2, R5.reuse, R2, R6 ; /* 0x0000000205027224 */
/* 0x040fe400078e0206 */
/*01d0*/ I2F R6, UR4 ; /* 0x0000000400067d06 */
/* 0x000fe60008201400 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fca0003f04070 */
/*01f0*/ MUFU.RCP R8, R7 ; /* 0x0000000700087308 */
/* 0x001e300000001000 */
/*0200*/ @!P0 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102028824 */
/* 0x000fe200078e0a05 */
/*0210*/ @!P0 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100008810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fc40003f05270 */
/*0230*/ ISETP.GE.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fe40003f26070 */
/*0240*/ LOP3.LUT R2, R4, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0004027a12 */
/* 0x000fe200078e3cff */
/*0250*/ FFMA R3, -R7, R8, 1 ; /* 0x3f80000007037423 */
/* 0x001fc60000000108 */
/*0260*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f46270 */
/*0270*/ FFMA R3, R8, R3, R8 ; /* 0x0000000308037223 */
/* 0x000fc80000000008 */
/*0280*/ FFMA R2, R6, R3, RZ ; /* 0x0000000306027223 */
/* 0x000fe400000000ff */
/*0290*/ @P1 IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100001810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ FCHK P1, R6, R7 ; /* 0x0000000706007302 */
/* 0x000e220000020000 */
/*02b0*/ FFMA R5, -R7, R2, R6 ; /* 0x0000000207057223 */
/* 0x000fc80000000106 */
/*02c0*/ @!P2 IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff00a224 */
/* 0x000fe200078e0a00 */
/*02d0*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff008a12 */
/* 0x000fe200078e33ff */
/*02e0*/ FFMA R5, R3, R5, R2 ; /* 0x0000000503057223 */
/* 0x000fc60000000002 */
/*02f0*/ IADD3 R9, -R0, RZ, RZ ; /* 0x000000ff00097210 */
/* 0x000fca0007ffe1ff */
/*0300*/ IMAD R3, R9, c[0x0][0x178], R4 ; /* 0x00005e0009037a24 */
/* 0x000fe200078e0204 */
/*0310*/ @!P1 BRA 0x360 ; /* 0x0000004000009947 */
/* 0x001fea0003800000 */
/*0320*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*0330*/ MOV R2, 0x350 ; /* 0x0000035000027802 */
/* 0x000fe40000000f00 */
/*0340*/ CALL.REL.NOINC 0x780 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0350*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0004 */
/*0360*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe40000000800 */
/*0370*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*0380*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fce0000000800 */
/*0390*/ I2F R7, UR4 ; /* 0x0000000400077d06 */
/* 0x000e220008201400 */
/*03a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*03b0*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fd2000fffe13f */
/*03c0*/ I2F R2, UR4 ; /* 0x0000000400027d06 */
/* 0x000e620008201400 */
/*03d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fce0000000a00 */
/*03e0*/ MUFU.RCP R4, R7 ; /* 0x0000000700047308 */
/* 0x001e300000001000 */
/*03f0*/ FCHK P0, R2, R7 ; /* 0x0000000702007302 */
/* 0x002e620000000000 */
/*0400*/ FFMA R9, -R7, R4, 1 ; /* 0x3f80000007097423 */
/* 0x001fc80000000104 */
/*0410*/ FFMA R9, R4, R9, R4 ; /* 0x0000000904097223 */
/* 0x000fc80000000004 */
/*0420*/ FFMA R4, R2, R9, RZ ; /* 0x0000000902047223 */
/* 0x000fc800000000ff */
/*0430*/ FFMA R6, -R7, R4, R2 ; /* 0x0000000407067223 */
/* 0x000fc80000000102 */
/*0440*/ FFMA R4, R9, R6, R4 ; /* 0x0000000609047223 */
/* 0x000fe20000000004 */
/*0450*/ @!P0 BRA 0x490 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0460*/ MOV R8, R2 ; /* 0x0000000200087202 */
/* 0x000fe40000000f00 */
/*0470*/ MOV R2, 0x490 ; /* 0x0000049000027802 */
/* 0x000fe40000000f00 */
/*0480*/ CALL.REL.NOINC 0x780 ; /* 0x000002f000007944 */
/* 0x000fea0003c00000 */
/*0490*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x000e700000201400 */
/*04a0*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x000ea20000201400 */
/*04b0*/ FMUL R5, R2, R5 ; /* 0x0000000502057220 */
/* 0x002fc40000400000 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fca00078e00ff */
/*04d0*/ F2I.FLOOR.NTZ R16, R5 ; /* 0x0000000500107305 */
/* 0x000fe20000207100 */
/*04e0*/ FMUL R4, R7, R4 ; /* 0x0000000407047220 */
/* 0x005fce0000400000 */
/*04f0*/ F2I.CEIL.NTZ R21, R5 ; /* 0x0000000500157305 */
/* 0x000e30000020b100 */
/*0500*/ F2I.CEIL.NTZ R6, R4 ; /* 0x0000000400067305 */
/* 0x000e62000020b100 */
/*0510*/ ISETP.NE.AND P0, PT, R16, R21, PT ; /* 0x000000151000720c */
/* 0x001fce0003f05270 */
/*0520*/ F2I.FLOOR.NTZ R7, R4 ; /* 0x0000000400077305 */
/* 0x000e220000207100 */
/*0530*/ IMAD R9, R6, c[0x0][0x170], R16 ; /* 0x00005c0006097a24 */
/* 0x002fc800078e0210 */
/*0540*/ IMAD.WIDE R8, R9, R2, c[0x0][0x160] ; /* 0x0000580009087625 */
/* 0x000fc800078e0202 */
/*0550*/ @P0 IMAD R15, R6, c[0x0][0x170], R21.reuse ; /* 0x00005c00060f0a24 */
/* 0x100fe400078e0215 */
/*0560*/ @P0 IMAD R11, R7, c[0x0][0x170], R21 ; /* 0x00005c00070b0a24 */
/* 0x001fe200078e0215 */
/*0570*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a2000c1e1900 */
/*0580*/ @P0 IMAD.WIDE R14, R15, R2, c[0x0][0x160] ; /* 0x000058000f0e0625 */
/* 0x000fc800078e0202 */
/*0590*/ IMAD R13, R7, c[0x0][0x170], R16 ; /* 0x00005c00070d7a24 */
/* 0x000fe400078e0210 */
/*05a0*/ @P0 IMAD.WIDE R10, R11, R2.reuse, c[0x0][0x160] ; /* 0x000058000b0a0625 */
/* 0x080fe200078e0202 */
/*05b0*/ @P0 LDG.E R14, [R14.64] ; /* 0x000000040e0e0981 */
/* 0x0002e6000c1e1900 */
/*05c0*/ IMAD.WIDE R12, R13, R2, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fe400078e0202 */
/*05d0*/ @P0 LDG.E R10, [R10.64] ; /* 0x000000040a0a0981 */
/* 0x000f28000c1e1900 */
/*05e0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*05f0*/ I2F R18, R21 ; /* 0x0000001500127306 */
/* 0x000e300000201400 */
/*0600*/ I2F R16, R16 ; /* 0x0000001000107306 */
/* 0x000e700000201400 */
/*0610*/ I2F R19, R6 ; /* 0x0000000600137306 */
/* 0x000e620000201400 */
/*0620*/ FADD R18, R5, -R18 ; /* 0x8000001205127221 */
/* 0x001fce0000000000 */
/*0630*/ I2F R17, R7 ; /* 0x0000000700117306 */
/* 0x000e220000201400 */
/*0640*/ FADD R5, -R5, R16 ; /* 0x0000001005057221 */
/* 0x002fe20000000100 */
/*0650*/ ISETP.NE.AND P1, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fe20003f25270 */
/*0660*/ FADD R15, R18, 1 ; /* 0x3f800000120f7421 */
/* 0x000fe40000000000 */
/*0670*/ FADD R9, R5, 1 ; /* 0x3f80000005097421 */
/* 0x000fe40000000000 */
/*0680*/ FADD R19, R4, -R19 ; /* 0x8000001304137221 */
/* 0x000fc80000000000 */
/*0690*/ FADD R19, R19, 1 ; /* 0x3f80000013137421 */
/* 0x000fe40000000000 */
/*06a0*/ FADD R17, -R4, R17 ; /* 0x0000001104117221 */
/* 0x001fe40000000100 */
/*06b0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fe400078e0203 */
/*06c0*/ FADD R17, R17, 1 ; /* 0x3f80000011117421 */
/* 0x000fe40000000000 */
/*06d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc800078e0202 */
/*06e0*/ @P0 FMUL R5, R15, R14 ; /* 0x0000000e0f050220 */
/* 0x008fc80000400000 */
/*06f0*/ @P0 FFMA R8, R9, R8, R5 ; /* 0x0000000809080223 */
/* 0x004fe40000000005 */
/*0700*/ @P0 FMUL R5, R15, R10 ; /* 0x0000000a0f050220 */
/* 0x010fe40000400000 */
/*0710*/ @P1 FMUL R7, R19, R8 ; /* 0x0000000813071220 */
/* 0x000fe40000400000 */
/*0720*/ @P0 FFMA R12, R9, R12, R5 ; /* 0x0000000c090c0223 */
/* 0x020fc80000000005 */
/*0730*/ @P1 FFMA R7, R17, R12, R7 ; /* 0x0000000c11071223 */
/* 0x000fca0000000007 */
/*0740*/ @P1 STG.E [R2.64], R7 ; /* 0x0000000702001986 */
/* 0x0001e2000c101904 */
/*0750*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0760*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ SHF.R.U32.HI R6, RZ, 0x17, R7 ; /* 0x00000017ff067819 */
/* 0x000fe40000011607 */
/*0790*/ SHF.R.U32.HI R4, RZ, 0x17, R8.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011608 */
/*07a0*/ LOP3.LUT R12, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff060c7812 */
/* 0x000fe400078ec0ff */
/*07b0*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*07c0*/ IMAD.MOV.U32 R4, RZ, RZ, R8 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0008 */
/*07d0*/ IADD3 R11, R12, -0x1, RZ ; /* 0xffffffff0c0b7810 */
/* 0x000fc40007ffe0ff */
/*07e0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0800*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*0810*/ @!P0 MOV R6, RZ ; /* 0x000000ff00068202 */
/* 0x000fe20000000f00 */
/*0820*/ @!P0 BRA 0x9a0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0830*/ FSETP.GTU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fe40003f1c200 */
/*0840*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0850*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0860*/ @P0 BRA 0xd80 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0870*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c804 */
/*0880*/ @!P0 BRA 0xd60 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0890*/ FSETP.NEU.FTZ.AND P2, PT, |R8|.reuse, +INF , PT ; /* 0x7f8000000800780b */
/* 0x040fe40003f5d200 */
/*08a0*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*08b0*/ FSETP.NEU.FTZ.AND P0, PT, |R8|, +INF , PT ; /* 0x7f8000000800780b */
/* 0x000fd60003f1d200 */
/*08c0*/ @!P1 BRA !P2, 0xd60 ; /* 0x0000049000009947 */
/* 0x000fea0005000000 */
/*08d0*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*08e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*08f0*/ @P1 BRA 0xd40 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*0910*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0920*/ @P0 BRA 0xd10 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0940*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0950*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0960*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0970*/ @!P0 FFMA R4, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008048823 */
/* 0x000fe400000000ff */
/*0980*/ @!P1 FFMA R7, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007079823 */
/* 0x000fe200000000ff */
/*0990*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*09a0*/ LEA R8, R12, 0xc0800000, 0x17 ; /* 0xc08000000c087811 */
/* 0x000fc800078eb8ff */
/*09b0*/ IADD3 R8, -R8, R7, RZ ; /* 0x0000000708087210 */
/* 0x000fe40007ffe1ff */
/*09c0*/ IADD3 R7, R10, -0x7f, RZ ; /* 0xffffff810a077810 */
/* 0x000fe40007ffe0ff */
/*09d0*/ MUFU.RCP R9, R8 ; /* 0x0000000800097308 */
/* 0x000e220000001000 */
/*09e0*/ FADD.FTZ R11, -R8, -RZ ; /* 0x800000ff080b7221 */
/* 0x000fe40000010100 */
/*09f0*/ IMAD R4, R7, -0x800000, R4 ; /* 0xff80000007047824 */
/* 0x000fe400078e0204 */
/*0a00*/ FFMA R10, R9, R11, 1 ; /* 0x3f800000090a7423 */
/* 0x001fc8000000000b */
/*0a10*/ FFMA R13, R9, R10, R9 ; /* 0x0000000a090d7223 */
/* 0x000fc80000000009 */
/*0a20*/ FFMA R9, R4, R13, RZ ; /* 0x0000000d04097223 */
/* 0x000fc800000000ff */
/*0a30*/ FFMA R10, R11, R9, R4 ; /* 0x000000090b0a7223 */
/* 0x000fc80000000004 */
/*0a40*/ FFMA R10, R13, R10, R9 ; /* 0x0000000a0d0a7223 */
/* 0x000fe20000000009 */
/*0a50*/ IADD3 R9, R7, 0x7f, -R12 ; /* 0x0000007f07097810 */
/* 0x000fc60007ffe80c */
/*0a60*/ FFMA R11, R11, R10, R4 ; /* 0x0000000a0b0b7223 */
/* 0x000fe40000000004 */
/*0a70*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x000fe400078e0206 */
/*0a80*/ FFMA R4, R13, R11, R10 ; /* 0x0000000b0d047223 */
/* 0x000fca000000000a */
/*0a90*/ SHF.R.U32.HI R7, RZ, 0x17, R4 ; /* 0x00000017ff077819 */
/* 0x000fc80000011604 */
/*0aa0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R12, R7, 0x1, R9 ; /* 0x00000001070c7824 */
/* 0x000fca00078e0209 */
/*0ac0*/ IADD3 R6, R12, -0x1, RZ ; /* 0xffffffff0c067810 */
/* 0x000fc80007ffe0ff */
/*0ad0*/ ISETP.GE.U32.AND P0, PT, R6, 0xfe, PT ; /* 0x000000fe0600780c */
/* 0x000fda0003f06070 */
/*0ae0*/ @!P0 BRA 0xcf0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0b00*/ @P0 BRA 0xcc0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0b10*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0b20*/ @P0 BRA 0xd90 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0b30*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0b40*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0b50*/ @!P0 BRA 0xd90 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0b60*/ FFMA.RZ R6, R13.reuse, R11.reuse, R10.reuse ; /* 0x0000000b0d067223 */
/* 0x1c0fe2000000c00a */
/*0b70*/ IADD3 R9, R12.reuse, 0x20, RZ ; /* 0x000000200c097810 */
/* 0x040fe20007ffe0ff */
/*0b80*/ FFMA.RM R7, R13.reuse, R11.reuse, R10.reuse ; /* 0x0000000b0d077223 */
/* 0x1c0fe2000000400a */
/*0b90*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f45270 */
/*0ba0*/ LOP3.LUT R8, R6, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06087812 */
/* 0x000fe200078ec0ff */
/*0bb0*/ FFMA.RP R6, R13, R11, R10 ; /* 0x0000000b0d067223 */
/* 0x000fe2000000800a */
/*0bc0*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*0bd0*/ LOP3.LUT R8, R8, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000008087812 */
/* 0x000fe400078efcff */
/*0be0*/ IADD3 R10, -R12, RZ, RZ ; /* 0x000000ff0c0a7210 */
/* 0x000fc40007ffe1ff */
/*0bf0*/ SHF.L.U32 R9, R8, R9, RZ ; /* 0x0000000908097219 */
/* 0x000fe400000006ff */
/*0c00*/ FSETP.NEU.FTZ.AND P0, PT, R6, R7, PT ; /* 0x000000070600720b */
/* 0x000fe40003f1d000 */
/*0c10*/ SEL R7, R10, RZ, P2 ; /* 0x000000ff0a077207 */
/* 0x000fe40001000000 */
/*0c20*/ ISETP.NE.AND P1, PT, R9, RZ, P1 ; /* 0x000000ff0900720c */
/* 0x000fe40000f25270 */
/*0c30*/ SHF.R.U32.HI R7, RZ, R7, R8 ; /* 0x00000007ff077219 */
/* 0x000fe40000011608 */
/*0c40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*0c50*/ SHF.R.U32.HI R9, RZ, 0x1, R7 ; /* 0x00000001ff097819 */
/* 0x000fe40000011607 */
/*0c60*/ SEL R6, RZ, 0x1, !P0 ; /* 0x00000001ff067807 */
/* 0x000fc80004000000 */
/*0c70*/ LOP3.LUT R6, R6, 0x1, R9, 0xf8, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ef809 */
/*0c80*/ LOP3.LUT R6, R6, R7, RZ, 0xc0, !PT ; /* 0x0000000706067212 */
/* 0x000fca00078ec0ff */
/*0c90*/ IMAD.IADD R9, R9, 0x1, R6 ; /* 0x0000000109097824 */
/* 0x000fca00078e0206 */
/*0ca0*/ LOP3.LUT R4, R9, R4, RZ, 0xfc, !PT ; /* 0x0000000409047212 */
/* 0x000fe200078efcff */
/*0cb0*/ BRA 0xd90 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*0cd0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0ce0*/ BRA 0xd90 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ IMAD R4, R9, 0x800000, R4 ; /* 0x0080000009047824 */
/* 0x000fe200078e0204 */
/*0d00*/ BRA 0xd90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0d10*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fc800078e4804 */
/*0d20*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0d30*/ BRA 0xd90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0d40*/ LOP3.LUT R4, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007047812 */
/* 0x000fe200078e4804 */
/*0d50*/ BRA 0xd90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0d60*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0d70*/ BRA 0xd90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0d80*/ FADD.FTZ R4, R8, R7 ; /* 0x0000000708047221 */
/* 0x000fe40000010000 */
/*0d90*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0da0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0db0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff24006007950 */
/* 0x000fea0003c3ffff */
/*0dc0*/ BRA 0xdc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22BilinearResampleKernelPfS_iiii
.globl _Z22BilinearResampleKernelPfS_iiii
.p2align 8
.type _Z22BilinearResampleKernelPfS_iiii,@function
_Z22BilinearResampleKernelPfS_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_ashr_i32 s8, s4, 31
s_load_b64 s[6:7], s[0:1], 0x10
s_add_i32 s2, s4, s8
v_ashrrev_i32_e32 v3, 31, v1
s_xor_b32 s9, s2, s8
s_add_i32 s3, s5, -1
v_cvt_f32_u32_e32 v0, s9
v_cvt_f32_i32_e32 v6, s3
s_sub_i32 s2, 0, s9
s_mov_b32 s5, exec_lo
v_add_nc_u32_e32 v5, v1, v3
v_rcp_iflag_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v3
v_xor_b32_e32 v3, s8, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, s3
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, v6, v6, v8
v_mul_lo_u32 v2, s2, v0
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_rcp_f32_e32 v11, v9
v_cvt_f32_i32_e32 v4, s2
s_add_i32 s2, s6, -1
v_cvt_f32_i32_e32 v7, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v2, v0, v2
v_div_scale_f32 v13, vcc_lo, v7, v4, v7
s_waitcnt_depctr 0xfff
v_fma_f32 v15, -v9, v11, 1.0
v_add_nc_u32_e32 v0, v0, v2
v_div_scale_f32 v2, null, v4, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v15, v11
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v2
v_mul_lo_u32 v12, v0, s9
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v2, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v10, v14, v10
v_sub_nc_u32_e32 v5, v5, v12
v_add_nc_u32_e32 v16, 1, v0
v_div_scale_f32 v12, s2, v8, v6, v8
v_mul_f32_e32 v15, v13, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v14, s9, v5
v_cmp_le_u32_e64 s3, s9, v5
v_fma_f32 v17, -v2, v15, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, v0, v16, s3
v_cndmask_b32_e64 v5, v5, v14, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_mul_f32 v16, v12, v11 :: v_dual_fmac_f32 v15, v17, v10
v_add_nc_u32_e32 v14, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e64 s3, s9, v5
v_fma_f32 v18, -v9, v16, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v5, -v2, v15, v13
v_cndmask_b32_e64 v0, v0, v14, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v16, v18, v11
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v9, v16, v12
v_sub_nc_u32_e32 v2, v0, v3
v_div_fmas_f32 v3, v5, v10, v15
s_mov_b32 vcc_lo, s2
s_load_b64 s[2:3], s[0:1], 0x0
v_div_fmas_f32 v0, v9, v11, v16
v_mul_lo_u32 v5, v2, s4
v_div_fixup_f32 v3, v3, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_div_fixup_f32 v6, v0, v6, v8
v_cvt_f32_i32_e32 v8, v2
v_sub_nc_u32_e32 v0, v1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, v6, v8
v_cvt_f32_i32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v5, v1
v_mul_f32_e32 v7, v3, v4
v_ceil_f32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v3, v5
v_floor_f32_e32 v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v4
v_mul_lo_u32 v9, v3, s6
v_ceil_f32_e32 v10, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v8, v5
v_mul_lo_u32 v11, v4, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v10, v10
v_add_nc_u32_e32 v5, v9, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v11, v8
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v12, vcc_lo, s2, v12
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[12:13], off
v_cmpx_ne_u32_e64 v8, v10
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v11, v11, v10
v_add_nc_u32_e32 v13, v9, v10
v_cvt_f32_i32_e32 v10, v10
v_cvt_f32_i32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v10, v7, v10 :: v_dual_sub_f32 v7, v8, v7
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_dual_add_f32 v8, 1.0, v10 :: v_dual_add_f32 v7, 1.0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v9, v[11:12], off
global_load_b32 v11, v[13:14], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v9, v8, v9
s_waitcnt vmcnt(0)
v_mul_f32_e32 v8, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v6, v7
v_fmac_f32_e32 v8, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v5, v8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
v_cvt_f32_i32_e32 v7, v3
v_cvt_f32_i32_e32 v9, v4
s_load_b64 s[0:1], s[0:1], 0x8
v_cmp_eq_u32_e32 vcc_lo, v3, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v7, v1
v_mad_u64_u32 v[7:8], null, v2, s4, v[0:1]
v_dual_sub_f32 v0, v1, v9 :: v_dual_add_f32 v1, 1.0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, 1.0, v0
v_ashrrev_i32_e32 v8, 31, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v1, v5
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v0, v6
v_lshlrev_b64 v[0:1], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22BilinearResampleKernelPfS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22BilinearResampleKernelPfS_iiii, .Lfunc_end0-_Z22BilinearResampleKernelPfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22BilinearResampleKernelPfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22BilinearResampleKernelPfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d3e34_00000000-6_BilinearResampleKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
.type _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii, @function
_Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22BilinearResampleKernelPfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii, .-_Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
.globl _Z22BilinearResampleKernelPfS_iiii
.type _Z22BilinearResampleKernelPfS_iiii, @function
_Z22BilinearResampleKernelPfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22BilinearResampleKernelPfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22BilinearResampleKernelPfS_iiii, .-_Z22BilinearResampleKernelPfS_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22BilinearResampleKernelPfS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22BilinearResampleKernelPfS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BilinearResampleKernel.hip"
.globl _Z37__device_stub__BilinearResampleKernelPfS_iiii # -- Begin function _Z37__device_stub__BilinearResampleKernelPfS_iiii
.p2align 4, 0x90
.type _Z37__device_stub__BilinearResampleKernelPfS_iiii,@function
_Z37__device_stub__BilinearResampleKernelPfS_iiii: # @_Z37__device_stub__BilinearResampleKernelPfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22BilinearResampleKernelPfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z37__device_stub__BilinearResampleKernelPfS_iiii, .Lfunc_end0-_Z37__device_stub__BilinearResampleKernelPfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22BilinearResampleKernelPfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22BilinearResampleKernelPfS_iiii,@object # @_Z22BilinearResampleKernelPfS_iiii
.section .rodata,"a",@progbits
.globl _Z22BilinearResampleKernelPfS_iiii
.p2align 3, 0x0
_Z22BilinearResampleKernelPfS_iiii:
.quad _Z37__device_stub__BilinearResampleKernelPfS_iiii
.size _Z22BilinearResampleKernelPfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22BilinearResampleKernelPfS_iiii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__BilinearResampleKernelPfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22BilinearResampleKernelPfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMalloc((void**)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result :%d \n",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMalloc((void**)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result :%d \n",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000dee9c_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result :%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $3, (%rsp)
movl $5, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMalloc((void**)&d_c,size);
a = 3;
b = 5;
cudaMemcpy(d_a,&a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,&b,size,cudaMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
cudaMemcpy(&c,d_c,size,cudaMemcpyDeviceToHost);
printf("Result :%d \n",c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result :%d \n",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result :%d \n",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
__global__ void add(int* a , int *b,int *c)
{
*c = *a + *b;
}
int main(void)
{
int a , b ,c;
int *d_a , *d_b ,*d_c;
int size = sizeof(int);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_c,size);
a = 3;
b = 5;
hipMemcpy(d_a,&a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,&b,size,hipMemcpyHostToDevice);
add<<<1,1>>>(d_a,d_b,d_c);
hipMemcpy(&c,d_c,size,hipMemcpyDeviceToHost);
printf("Result :%d \n",c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "sample.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $3, 28(%rsp)
movl $5, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result :%d \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dee9c_00000000-6_sample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result :%d \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $3, (%rsp)
movl $5, 4(%rsp)
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl 44(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movl $3, 28(%rsp)
movl $5, 24(%rsp)
movq 16(%rsp), %rdi
leaq 28(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 40(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 32(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Result :%d \n"
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size_a);
cudaMemcpy(d_A.elements, A.elements, size_a, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size_b);
cudaMemcpy(d_B.elements, B.elements, size_b, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size_c, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x160], R2 ; /* 0x0000580003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R0 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size_a);
cudaMemcpy(d_A.elements, A.elements, size_a, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size_b);
cudaMemcpy(d_B.elements, B.elements, size_b, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size_c, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} | .file "tmpxft_001257fa_00000000-6_matrixmultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, 16(%rsp)
movq %r8, %r15
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r13
sarq $32, %r13
movq %r8, %r12
sarq $32, %r12
movl %edi, 64(%rsp)
movl %r14d, 68(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 80(%rsp)
movl %r13d, 84(%rsp)
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
addl $15, %ebp
shrl $4, %ebp
movl %ebp, 52(%rsp)
addl $15, %r14d
shrl $4, %r14d
movl %r14d, 56(%rsp)
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %r12, %rdx
movq 104(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 64(%rsp), %xmm0
movaps %xmm0, 112(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
leaq 144(%rsp), %rdx
leaq 128(%rsp), %rsi
leaq 112(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\t"
.LC1:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "=========================================\n"
.section .rodata.str1.1
.LC3:
.string "%5f\t"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $60, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $15, %rax
jne .L18
movl $60, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $15, %rax
jne .L19
movl $0, %ebx
leaq .LC0(%rip), %rbp
leaq .LC1(%rip), %r14
jmp .L21
.L20:
addq $1, %rbx
cmpq $15, %rbx
je .L34
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $2, %eax
jne .L20
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L34:
movl $0, %ebx
leaq .LC0(%rip), %rbp
leaq .LC1(%rip), %r14
jmp .L23
.L22:
addq $1, %rbx
cmpq $15, %rbx
je .L35
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L22
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L24
movabsq $21474836480, %r8
movq %r8, %rdi
orq $3, %rdi
orq $5, %r8
movq %rbp, %r9
movabsq $12884901893, %rdx
movq %r13, %rcx
movq %r12, %rsi
call _Z6MatMul6MatrixS_S_
movl $0, %ebx
leaq .LC3(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L26
.L25:
addq $1, %rbx
cmpq $25, %rbx
je .L36
.L26:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L36:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
cudaMalloc((void **)&d_A.elements, size_a);
cudaMemcpy(d_A.elements, A.elements, size_a, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
cudaMalloc((void **)&d_B.elements, size_b);
cudaMemcpy(d_B.elements, B.elements, size_b, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
cudaMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size_c, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
hipMalloc((void **)&d_A.elements, size_a);
hipMemcpy(d_A.elements, A.elements, size_a, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
hipMalloc((void **)&d_B.elements, size_b);
hipMemcpy(d_B.elements, B.elements, size_b, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
hipMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size_c, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
hipMalloc((void **)&d_A.elements, size_a);
hipMemcpy(d_A.elements, A.elements, size_a, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
hipMalloc((void **)&d_B.elements, size_b);
hipMemcpy(d_B.elements, B.elements, size_b, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
hipMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size_c, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b64 s[4:5], s[4:5], 0x8
v_mul_lo_u32 v2, v0, s7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 16
typedef struct {
int width;
int height;
float* elements;
} Matrix;
__global__
void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < A.height && col < B.width){
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
}
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size_a = A.width * A.height * sizeof(float);
hipMalloc((void **)&d_A.elements, size_a);
hipMemcpy(d_A.elements, A.elements, size_a, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size_t size_b = B.width * B.height * sizeof(float);
hipMalloc((void **)&d_B.elements, size_b);
hipMemcpy(d_B.elements, B.elements, size_b, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size_t size_c = C.width * C.height * sizeof(float);
hipMalloc((void **)&d_C.elements, size_c);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid((B.width + dimBlock.x - 1) / dimBlock.x, (A.height + dimBlock.y - 1)/ dimBlock.y);
// dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
//cudaDeviceSynchronize();
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size_c, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
int main(int argc, char **argv){
//Initialize matrixs
Matrix A;
A.width = 3;
A.height = 5;
A.elements = (float*) malloc(A.width*A.height*sizeof(float));
for(int i = 0 ; i < A.width*A.height ; i++ ){
A.elements[i] = float(i);
}
Matrix B;
B.width = 5;
B.height = 3;
B.elements = (float*) malloc(B.width*B.height*sizeof(float));
for(int i = 0 ; i < B.width*B.height ; i++ ){
B.elements[i] = float(i);
}
for(int i = 0 ; i < A.width*A.height ; i++ ){
printf("%f\t", A.elements[i]);
if((i % A.width ) == A.width - 1){printf("\n");}
}
for(int i = 0 ; i < B.width*B.height ; i++ ){
printf("%f\t", B.elements[i]);
if((i % B.width ) == B.width - 1){printf("\n");}
}
printf("=========================================\n");
Matrix C;
C.width = 5;
C.height = 5;
C.elements = (float*) malloc(C.width*C.height*sizeof(float));
for(int i = 0 ; i < C.width*C.height ; i++ ){
C.elements[i] = float(i);
}
MatMul(A, B, C);
for(int i = 0 ; i < C.width*C.height ; i++ ){
printf("%5f\t", C.elements[i]);
if((i % C.width ) == C.width - 1){printf("\n");}
}
return 0;
} | .text
.file "matrixmultiply.hip"
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 72(%rsp) # 8-byte Spill
movq %r8, %r14
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdx, %r15
shrq $32, %r15
shrq $32, %r14
movq %rdi, 40(%rsp)
movq %rdi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %edi, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 24(%rsp)
imull %r12d, %r15d
movslq %r15d, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, 8(%rsp)
imull %eax, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
shrl $4, %eax
shlq $28, %rbx
orq %rax, %rbx
movl $4026531840, %eax # imm = 0xF0000000
addq %rbx, %rax
movabsq $1152921500580315135, %rdi # imm = 0xFFFFFFF0FFFFFFF
andq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 40(%rsp), %xmm0
movups 24(%rsp), %xmm1
movups 8(%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end1-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $60, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $15, %rax
jne .LBB2_1
# %bb.2:
movl $60, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $15, %rax
jne .LBB2_3
# %bb.4: # %.preheader88.preheader
xorl %r15d, %r15d
movabsq $-6148914691236517205, %r12 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r15
cmpq $15, %r15
je .LBB2_8
.LBB2_5: # %.preheader88
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r12
shrq %rdx
leal (%rdx,%rdx,2), %ebp
addl $2, %ebp
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %r15d, %ebp
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8: # %.preheader.preheader
xorl %r15d, %r15d
movabsq $-3689348814741910323, %r12 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
incq %r15
cmpq $15, %r15
je .LBB2_12
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r12
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %r15d, %ebp
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $.Lstr, %edi
callq puts@PLT
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB2_13
# %bb.14:
movabsq $21474836483, %rdi # imm = 0x500000003
leaq 2(%rdi), %r8
movabsq $12884901893, %rdx # imm = 0x300000005
movq %rbx, %rsi
movq %r14, %rcx
movq %r15, %r9
callq _Z6MatMul6MatrixS_S_
xorl %ebx, %ebx
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=1
incq %rbx
cmpq $25, %rbx
je .LBB2_18
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r12
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB2_17
# %bb.16: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_17
.LBB2_18:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\t"
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%5f\t"
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "========================================="
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x164], P0 ; /* 0x0000590003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R3, c[0x0][0x160], RZ ; /* 0x0000580003067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fcc00078e0209 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R3, c[0x0][0x160], R2 ; /* 0x0000580003067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R0 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0200 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R3, c[0x0][0x180], R0 ; /* 0x0000600003037a24 */
/* 0x000fc800078e0200 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x4
s_load_b32 s6, s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s7, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v0
v_cmp_gt_i32_e64 s2, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s7, s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s7, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b64 s[4:5], s[4:5], 0x8
v_mul_lo_u32 v2, v0, s7
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s7, s7, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s7, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b32 s0, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001257fa_00000000-6_matrixmultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, 16(%rsp)
movq %r8, %r15
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r13
sarq $32, %r13
movq %r8, %r12
sarq $32, %r12
movl %edi, 64(%rsp)
movl %r14d, 68(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 80(%rsp)
movl %r13d, 84(%rsp)
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
addl $15, %ebp
shrl $4, %ebp
movl %ebp, 52(%rsp)
addl $15, %r14d
shrl $4, %r14d
movl %r14d, 56(%rsp)
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %r12, %rdx
movq 104(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movdqa 64(%rsp), %xmm0
movaps %xmm0, 112(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
leaq 144(%rsp), %rdx
leaq 128(%rsp), %rsi
leaq 112(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f\t"
.LC1:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "=========================================\n"
.section .rodata.str1.1
.LC3:
.string "%5f\t"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $60, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $15, %rax
jne .L18
movl $60, %edi
call malloc@PLT
movq %rax, %r13
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13,%rax,4)
addq $1, %rax
cmpq $15, %rax
jne .L19
movl $0, %ebx
leaq .LC0(%rip), %rbp
leaq .LC1(%rip), %r14
jmp .L21
.L20:
addq $1, %rbx
cmpq $15, %rbx
je .L34
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $2, %eax
jne .L20
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L34:
movl $0, %ebx
leaq .LC0(%rip), %rbp
leaq .LC1(%rip), %r14
jmp .L23
.L22:
addq $1, %rbx
cmpq $15, %rbx
je .L35
.L23:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L22
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L35:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L24:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L24
movabsq $21474836480, %r8
movq %r8, %rdi
orq $3, %rdi
orq $5, %r8
movq %rbp, %r9
movabsq $12884901893, %rdx
movq %r13, %rcx
movq %r12, %rsi
call _Z6MatMul6MatrixS_S_
movl $0, %ebx
leaq .LC3(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L26
.L25:
addq $1, %rbx
cmpq $25, %rbx
je .L36
.L26:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L25
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.L36:
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixmultiply.hip"
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 72(%rsp) # 8-byte Spill
movq %r8, %r14
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdx, %r15
shrq $32, %r15
shrq $32, %r14
movq %rdi, 40(%rsp)
movq %rdi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %edi, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 24(%rsp)
imull %r12d, %r15d
movslq %r15d, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, 8(%rsp)
imull %eax, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
shrl $4, %eax
shlq $28, %rbx
orq %rax, %rbx
movl $4026531840, %eax # imm = 0xF0000000
addq %rbx, %rax
movabsq $1152921500580315135, %rdi # imm = 0xFFFFFFF0FFFFFFF
andq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 40(%rsp), %xmm0
movups 24(%rsp), %xmm1
movups 8(%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end1-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $60, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $15, %rax
jne .LBB2_1
# %bb.2:
movl $60, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $15, %rax
jne .LBB2_3
# %bb.4: # %.preheader88.preheader
xorl %r15d, %r15d
movabsq $-6148914691236517205, %r12 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r15
cmpq $15, %r15
je .LBB2_8
.LBB2_5: # %.preheader88
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r12
shrq %rdx
leal (%rdx,%rdx,2), %ebp
addl $2, %ebp
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %r15d, %ebp
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8: # %.preheader.preheader
xorl %r15d, %r15d
movabsq $-3689348814741910323, %r12 # imm = 0xCCCCCCCCCCCCCCCD
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
incq %r15
cmpq $15, %r15
je .LBB2_12
.LBB2_9: # %.preheader
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r12
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %r15d, %ebp
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $.Lstr, %edi
callq puts@PLT
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB2_13
# %bb.14:
movabsq $21474836483, %rdi # imm = 0x500000003
leaq 2(%rdi), %r8
movabsq $12884901893, %rdx # imm = 0x300000005
movq %rbx, %rsi
movq %r14, %rcx
movq %r15, %r9
callq _Z6MatMul6MatrixS_S_
xorl %ebx, %ebx
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=1
incq %rbx
cmpq $25, %rbx
je .LBB2_18
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq %rbx, %rax
mulq %r12
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB2_17
# %bb.16: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_17
.LBB2_18:
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\t"
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%5f\t"
.size .L.str.3, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "========================================="
.size .Lstr, 42
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * M*N,
cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(
cudaMemcpy(B_d, B_h, sizeof(int) * N*K,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
cudaMemcpy(C_h, C_d, sizeof(int) * M*K,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) B_d));
CUDA_CHECK_RETURN(cudaFree((void* ) C_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} | code for sm_80
Function : _Z15MatrixMulKerneliiiiiiPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R6, R0, 0x2, R3 ; /* 0x0000000200067824 */
/* 0x001fc400078e0203 */
/*00a0*/ IMAD R7, R2, 0x2, R5 ; /* 0x0000000202077824 */
/* 0x002fc800078e0205 */
/*00b0*/ @!P0 BRA 0xb10 ; /* 0x00000a5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fc6000001ff00 */
/*00e0*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fc800078f08ff */
/*00f0*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0100*/ IMNMX R11, R4, 0x1, !PT ; /* 0x00000001040b7817 */
/* 0x000fc80007800200 */
/*0110*/ IADD3 R4, R11.reuse, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R8, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b087812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0140*/ SHF.L.U32 R4, R3, 0x3, RZ ; /* 0x0000000303047819 */
/* 0x000fe400000006ff */
/*0150*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f25270 */
/*0160*/ IMAD R9, R5, 0x4, R4 ; /* 0x0000000405097824 */
/* 0x000fcc00078e0204 */
/*0170*/ @!P0 BRA 0x8c0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R14, R3.reuse, 0x6, RZ ; /* 0x00000006030e7810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD R12, R6, c[0x0][0x164], R5.reuse ; /* 0x00005900060c7a24 */
/* 0x100fe200078e0205 */
/*01a0*/ IADD3 R16, R3.reuse, 0x4, RZ ; /* 0x0000000403107810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD R17, R3.reuse, c[0x0][0x16c], R5.reuse ; /* 0x00005b0003117a24 */
/* 0x140fe200078e0205 */
/*01c0*/ IADD3 R18, R3, 0x2, RZ ; /* 0x0000000203127810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R21, R14, c[0x0][0x16c], R5.reuse ; /* 0x00005b000e157a24 */
/* 0x100fe200078e0205 */
/*01e0*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fe20003f46270 */
/*01f0*/ IMAD R15, R16, c[0x0][0x16c], R5.reuse ; /* 0x00005b00100f7a24 */
/* 0x100fe200078e0205 */
/*0200*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R23, R18, c[0x0][0x16c], R5 ; /* 0x00005b0012177a24 */
/* 0x000fe200078e0205 */
/*0220*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0230*/ IMAD R10, R6, R13, 0x2 ; /* 0x00000002060a7424 */
/* 0x000fe200078e020d */
/*0240*/ IADD3 R12, R12, 0x6, RZ ; /* 0x000000060c0c7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0260*/ LEA R21, R2, R21, 0x1 ; /* 0x0000001502157211 */
/* 0x000fe200078e08ff */
/*0270*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fc400078e0005 */
/*0280*/ IMAD R20, R2.reuse, 0x2, R17 ; /* 0x0000000202147824 */
/* 0x040fe400078e0211 */
/*0290*/ IMAD R22, R2.reuse, 0x2, R15 ; /* 0x0000000202167824 */
/* 0x040fe400078e020f */
/*02a0*/ IMAD R23, R2, 0x2, R23 ; /* 0x0000000202177824 */
/* 0x000fe400078e0217 */
/*02b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*02d0*/ ISETP.GE.U32.OR P3, PT, R13, c[0x0][0x164], P2 ; /* 0x000059000d007a0c */
/* 0x000fe40001766470 */
/*02e0*/ ISETP.GE.U32.OR P4, PT, R4, c[0x0][0x168], P0 ; /* 0x00005a0004007a0c */
/* 0x000fd60000786470 */
/*02f0*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe20000000f00 */
/*0300*/ @!P3 IMAD R16, R6, c[0x0][0x164], R13 ; /* 0x000059000610ba24 */
/* 0x000fe400078e020d */
/*0310*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fc424 */
/* 0x000fe400078e00ff */
/*0320*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x178] ; /* 0x00005e001010b625 */
/* 0x000fc800078e0011 */
/*0330*/ @!P4 IMAD.WIDE.U32 R14, R20, R15, c[0x0][0x180] ; /* 0x00006000140ec625 */
/* 0x000fe200078e000f */
/*0340*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0000a8000c1e1900 */
/*0350*/ @!P4 LDG.E R29, [R14.64] ; /* 0x000000040e1dc981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R18, R13, 0x2, RZ ; /* 0x000000020d127810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GE.U32.OR P3, PT, R18, c[0x0][0x164], P2 ; /* 0x0000590012007a0c */
/* 0x000fe20001766470 */
/*0380*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x001fd800078e00ff */
/*0390*/ @!P3 MOV R19, 0x4 ; /* 0x000000040013b802 */
/* 0x000fe20000000f00 */
/*03a0*/ @!P3 IMAD.IADD R18, R10, 0x1, R13 ; /* 0x000000010a12b824 */
/* 0x000fc800078e020d */
/*03b0*/ @!P3 IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x178] ; /* 0x00005e001212b625 */
/* 0x000fe200078e0013 */
/*03c0*/ STS [R9], R28 ; /* 0x0000001c09007388 */
/* 0x0041e80000000800 */
/*03d0*/ STS [R9+0x10], R29 ; /* 0x0000101d09007388 */
/* 0x008fe80000000800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R27, [R5.X4+0x10] ; /* 0x00001000051b7984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R26, [R5.X4+0x18] ; /* 0x00001800051a7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e680000008a00 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ @!P3 LDG.E R16, [R18.64] ; /* 0x000000041210b981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R17, R4, 0x2, RZ ; /* 0x0000000204117810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fc600078e00ff */
/*0460*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x168], P0 ; /* 0x00005a0011007a0c */
/* 0x000fda0000766470 */
/*0470*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe20000000f00 */
/*0480*/ STS [R9], R16 ; /* 0x0000001009007388 */
/* 0x0041e80000000800 */
/*0490*/ @!P3 IMAD.WIDE.U32 R16, R23, R17, c[0x0][0x180] ; /* 0x000060001710b625 */
/* 0x001fca00078e0011 */
/*04a0*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0000a2000c1e1900 */
/*04b0*/ IMAD R14, R27, R14, R25 ; /* 0x0000000e1b0e7224 */
/* 0x002fe200078e0219 */
/*04c0*/ IADD3 R25, R13, 0x4, RZ ; /* 0x000000040d197810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ IMAD R14, R26, R15, R14 ; /* 0x0000000f1a0e7224 */
/* 0x000fe200078e020e */
/*04e0*/ ISETP.GE.U32.OR P3, PT, R25, c[0x0][0x164], P2 ; /* 0x0000590019007a0c */
/* 0x000fe40001766470 */
/*04f0*/ IADD3 R25, R4, 0x4, RZ ; /* 0x0000000404197810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GE.U32.OR P4, PT, R25, c[0x0][0x168], P0 ; /* 0x00005a0019007a0c */
/* 0x000fce0000786470 */
/*0510*/ @!P3 IADD3 R16, R12, -0x2, RZ ; /* 0xfffffffe0c10b810 */
/* 0x001fe40007ffe0ff */
/*0520*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fc80000000f00 */
/*0530*/ @!P4 MOV R15, 0x4 ; /* 0x00000004000fc802 */
/* 0x000fe20000000f00 */
/*0540*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x178] ; /* 0x00005e001010b625 */
/* 0x000fe200078e0011 */
/*0550*/ STS [R9+0x10], R28 ; /* 0x0000101c09007388 */
/* 0x0041e80000000800 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0570*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fca00078e00ff */
/*0580*/ LDS R29, [R5.X4+0x10] ; /* 0x00001000051d7984 */
/* 0x000fe80000004800 */
/*0590*/ LDS.64 R18, [R3.X8] ; /* 0x0000000003127984 */
/* 0x000e240000008a00 */
/*05a0*/ IMAD R25, R29, R18, R14 ; /* 0x000000121d197224 */
/* 0x001fe400078e020e */
/*05b0*/ LDS R18, [R5.X4+0x18] ; /* 0x0000180005127984 */
/* 0x000e280000004800 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc400078e00ff */
/*05e0*/ @!P4 IMAD.WIDE.U32 R14, R22, R15, c[0x0][0x180] ; /* 0x00006000160ec625 */
/* 0x000fc600078e000f */
/*05f0*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0002a8000c1e1900 */
/*0600*/ @!P4 LDG.E R29, [R14.64] ; /* 0x000000040e1dc981 */
/* 0x000ee2000c1e1900 */
/*0610*/ IADD3 R26, R13, 0x6, RZ ; /* 0x000000060d1a7810 */
/* 0x000fc80007ffe0ff */
/*0620*/ ISETP.GE.U32.OR P3, PT, R26, c[0x0][0x164], P2 ; /* 0x000059001a007a0c */
/* 0x000fe20001766470 */
/*0630*/ IMAD R25, R18, R19, R25 ; /* 0x0000001312197224 */
/* 0x001fe400078e0219 */
/*0640*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd400078e00ff */
/*0650*/ @!P3 MOV R27, 0x4 ; /* 0x00000004001bb802 */
/* 0x000fca0000000f00 */
/*0660*/ @!P3 IMAD.WIDE.U32 R16, R12, R27, c[0x0][0x178] ; /* 0x00005e000c10b625 */
/* 0x002fe200078e001b */
/*0670*/ STS [R9], R28 ; /* 0x0000001c09007388 */
/* 0x0041e80000000800 */
/*0680*/ STS [R9+0x10], R29 ; /* 0x0000101d09007388 */
/* 0x008fe80000000800 */
/*0690*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06a0*/ LDS R27, [R5.X4+0x10] ; /* 0x00001000051b7984 */
/* 0x000fe80000004800 */
/*06b0*/ LDS R26, [R5.X4+0x18] ; /* 0x00001800051a7984 */
/* 0x000fe80000004800 */
/*06c0*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e680000008a00 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ @!P3 LDG.E R18, [R16.64] ; /* 0x000000041012b981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R19, R4, 0x6, RZ ; /* 0x0000000604137810 */
/* 0x000fe20007ffe0ff */
/*0700*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fc600078e00ff */
/*0710*/ ISETP.GE.U32.OR P0, PT, R19, c[0x0][0x168], P0 ; /* 0x00005a0013007a0c */
/* 0x000fda0000706470 */
/*0720*/ @!P0 MOV R19, 0x4 ; /* 0x0000000400138802 */
/* 0x000fe20000000f00 */
/*0730*/ STS [R9], R18 ; /* 0x0000001209007388 */
/* 0x0041e80000000800 */
/*0740*/ @!P0 IMAD.WIDE.U32 R18, R21, R19, c[0x0][0x180] ; /* 0x0000600015128625 */
/* 0x001fca00078e0013 */
/*0750*/ @!P0 LDG.E R28, [R18.64] ; /* 0x00000004121c8981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD R14, R27, R14, R25 ; /* 0x0000000e1b0e7224 */
/* 0x002fe200078e0219 */
/*0770*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD R26, R26, R15, R14 ; /* 0x0000000f1a1a7224 */
/* 0x000fe200078e020e */
/*07a0*/ IADD3 R14, R11, R24, RZ ; /* 0x000000180b0e7210 */
/* 0x000fe20007ffe0ff */
/*07b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe200078e00ff */
/*07c0*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f05270 */
/*07e0*/ IMAD R21, R15.reuse, c[0x0][0x16c], R21 ; /* 0x00005b000f157a24 */
/* 0x040fe200078e0215 */
/*07f0*/ IADD3 R12, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD R22, R15, c[0x0][0x16c], R22 ; /* 0x00005b000f167a24 */
/* 0x000fc400078e0216 */
/*0810*/ IMAD R23, R15.reuse, c[0x0][0x16c], R23 ; /* 0x00005b000f177a24 */
/* 0x040fe400078e0217 */
/*0820*/ IMAD R20, R15, c[0x0][0x16c], R20 ; /* 0x00005b000f147a24 */
/* 0x000fe200078e0214 */
/*0830*/ STS [R9+0x10], R28 ; /* 0x0000101c09007388 */
/* 0x004fe80000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0850*/ LDS R29, [R5.X4+0x10] ; /* 0x00001000051d7984 */
/* 0x000fe80000004800 */
/*0860*/ LDS.64 R16, [R3.X8] ; /* 0x0000000003107984 */
/* 0x000e280000008a00 */
/*0870*/ LDS R25, [R5.X4+0x18] ; /* 0x0000180005197984 */
/* 0x000e620000004800 */
/*0880*/ IMAD R16, R29, R16, R26 ; /* 0x000000101d107224 */
/* 0x001fc800078e021a */
/*0890*/ IMAD R25, R25, R17, R16 ; /* 0x0000001119197224 */
/* 0x002fe200078e0210 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08b0*/ @P0 BRA 0x2b0 ; /* 0xfffff9f000000947 */
/* 0x000fea000383ffff */
/*08c0*/ @!P1 BRA 0xb10 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LEA R4, R24, R3, 0x1 ; /* 0x0000000318047211 */
/* 0x000fe200078e08ff */
/*08e0*/ IMAD R17, R6, c[0x0][0x164], R5 ; /* 0x0000590006117a24 */
/* 0x000fe400078e0205 */
/*08f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0a08 */
/*0900*/ IMAD R11, R4, c[0x0][0x16c], R5.reuse ; /* 0x00005b00040b7a24 */
/* 0x100fe200078e0205 */
/*0910*/ LEA R17, R24.reuse, R17, 0x1 ; /* 0x0000001118117211 */
/* 0x040fe200078e08ff */
/*0920*/ IMAD R24, R24, 0x2, R5 ; /* 0x0000000218187824 */
/* 0x000fc600078e0205 */
/*0930*/ LEA R16, R2, R11, 0x1 ; /* 0x0000000b02107211 */
/* 0x000fe400078e08ff */
/*0940*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe20003f26070 */
/*0950*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0960*/ ISETP.GE.U32.AND P0, PT, R24, c[0x0][0x164], PT ; /* 0x0000590018007a0c */
/* 0x000fe20003f06070 */
/*0970*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0980*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x16c], P1 ; /* 0x00005b0007007a0c */
/* 0x000fe40000f26670 */
/*0990*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fd60000706670 */
/*09a0*/ @!P1 MOV R13, 0x4 ; /* 0x00000004000d9802 */
/* 0x000fe40000000f00 */
/*09b0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a8424 */
/* 0x000fc600078e00ff */
/*09c0*/ @!P1 IMAD.WIDE.U32 R12, R16, R13, c[0x0][0x180] ; /* 0x00006000100c9625 */
/* 0x000fc800078e000d */
/*09d0*/ @!P0 IMAD.WIDE.U32 R10, R17, R10, c[0x0][0x178] ; /* 0x00005e00110a8625 */
/* 0x000fe200078e000a */
/*09e0*/ @!P1 LDG.E R18, [R12.64] ; /* 0x000000040c129981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ @!P0 LDG.E R20, [R10.64] ; /* 0x000000040a148981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0a20*/ IMAD.MOV.U32 R23, RZ, RZ, 0x2 ; /* 0x00000002ff177424 */
/* 0x000fe200078e00ff */
/*0a30*/ IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R24, R24, 0x2, RZ ; /* 0x0000000218187810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD R16, R23, c[0x0][0x16c], R16 ; /* 0x00005b0017107a24 */
/* 0x000fe200078e0210 */
/*0a60*/ IADD3 R17, R17, 0x2, RZ ; /* 0x0000000211117810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ STS [R9+0x10], R18 ; /* 0x0000101209007388 */
/* 0x004fe80000000800 */
/*0a80*/ STS [R9], R20 ; /* 0x0000001409007388 */
/* 0x008fe80000000800 */
/*0a90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0aa0*/ LDS R19, [R5.X4+0x10] ; /* 0x0000100005137984 */
/* 0x000fe80000004800 */
/*0ab0*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e280000008a00 */
/*0ac0*/ LDS R21, [R5.X4+0x18] ; /* 0x0000180005157984 */
/* 0x000e620000004800 */
/*0ad0*/ IMAD R14, R19, R14, R25 ; /* 0x0000000e130e7224 */
/* 0x001fc800078e0219 */
/*0ae0*/ IMAD R25, R21, R15, R14 ; /* 0x0000000f15197224 */
/* 0x002fe200078e020e */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ @P0 BRA 0x940 ; /* 0xfffffe3000000947 */
/* 0x000fea000383ffff */
/*0b10*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fc80003f06270 */
/*0b20*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x170], P0 ; /* 0x00005c0006007a0c */
/* 0x000fda0000706670 */
/*0b30*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b40*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x000fe200078e0203 */
/*0b50*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x000fc800078e0205 */
/*0b70*/ IMAD R0, R0, c[0x0][0x174], R5 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e0205 */
/*0b80*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fca00078e0003 */
/*0b90*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * M*N,
cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(
cudaMemcpy(B_d, B_h, sizeof(int) * N*K,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
cudaMemcpy(C_h, C_d, sizeof(int) * M*K,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) B_d));
CUDA_CHECK_RETURN(cudaFree((void* ) C_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} | .file "tmpxft_00061c9a_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_
.type _Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_, @function
_Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 208(%rsp), %rax
movq %rax, 16(%rsp)
movq 216(%rsp), %rax
movq %rax, 8(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movq %rsp, %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKerneliiiiiiPjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_, .-_Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_
.globl _Z15MatrixMulKerneliiiiiiPjS_S_
.type _Z15MatrixMulKerneliiiiiiPjS_S_, @function
_Z15MatrixMulKerneliiiiiiPjS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15MatrixMulKerneliiiiiiPjS_S_, .-_Z15MatrixMulKerneliiiiiiPjS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/kusht07/Parallel-Cuda-codes/master/matrixMulnxm/src/matrixMul.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\033[2J\033[1;1H"
.section .rodata.str1.8
.align 8
.LC3:
.string "Allocating arrays on host ... "
.align 8
.LC4:
.string "done.\nPopluating input matrix on host ..."
.align 8
.LC5:
.string "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.align 8
.LC6:
.string "done.\nAllocating arrays on device ... "
.align 8
.LC7:
.string "done.\nCopying arrays from host to device ... "
.section .rodata.str1.1
.LC8:
.string "done.\nLaunching kernel ... "
.LC9:
.string "done.\nElapsed kernel time: "
.LC10:
.string " ms\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Copying results back to host .... \n"
.align 8
.LC12:
.string "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.align 8
.LC13:
.string "\ndone.\n***GPU results are incorrect***"
.section .rodata.str1.1
.LC14:
.string "done\n"
.LC15:
.string "GPU results are valid.\n"
.LC16:
.string "Elapsed time on host: "
.LC19:
.string " ms"
.LC20:
.string "Freeing memory on device ... "
.section .rodata.str1.8
.align 8
.LC21:
.string "done.\nFreeing memory on host ... "
.section .rodata.str1.1
.LC22:
.string "done.\nExiting program.\n"
.LC23:
.string " Kushagra Trivedi\n 3080669\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $216, %rsp
.cfi_def_cfa_offset 272
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L79
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $60, %edi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $80, %edi
call _Znam@PLT
movq %rax, 40(%rsp)
movl $48, %edi
call _Znam@PLT
movq %rax, 32(%rsp)
movl $24, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $20, %edi
call _Znam@PLT
movq %rax, (%rbx)
movl $20, %edi
call _Znam@PLT
movq %rax, 8(%rbx)
movl $20, %edi
call _Znam@PLT
movq %rax, 16(%rbx)
movl $40, %edi
call _Znam@PLT
movq %rax, %rbp
movq %rax, %r12
leaq 40(%rax), %r13
movq %rax, %rbx
.L13:
movl $16, %edi
call _Znam@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L13
movl $24, %edi
call _Znam@PLT
movq %rax, %r14
movl $16, %edi
call _Znam@PLT
movq %rax, (%r14)
movl $16, %edi
call _Znam@PLT
movq %rax, 8(%r14)
movl $16, %edi
call _Znam@PLT
movq %rax, 16(%r14)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq (%rsp), %r15
movq %r15, %rbx
leaq 24(%r15), %rax
movq %rax, 8(%rsp)
movq %rbp, 16(%rsp)
.L14:
movl $0, %ebp
.L15:
call rand@PLT
movq (%r15), %rcx
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %esi
leal (%rdx,%rsi,2), %edx
subl %edx, %eax
movl %eax, (%rcx,%rbp)
addq $4, %rbp
cmpq $20, %rbp
jne .L15
addq $8, %r15
movq 8(%rsp), %rax
cmpq %rax, %r15
jne .L14
movq 16(%rsp), %rbp
movq %rbp, %r15
jmp .L16
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $94, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
addq $8, %r15
cmpq %r13, %r15
je .L80
.L16:
movl $0, %ebp
.L17:
call rand@PLT
movq (%r15), %rcx
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %esi
leal (%rdx,%rsi,2), %edx
subl %edx, %eax
movl %eax, (%rcx,%rbp)
addq $4, %rbp
cmpq $16, %rbp
jne .L17
jmp .L81
.L80:
movq 16(%rsp), %rbp
movq %r14, 56(%rsp)
leaq 24(%r14), %rcx
movq %r14, %rdx
.L18:
movq (%rdx), %rax
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
movl $0, 12(%rax)
addq $8, %rdx
cmpq %rcx, %rdx
jne .L18
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rcx
movl $0, %edi
movq (%rsp), %r8
.L19:
movq (%r8,%rdi,8), %rsi
movl $0, %eax
.L20:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L20
addq $1, %rdi
addq $20, %rcx
cmpq $3, %rdi
jne .L19
movq 40(%rsp), %rcx
movl $0, %edi
jmp .L21
.L82:
addq $1, %rdi
addq $16, %rcx
cmpq $5, %rdi
je .L23
.L21:
movq 0(%rbp,%rdi,8), %rsi
movl $0, %eax
.L22:
movl (%rsi,%rax), %edx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $16, %rax
jne .L22
jmp .L82
.L23:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 80(%rsp), %rdi
movl $60, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L83
leaq 88(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L84
leaq 96(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L85
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ecx
movl $60, %edx
movq 24(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L86
movl $1, %ecx
movl $80, %edx
movq 40(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L87
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, 120(%rsp)
movl $2, 124(%rsp)
movl $1, 128(%rsp)
movl $2, 132(%rsp)
movl $2, 136(%rsp)
movl $1, 140(%rsp)
leaq 104(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L88
leaq 112(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L89
movl $0, %esi
movq 104(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L90
movl 140(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 132(%rsp), %rdx
movq 120(%rsp), %rdi
movl 128(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L91
.L32:
movl $0, %esi
movq 112(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L92
movq 112(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L93
leaq 76(%rsp), %rdi
movq 112(%rsp), %rdx
movq 104(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L94
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L95
call cudaGetLastError@PLT
testl %eax, %eax
jne .L96
movq 104(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L97
movq 112(%rsp), %rdi
call cudaEventDestroy@PLT
testl %eax, %eax
jne .L98
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC11(%rip), %rsi
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $2, %ecx
movl $48, %edx
movq 96(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L99
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 32(%rsp), %rcx
movl $0, %edi
.L41:
movq (%r14,%rdi,8), %rsi
movl $0, %eax
.L42:
movl (%rcx,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq $16, %rax
jne .L42
addq $1, %rdi
addq $16, %rcx
cmpq $3, %rdi
jne .L41
call clock@PLT
movq %rax, 48(%rsp)
leaq 144(%rsp), %rax
leaq 192(%rsp), %rdx
movq %rax, %rcx
movq (%rsp), %r10
movq %rdx, 16(%rsp)
.L44:
movq (%r10), %r9
movq %rcx, %r11
movl $0, %r8d
.L46:
movq %r11, %r14
movl %r15d, %edi
movl $0, %edx
.L45:
movq 0(%rbp,%rdx,8), %rsi
movl (%rsi,%r8), %esi
imull (%r9,%rdx,4), %esi
addl %esi, %edi
addq $1, %rdx
cmpq $5, %rdx
jne .L45
movl %edi, (%r14)
addq $4, %r11
addq $4, %r8
cmpq $16, %r8
jne .L46
addq $8, %r10
addq $16, %rcx
cmpq %rcx, 16(%rsp)
jne .L44
movq 16(%rsp), %rdx
movq 56(%rsp), %rdi
.L47:
movq (%rdi), %rsi
movl $0, %ecx
.L50:
movl (%rax,%rcx), %r10d
cmpl %r10d, (%rsi,%rcx)
jne .L100
addq $4, %rcx
cmpq $16, %rcx
jne .L50
addq $8, %rdi
addq $16, %rax
cmpq %rax, %rdx
jne .L47
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC15(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L49:
call clock@PLT
movq 48(%rsp), %rcx
subq %rcx, %rax
movq %rax, %r14
leaq .LC16(%rip), %rsi
leaq _ZSt4cout(%rip), %r15
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtsi2ssq %r14, %xmm0
divss .LC17(%rip), %xmm0
mulss .LC18(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC20(%rip), %rsi
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L101
movq 88(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L102
movq 96(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L103
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L104
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movq 40(%rsp), %rdi
call _ZdaPv@PLT
movq 32(%rsp), %rdi
call _ZdaPv@PLT
movq 8(%rsp), %r14
jmp .L57
.L83:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $154, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $156, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $158, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L86:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $163, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $166, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $183, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $184, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $187, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
subq $8, %rsp
.cfi_def_cfa_offset 280
pushq 104(%rsp)
.cfi_def_cfa_offset 288
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
movl $4, %r9d
movl $3, %r8d
movl $4, %ecx
movl $5, %edx
movl $5, %esi
movl $3, %edi
call _Z45__device_stub__Z15MatrixMulKerneliiiiiiPjS_S_iiiiiiPjS_S_
addq $32, %rsp
.cfi_def_cfa_offset 272
jmp .L32
.L92:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $197, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $199, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $200, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $201, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L96:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $202, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L97:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $203, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L98:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $204, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L99:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $208, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L100:
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC14(%rip), %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L49
.L101:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $279, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L102:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $280, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L103:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $281, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L104:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $282, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
addq $8, %rbx
cmpq %r14, %rbx
je .L105
.L57:
movq (%rbx), %rdi
testq %rdi, %rdi
je .L56
call _ZdaPv@PLT
jmp .L56
.L105:
movq (%rsp), %rdi
call _ZdaPv@PLT
jmp .L59
.L107:
call _ZdaPv@PLT
.L58:
addq $8, %r12
cmpq %r13, %r12
je .L106
.L59:
movq (%r12), %rdi
testq %rdi, %rdi
jne .L107
jmp .L58
.L106:
movq %rbp, %rdi
call _ZdaPv@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L108
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L108:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC24:
.string "_Z15MatrixMulKerneliiiiiiPjS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKerneliiiiiiPjS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1232348160
.align 4
.LC18:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //---------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
cudaError_t _m_cudaStat = value; \
if (_m_cudaStat != cudaSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(cudaSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
cudaMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
cudaMemcpy(A_d, A_h, sizeof(int) * M*N,
cudaMemcpyHostToDevice));
CUDA_CHECK_RETURN(
cudaMemcpy(B_d, B_h, sizeof(int) * N*K,
cudaMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
cudaEvent_t start, stop;
CUDA_CHECK_RETURN(cudaEventCreate(&start));
CUDA_CHECK_RETURN(cudaEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(cudaEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(cudaEventRecord(stop, 0));
CUDA_CHECK_RETURN(cudaEventSynchronize(stop));
CUDA_CHECK_RETURN(cudaEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(cudaThreadSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(cudaGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(cudaEventDestroy(start));
CUDA_CHECK_RETURN(cudaEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
cudaMemcpy(C_h, C_d, sizeof(int) * M*K,
cudaMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(cudaFree((void* ) A_d));
CUDA_CHECK_RETURN(cudaFree((void* ) B_d));
CUDA_CHECK_RETURN(cudaFree((void* ) C_d));
CUDA_CHECK_RETURN(cudaDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * M*N,
hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(
hipMemcpy(B_d, B_h, sizeof(int) * N*K,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
hipMemcpy(C_h, C_d, sizeof(int) * M*K,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) B_d));
CUDA_CHECK_RETURN(hipFree((void* ) C_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * M*N,
hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(
hipMemcpy(B_d, B_h, sizeof(int) * N*K,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
hipMemcpy(C_h, C_d, sizeof(int) * M*K,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) B_d));
CUDA_CHECK_RETURN(hipFree((void* ) C_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKerneliiiiiiPjS_S_
.globl _Z15MatrixMulKerneliiiiiiPjS_S_
.p2align 8
.type _Z15MatrixMulKerneliiiiiiPjS_S_,@function
_Z15MatrixMulKerneliiiiiiPjS_S_:
s_load_b32 s3, s[0:1], 0x4
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, s15, 1, v1
v_lshl_add_u32 v2, s14, 1, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_13
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v10, 2, v0
v_lshlrev_b32_e32 v8, 3, v1
v_mov_b32_e32 v6, 0
v_mad_u64_u32 v[4:5], null, v7, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, 16, v10
s_add_i32 s11, s3, 1
v_add_nc_u32_e32 v10, v8, v10
s_lshr_b32 s11, s11, 1
s_mov_b32 s10, 0
v_add_nc_u32_e32 v11, v9, v8
s_max_i32 s11, s11, 1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s9, v2
s_xor_b32 s12, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s13, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s13, v0
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s16, s12, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s17, s16
s_xor_b32 s16, exec_lo, s17
s_cbranch_execz .LBB0_4
ds_store_b32 v10, v6
.LBB0_4:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v5, s13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v5, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_or_b32 s13, s2, vcc_lo
s_and_saveexec_b32 s16, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s16
s_cbranch_execz .LBB0_8
ds_store_b32 v11, v6
.LBB0_8:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v5, s9, v[2:3]
v_mov_b32_e32 v13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v5, v9
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s13, v8
s_add_i32 s13, s13, 4
ds_load_b32 v14, v5
ds_load_b32 v15, v12
v_add_nc_u32_e32 v5, 8, v5
s_cmp_lg_u32 s13, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v15, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v3, 0
.LBB0_14:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, s3
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKerneliiiiiiPjS_S_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKerneliiiiiiPjS_S_, .Lfunc_end0-_Z15MatrixMulKerneliiiiiiPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKerneliiiiiiPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKerneliiiiiiPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //---------------------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <iostream>
//---------------------------------------------------------------------------------
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** A = M x N **** AxB=C
//**** B = N x K ****
//**** C = M x K ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
static const int M = 3;
static const int N = 5;
static const int K = 4;
static const int TILE_WIDTH = 2;
using namespace std;
//---------------------------------------------------------------------------------
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN(value) { \
hipError_t _m_cudaStat = value; \
if (_m_cudaStat != hipSuccess) { \
fprintf(stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(_m_cudaStat), __LINE__, __FILE__); \
exit(1); \
} }
//---------------------------------------------------------------------------------
__global__ void MatrixMulKernel(int ARows,int ACols, int BRows,
int BCols, int CRows, int CCols,unsigned int* A_d, unsigned int *B_d, unsigned int *C_d) {
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Populate matrixMultiplication kernel function ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
int CValue = 0;
int Row = blockIdx.y*TILE_WIDTH + threadIdx.y;
int Col = blockIdx.x*TILE_WIDTH + threadIdx.x;
__shared__ int As[TILE_WIDTH][TILE_WIDTH];
__shared__ int Bs[TILE_WIDTH][TILE_WIDTH];
for (int k = 0; k < (TILE_WIDTH + ACols - 1)/TILE_WIDTH; k++) {
if (k*TILE_WIDTH + threadIdx.x < ACols && Row < ARows)
As[threadIdx.y][threadIdx.x] = A_d[Row*ACols + k*TILE_WIDTH + threadIdx.x];
else
As[threadIdx.y][threadIdx.x] = 0;
if (k*TILE_WIDTH + threadIdx.y < BRows && Col < BCols)
Bs[threadIdx.y][threadIdx.x] = B_d[(k*TILE_WIDTH + threadIdx.y)*BCols + Col];
else
Bs[threadIdx.y][threadIdx.x] = 0;
__syncthreads();
for (int n = 0; n < TILE_WIDTH; ++n)
CValue += As[threadIdx.y][n] * Bs[n][threadIdx.x];
__syncthreads();
}
if (Row < CRows && Col < CCols)
C_d[((blockIdx.y * blockDim.y + threadIdx.y)*CCols) +
(blockIdx.x * blockDim.x)+ threadIdx.x] = CValue;
}
//---------------------------------------------------------------------------------
int main(void) {
unsigned int **A ;
unsigned int **B ;
unsigned int **C ;
unsigned int *A_h;
unsigned int *A_d;
unsigned int *B_h;
unsigned int *B_d;
unsigned int *C_h;
unsigned int *C_d;
unsigned int D[M][K];
//Set Device
CUDA_CHECK_RETURN(hipSetDevice(0));
//See random number generator
srand(time(NULL));
//Clear command prompt
cout << "\033[2J\033[1;1H";
cout << "Allocating arrays on host ... ";
A_h = new unsigned int[M*N];
B_h = new unsigned int[N*K];
C_h = new unsigned int[M*K];
A = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
A[i] = new unsigned int[N];
}
B = new unsigned int* [N];
for (int i = 0; i < N; ++i) {
B[i] = new unsigned int[K];
}
C = new unsigned int* [M];
for (int i = 0; i < M; ++i) {
C[i] = new unsigned int[K];
}
cout << "done.\nPopluating input matrix on host ...";
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A[i][j] = rand()% 11;
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B[i][j] = rand()% 11;
}
}
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =0;
}
}
cout << "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 2-dimensional input matrix to 1-dimensional array here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < N; ++j) {
A_h[i*N+j] = A[i][j];
}
}
for (int i = 0; i < N; ++i) {
for (int j = 0; j < K; ++j) {
B_h[i*K+j] = B[i][j];
}
}
cout << "done.\nAllocating arrays on device ... ";
CUDA_CHECK_RETURN(
hipMalloc((void** ) &A_d, sizeof(unsigned int) * M*N));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &B_d, sizeof(unsigned int) * N*K));
CUDA_CHECK_RETURN(
hipMalloc((void** ) &C_d, sizeof(unsigned int) * M*K));
cout << "done.\nCopying arrays from host to device ... ";
CUDA_CHECK_RETURN(
hipMemcpy(A_d, A_h, sizeof(int) * M*N,
hipMemcpyHostToDevice));
CUDA_CHECK_RETURN(
hipMemcpy(B_d, B_h, sizeof(int) * N*K,
hipMemcpyHostToDevice));
cout << "done.\nLaunching kernel ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** define kernel launch parameters ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
dim3 dimGrid(((K-1)/TILE_WIDTH+1), ((M-1)/TILE_WIDTH+1), 1);
dim3 dimBlock(TILE_WIDTH, TILE_WIDTH, 1);
//Time kernel launch
//Time kernel launch
hipEvent_t start, stop;
CUDA_CHECK_RETURN(hipEventCreate(&start));
CUDA_CHECK_RETURN(hipEventCreate(&stop));
float elapsedTime;
CUDA_CHECK_RETURN(hipEventRecord(start, 0));
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add kernel call here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
MatrixMulKernel<<< dimGrid, dimBlock >>>(M,N,N,K,M,K,A_d, B_d, C_d);
CUDA_CHECK_RETURN(hipEventRecord(stop, 0));
CUDA_CHECK_RETURN(hipEventSynchronize(stop));
CUDA_CHECK_RETURN(hipEventElapsedTime(&elapsedTime, start, stop));
CUDA_CHECK_RETURN(hipDeviceSynchronize()); // Wait for the GPU launched work to complete
CUDA_CHECK_RETURN(hipGetLastError()); //Check if an error occurred in device code
CUDA_CHECK_RETURN(hipEventDestroy(start));
CUDA_CHECK_RETURN(hipEventDestroy(stop));
cout << "done.\nElapsed kernel time: " << elapsedTime << " ms\n";
cout << "Copying results back to host .... \n";
CUDA_CHECK_RETURN(
hipMemcpy(C_h, C_d, sizeof(int) * M*K,
hipMemcpyDeviceToHost));
cout << "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... ";
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Add code for converting 1-dimensional output array to 2-dimensional matrix here ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
C[i][j] =C_h[i*K+j] ;
}
}
clock_t st, ed;
st = clock();
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
// **** Check that results from kernel are correct ****
// **** Complete validation code below ****
//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
for(int i=0;i<M;++i)
{
for(int j=0;j<K;++j)
{
D[i][j]=0;
for(int k=0;k<N;++k)
D[i][j]=D[i][j]+(A[i][k]*B[k][j]);
}
}
bool valid = true;
for (int i = 0; i < M; ++i) {
for (int j = 0; j < K; ++j) {
if(C[i][j] != D[i][j])
{
cout << "\ndone.\n***GPU results are incorrect***";
valid = false;
break;
}
}
if(!valid){
break;
}
}
cout<<"done\n";
if (valid) {
cout << "GPU results are valid.\n";
}
ed = clock() - st;
cout << "Elapsed time on host: " << ((float) ed) / CLOCKS_PER_SEC * 1000
<< " ms" << endl;
cout << "Freeing memory on device ... ";
CUDA_CHECK_RETURN(hipFree((void* ) A_d));
CUDA_CHECK_RETURN(hipFree((void* ) B_d));
CUDA_CHECK_RETURN(hipFree((void* ) C_d));
CUDA_CHECK_RETURN(hipDeviceReset());
cout << "done.\nFreeing memory on host ... ";
delete[] A_h;
delete[] B_h;
delete[] C_h;
for (int i = 0; i < M; ++i) {
delete[] A[i];
}
delete[] A;
for (int i = 0; i < N; ++i) {
delete[] B[i];
}
delete[] B;
cout << "done.\nExiting program.\n";
cout<<" Kushagra Trivedi\n 3080669\n";
return 0;
} | .text
.file "matrixMul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_ # -- Begin function _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_,@function
_Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_: # @_Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15MatrixMulKerneliiiiiiPjS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_, .Lfunc_end0-_Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3:
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $30, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $60, %edi
callq _Znam
movq %rax, %r13
movl $80, %edi
callq _Znam
movq %rax, %r12
movl $48, %edi
callq _Znam
movq %rax, 88(%rsp) # 8-byte Spill
movl $24, %edi
callq _Znam
movq %rax, %r14
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl $20, %edi
callq _Znam
movq %rax, (%r14,%rbx,8)
incq %rbx
cmpq $3, %rbx
jne .LBB1_4
# %bb.5:
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl $16, %edi
callq _Znam
movq %rax, (%rbx,%r15,8)
incq %r15
cmpq $5, %r15
jne .LBB1_6
# %bb.7:
movl $24, %edi
callq _Znam
movq %rax, %rbp
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
movl $16, %edi
callq _Znam
movq %rax, (%rbp,%r15,8)
incq %r15
cmpq $3, %r15
jne .LBB1_8
# %bb.9:
movq %r12, 96(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $41, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_10: # %.preheader239
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movq (%r14,%r15,8), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
cmpq $5, %r12
jne .LBB1_11
# %bb.12: # in Loop: Header=BB1_10 Depth=1
incq %r15
cmpq $3, %r15
jne .LBB1_10
# %bb.13: # %.preheader237.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_14: # %.preheader237
# =>This Loop Header: Depth=1
# Child Loop BB1_15 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_15: # Parent Loop BB1_14 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movq (%rbx,%r15,8), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
cmpq $4, %r12
jne .LBB1_15
# %bb.16: # in Loop: Header=BB1_14 Depth=1
incq %r15
cmpq $5, %r15
jne .LBB1_14
# %bb.17: # %.preheader235.preheader
xorl %eax, %eax
xorps %xmm0, %xmm0
.p2align 4, 0x90
.LBB1_18: # %.preheader235
# =>This Inner Loop Header: Depth=1
movq (%rbp,%rax,8), %rcx
movups %xmm0, (%rcx)
incq %rax
cmpq $3, %rax
jne .LBB1_18
# %bb.19:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $79, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
movq %r13, %rcx
movq 96(%rsp), %r15 # 8-byte Reload
.p2align 4, 0x90
.LBB1_20: # %.preheader234
# =>This Loop Header: Depth=1
# Child Loop BB1_21 Depth 2
movq (%r14,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_21: # Parent Loop BB1_20 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rsi,4), %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq $5, %rsi
jne .LBB1_21
# %bb.22: # in Loop: Header=BB1_20 Depth=1
incq %rax
addq $20, %rcx
cmpq $3, %rax
jne .LBB1_20
# %bb.23: # %.preheader232.preheader
xorl %eax, %eax
movq %r15, %rcx
.p2align 4, 0x90
.LBB1_24: # %.preheader232
# =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
movq (%rbx,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_25: # Parent Loop BB1_24 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rsi,4), %edi
movl %edi, (%rcx,%rsi,4)
incq %rsi
cmpq $4, %rsi
jne .LBB1_25
# %bb.26: # in Loop: Header=BB1_24 Depth=1
incq %rax
addq $16, %rcx
cmpq $5, %rax
jne .LBB1_24
# %bb.27:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 40(%rsp), %rdi
movl $60, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_28
# %bb.29:
leaq 32(%rsp), %rdi
movl $80, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.31:
leaq 24(%rsp), %rdi
movl $48, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_32
# %bb.33:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 40(%rsp), %rdi
movl $60, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_34
# %bb.35:
movq 32(%rsp), %rdi
movl $80, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_36
# %bb.37:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
movq 88(%rsp), %r15 # 8-byte Reload
jne .LBB1_38
# %bb.39:
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_40
# %bb.41:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_42
# %bb.43:
movabsq $8589934594, %rdi # imm = 0x200000002
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_45
# %bb.44:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movl $3, 68(%rsp)
movl $5, 64(%rsp)
movl $5, 60(%rsp)
movl $4, 56(%rsp)
movl $3, 52(%rsp)
movl $4, 48(%rsp)
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
leaq 68(%rsp), %rax
movq %rax, 176(%rsp)
leaq 64(%rsp), %rax
movq %rax, 184(%rsp)
leaq 60(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 52(%rsp), %rax
movq %rax, 208(%rsp)
leaq 48(%rsp), %rax
movq %rax, 216(%rsp)
leaq 168(%rsp), %rax
movq %rax, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 232(%rsp)
leaq 152(%rsp), %rax
movq %rax, 240(%rsp)
leaq 72(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z15MatrixMulKerneliiiiiiPjS_S_, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_45:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_46
# %bb.47:
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_48
# %bb.49:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 72(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_50
# %bb.51:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_52
# %bb.53:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_54
# %bb.55:
movq 16(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_56
# %bb.57:
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %eax, %eax
jne .LBB1_58
# %bb.59:
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 72(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.10, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rsi
movl $48, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_60
# %bb.61:
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $80, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_62: # %.preheader231
# =>This Loop Header: Depth=1
# Child Loop BB1_63 Depth 2
movq (%rbp,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_63: # Parent Loop BB1_62 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rsi,4), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $4, %rsi
jne .LBB1_63
# %bb.64: # in Loop: Header=BB1_62 Depth=1
incq %rax
addq $16, %r15
cmpq $3, %rax
jne .LBB1_62
# %bb.65:
movq %r13, 112(%rsp) # 8-byte Spill
xorl %r15d, %r15d
callq clock
movq %rax, 104(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_66: # %.preheader230
# =>This Loop Header: Depth=1
# Child Loop BB1_67 Depth 2
# Child Loop BB1_68 Depth 3
movq (%r14,%r15,8), %rax
movq %r15, %rcx
shlq $4, %rcx
addq %rsp, %rcx
addq $176, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_67: # Parent Loop BB1_66 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_68 Depth 3
leaq (%rcx,%rdx,4), %rsi
movl $0, (%rcx,%rdx,4)
xorl %edi, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_68: # Parent Loop BB1_66 Depth=1
# Parent Loop BB1_67 Depth=2
# => This Inner Loop Header: Depth=3
movq (%rbx,%rdi,8), %r9
movl (%r9,%rdx,4), %r9d
imull (%rax,%rdi,4), %r9d
addl %r9d, %r8d
incq %rdi
cmpq $5, %rdi
jne .LBB1_68
# %bb.69: # in Loop: Header=BB1_67 Depth=2
movl %r8d, (%rsi)
incq %rdx
cmpq $4, %rdx
jne .LBB1_67
# %bb.70: # in Loop: Header=BB1_66 Depth=1
incq %r15
cmpq $3, %r15
jne .LBB1_66
# %bb.71: # %.preheader.preheader
movb $1, %r12b
leaq 176(%rsp), %r13
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_72: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_74 Depth 2
movq (%rbp,%r15,8), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_74: # Parent Loop BB1_72 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rax,%rcx,4), %edx
cmpl (%r13,%rcx,4), %edx
jne .LBB1_75
# %bb.73: # in Loop: Header=BB1_74 Depth=2
incq %rcx
cmpq $4, %rcx
jne .LBB1_74
# %bb.76: # %.loopexit
# in Loop: Header=BB1_72 Depth=1
testb $1, %r12b
jne .LBB1_77
jmp .LBB1_78
.p2align 4, 0x90
.LBB1_75: # in Loop: Header=BB1_72 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r12d, %r12d
testb $1, %r12b
je .LBB1_78
.LBB1_77: # %.loopexit
# in Loop: Header=BB1_72 Depth=1
incq %r15
addq $16, %r13
cmpq $3, %r15
jne .LBB1_72
.LBB1_78:
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testb $1, %r12b
je .LBB1_80
# %bb.79:
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB1_80:
callq clock
movq %rax, %rbp
subq 104(%rsp), %rbp # 8-byte Folded Reload
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cvtsi2ss %rbp, %xmm0
divss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.17, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %rbp
testq %rbp, %rbp
movq 112(%rsp), %r12 # 8-byte Reload
je .LBB1_101
# %bb.81: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB1_83
# %bb.82:
movzbl 67(%rbp), %eax
jmp .LBB1_84
.LBB1_83:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_84: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_85
# %bb.86:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
movq 88(%rsp), %r15 # 8-byte Reload
jne .LBB1_87
# %bb.88:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_89
# %bb.90:
callq hipDeviceReset
testl %eax, %eax
jne .LBB1_91
# %bb.92:
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r12, %rdi
callq _ZdaPv
movq 96(%rsp), %rdi # 8-byte Reload
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %r15d, %r15d
jmp .LBB1_93
.p2align 4, 0x90
.LBB1_95: # in Loop: Header=BB1_93 Depth=1
incq %r15
cmpq $3, %r15
je .LBB1_96
.LBB1_93: # =>This Inner Loop Header: Depth=1
movq (%r14,%r15,8), %rdi
testq %rdi, %rdi
je .LBB1_95
# %bb.94: # in Loop: Header=BB1_93 Depth=1
callq _ZdaPv
jmp .LBB1_95
.LBB1_96:
movq %r14, %rdi
callq _ZdaPv
xorl %r14d, %r14d
jmp .LBB1_97
.p2align 4, 0x90
.LBB1_99: # in Loop: Header=BB1_97 Depth=1
incq %r14
cmpq $5, %r14
je .LBB1_100
.LBB1_97: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rdi
testq %rdi, %rdi
je .LBB1_99
# %bb.98: # in Loop: Header=BB1_97 Depth=1
callq _ZdaPv
jmp .LBB1_99
.LBB1_100:
movq %rbx, %rdi
callq _ZdaPv
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.21, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %ecx
jmp .LBB1_2
.LBB1_28:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $157, %ecx
jmp .LBB1_2
.LBB1_30:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $159, %ecx
jmp .LBB1_2
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $161, %ecx
jmp .LBB1_2
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $167, %ecx
jmp .LBB1_2
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $170, %ecx
jmp .LBB1_2
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $185, %ecx
jmp .LBB1_2
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $186, %ecx
jmp .LBB1_2
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $189, %ecx
jmp .LBB1_2
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $199, %ecx
jmp .LBB1_2
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $201, %ecx
jmp .LBB1_2
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $202, %ecx
jmp .LBB1_2
.LBB1_52:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $203, %ecx
jmp .LBB1_2
.LBB1_54:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $204, %ecx
jmp .LBB1_2
.LBB1_56:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $205, %ecx
jmp .LBB1_2
.LBB1_58:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $206, %ecx
jmp .LBB1_2
.LBB1_60:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $212, %ecx
jmp .LBB1_2
.LBB1_101:
callq _ZSt16__throw_bad_castv
.LBB1_85:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $281, %ecx # imm = 0x119
jmp .LBB1_2
.LBB1_87:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $282, %ecx # imm = 0x11A
jmp .LBB1_2
.LBB1_89:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $283, %ecx # imm = 0x11B
jmp .LBB1_2
.LBB1_91:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $284, %ecx # imm = 0x11C
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKerneliiiiiiPjS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKerneliiiiiiPjS_S_,@object # @_Z15MatrixMulKerneliiiiiiPjS_S_
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKerneliiiiiiPjS_S_
.p2align 3, 0x0
_Z15MatrixMulKerneliiiiiiPjS_S_:
.quad _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_
.size _Z15MatrixMulKerneliiiiiiPjS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/kusht07/Parallel-Cuda-codes/master/matrixMulnxm/src/matrixMul.hip"
.size .L.str.1, 123
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\033[2J\033[1
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocating arrays on host ... "
.size .L.str.3, 31
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "done.\nPopluating input matrix on host ..."
.size .L.str.4, 42
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "done.\nConverting 2-dimensional input matrix to 1-dimensional array on host ... "
.size .L.str.5, 80
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "done.\nAllocating arrays on device ... "
.size .L.str.6, 39
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "done.\nCopying arrays from host to device ... "
.size .L.str.7, 46
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "done.\nLaunching kernel ... "
.size .L.str.8, 28
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "done.\nElapsed kernel time: "
.size .L.str.9, 28
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " ms\n"
.size .L.str.10, 5
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Copying results back to host .... \n"
.size .L.str.11, 36
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "done.\nConverting 1-dimensional output array to 2-dimensional matrix on host ... "
.size .L.str.12, 81
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\ndone.\n***GPU results are incorrect***"
.size .L.str.13, 39
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "done\n"
.size .L.str.14, 6
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "GPU results are valid.\n"
.size .L.str.15, 24
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "Elapsed time on host: "
.size .L.str.16, 23
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " ms"
.size .L.str.17, 4
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Freeing memory on device ... "
.size .L.str.18, 30
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "done.\nFreeing memory on host ... "
.size .L.str.19, 34
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "done.\nExiting program.\n"
.size .L.str.20, 24
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " Kushagra Trivedi\n 3080669\n"
.size .L.str.21, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15MatrixMulKerneliiiiiiPjS_S_"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKerneliiiiiiPjS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKerneliiiiiiPjS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKerneliiiiiiPjS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff0d7624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R25, -RZ, RZ, 0, 0 ; /* 0x00000000ff197435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R6, R0, 0x2, R3 ; /* 0x0000000200067824 */
/* 0x001fc400078e0203 */
/*00a0*/ IMAD R7, R2, 0x2, R5 ; /* 0x0000000202077824 */
/* 0x002fc800078e0205 */
/*00b0*/ @!P0 BRA 0xb10 ; /* 0x00000a5000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R4, R13, 0x1, RZ ; /* 0x000000010d047810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fc6000001ff00 */
/*00e0*/ LEA.HI R4, R4, R4, RZ, 0x1 ; /* 0x0000000404047211 */
/* 0x000fc800078f08ff */
/*00f0*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0100*/ IMNMX R11, R4, 0x1, !PT ; /* 0x00000001040b7817 */
/* 0x000fc80007800200 */
/*0110*/ IADD3 R4, R11.reuse, -0x1, RZ ; /* 0xffffffff0b047810 */
/* 0x040fe40007ffe0ff */
/*0120*/ LOP3.LUT R8, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b087812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0140*/ SHF.L.U32 R4, R3, 0x3, RZ ; /* 0x0000000303047819 */
/* 0x000fe400000006ff */
/*0150*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f25270 */
/*0160*/ IMAD R9, R5, 0x4, R4 ; /* 0x0000000405097824 */
/* 0x000fcc00078e0204 */
/*0170*/ @!P0 BRA 0x8c0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R14, R3.reuse, 0x6, RZ ; /* 0x00000006030e7810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD R12, R6, c[0x0][0x164], R5.reuse ; /* 0x00005900060c7a24 */
/* 0x100fe200078e0205 */
/*01a0*/ IADD3 R16, R3.reuse, 0x4, RZ ; /* 0x0000000403107810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD R17, R3.reuse, c[0x0][0x16c], R5.reuse ; /* 0x00005b0003117a24 */
/* 0x140fe200078e0205 */
/*01c0*/ IADD3 R18, R3, 0x2, RZ ; /* 0x0000000203127810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R21, R14, c[0x0][0x16c], R5.reuse ; /* 0x00005b000e157a24 */
/* 0x100fe200078e0205 */
/*01e0*/ ISETP.GE.AND P2, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fe20003f46270 */
/*01f0*/ IMAD R15, R16, c[0x0][0x16c], R5.reuse ; /* 0x00005b00100f7a24 */
/* 0x100fe200078e0205 */
/*0200*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R23, R18, c[0x0][0x16c], R5 ; /* 0x00005b0012177a24 */
/* 0x000fe200078e0205 */
/*0220*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0230*/ IMAD R10, R6, R13, 0x2 ; /* 0x00000002060a7424 */
/* 0x000fe200078e020d */
/*0240*/ IADD3 R12, R12, 0x6, RZ ; /* 0x000000060c0c7810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*0260*/ LEA R21, R2, R21, 0x1 ; /* 0x0000001502157211 */
/* 0x000fe200078e08ff */
/*0270*/ IMAD.MOV.U32 R13, RZ, RZ, R5 ; /* 0x000000ffff0d7224 */
/* 0x000fc400078e0005 */
/*0280*/ IMAD R20, R2.reuse, 0x2, R17 ; /* 0x0000000202147824 */
/* 0x040fe400078e0211 */
/*0290*/ IMAD R22, R2.reuse, 0x2, R15 ; /* 0x0000000202167824 */
/* 0x040fe400078e020f */
/*02a0*/ IMAD R23, R2, 0x2, R23 ; /* 0x0000000202177824 */
/* 0x000fe400078e0217 */
/*02b0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x16c], PT ; /* 0x00005b0007007a0c */
/* 0x000fe20003f06270 */
/*02c0*/ CS2R R28, SRZ ; /* 0x00000000001c7805 */
/* 0x000fe2000001ff00 */
/*02d0*/ ISETP.GE.U32.OR P3, PT, R13, c[0x0][0x164], P2 ; /* 0x000059000d007a0c */
/* 0x000fe40001766470 */
/*02e0*/ ISETP.GE.U32.OR P4, PT, R4, c[0x0][0x168], P0 ; /* 0x00005a0004007a0c */
/* 0x000fd60000786470 */
/*02f0*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe20000000f00 */
/*0300*/ @!P3 IMAD R16, R6, c[0x0][0x164], R13 ; /* 0x000059000610ba24 */
/* 0x000fe400078e020d */
/*0310*/ @!P4 IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0fc424 */
/* 0x000fe400078e00ff */
/*0320*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x178] ; /* 0x00005e001010b625 */
/* 0x000fc800078e0011 */
/*0330*/ @!P4 IMAD.WIDE.U32 R14, R20, R15, c[0x0][0x180] ; /* 0x00006000140ec625 */
/* 0x000fe200078e000f */
/*0340*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0000a8000c1e1900 */
/*0350*/ @!P4 LDG.E R29, [R14.64] ; /* 0x000000040e1dc981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R18, R13, 0x2, RZ ; /* 0x000000020d127810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GE.U32.OR P3, PT, R18, c[0x0][0x164], P2 ; /* 0x0000590012007a0c */
/* 0x000fe20001766470 */
/*0380*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x001fd800078e00ff */
/*0390*/ @!P3 MOV R19, 0x4 ; /* 0x000000040013b802 */
/* 0x000fe20000000f00 */
/*03a0*/ @!P3 IMAD.IADD R18, R10, 0x1, R13 ; /* 0x000000010a12b824 */
/* 0x000fc800078e020d */
/*03b0*/ @!P3 IMAD.WIDE.U32 R18, R18, R19, c[0x0][0x178] ; /* 0x00005e001212b625 */
/* 0x000fe200078e0013 */
/*03c0*/ STS [R9], R28 ; /* 0x0000001c09007388 */
/* 0x0041e80000000800 */
/*03d0*/ STS [R9+0x10], R29 ; /* 0x0000101d09007388 */
/* 0x008fe80000000800 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R27, [R5.X4+0x10] ; /* 0x00001000051b7984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R26, [R5.X4+0x18] ; /* 0x00001800051a7984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e680000008a00 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ @!P3 LDG.E R16, [R18.64] ; /* 0x000000041210b981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IADD3 R17, R4, 0x2, RZ ; /* 0x0000000204117810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fc600078e00ff */
/*0460*/ ISETP.GE.U32.OR P3, PT, R17, c[0x0][0x168], P0 ; /* 0x00005a0011007a0c */
/* 0x000fda0000766470 */
/*0470*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fe20000000f00 */
/*0480*/ STS [R9], R16 ; /* 0x0000001009007388 */
/* 0x0041e80000000800 */
/*0490*/ @!P3 IMAD.WIDE.U32 R16, R23, R17, c[0x0][0x180] ; /* 0x000060001710b625 */
/* 0x001fca00078e0011 */
/*04a0*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0000a2000c1e1900 */
/*04b0*/ IMAD R14, R27, R14, R25 ; /* 0x0000000e1b0e7224 */
/* 0x002fe200078e0219 */
/*04c0*/ IADD3 R25, R13, 0x4, RZ ; /* 0x000000040d197810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ IMAD R14, R26, R15, R14 ; /* 0x0000000f1a0e7224 */
/* 0x000fe200078e020e */
/*04e0*/ ISETP.GE.U32.OR P3, PT, R25, c[0x0][0x164], P2 ; /* 0x0000590019007a0c */
/* 0x000fe40001766470 */
/*04f0*/ IADD3 R25, R4, 0x4, RZ ; /* 0x0000000404197810 */
/* 0x000fc80007ffe0ff */
/*0500*/ ISETP.GE.U32.OR P4, PT, R25, c[0x0][0x168], P0 ; /* 0x00005a0019007a0c */
/* 0x000fce0000786470 */
/*0510*/ @!P3 IADD3 R16, R12, -0x2, RZ ; /* 0xfffffffe0c10b810 */
/* 0x001fe40007ffe0ff */
/*0520*/ @!P3 MOV R17, 0x4 ; /* 0x000000040011b802 */
/* 0x000fc80000000f00 */
/*0530*/ @!P4 MOV R15, 0x4 ; /* 0x00000004000fc802 */
/* 0x000fe20000000f00 */
/*0540*/ @!P3 IMAD.WIDE.U32 R16, R16, R17, c[0x0][0x178] ; /* 0x00005e001010b625 */
/* 0x000fe200078e0011 */
/*0550*/ STS [R9+0x10], R28 ; /* 0x0000101c09007388 */
/* 0x0041e80000000800 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0570*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fca00078e00ff */
/*0580*/ LDS R29, [R5.X4+0x10] ; /* 0x00001000051d7984 */
/* 0x000fe80000004800 */
/*0590*/ LDS.64 R18, [R3.X8] ; /* 0x0000000003127984 */
/* 0x000e240000008a00 */
/*05a0*/ IMAD R25, R29, R18, R14 ; /* 0x000000121d197224 */
/* 0x001fe400078e020e */
/*05b0*/ LDS R18, [R5.X4+0x18] ; /* 0x0000180005127984 */
/* 0x000e280000004800 */
/*05c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*05d0*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc400078e00ff */
/*05e0*/ @!P4 IMAD.WIDE.U32 R14, R22, R15, c[0x0][0x180] ; /* 0x00006000160ec625 */
/* 0x000fc600078e000f */
/*05f0*/ @!P3 LDG.E R28, [R16.64] ; /* 0x00000004101cb981 */
/* 0x0002a8000c1e1900 */
/*0600*/ @!P4 LDG.E R29, [R14.64] ; /* 0x000000040e1dc981 */
/* 0x000ee2000c1e1900 */
/*0610*/ IADD3 R26, R13, 0x6, RZ ; /* 0x000000060d1a7810 */
/* 0x000fc80007ffe0ff */
/*0620*/ ISETP.GE.U32.OR P3, PT, R26, c[0x0][0x164], P2 ; /* 0x000059001a007a0c */
/* 0x000fe20001766470 */
/*0630*/ IMAD R25, R18, R19, R25 ; /* 0x0000001312197224 */
/* 0x001fe400078e0219 */
/*0640*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fd400078e00ff */
/*0650*/ @!P3 MOV R27, 0x4 ; /* 0x00000004001bb802 */
/* 0x000fca0000000f00 */
/*0660*/ @!P3 IMAD.WIDE.U32 R16, R12, R27, c[0x0][0x178] ; /* 0x00005e000c10b625 */
/* 0x002fe200078e001b */
/*0670*/ STS [R9], R28 ; /* 0x0000001c09007388 */
/* 0x0041e80000000800 */
/*0680*/ STS [R9+0x10], R29 ; /* 0x0000101d09007388 */
/* 0x008fe80000000800 */
/*0690*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06a0*/ LDS R27, [R5.X4+0x10] ; /* 0x00001000051b7984 */
/* 0x000fe80000004800 */
/*06b0*/ LDS R26, [R5.X4+0x18] ; /* 0x00001800051a7984 */
/* 0x000fe80000004800 */
/*06c0*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e680000008a00 */
/*06d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06e0*/ @!P3 LDG.E R18, [R16.64] ; /* 0x000000041012b981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R19, R4, 0x6, RZ ; /* 0x0000000604137810 */
/* 0x000fe20007ffe0ff */
/*0700*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x001fc600078e00ff */
/*0710*/ ISETP.GE.U32.OR P0, PT, R19, c[0x0][0x168], P0 ; /* 0x00005a0013007a0c */
/* 0x000fda0000706470 */
/*0720*/ @!P0 MOV R19, 0x4 ; /* 0x0000000400138802 */
/* 0x000fe20000000f00 */
/*0730*/ STS [R9], R18 ; /* 0x0000001209007388 */
/* 0x0041e80000000800 */
/*0740*/ @!P0 IMAD.WIDE.U32 R18, R21, R19, c[0x0][0x180] ; /* 0x0000600015128625 */
/* 0x001fca00078e0013 */
/*0750*/ @!P0 LDG.E R28, [R18.64] ; /* 0x00000004121c8981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD R14, R27, R14, R25 ; /* 0x0000000e1b0e7224 */
/* 0x002fe200078e0219 */
/*0770*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*0780*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD R26, R26, R15, R14 ; /* 0x0000000f1a1a7224 */
/* 0x000fe200078e020e */
/*07a0*/ IADD3 R14, R11, R24, RZ ; /* 0x000000180b0e7210 */
/* 0x000fe20007ffe0ff */
/*07b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f7424 */
/* 0x000fe200078e00ff */
/*07c0*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fe40007ffe0ff */
/*07d0*/ ISETP.NE.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f05270 */
/*07e0*/ IMAD R21, R15.reuse, c[0x0][0x16c], R21 ; /* 0x00005b000f157a24 */
/* 0x040fe200078e0215 */
/*07f0*/ IADD3 R12, R12, 0x8, RZ ; /* 0x000000080c0c7810 */
/* 0x000fe20007ffe0ff */
/*0800*/ IMAD R22, R15, c[0x0][0x16c], R22 ; /* 0x00005b000f167a24 */
/* 0x000fc400078e0216 */
/*0810*/ IMAD R23, R15.reuse, c[0x0][0x16c], R23 ; /* 0x00005b000f177a24 */
/* 0x040fe400078e0217 */
/*0820*/ IMAD R20, R15, c[0x0][0x16c], R20 ; /* 0x00005b000f147a24 */
/* 0x000fe200078e0214 */
/*0830*/ STS [R9+0x10], R28 ; /* 0x0000101c09007388 */
/* 0x004fe80000000800 */
/*0840*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0850*/ LDS R29, [R5.X4+0x10] ; /* 0x00001000051d7984 */
/* 0x000fe80000004800 */
/*0860*/ LDS.64 R16, [R3.X8] ; /* 0x0000000003107984 */
/* 0x000e280000008a00 */
/*0870*/ LDS R25, [R5.X4+0x18] ; /* 0x0000180005197984 */
/* 0x000e620000004800 */
/*0880*/ IMAD R16, R29, R16, R26 ; /* 0x000000101d107224 */
/* 0x001fc800078e021a */
/*0890*/ IMAD R25, R25, R17, R16 ; /* 0x0000001119197224 */
/* 0x002fe200078e0210 */
/*08a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08b0*/ @P0 BRA 0x2b0 ; /* 0xfffff9f000000947 */
/* 0x000fea000383ffff */
/*08c0*/ @!P1 BRA 0xb10 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*08d0*/ LEA R4, R24, R3, 0x1 ; /* 0x0000000318047211 */
/* 0x000fe200078e08ff */
/*08e0*/ IMAD R17, R6, c[0x0][0x164], R5 ; /* 0x0000590006117a24 */
/* 0x000fe400078e0205 */
/*08f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fc400078e0a08 */
/*0900*/ IMAD R11, R4, c[0x0][0x16c], R5.reuse ; /* 0x00005b00040b7a24 */
/* 0x100fe200078e0205 */
/*0910*/ LEA R17, R24.reuse, R17, 0x1 ; /* 0x0000001118117211 */
/* 0x040fe200078e08ff */
/*0920*/ IMAD R24, R24, 0x2, R5 ; /* 0x0000000218187824 */
/* 0x000fc600078e0205 */
/*0930*/ LEA R16, R2, R11, 0x1 ; /* 0x0000000b02107211 */
/* 0x000fe400078e08ff */
/*0940*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fe20003f26070 */
/*0950*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0960*/ ISETP.GE.U32.AND P0, PT, R24, c[0x0][0x164], PT ; /* 0x0000590018007a0c */
/* 0x000fe20003f06070 */
/*0970*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0980*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x16c], P1 ; /* 0x00005b0007007a0c */
/* 0x000fe40000f26670 */
/*0990*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x160], P0 ; /* 0x0000580006007a0c */
/* 0x000fd60000706670 */
/*09a0*/ @!P1 MOV R13, 0x4 ; /* 0x00000004000d9802 */
/* 0x000fe40000000f00 */
/*09b0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a8424 */
/* 0x000fc600078e00ff */
/*09c0*/ @!P1 IMAD.WIDE.U32 R12, R16, R13, c[0x0][0x180] ; /* 0x00006000100c9625 */
/* 0x000fc800078e000d */
/*09d0*/ @!P0 IMAD.WIDE.U32 R10, R17, R10, c[0x0][0x178] ; /* 0x00005e00110a8625 */
/* 0x000fe200078e000a */
/*09e0*/ @!P1 LDG.E R18, [R12.64] ; /* 0x000000040c129981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ @!P0 LDG.E R20, [R10.64] ; /* 0x000000040a148981 */
/* 0x000ee2000c1e1900 */
/*0a00*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0a10*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0a20*/ IMAD.MOV.U32 R23, RZ, RZ, 0x2 ; /* 0x00000002ff177424 */
/* 0x000fe200078e00ff */
/*0a30*/ IADD3 R4, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R24, R24, 0x2, RZ ; /* 0x0000000218187810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ IMAD R16, R23, c[0x0][0x16c], R16 ; /* 0x00005b0017107a24 */
/* 0x000fe200078e0210 */
/*0a60*/ IADD3 R17, R17, 0x2, RZ ; /* 0x0000000211117810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ STS [R9+0x10], R18 ; /* 0x0000101209007388 */
/* 0x004fe80000000800 */
/*0a80*/ STS [R9], R20 ; /* 0x0000001409007388 */
/* 0x008fe80000000800 */
/*0a90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0aa0*/ LDS R19, [R5.X4+0x10] ; /* 0x0000100005137984 */
/* 0x000fe80000004800 */
/*0ab0*/ LDS.64 R14, [R3.X8] ; /* 0x00000000030e7984 */
/* 0x000e280000008a00 */
/*0ac0*/ LDS R21, [R5.X4+0x18] ; /* 0x0000180005157984 */
/* 0x000e620000004800 */
/*0ad0*/ IMAD R14, R19, R14, R25 ; /* 0x0000000e130e7224 */
/* 0x001fc800078e0219 */
/*0ae0*/ IMAD R25, R21, R15, R14 ; /* 0x0000000f15197224 */
/* 0x002fe200078e020e */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ @P0 BRA 0x940 ; /* 0xfffffe3000000947 */
/* 0x000fea000383ffff */
/*0b10*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fc80003f06270 */
/*0b20*/ ISETP.GE.OR P0, PT, R6, c[0x0][0x170], P0 ; /* 0x00005c0006007a0c */
/* 0x000fda0000706670 */
/*0b30*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0b40*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x000fe200078e0203 */
/*0b50*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R5, R2, c[0x0][0x0], R5 ; /* 0x0000000002057a24 */
/* 0x000fc800078e0205 */
/*0b70*/ IMAD R0, R0, c[0x0][0x174], R5 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e0205 */
/*0b80*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fca00078e0003 */
/*0b90*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x000fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKerneliiiiiiPjS_S_
.globl _Z15MatrixMulKerneliiiiiiPjS_S_
.p2align 8
.type _Z15MatrixMulKerneliiiiiiPjS_S_,@function
_Z15MatrixMulKerneliiiiiiPjS_S_:
s_load_b32 s3, s[0:1], 0x4
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v7, s15, 1, v1
v_lshl_add_u32 v2, s14, 1, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_13
s_clause 0x2
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v10, 2, v0
v_lshlrev_b32_e32 v8, 3, v1
v_mov_b32_e32 v6, 0
v_mad_u64_u32 v[4:5], null, v7, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, 16, v10
s_add_i32 s11, s3, 1
v_add_nc_u32_e32 v10, v8, v10
s_lshr_b32 s11, s11, 1
s_mov_b32 s10, 0
v_add_nc_u32_e32 v11, v9, v8
s_max_i32 s11, s11, 1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s9, v2
s_xor_b32 s12, vcc_lo, -1
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s13, s10, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s13, v0
v_cmp_le_u32_e32 vcc_lo, s3, v5
s_or_b32 s16, s12, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s17, s16
s_xor_b32 s16, exec_lo, s17
s_cbranch_execz .LBB0_4
ds_store_b32 v10, v6
.LBB0_4:
s_and_not1_saveexec_b32 s16, s16
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v5, s13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[5:6]
v_add_co_u32 v12, vcc_lo, s4, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v5, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s8, v5
s_or_b32 s13, s2, vcc_lo
s_and_saveexec_b32 s16, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s16
s_cbranch_execz .LBB0_8
ds_store_b32 v11, v6
.LBB0_8:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v5, s9, v[2:3]
v_mov_b32_e32 v13, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_u32 v12, vcc_lo, s6, v12
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
global_load_b32 v5, v[12:13], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v5, v9
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s13, v8
s_add_i32 s13, s13, 4
ds_load_b32 v14, v5
ds_load_b32 v15, v12
v_add_nc_u32_e32 v5, 8, v5
s_cmp_lg_u32 s13, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[12:13], null, v14, v15, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v3, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v3, 0
.LBB0_14:
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v4, s3
v_add3_u32 v0, s14, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKerneliiiiiiPjS_S_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKerneliiiiiiPjS_S_, .Lfunc_end0-_Z15MatrixMulKerneliiiiiiPjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKerneliiiiiiPjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKerneliiiiiiPjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
cudaMalloc((void **) &ha, size);
float *hb;
cudaMalloc((void **) &hb, size);
cudaMemcpy(ha, a, size, cudaMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
cudaMemcpy(b, hb, size, cudaMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} | code for sm_80
Function : _Z17vectorMultiplyBy2PfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R2, R2 ; /* 0x0000000202077221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
cudaMalloc((void **) &ha, size);
float *hb;
cudaMalloc((void **) &hb, size);
cudaMemcpy(ha, a, size, cudaMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
cudaMemcpy(b, hb, size, cudaMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} | .file "tmpxft_0019ea13_00000000-6_vector_multiply_by_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
.type _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m, @function
_Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vectorMultiplyBy2PfS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m, .-_Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
.globl _Z17vectorMultiplyBy2PfS_m
.type _Z17vectorMultiplyBy2PfS_m, @function
_Z17vectorMultiplyBy2PfS_m:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17vectorMultiplyBy2PfS_m, .-_Z17vectorMultiplyBy2PfS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of blocks is %d\n"
.LC1:
.string "Arrays are equal.\n"
.LC2:
.string "Arrays are not equal.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1073741824, %rax
jne .L12
movl $0, %eax
movabsq $4294967296, %rdx
.L13:
movss (%rbx,%rax), %xmm0
addss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movq %rsp, %rdi
movabsq $4294967296, %r13
movq %r13, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $32768, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32768, 28(%rsp)
movl $32768, 32(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movabsq $4294967296, %rbx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L16:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1073741824, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
jmp .L14
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17vectorMultiplyBy2PfS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vectorMultiplyBy2PfS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
cudaMalloc((void **) &ha, size);
float *hb;
cudaMalloc((void **) &hb, size);
cudaMemcpy(ha, a, size, cudaMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
cudaMemcpy(b, hb, size, cudaMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
hipMalloc((void **) &ha, size);
float *hb;
hipMalloc((void **) &hb, size);
hipMemcpy(ha, a, size, hipMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
hipMemcpy(b, hb, size, hipMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
hipMalloc((void **) &ha, size);
float *hb;
hipMalloc((void **) &hb, size);
hipMemcpy(ha, a, size, hipMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
hipMemcpy(b, hb, size, hipMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17vectorMultiplyBy2PfS_m
.globl _Z17vectorMultiplyBy2PfS_m
.p2align 8
.type _Z17vectorMultiplyBy2PfS_m,@function
_Z17vectorMultiplyBy2PfS_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17vectorMultiplyBy2PfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17vectorMultiplyBy2PfS_m, .Lfunc_end0-_Z17vectorMultiplyBy2PfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17vectorMultiplyBy2PfS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17vectorMultiplyBy2PfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void vectorMultiplyBy2(float *v, float *w, size_t n)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
w[i] = v[i] * 2;
}
int main() {
size_t N = 1024 * 1024 * 1024;
size_t size = N * sizeof(float);
float *a = (float *) malloc(size);
float *b = (float *) malloc(size);
float *b_check = (float *) malloc(size);
for (int i = 0; i < N; i++) {
a[i] = i;
}
for (int i = 0; i < N; i++) {
b_check[i] = a[i] * 2;
}
float *ha;
hipMalloc((void **) &ha, size);
float *hb;
hipMalloc((void **) &hb, size);
hipMemcpy(ha, a, size, hipMemcpyHostToDevice);
int tInB = 1024;
dim3 threadsInBlock(tInB);
int numberOfBlocks = 32768;
printf("Number of blocks is %d\n", numberOfBlocks);
dim3 nBlocks(numberOfBlocks, 32768);
vectorMultiplyBy2<<<nBlocks, threadsInBlock>>>(ha, hb, N);
hipMemcpy(b, hb, size, hipMemcpyDeviceToHost);
int cmp = memcmp(b, b_check, size);
if (cmp == 0) {
printf("Arrays are equal.\n");
} else {
printf("Arrays are not equal.\n");
}
return 0;
} | .text
.file "vector_multiply_by_2.hip"
.globl _Z32__device_stub__vectorMultiplyBy2PfS_m # -- Begin function _Z32__device_stub__vectorMultiplyBy2PfS_m
.p2align 4, 0x90
.type _Z32__device_stub__vectorMultiplyBy2PfS_m,@function
_Z32__device_stub__vectorMultiplyBy2PfS_m: # @_Z32__device_stub__vectorMultiplyBy2PfS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vectorMultiplyBy2PfS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__vectorMultiplyBy2PfS_m, .Lfunc_end0-_Z32__device_stub__vectorMultiplyBy2PfS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967296, %rbx # imm = 0x100000000
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq $1073741824, %rax # imm = 0x40000000
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1073741824, %rax # imm = 0x40000000
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $32768, %esi # imm = 0x8000
xorl %eax, %eax
callq printf
leaq 1024(%rbx), %rdx
movabsq $140737488388096, %rdi # imm = 0x800000008000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1073741824, 72(%rsp) # imm = 0x40000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17vectorMultiplyBy2PfS_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq bcmp@PLT
testl %eax, %eax
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vectorMultiplyBy2PfS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17vectorMultiplyBy2PfS_m,@object # @_Z17vectorMultiplyBy2PfS_m
.section .rodata,"a",@progbits
.globl _Z17vectorMultiplyBy2PfS_m
.p2align 3, 0x0
_Z17vectorMultiplyBy2PfS_m:
.quad _Z32__device_stub__vectorMultiplyBy2PfS_m
.size _Z17vectorMultiplyBy2PfS_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of blocks is %d\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17vectorMultiplyBy2PfS_m"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Arrays are not equal."
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Arrays are equal."
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vectorMultiplyBy2PfS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vectorMultiplyBy2PfS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17vectorMultiplyBy2PfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ FADD R7, R2, R2 ; /* 0x0000000202077221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17vectorMultiplyBy2PfS_m
.globl _Z17vectorMultiplyBy2PfS_m
.p2align 8
.type _Z17vectorMultiplyBy2PfS_m,@function
_Z17vectorMultiplyBy2PfS_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17vectorMultiplyBy2PfS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17vectorMultiplyBy2PfS_m, .Lfunc_end0-_Z17vectorMultiplyBy2PfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17vectorMultiplyBy2PfS_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17vectorMultiplyBy2PfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019ea13_00000000-6_vector_multiply_by_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
.type _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m, @function
_Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17vectorMultiplyBy2PfS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m, .-_Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
.globl _Z17vectorMultiplyBy2PfS_m
.type _Z17vectorMultiplyBy2PfS_m, @function
_Z17vectorMultiplyBy2PfS_m:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17vectorMultiplyBy2PfS_m, .-_Z17vectorMultiplyBy2PfS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Number of blocks is %d\n"
.LC1:
.string "Arrays are equal.\n"
.LC2:
.string "Arrays are not equal.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movabsq $4294967296, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1073741824, %rax
jne .L12
movl $0, %eax
movabsq $4294967296, %rdx
.L13:
movss (%rbx,%rax), %xmm0
addss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movq %rsp, %rdi
movabsq $4294967296, %r13
movq %r13, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $32768, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32768, 28(%rsp)
movl $32768, 32(%rsp)
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl $2, %ecx
movabsq $4294967296, %rbx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L16:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $1073741824, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z40__device_stub__Z17vectorMultiplyBy2PfS_mPfS_m
jmp .L14
.L15:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z17vectorMultiplyBy2PfS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z17vectorMultiplyBy2PfS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_multiply_by_2.hip"
.globl _Z32__device_stub__vectorMultiplyBy2PfS_m # -- Begin function _Z32__device_stub__vectorMultiplyBy2PfS_m
.p2align 4, 0x90
.type _Z32__device_stub__vectorMultiplyBy2PfS_m,@function
_Z32__device_stub__vectorMultiplyBy2PfS_m: # @_Z32__device_stub__vectorMultiplyBy2PfS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17vectorMultiplyBy2PfS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z32__device_stub__vectorMultiplyBy2PfS_m, .Lfunc_end0-_Z32__device_stub__vectorMultiplyBy2PfS_m
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967296, %rbx # imm = 0x100000000
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %r14
movq %rbx, %rdi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
incq %rax
cmpq $1073741824, %rax # imm = 0x40000000
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss %xmm0, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $1073741824, %rax # imm = 0x40000000
jne .LBB1_3
# %bb.4:
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.L.str, %edi
movl $32768, %esi # imm = 0x8000
xorl %eax, %eax
callq printf
leaq 1024(%rbx), %rdx
movabsq $140737488388096, %rdi # imm = 0x800000008000
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1073741824, 72(%rsp) # imm = 0x40000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17vectorMultiplyBy2PfS_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq %r14, %rdi
movq %r15, %rsi
movq %rbx, %rdx
callq bcmp@PLT
testl %eax, %eax
movl $.Lstr.1, %eax
movl $.Lstr, %edi
cmoveq %rax, %rdi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17vectorMultiplyBy2PfS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17vectorMultiplyBy2PfS_m,@object # @_Z17vectorMultiplyBy2PfS_m
.section .rodata,"a",@progbits
.globl _Z17vectorMultiplyBy2PfS_m
.p2align 3, 0x0
_Z17vectorMultiplyBy2PfS_m:
.quad _Z32__device_stub__vectorMultiplyBy2PfS_m
.size _Z17vectorMultiplyBy2PfS_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of blocks is %d\n"
.size .L.str, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17vectorMultiplyBy2PfS_m"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Arrays are not equal."
.size .Lstr, 22
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Arrays are equal."
.size .Lstr.1, 18
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__vectorMultiplyBy2PfS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17vectorMultiplyBy2PfS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* ----------------------------------------------------------------------------
* This file was automatically generated by SWIG (http://www.swig.org).
* Version 4.0.0
*
* This file is not intended to be easily readable and contains a number of
* coding conventions designed to improve portability and efficiency. Do not make
* changes to this file unless you know what you are doing--modify the SWIG
* interface file instead.
* ----------------------------------------------------------------------------- */
#ifdef __cplusplus
/* SwigValueWrapper is described in swig.swg */
template<typename T> class SwigValueWrapper {
struct SwigMovePointer {
T *ptr;
SwigMovePointer(T *p) : ptr(p) { }
~SwigMovePointer() { delete ptr; }
SwigMovePointer& operator=(SwigMovePointer& rhs) { T* oldptr = ptr; ptr = 0; delete oldptr; ptr = rhs.ptr; rhs.ptr = 0; return *this; }
} pointer;
SwigValueWrapper& operator=(const SwigValueWrapper<T>& rhs);
SwigValueWrapper(const SwigValueWrapper<T>& rhs);
public:
SwigValueWrapper() : pointer(0) { }
SwigValueWrapper& operator=(const T& t) { SwigMovePointer tmp(new T(t)); pointer = tmp; return *this; }
operator T&() const { return *pointer.ptr; }
T *operator&() { return pointer.ptr; }
};
template <typename T> T SwigValueInit() {
return T();
}
#endif
/* -----------------------------------------------------------------------------
* This section contains generic SWIG labels for method/variable
* declarations/attributes, and other compiler dependent labels.
* ----------------------------------------------------------------------------- */
/* template workaround for compilers that cannot correctly implement the C++ standard */
#ifndef SWIGTEMPLATEDISAMBIGUATOR
# if defined(__SUNPRO_CC) && (__SUNPRO_CC <= 0x560)
# define SWIGTEMPLATEDISAMBIGUATOR template
# elif defined(__HP_aCC)
/* Needed even with `aCC -AA' when `aCC -V' reports HP ANSI C++ B3910B A.03.55 */
/* If we find a maximum version that requires this, the test would be __HP_aCC <= 35500 for A.03.55 */
# define SWIGTEMPLATEDISAMBIGUATOR template
# else
# define SWIGTEMPLATEDISAMBIGUATOR
# endif
#endif
/* inline attribute */
#ifndef SWIGINLINE
# if defined(__cplusplus) || (defined(__GNUC__) && !defined(__STRICT_ANSI__))
# define SWIGINLINE inline
# else
# define SWIGINLINE
# endif
#endif
/* attribute recognised by some compilers to avoid 'unused' warnings */
#ifndef SWIGUNUSED
# if defined(__GNUC__)
# if !(defined(__cplusplus)) || (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4))
# define SWIGUNUSED __attribute__ ((__unused__))
# else
# define SWIGUNUSED
# endif
# elif defined(__ICC)
# define SWIGUNUSED __attribute__ ((__unused__))
# else
# define SWIGUNUSED
# endif
#endif
#ifndef SWIG_MSC_UNSUPPRESS_4505
# if defined(_MSC_VER)
# pragma warning(disable : 4505) /* unreferenced local function has been removed */
# endif
#endif
#ifndef SWIGUNUSEDPARM
# ifdef __cplusplus
# define SWIGUNUSEDPARM(p)
# else
# define SWIGUNUSEDPARM(p) p SWIGUNUSED
# endif
#endif
/* internal SWIG method */
#ifndef SWIGINTERN
# define SWIGINTERN static SWIGUNUSED
#endif
/* internal inline SWIG method */
#ifndef SWIGINTERNINLINE
# define SWIGINTERNINLINE SWIGINTERN SWIGINLINE
#endif
/* qualifier for exported *const* global data variables*/
#ifndef SWIGEXTERN
# ifdef __cplusplus
# define SWIGEXTERN extern
# else
# define SWIGEXTERN
# endif
#endif
/* exporting methods */
#if defined(__GNUC__)
# if (__GNUC__ >= 4) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
# ifndef GCC_HASCLASSVISIBILITY
# define GCC_HASCLASSVISIBILITY
# endif
# endif
#endif
#ifndef SWIGEXPORT
# if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
# if defined(STATIC_LINKED)
# define SWIGEXPORT
# else
# define SWIGEXPORT __declspec(dllexport)
# endif
# else
# if defined(__GNUC__) && defined(GCC_HASCLASSVISIBILITY)
# define SWIGEXPORT __attribute__ ((visibility("default")))
# else
# define SWIGEXPORT
# endif
# endif
#endif
/* calling conventions for Windows */
#ifndef SWIGSTDCALL
# if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
# define SWIGSTDCALL __stdcall
# else
# define SWIGSTDCALL
# endif
#endif
/* Deal with Microsoft's attempt at deprecating C standard runtime functions */
#if !defined(SWIG_NO_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
# define _CRT_SECURE_NO_DEPRECATE
#endif
/* Deal with Microsoft's attempt at deprecating methods in the standard C++ library */
#if !defined(SWIG_NO_SCL_SECURE_NO_DEPRECATE) && defined(_MSC_VER) && !defined(_SCL_SECURE_NO_DEPRECATE)
# define _SCL_SECURE_NO_DEPRECATE
#endif
/* Deal with Apple's deprecated 'AssertMacros.h' from Carbon-framework */
#if defined(__APPLE__) && !defined(__ASSERT_MACROS_DEFINE_VERSIONS_WITHOUT_UNDERSCORES)
# define __ASSERT_MACROS_DEFINE_VERSIONS_WITHOUT_UNDERSCORES 0
#endif
/* Intel's compiler complains if a variable which was never initialised is
* cast to void, which is a common idiom which we use to indicate that we
* are aware a variable isn't used. So we just silence that warning.
* See: https://github.com/swig/swig/issues/192 for more discussion.
*/
#ifdef __INTEL_COMPILER
# pragma warning disable 592
#endif
/* Errors in SWIG */
#define SWIG_UnknownError -1
#define SWIG_IOError -2
#define SWIG_RuntimeError -3
#define SWIG_IndexError -4
#define SWIG_TypeError -5
#define SWIG_DivisionByZero -6
#define SWIG_OverflowError -7
#define SWIG_SyntaxError -8
#define SWIG_ValueError -9
#define SWIG_SystemError -10
#define SWIG_AttributeError -11
#define SWIG_MemoryError -12
#define SWIG_NullReferenceError -13
#define SWIG_exception_impl(DECL, CODE, MSG, RETURNNULL) \
{ throw std::logic_error("In " DECL ": " MSG); }
#include <stdexcept>
#define SWIGVERSION 0x040000
#define SWIG_VERSION SWIGVERSION
#define SWIG_as_voidptr(a) const_cast< void * >(static_cast< const void * >(a))
#define SWIG_as_voidptrptr(a) ((void)SWIG_as_voidptr(*a),reinterpret_cast< void** >(a))
#include <thrust/device_ptr.h>
#include <thrust/sort.h>
template<typename T>
void swig_thrust_sort(thrust::device_ptr<T> DATA, size_t SIZE) {
thrust::sort(DATA, DATA + SIZE);
}
#include <stdlib.h>
#ifdef _MSC_VER
# ifndef strtoull
# define strtoull _strtoui64
# endif
# ifndef strtoll
# define strtoll _strtoi64
# endif
#endif
struct SwigArrayWrapper {
void* data;
size_t size;
};
SWIGINTERN SwigArrayWrapper SwigArrayWrapper_uninitialized() {
SwigArrayWrapper result;
result.data = NULL;
result.size = 0;
return result;
}
#ifdef __cplusplus
extern "C" {
#endif
SWIGEXPORT void _wrap_sort(SwigArrayWrapper *farg1) {
thrust::device_ptr< float > arg1 ;
size_t arg2 ;
arg1 = thrust::device_ptr< float >(static_cast<float*>(farg1->data));
arg2 = farg1->size;
if (arg2 && !thrust::raw_pointer_cast(arg1)) {
SWIG_exception_impl("swig_thrust_sort< float >(thrust::device_ptr< float >,size_t)", SWIG_TypeError, \
"Array is not present on device", return ); \
}
swig_thrust_sort< float >(arg1,arg2);
}
#ifdef __cplusplus
}
#endif | /* ----------------------------------------------------------------------------
* This file was automatically generated by SWIG (http://www.swig.org).
* Version 4.0.0
*
* This file is not intended to be easily readable and contains a number of
* coding conventions designed to improve portability and efficiency. Do not make
* changes to this file unless you know what you are doing--modify the SWIG
* interface file instead.
* ----------------------------------------------------------------------------- */
#ifdef __cplusplus
/* SwigValueWrapper is described in swig.swg */
template<typename T> class SwigValueWrapper {
struct SwigMovePointer {
T *ptr;
SwigMovePointer(T *p) : ptr(p) { }
~SwigMovePointer() { delete ptr; }
SwigMovePointer& operator=(SwigMovePointer& rhs) { T* oldptr = ptr; ptr = 0; delete oldptr; ptr = rhs.ptr; rhs.ptr = 0; return *this; }
} pointer;
SwigValueWrapper& operator=(const SwigValueWrapper<T>& rhs);
SwigValueWrapper(const SwigValueWrapper<T>& rhs);
public:
SwigValueWrapper() : pointer(0) { }
SwigValueWrapper& operator=(const T& t) { SwigMovePointer tmp(new T(t)); pointer = tmp; return *this; }
operator T&() const { return *pointer.ptr; }
T *operator&() { return pointer.ptr; }
};
template <typename T> T SwigValueInit() {
return T();
}
#endif
/* -----------------------------------------------------------------------------
* This section contains generic SWIG labels for method/variable
* declarations/attributes, and other compiler dependent labels.
* ----------------------------------------------------------------------------- */
/* template workaround for compilers that cannot correctly implement the C++ standard */
#ifndef SWIGTEMPLATEDISAMBIGUATOR
# if defined(__SUNPRO_CC) && (__SUNPRO_CC <= 0x560)
# define SWIGTEMPLATEDISAMBIGUATOR template
# elif defined(__HP_aCC)
/* Needed even with `aCC -AA' when `aCC -V' reports HP ANSI C++ B3910B A.03.55 */
/* If we find a maximum version that requires this, the test would be __HP_aCC <= 35500 for A.03.55 */
# define SWIGTEMPLATEDISAMBIGUATOR template
# else
# define SWIGTEMPLATEDISAMBIGUATOR
# endif
#endif
/* inline attribute */
#ifndef SWIGINLINE
# if defined(__cplusplus) || (defined(__GNUC__) && !defined(__STRICT_ANSI__))
# define SWIGINLINE inline
# else
# define SWIGINLINE
# endif
#endif
/* attribute recognised by some compilers to avoid 'unused' warnings */
#ifndef SWIGUNUSED
# if defined(__GNUC__)
# if !(defined(__cplusplus)) || (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4))
# define SWIGUNUSED __attribute__ ((__unused__))
# else
# define SWIGUNUSED
# endif
# elif defined(__ICC)
# define SWIGUNUSED __attribute__ ((__unused__))
# else
# define SWIGUNUSED
# endif
#endif
#ifndef SWIG_MSC_UNSUPPRESS_4505
# if defined(_MSC_VER)
# pragma warning(disable : 4505) /* unreferenced local function has been removed */
# endif
#endif
#ifndef SWIGUNUSEDPARM
# ifdef __cplusplus
# define SWIGUNUSEDPARM(p)
# else
# define SWIGUNUSEDPARM(p) p SWIGUNUSED
# endif
#endif
/* internal SWIG method */
#ifndef SWIGINTERN
# define SWIGINTERN static SWIGUNUSED
#endif
/* internal inline SWIG method */
#ifndef SWIGINTERNINLINE
# define SWIGINTERNINLINE SWIGINTERN SWIGINLINE
#endif
/* qualifier for exported *const* global data variables*/
#ifndef SWIGEXTERN
# ifdef __cplusplus
# define SWIGEXTERN extern
# else
# define SWIGEXTERN
# endif
#endif
/* exporting methods */
#if defined(__GNUC__)
# if (__GNUC__ >= 4) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
# ifndef GCC_HASCLASSVISIBILITY
# define GCC_HASCLASSVISIBILITY
# endif
# endif
#endif
#ifndef SWIGEXPORT
# if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
# if defined(STATIC_LINKED)
# define SWIGEXPORT
# else
# define SWIGEXPORT __declspec(dllexport)
# endif
# else
# if defined(__GNUC__) && defined(GCC_HASCLASSVISIBILITY)
# define SWIGEXPORT __attribute__ ((visibility("default")))
# else
# define SWIGEXPORT
# endif
# endif
#endif
/* calling conventions for Windows */
#ifndef SWIGSTDCALL
# if defined(_WIN32) || defined(__WIN32__) || defined(__CYGWIN__)
# define SWIGSTDCALL __stdcall
# else
# define SWIGSTDCALL
# endif
#endif
/* Deal with Microsoft's attempt at deprecating C standard runtime functions */
#if !defined(SWIG_NO_CRT_SECURE_NO_DEPRECATE) && defined(_MSC_VER) && !defined(_CRT_SECURE_NO_DEPRECATE)
# define _CRT_SECURE_NO_DEPRECATE
#endif
/* Deal with Microsoft's attempt at deprecating methods in the standard C++ library */
#if !defined(SWIG_NO_SCL_SECURE_NO_DEPRECATE) && defined(_MSC_VER) && !defined(_SCL_SECURE_NO_DEPRECATE)
# define _SCL_SECURE_NO_DEPRECATE
#endif
/* Deal with Apple's deprecated 'AssertMacros.h' from Carbon-framework */
#if defined(__APPLE__) && !defined(__ASSERT_MACROS_DEFINE_VERSIONS_WITHOUT_UNDERSCORES)
# define __ASSERT_MACROS_DEFINE_VERSIONS_WITHOUT_UNDERSCORES 0
#endif
/* Intel's compiler complains if a variable which was never initialised is
* cast to void, which is a common idiom which we use to indicate that we
* are aware a variable isn't used. So we just silence that warning.
* See: https://github.com/swig/swig/issues/192 for more discussion.
*/
#ifdef __INTEL_COMPILER
# pragma warning disable 592
#endif
/* Errors in SWIG */
#define SWIG_UnknownError -1
#define SWIG_IOError -2
#define SWIG_RuntimeError -3
#define SWIG_IndexError -4
#define SWIG_TypeError -5
#define SWIG_DivisionByZero -6
#define SWIG_OverflowError -7
#define SWIG_SyntaxError -8
#define SWIG_ValueError -9
#define SWIG_SystemError -10
#define SWIG_AttributeError -11
#define SWIG_MemoryError -12
#define SWIG_NullReferenceError -13
#define SWIG_exception_impl(DECL, CODE, MSG, RETURNNULL) \
{ throw std::logic_error("In " DECL ": " MSG); }
#include <hip/hip_runtime.h>
#include <stdexcept>
#define SWIGVERSION 0x040000
#define SWIG_VERSION SWIGVERSION
#define SWIG_as_voidptr(a) const_cast< void * >(static_cast< const void * >(a))
#define SWIG_as_voidptrptr(a) ((void)SWIG_as_voidptr(*a),reinterpret_cast< void** >(a))
#include <thrust/device_ptr.h>
#include <thrust/sort.h>
template<typename T>
void swig_thrust_sort(thrust::device_ptr<T> DATA, size_t SIZE) {
thrust::sort(DATA, DATA + SIZE);
}
#include <stdlib.h>
#ifdef _MSC_VER
# ifndef strtoull
# define strtoull _strtoui64
# endif
# ifndef strtoll
# define strtoll _strtoi64
# endif
#endif
struct SwigArrayWrapper {
void* data;
size_t size;
};
SWIGINTERN SwigArrayWrapper SwigArrayWrapper_uninitialized() {
SwigArrayWrapper result;
result.data = NULL;
result.size = 0;
return result;
}
#ifdef __cplusplus
extern "C" {
#endif
SWIGEXPORT void _wrap_sort(SwigArrayWrapper *farg1) {
thrust::device_ptr< float > arg1 ;
size_t arg2 ;
arg1 = thrust::device_ptr< float >(static_cast<float*>(farg1->data));
arg2 = farg1->size;
if (arg2 && !thrust::raw_pointer_cast(arg1)) {
SWIG_exception_impl("swig_thrust_sort< float >(thrust::device_ptr< float >,size_t)", SWIG_TypeError, \
"Array is not present on device", return ); \
}
swig_thrust_sort< float >(arg1,arg2);
}
#ifdef __cplusplus
}
#endif |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
cudaGetLastError();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
cudaGetLastError();
return 0;
} | .file "tmpxft_000bbab2_00000000-6_matrixNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
cudaGetLastError();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
hipGetLastError();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
hipGetLastError();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
__global__ void cuda_hello(){
printf("Hello World from GPU!\n");
}
int main(){
cuda_hello<<<1,1>>>();
printf("Hello World from CPU!\n");
hipGetLastError();
return 0;
} | .text
.file "matrixNorm.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipGetLastError
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bbab2_00000000-6_matrixNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixNorm.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipGetLastError
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void variance2(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider){
double mean = reduce_sum[0] / sum_divider;
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = pow(g_idata[i] - mean, 2.0);
//sdata[tid] = g_idata[i] - mean;
//sdata[tid] *= sdata[tid];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
// HALVE THE NUMBER OF BLOCKS, AND REPLACE SINGLE LOAD
__global__ void variance3(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider){
/*
jeli zmniejszamy liczbê bloków o po³owê to tablica wynikowa te¿ powinna byæ krótsza po³owê
*/
double mean = reduce_sum[0] / sum_divider;
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// perform first level of reduction
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
sdata[tid] = pow(g_idata[i] - mean, 2.0) + pow(g_idata[i+blockDim.x] - mean, 2.0);
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
// poczekaj ...
// konsekwencj¹ tego, ¿e zmniejszamy liczbê bloków o po³owê jest to, ¿e mamy krótsz¹ o po³owê tablicê wynikow¹
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void norm_fro(double *g_idata, double *g_odata){
/*
function performs operation: sqrt(sum(diag(v'*v)))
*/
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
//sdata[tid] = pow(g_idata[i], 2.0);
sdata[tid] = g_idata[i]*g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void norm_fro2(double *g_idata1, double *g_idata2, double *g_odata){
/*
function performs operation: sqrt(sum(diag(v'*v))) for v = g_idata1 - g_idata2
*/
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = pow(g_idata1[i] - g_idata2[i], 2.0);
//sdata[tid] *= sdata[tid];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void max_value(double *g_idata, double *g_odata){
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] = sdata[tid]*(sdata[tid]>=sdata[tid+s]) + sdata[tid+s]*(sdata[tid]<sdata[tid+s]);
// a mo¿e w sdata[tid+s] zapisywaæ min ?? - do przemylenia
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void min_value(double *g_idata, double *g_odata){
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] = sdata[tid]*(sdata[tid]<=sdata[tid+s]) + sdata[tid+s]*(sdata[tid]>sdata[tid+s]);
// a mo¿e w sdata[tid+s] zapisywaæ min ?? - do przemylenia
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
} | .file "tmpxft_00065d53_00000000-6_reductionMixed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
.type _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d, @function
_Z33__device_stub__Z9variance2PdS_S_dPdS_S_d:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9variance2PdS_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d, .-_Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
.globl _Z9variance2PdS_S_d
.type _Z9variance2PdS_S_d, @function
_Z9variance2PdS_S_d:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9variance2PdS_S_d, .-_Z9variance2PdS_S_d
.globl _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
.type _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d, @function
_Z33__device_stub__Z9variance3PdS_S_dPdS_S_d:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9variance3PdS_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d, .-_Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
.globl _Z9variance3PdS_S_d
.type _Z9variance3PdS_S_d, @function
_Z9variance3PdS_S_d:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9variance3PdS_S_d, .-_Z9variance3PdS_S_d
.globl _Z29__device_stub__Z8norm_froPdS_PdS_
.type _Z29__device_stub__Z8norm_froPdS_PdS_, @function
_Z29__device_stub__Z8norm_froPdS_PdS_:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8norm_froPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z8norm_froPdS_PdS_, .-_Z29__device_stub__Z8norm_froPdS_PdS_
.globl _Z8norm_froPdS_
.type _Z8norm_froPdS_, @function
_Z8norm_froPdS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8norm_froPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z8norm_froPdS_, .-_Z8norm_froPdS_
.globl _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
.type _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_, @function
_Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9norm_fro2PdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_, .-_Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
.globl _Z9norm_fro2PdS_S_
.type _Z9norm_fro2PdS_S_, @function
_Z9norm_fro2PdS_S_:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9norm_fro2PdS_S_, .-_Z9norm_fro2PdS_S_
.globl _Z30__device_stub__Z9max_valuePdS_PdS_
.type _Z30__device_stub__Z9max_valuePdS_PdS_, @function
_Z30__device_stub__Z9max_valuePdS_PdS_:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9max_valuePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z30__device_stub__Z9max_valuePdS_PdS_, .-_Z30__device_stub__Z9max_valuePdS_PdS_
.globl _Z9max_valuePdS_
.type _Z9max_valuePdS_, @function
_Z9max_valuePdS_:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9max_valuePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9max_valuePdS_, .-_Z9max_valuePdS_
.globl _Z30__device_stub__Z9min_valuePdS_PdS_
.type _Z30__device_stub__Z9min_valuePdS_PdS_, @function
_Z30__device_stub__Z9min_valuePdS_PdS_:
.LFB2061:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9min_valuePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z30__device_stub__Z9min_valuePdS_PdS_, .-_Z30__device_stub__Z9min_valuePdS_PdS_
.globl _Z9min_valuePdS_
.type _Z9min_valuePdS_, @function
_Z9min_valuePdS_:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9min_valuePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9min_valuePdS_, .-_Z9min_valuePdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9min_valuePdS_"
.LC1:
.string "_Z9max_valuePdS_"
.LC2:
.string "_Z9norm_fro2PdS_S_"
.LC3:
.string "_Z8norm_froPdS_"
.LC4:
.string "_Z9variance3PdS_S_d"
.LC5:
.string "_Z9variance2PdS_S_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9min_valuePdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_valuePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9norm_fro2PdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8norm_froPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9variance3PdS_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9variance2PdS_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void variance2(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider){
double mean = reduce_sum[0] / sum_divider;
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = pow(g_idata[i] - mean, 2.0);
//sdata[tid] = g_idata[i] - mean;
//sdata[tid] *= sdata[tid];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
// HALVE THE NUMBER OF BLOCKS, AND REPLACE SINGLE LOAD
__global__ void variance3(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider){
/*
jeli zmniejszamy liczbê bloków o po³owê to tablica wynikowa te¿ powinna byæ krótsza po³owê
*/
double mean = reduce_sum[0] / sum_divider;
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// perform first level of reduction
// reading from global memory, writing to shared memory
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockDim.x*2) + threadIdx.x;
sdata[tid] = pow(g_idata[i] - mean, 2.0) + pow(g_idata[i+blockDim.x] - mean, 2.0);
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
// poczekaj ...
// konsekwencj¹ tego, ¿e zmniejszamy liczbê bloków o po³owê jest to, ¿e mamy krótsz¹ o po³owê tablicê wynikow¹
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void norm_fro(double *g_idata, double *g_odata){
/*
function performs operation: sqrt(sum(diag(v'*v)))
*/
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
//sdata[tid] = pow(g_idata[i], 2.0);
sdata[tid] = g_idata[i]*g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void norm_fro2(double *g_idata1, double *g_idata2, double *g_odata){
/*
function performs operation: sqrt(sum(diag(v'*v))) for v = g_idata1 - g_idata2
*/
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = pow(g_idata1[i] - g_idata2[i], 2.0);
//sdata[tid] *= sdata[tid];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] += sdata[tid+s];
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void max_value(double *g_idata, double *g_odata){
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] = sdata[tid]*(sdata[tid]>=sdata[tid+s]) + sdata[tid+s]*(sdata[tid]<sdata[tid+s]);
// a mo¿e w sdata[tid+s] zapisywaæ min ?? - do przemylenia
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
}
__global__ void min_value(double *g_idata, double *g_odata){
// Sequential addressing is conflict free
extern __shared__ double sdata[];
// each thread loads one element from global to shared mem
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
sdata[tid] = g_idata[i];
__syncthreads();
for (unsigned int s=blockDim.x/2; s>0; s>>=1){
if (tid < s){
sdata[tid] = sdata[tid]*(sdata[tid]<=sdata[tid+s]) + sdata[tid+s]*(sdata[tid]>sdata[tid+s]);
// a mo¿e w sdata[tid+s] zapisywaæ min ?? - do przemylenia
}
__syncthreads();
}
if (tid==0) g_odata[blockIdx.x] = sdata[0];
} | #include <hip/hip_runtime.h>
//#ifndef VARIANCE_CUDA_H
//#define VARIANCE_CUDA_H
__global__ void variance2(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider);
__global__ void norm_fro(double *g_idata, double *g_odata);
__global__ void norm_fro2(double *g_idata1, double *g_idata2, double *g_odata);
__global__ void min_value(double *g_idata, double *g_odata);
__global__ void max_value(double *g_idata, double *g_odata);
template <unsigned int blockSize> __global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider);
template <unsigned int blockSize>
__global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider){
double mean = reduce_sum[0] / sum_divider;
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) { sdata[tid] += pow(g_idata[i] - mean, 2.0) + pow(g_idata[i+blockSize] - mean, 2.0); i += gridSize; }
__syncthreads();
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
//#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#ifndef VARIANCE_CUDA_H
//#define VARIANCE_CUDA_H
__global__ void variance2(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider);
__global__ void norm_fro(double *g_idata, double *g_odata);
__global__ void norm_fro2(double *g_idata1, double *g_idata2, double *g_odata);
__global__ void min_value(double *g_idata, double *g_odata);
__global__ void max_value(double *g_idata, double *g_odata);
template <unsigned int blockSize> __global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider);
template <unsigned int blockSize>
__global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider){
double mean = reduce_sum[0] / sum_divider;
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) { sdata[tid] += pow(g_idata[i] - mean, 2.0) + pow(g_idata[i+blockSize] - mean, 2.0); i += gridSize; }
__syncthreads();
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
//#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#ifndef VARIANCE_CUDA_H
//#define VARIANCE_CUDA_H
__global__ void variance2(double *g_idata, double *g_odata, double* reduce_sum, double sum_divider);
__global__ void norm_fro(double *g_idata, double *g_odata);
__global__ void norm_fro2(double *g_idata1, double *g_idata2, double *g_odata);
__global__ void min_value(double *g_idata, double *g_odata);
__global__ void max_value(double *g_idata, double *g_odata);
template <unsigned int blockSize> __global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider);
template <unsigned int blockSize>
__global__ void variance6(double *g_idata, double* g_odata, unsigned int n, double* reduce_sum, double sum_divider){
double mean = reduce_sum[0] / sum_divider;
extern __shared__ double sdata[];
unsigned int tid = threadIdx.x;
unsigned int i = blockIdx.x*(blockSize*2) + tid;
unsigned int gridSize = blockSize*2*gridDim.x;
sdata[tid] = 0;
while (i < n) { sdata[tid] += pow(g_idata[i] - mean, 2.0) + pow(g_idata[i+blockSize] - mean, 2.0); i += gridSize; }
__syncthreads();
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) {
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
if (tid == 0) g_odata[blockIdx.x] = sdata[0];
}
//#endif | .text
.file "reductionMixed.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00065d53_00000000-6_reductionMixed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
.type _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d, @function
_Z33__device_stub__Z9variance2PdS_S_dPdS_S_d:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9variance2PdS_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d, .-_Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
.globl _Z9variance2PdS_S_d
.type _Z9variance2PdS_S_d, @function
_Z9variance2PdS_S_d:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9variance2PdS_S_dPdS_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9variance2PdS_S_d, .-_Z9variance2PdS_S_d
.globl _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
.type _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d, @function
_Z33__device_stub__Z9variance3PdS_S_dPdS_S_d:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9variance3PdS_S_d(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d, .-_Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
.globl _Z9variance3PdS_S_d
.type _Z9variance3PdS_S_d, @function
_Z9variance3PdS_S_d:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9variance3PdS_S_dPdS_S_d
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z9variance3PdS_S_d, .-_Z9variance3PdS_S_d
.globl _Z29__device_stub__Z8norm_froPdS_PdS_
.type _Z29__device_stub__Z8norm_froPdS_PdS_, @function
_Z29__device_stub__Z8norm_froPdS_PdS_:
.LFB2055:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8norm_froPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z8norm_froPdS_PdS_, .-_Z29__device_stub__Z8norm_froPdS_PdS_
.globl _Z8norm_froPdS_
.type _Z8norm_froPdS_, @function
_Z8norm_froPdS_:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8norm_froPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z8norm_froPdS_, .-_Z8norm_froPdS_
.globl _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
.type _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_, @function
_Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9norm_fro2PdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_, .-_Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
.globl _Z9norm_fro2PdS_S_
.type _Z9norm_fro2PdS_S_, @function
_Z9norm_fro2PdS_S_:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9norm_fro2PdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9norm_fro2PdS_S_, .-_Z9norm_fro2PdS_S_
.globl _Z30__device_stub__Z9max_valuePdS_PdS_
.type _Z30__device_stub__Z9max_valuePdS_PdS_, @function
_Z30__device_stub__Z9max_valuePdS_PdS_:
.LFB2059:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9max_valuePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z30__device_stub__Z9max_valuePdS_PdS_, .-_Z30__device_stub__Z9max_valuePdS_PdS_
.globl _Z9max_valuePdS_
.type _Z9max_valuePdS_, @function
_Z9max_valuePdS_:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9max_valuePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9max_valuePdS_, .-_Z9max_valuePdS_
.globl _Z30__device_stub__Z9min_valuePdS_PdS_
.type _Z30__device_stub__Z9min_valuePdS_PdS_, @function
_Z30__device_stub__Z9min_valuePdS_PdS_:
.LFB2061:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9min_valuePdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z30__device_stub__Z9min_valuePdS_PdS_, .-_Z30__device_stub__Z9min_valuePdS_PdS_
.globl _Z9min_valuePdS_
.type _Z9min_valuePdS_, @function
_Z9min_valuePdS_:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9min_valuePdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z9min_valuePdS_, .-_Z9min_valuePdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9min_valuePdS_"
.LC1:
.string "_Z9max_valuePdS_"
.LC2:
.string "_Z9norm_fro2PdS_S_"
.LC3:
.string "_Z8norm_froPdS_"
.LC4:
.string "_Z9variance3PdS_S_d"
.LC5:
.string "_Z9variance2PdS_S_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9min_valuePdS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9max_valuePdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9norm_fro2PdS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8norm_froPdS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9variance3PdS_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9variance2PdS_S_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reductionMixed.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} | code for sm_80
Function : _Z3fooPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, 0x2, RZ ; /* 0x0000000205057810 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} | .file "tmpxft_0015cd7c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1fi
.type _Z1fi, @function
_Z1fi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z1fi, .-_Z1fi
.globl _Z23__device_stub__Z3fooPiiPii
.type _Z23__device_stub__Z3fooPiiPii, @function
_Z23__device_stub__Z3fooPiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z3fooPiiPii, .-_Z23__device_stub__Z3fooPiiPii
.globl _Z3fooPii
.type _Z3fooPii, @function
_Z3fooPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z3fooPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3fooPii, .-_Z3fooPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPii
.globl _Z3fooPii
.p2align 8
.type _Z3fooPii,@function
_Z3fooPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s2, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPii, .Lfunc_end0-_Z3fooPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPii
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z3fooPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <assert.h>
#define N 2//64
__device__ int f(int x) {
return x + 2;
}
__global__ void foo(int *y, int x) {
*y = f(x);
} | .text
.file "main.hip"
.globl _Z18__device_stub__fooPii # -- Begin function _Z18__device_stub__fooPii
.p2align 4, 0x90
.type _Z18__device_stub__fooPii,@function
_Z18__device_stub__fooPii: # @_Z18__device_stub__fooPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3fooPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPii, .Lfunc_end0-_Z18__device_stub__fooPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPii,@object # @_Z3fooPii
.section .rodata,"a",@progbits
.globl _Z3fooPii
.p2align 3, 0x0
_Z3fooPii:
.quad _Z18__device_stub__fooPii
.size _Z3fooPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPii"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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