system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* dijkstras-test.cu
*
* Created on: Apr 20, 2015
* Author: luke
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <climits>
#include <stdint.h>
#include <ctime>
void CudaMallocErrorCheck(void** ptr, int size);
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e);
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex);
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source);
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src);
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e);
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e);
__global__ void Update(int *U, int *F, int *sigma, int delta, int size);
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma);
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma);
uint32_t NearestPowerTwo(uint32_t N);
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power);
// Generate V_a, E_a, Start_a, End_a, Weight_a
int main(int argc, char **argv) {
// Initialize graph
int V[] = {0, 1, 5, 7, 9};
int E[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int Sv[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4};
int Ev[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int We[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
// Initialize Unsettled, Frontier, Sigma function
int sigma[]= {0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; // -1 = inf
int F[] = {1, 0, 0, 0, 0};
int U[] = {0, 1, 1, 1, 1};
DijkstrasSetupCuda(V, E, We, sigma, F, U, 5, 12);
}
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e) {
int extrema_vertex;
Extremas(V, E, num_v, num_e, &extrema_vertex, 0);
}
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex) {
// Define Unsettled sigma and Frontier nodes
int *dev_U, *dev_sigma, *dev_F, *dev_V, *dev_E, *dev_src, *dev_dest;
int delta = 0;
float elapsedTime=0;
// Initialize reduce function mem
CudaMallocErrorCheck((void**)&dev_src, num_v*sizeof(int));
CudaMallocErrorCheck((void**)&dev_dest, num_v*sizeof(int));
Initialize(V, E, num_v, num_e, &dev_V, &dev_E, &dev_U, &dev_F, &dev_sigma, source_vertex);
// Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
// int test = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
// Update<<<1,5>>>(dev_U, dev_F, dev_sigma, test, num_v);
// printf("Test: %d\n", test);
//
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
while (delta != INT_MAX) {
Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
delta = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
Update<<<1, 5>>>(dev_U, dev_F, dev_sigma, delta, num_v);
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&elapsedTime, start, end);
printf("Elapsed Time: %f\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
int sigma[num_v];
// int V_t[num_v];
// int U_t[num_v];
cudaMemcpy(sigma, dev_sigma, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(V_t, dev_F, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(U_t, dev_U, num_v*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_v; ++i) {
printf("Sigma[%d] : %d\n", i, sigma[i]);
// printf("Frontier[%d] : %d\n", i, V_t[i]);
// printf("Unsettled[%d]: %d\n", i, U_t[i]);
}
}
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source) {
// Allocate the device memory
CudaMallocErrorCheck((void**)dev_V, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_E, num_e*sizeof(int));
CudaMallocErrorCheck((void**)dev_U, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_F, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_sigma, num_v*sizeof(int));
// copy graph to device
cudaMemcpy(*dev_V, V, num_v*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(*dev_E, E, num_e*sizeof(int), cudaMemcpyHostToDevice);
// initialize Frontier
// Initialize Unselttled
// Initialize Sigma distance function
int threads_per_block, blocks_per_dim;
blocks_per_dim = num_v / 1024 + 1;
threads_per_block = num_v / blocks_per_dim;
InitializeGPU<<<blocks_per_dim, threads_per_block>>>(*dev_V, *dev_E, *dev_U, *dev_F, *dev_sigma, source, num_e, num_v);
}
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
int U_t, F_t, sigma_t;
if (offset < size_v) {
U_t = 1;
F_t = 0;
sigma_t = INT_MAX - 1;
if (offset == src) {
U_t = 0;
F_t = 1;
sigma_t = 0;
}
U[offset] = U_t;
F[offset] = F_t;
sigma[offset] = sigma_t;
}
}
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < num_v) {
if (F[offset] == 1) {
for (int i = V[offset]; i < V[offset+1] && i < num_e; ++i) {
if (U[E[i]] == 1) {
atomicMin(&sigma[E[i]], sigma[offset] + 1);
}
}
}
}
}
__global__ void Update(int *U, int *F, int *sigma, int delta, int size) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < size){
F[offset] = 0;
if (U[offset] == 1 && sigma[offset] <= delta) {
U[offset] = 0;
F[offset] = 1;
}
}
}
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src) {
uint32_t blocks = (num_v+1) / 1024 + 1;
uint32_t threads = (num_v+1) / blocks / 2;
uint32_t loops;
uint32_t n_multiple = NearestPowerBase(num_v, threads * blocks * 2, loops);
uint32_t dev_dest_size = NearestPowerTwo(blocks*loops);
uint32_t share = NearestPowerTwo(threads);
// printf("Blocks: %d, Threads:%d\n", blocks, threads);
reduce_fix<<<blocks, threads, share*sizeof(int)>>>(V, dev_dest, n_multiple,
share, loops, U, sigma);
// Recall GPU function: Assumption Destination is power of 2. calculate block
// and threads for each call.
// GPU Call loop until Threshold
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
while (dev_dest_size > 1) {
int * temp = dev_dest;
dev_dest = dev_src;
dev_src = temp;
reduce<<<blocks, threads, threads*sizeof(int)>>>(dev_src, dev_dest,
dev_dest_size, U, sigma);
dev_dest_size = blocks;
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
}
int result;
cudaMemcpy(&result, dev_dest, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
void CudaMallocErrorCheck(void** ptr, int size) {
cudaError_t err = cudaMalloc(ptr, size);
if (err != cudaSuccess) {
printf("Error: %s", cudaGetErrorString(err));
exit(1);
}
}
uint32_t NearestPowerTwo(uint32_t N) {
uint32_t result = 1;
while (result < N) {
result <<= 1;
}
return result;
}
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power) {
uint32_t result = base;
power = 1;
while (result < N) {
result += base;
power++;
}
return result;
}
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
unsigned int block_id = blockIdx.x;
unsigned int block_dim = blockDim.x;
unsigned int offset = block_id*block_dim*2 + thread_id;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + block_dim < n && U[offset + block_dim] == 1)
result = min(result, g_idata[offset+block_dim]);
share_mem[thread_id] = result;
// Sync Threads in a single Block
__syncthreads();
// store result to shared memory
for (unsigned int s=block_dim/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) g_odata[block_id] = result;
}
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
for (int i = 0; i < loops; ++i) {
unsigned int offset = blockIdx.x*blockDim.x*2 + threadIdx.x + blockDim.x * 2 * gridDim.x * i;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + blockDim.x < n && U[offset + blockDim.x] == 1)
result = min(result, g_idata[offset+blockDim.x]);
share_mem[thread_id] = result;
// printf("Result: %d\n", result);
// Sync Threads in a single Block
int delta = s_size - blockDim.x;
if (thread_id + delta > blockDim.x-1) {
share_mem[thread_id+delta] = INT_MAX;
}
__syncthreads();
// store result to shared memory
for (unsigned int s=s_size/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) {
g_odata[blockIdx.x+ gridDim.x*i] = result;
}
}
} | .file "tmpxft_000e5628_00000000-6_dijkstra-test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %s"
.text
.globl _Z20CudaMallocErrorCheckPPvi
.type _Z20CudaMallocErrorCheckPPvi, @function
_Z20CudaMallocErrorCheckPPvi:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %esi, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L6
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z20CudaMallocErrorCheckPPvi, .-_Z20CudaMallocErrorCheckPPvi
.globl _Z15NearestPowerTwoj
.type _Z15NearestPowerTwoj, @function
_Z15NearestPowerTwoj:
.LFB2063:
.cfi_startproc
endbr64
cmpl $1, %edi
jbe .L10
movl $1, %eax
.L9:
addl %eax, %eax
cmpl %edi, %eax
jb .L9
ret
.L10:
movl $1, %eax
ret
.cfi_endproc
.LFE2063:
.size _Z15NearestPowerTwoj, .-_Z15NearestPowerTwoj
.globl _Z16NearestPowerBasejjRj
.type _Z16NearestPowerBasejjRj, @function
_Z16NearestPowerBasejjRj:
.LFB2064:
.cfi_startproc
endbr64
movl %esi, %eax
movl $2, %ecx
cmpl %edi, %esi
jnb .L18
.L13:
addl %esi, %eax
movl %ecx, %r8d
addl $1, %ecx
cmpl %edi, %eax
jb .L13
movl %r8d, (%rdx)
ret
.L18:
movl $1, (%rdx)
ret
.cfi_endproc
.LFE2064:
.size _Z16NearestPowerBasejjRj, .-_Z16NearestPowerBasejjRj
.globl _Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii
.type _Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii, @function
_Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii:
.LFB2089:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13InitializeGPUPiS_S_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii, .-_Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii
.globl _Z13InitializeGPUPiS_S_S_S_iii
.type _Z13InitializeGPUPiS_S_S_S_iii, @function
_Z13InitializeGPUPiS_S_S_S_iii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z13InitializeGPUPiS_S_S_S_iii, .-_Z13InitializeGPUPiS_S_S_S_iii
.globl _Z10InitializePiS_iiPS_S0_S0_S0_S0_i
.type _Z10InitializePiS_iiPS_S0_S0_S0_S0_i, @function
_Z10InitializePiS_iiPS_S0_S0_S0_S0_i:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, %ebx
movl %ecx, %ebp
movq %r8, %r12
movq %r9, %r13
movslq %edx, %r15
leal 0(,%rdx,4), %r14d
movl %r14d, %esi
movq %r8, %rdi
call _Z20CudaMallocErrorCheckPPvi
movslq %ebp, %rax
movq %rax, 8(%rsp)
leal 0(,%rbp,4), %esi
movq %r13, %rdi
call _Z20CudaMallocErrorCheckPPvi
movl %r14d, %esi
movq 128(%rsp), %rdi
call _Z20CudaMallocErrorCheckPPvi
movl %r14d, %esi
movq 136(%rsp), %rdi
call _Z20CudaMallocErrorCheckPPvi
movl %r14d, %esi
movq 144(%rsp), %rdi
call _Z20CudaMallocErrorCheckPPvi
leaq 0(,%r15,4), %rdx
movq (%r12), %rdi
movl $1, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rax
leaq 0(,%rax,4), %rdx
movq 0(%r13), %rdi
movl $1, %ecx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
leal 1023(%rbx), %ecx
testl %ebx, %ebx
cmovns %ebx, %ecx
sarl $10, %ecx
addl $1, %ecx
movl %ebx, %eax
cltd
idivl %ecx
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl %ecx, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L27:
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq 136(%rsp), %rax
movq (%rax), %rcx
movq 128(%rsp), %rax
movq (%rax), %rdx
movq 0(%r13), %rsi
movq (%r12), %rdi
pushq %rbx
.cfi_def_cfa_offset 136
pushq %rbp
.cfi_def_cfa_offset 144
movl 168(%rsp), %r9d
movq 160(%rsp), %rax
movq (%rax), %r8
call _Z44__device_stub__Z13InitializeGPUPiS_S_S_S_iiiPiS_S_S_S_iii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.cfi_endproc
.LFE2060:
.size _Z10InitializePiS_iiPS_S0_S0_S0_S0_i, .-_Z10InitializePiS_iiPS_S0_S0_S0_S0_i
.globl _Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii
.type _Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii, @function
_Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5RelaxPiS_S_S_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L31
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii, .-_Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii
.globl _Z5RelaxPiS_S_S_S_ii
.type _Z5RelaxPiS_S_S_S_ii, @function
_Z5RelaxPiS_S_S_S_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z5RelaxPiS_S_S_S_ii, .-_Z5RelaxPiS_S_S_S_ii
.globl _Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii
.type _Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii, @function
_Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L43
.L39:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L44
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6UpdatePiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L39
.L44:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii, .-_Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii
.globl _Z6UpdatePiS_S_ii
.type _Z6UpdatePiS_S_ii, @function
_Z6UpdatePiS_S_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z6UpdatePiS_S_ii, .-_Z6UpdatePiS_S_ii
.globl _Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_
.type _Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_, @function
_Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_:
.LFB2095:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L51
.L47:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6reducePiS_jS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L47
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_, .-_Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_
.globl _Z6reducePiS_jS_S_
.type _Z6reducePiS_jS_S_, @function
_Z6reducePiS_jS_S_:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z6reducePiS_jS_S_, .-_Z6reducePiS_jS_S_
.globl _Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_
.type _Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_, @function
_Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_:
.LFB2097:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L59
.L55:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L60
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10reduce_fixPiS_jjjS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L55
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2097:
.size _Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_, .-_Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_
.globl _Z10reduce_fixPiS_jjjS_S_
.type _Z10reduce_fixPiS_jjjS_S_, @function
_Z10reduce_fixPiS_jjjS_S_:
.LFB2098:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _Z10reduce_fixPiS_jjjS_S_, .-_Z10reduce_fixPiS_jjjS_S_
.globl _Z7MinimumPiS_S_S_iiS_S_
.type _Z7MinimumPiS_S_S_iiS_S_, @function
_Z7MinimumPiS_S_S_iiS_S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rdx, 24(%rsp)
movl %r8d, %edi
movq 144(%rsp), %r13
movq 152(%rsp), %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leal 1024(%r8), %r14d
movl %r8d, %eax
addl $1, %eax
cmovns %eax, %r14d
sarl $10, %r14d
addl $1, %r14d
movl $0, %edx
divl %r14d
movl %eax, %ebp
movl %eax, %r15d
shrl %r15d
leaq 44(%rsp), %rdx
movl %r14d, %esi
imull %r15d, %esi
addl %esi, %esi
call _Z16NearestPowerBasejjRj
movl %eax, 20(%rsp)
movl 44(%rsp), %eax
movl %eax, 16(%rsp)
imull %r14d, %eax
cmpl $1, %eax
jbe .L77
movl $1, %ebx
.L65:
addl %ebx, %ebx
cmpl %eax, %ebx
jb .L65
.L64:
cmpl $3, %ebp
jbe .L78
movl $1, %ebp
.L67:
addl %ebp, %ebp
cmpl %r15d, %ebp
jb .L67
.L66:
movl %r15d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r14d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %ebp, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L68:
cmpl $1024, %ebx
jbe .L69
movl %ebx, %ebp
shrl $10, %ebp
movl $512, %eax
.L70:
movl $512, %r14d
jmp .L75
.L77:
movl $1, %ebx
jmp .L64
.L78:
movl $1, %ebp
jmp .L66
.L83:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq 16(%rsp)
.cfi_def_cfa_offset 160
movq 16(%rsp), %r9
movl 32(%rsp), %r8d
movl %ebp, %ecx
movl 36(%rsp), %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call _Z39__device_stub__Z10reduce_fixPiS_jjjS_S_PiS_jjjS_S_
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L68
.L69:
movl %ebx, %eax
shrl %eax
cmpl $1, %ebx
jbe .L79
movl $1, %ebp
jmp .L70
.L84:
movq 8(%rsp), %r8
movq (%rsp), %rcx
movl %ebx, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z32__device_stub__Z6reducePiS_jS_S_PiS_jS_S_
jmp .L72
.L73:
movl %ebp, %eax
shrl %eax
cmpl $1, %ebp
jbe .L71
movl $1, %edx
.L74:
movl %ebp, %ebx
movl %edx, %ebp
movq %r13, %rdx
movq %r12, %r13
movq %rdx, %r12
.L75:
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %ebp, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl %eax, %eax
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L72:
cmpl $1024, %ebp
jbe .L73
movl %ebp, %edx
shrl $10, %edx
movl %r14d, %eax
jmp .L74
.L79:
movq %r13, %r12
.L71:
leaq 60(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq %r12, %rsi
call cudaMemcpy@PLT
movl 60(%rsp), %eax
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L85
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z7MinimumPiS_S_S_iiS_S_, .-_Z7MinimumPiS_S_S_iiS_S_
.section .rodata.str1.1
.LC2:
.string "Elapsed Time: %f\n"
.LC3:
.string "Sigma[%d] : %d\n"
.text
.globl _Z8ExtremasPiS_iiS_i
.type _Z8ExtremasPiS_iiS_i, @function
_Z8ExtremasPiS_iiS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rdi, -168(%rbp)
movq %rsi, -176(%rbp)
movl %edx, %ebx
movl %ecx, %r12d
movl %r9d, %r14d
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl $0x00000000, -156(%rbp)
movslq %edx, %r13
leal 0(,%rdx,4), %r15d
leaq -112(%rbp), %rdi
movl %r15d, %esi
call _Z20CudaMallocErrorCheckPPvi
leaq -104(%rbp), %rdi
movl %r15d, %esi
call _Z20CudaMallocErrorCheckPPvi
pushq %r14
leaq -144(%rbp), %rax
pushq %rax
leaq -136(%rbp), %rax
pushq %rax
leaq -152(%rbp), %rax
pushq %rax
leaq -120(%rbp), %r9
leaq -128(%rbp), %r8
movl %r12d, %ecx
movl %ebx, %edx
movq -176(%rbp), %rsi
movq -168(%rbp), %rdi
call _Z10InitializePiS_iiPS_S0_S0_S0_S0_i
addq $32, %rsp
leaq -96(%rbp), %rdi
call cudaEventCreate@PLT
leaq -88(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -96(%rbp), %rdi
call cudaEventRecord@PLT
jmp .L89
.L100:
subq $8, %rsp
pushq %r12
movl %ebx, %r9d
movq -120(%rbp), %r8
movq -128(%rbp), %rcx
movq -144(%rbp), %rdx
movq -136(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z34__device_stub__Z5RelaxPiS_S_S_S_iiPiS_S_S_S_ii
addq $16, %rsp
jmp .L87
.L88:
cmpl $2147483647, %r14d
je .L99
.L89:
movl $5, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L100
.L87:
pushq -112(%rbp)
pushq -104(%rbp)
movl %r12d, %r9d
movl %ebx, %r8d
movq -120(%rbp), %rcx
movq -128(%rbp), %rdx
movq -144(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z7MinimumPiS_S_S_iiS_S_
movl %eax, %r14d
movl $5, -68(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -80(%rbp)
movl $1, -76(%rbp)
movl $1, -72(%rbp)
addq $16, %rsp
movl $0, %r9d
movl $0, %r8d
movq -68(%rbp), %rdx
movl $1, %ecx
movq -80(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L88
movl %ebx, %r8d
movl %r14d, %ecx
movq -144(%rbp), %rdx
movq -136(%rbp), %rsi
movq -152(%rbp), %rdi
call _Z31__device_stub__Z6UpdatePiS_S_iiPiS_S_ii
jmp .L88
.L99:
movl $0, %esi
movq -88(%rbp), %rdi
call cudaEventRecord@PLT
movq -88(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -156(%rbp), %rdi
movq -88(%rbp), %rdx
movq -96(%rbp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd -156(%rbp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -96(%rbp), %rdi
call cudaEventDestroy@PLT
movq -88(%rbp), %rdi
call cudaEventDestroy@PLT
leaq 0(,%r13,4), %rdx
leaq 15(%rdx), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L90:
cmpq %rcx, %rsp
je .L91
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L90
.L91:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L92
orq $0, -8(%rsp,%rax)
.L92:
movq %rsp, %r12
movl $2, %ecx
movq -144(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %ebx, %ebx
jle .L86
movl $0, %ebx
leaq .LC3(%rip), %r14
.L94:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r13
jne .L94
.L86:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L101
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L101:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z8ExtremasPiS_iiS_i, .-_Z8ExtremasPiS_iiS_i
.globl _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii
.type _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii, @function
_Z18DijkstrasSetupCudaPiS_S_S_S_S_ii:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movl $0, %r9d
leaq 4(%rsp), %r8
movl 40(%rsp), %ecx
movl 32(%rsp), %edx
call _Z8ExtremasPiS_iiS_i
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L105
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L105:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii, .-_Z18DijkstrasSetupCudaPiS_S_S_S_S_ii
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, 16(%rsp)
movl $1, 20(%rsp)
movl $5, 24(%rsp)
movl $7, 28(%rsp)
movl $9, 32(%rsp)
movl $1, 48(%rsp)
movl $0, 52(%rsp)
movl $2, 56(%rsp)
movl $3, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $4, 72(%rsp)
movl $1, 76(%rsp)
movl $4, 80(%rsp)
movl $1, 84(%rsp)
movl $2, 88(%rsp)
movl $3, 92(%rsp)
leaq 48(%rsp), %rsi
leaq 16(%rsp), %rdi
movl $0, %r9d
leaq 12(%rsp), %r8
movl $12, %ecx
movl $5, %edx
call _Z8ExtremasPiS_iiS_i
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L109
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L109:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10reduce_fixPiS_jjjS_S_"
.LC5:
.string "_Z6reducePiS_jS_S_"
.LC6:
.string "_Z6UpdatePiS_S_ii"
.LC7:
.string "_Z5RelaxPiS_S_S_S_ii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "_Z13InitializeGPUPiS_S_S_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2100:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10reduce_fixPiS_jjjS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6reducePiS_jS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6UpdatePiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z5RelaxPiS_S_S_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13InitializeGPUPiS_S_S_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2100:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* dijkstras-test.cu
*
* Created on: Apr 20, 2015
* Author: luke
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <climits>
#include <stdint.h>
#include <ctime>
void CudaMallocErrorCheck(void** ptr, int size);
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e);
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex);
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source);
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src);
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e);
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e);
__global__ void Update(int *U, int *F, int *sigma, int delta, int size);
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma);
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma);
uint32_t NearestPowerTwo(uint32_t N);
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power);
// Generate V_a, E_a, Start_a, End_a, Weight_a
int main(int argc, char **argv) {
// Initialize graph
int V[] = {0, 1, 5, 7, 9};
int E[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int Sv[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4};
int Ev[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int We[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
// Initialize Unsettled, Frontier, Sigma function
int sigma[]= {0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; // -1 = inf
int F[] = {1, 0, 0, 0, 0};
int U[] = {0, 1, 1, 1, 1};
DijkstrasSetupCuda(V, E, We, sigma, F, U, 5, 12);
}
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e) {
int extrema_vertex;
Extremas(V, E, num_v, num_e, &extrema_vertex, 0);
}
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex) {
// Define Unsettled sigma and Frontier nodes
int *dev_U, *dev_sigma, *dev_F, *dev_V, *dev_E, *dev_src, *dev_dest;
int delta = 0;
float elapsedTime=0;
// Initialize reduce function mem
CudaMallocErrorCheck((void**)&dev_src, num_v*sizeof(int));
CudaMallocErrorCheck((void**)&dev_dest, num_v*sizeof(int));
Initialize(V, E, num_v, num_e, &dev_V, &dev_E, &dev_U, &dev_F, &dev_sigma, source_vertex);
// Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
// int test = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
// Update<<<1,5>>>(dev_U, dev_F, dev_sigma, test, num_v);
// printf("Test: %d\n", test);
//
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start, 0);
while (delta != INT_MAX) {
Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
delta = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
Update<<<1, 5>>>(dev_U, dev_F, dev_sigma, delta, num_v);
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&elapsedTime, start, end);
printf("Elapsed Time: %f\n", elapsedTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
int sigma[num_v];
// int V_t[num_v];
// int U_t[num_v];
cudaMemcpy(sigma, dev_sigma, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(V_t, dev_F, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(U_t, dev_U, num_v*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_v; ++i) {
printf("Sigma[%d] : %d\n", i, sigma[i]);
// printf("Frontier[%d] : %d\n", i, V_t[i]);
// printf("Unsettled[%d]: %d\n", i, U_t[i]);
}
}
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source) {
// Allocate the device memory
CudaMallocErrorCheck((void**)dev_V, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_E, num_e*sizeof(int));
CudaMallocErrorCheck((void**)dev_U, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_F, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_sigma, num_v*sizeof(int));
// copy graph to device
cudaMemcpy(*dev_V, V, num_v*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(*dev_E, E, num_e*sizeof(int), cudaMemcpyHostToDevice);
// initialize Frontier
// Initialize Unselttled
// Initialize Sigma distance function
int threads_per_block, blocks_per_dim;
blocks_per_dim = num_v / 1024 + 1;
threads_per_block = num_v / blocks_per_dim;
InitializeGPU<<<blocks_per_dim, threads_per_block>>>(*dev_V, *dev_E, *dev_U, *dev_F, *dev_sigma, source, num_e, num_v);
}
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
int U_t, F_t, sigma_t;
if (offset < size_v) {
U_t = 1;
F_t = 0;
sigma_t = INT_MAX - 1;
if (offset == src) {
U_t = 0;
F_t = 1;
sigma_t = 0;
}
U[offset] = U_t;
F[offset] = F_t;
sigma[offset] = sigma_t;
}
}
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < num_v) {
if (F[offset] == 1) {
for (int i = V[offset]; i < V[offset+1] && i < num_e; ++i) {
if (U[E[i]] == 1) {
atomicMin(&sigma[E[i]], sigma[offset] + 1);
}
}
}
}
}
__global__ void Update(int *U, int *F, int *sigma, int delta, int size) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < size){
F[offset] = 0;
if (U[offset] == 1 && sigma[offset] <= delta) {
U[offset] = 0;
F[offset] = 1;
}
}
}
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src) {
uint32_t blocks = (num_v+1) / 1024 + 1;
uint32_t threads = (num_v+1) / blocks / 2;
uint32_t loops;
uint32_t n_multiple = NearestPowerBase(num_v, threads * blocks * 2, loops);
uint32_t dev_dest_size = NearestPowerTwo(blocks*loops);
uint32_t share = NearestPowerTwo(threads);
// printf("Blocks: %d, Threads:%d\n", blocks, threads);
reduce_fix<<<blocks, threads, share*sizeof(int)>>>(V, dev_dest, n_multiple,
share, loops, U, sigma);
// Recall GPU function: Assumption Destination is power of 2. calculate block
// and threads for each call.
// GPU Call loop until Threshold
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
while (dev_dest_size > 1) {
int * temp = dev_dest;
dev_dest = dev_src;
dev_src = temp;
reduce<<<blocks, threads, threads*sizeof(int)>>>(dev_src, dev_dest,
dev_dest_size, U, sigma);
dev_dest_size = blocks;
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
}
int result;
cudaMemcpy(&result, dev_dest, sizeof(int), cudaMemcpyDeviceToHost);
return result;
}
void CudaMallocErrorCheck(void** ptr, int size) {
cudaError_t err = cudaMalloc(ptr, size);
if (err != cudaSuccess) {
printf("Error: %s", cudaGetErrorString(err));
exit(1);
}
}
uint32_t NearestPowerTwo(uint32_t N) {
uint32_t result = 1;
while (result < N) {
result <<= 1;
}
return result;
}
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power) {
uint32_t result = base;
power = 1;
while (result < N) {
result += base;
power++;
}
return result;
}
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
unsigned int block_id = blockIdx.x;
unsigned int block_dim = blockDim.x;
unsigned int offset = block_id*block_dim*2 + thread_id;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + block_dim < n && U[offset + block_dim] == 1)
result = min(result, g_idata[offset+block_dim]);
share_mem[thread_id] = result;
// Sync Threads in a single Block
__syncthreads();
// store result to shared memory
for (unsigned int s=block_dim/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) g_odata[block_id] = result;
}
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
for (int i = 0; i < loops; ++i) {
unsigned int offset = blockIdx.x*blockDim.x*2 + threadIdx.x + blockDim.x * 2 * gridDim.x * i;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + blockDim.x < n && U[offset + blockDim.x] == 1)
result = min(result, g_idata[offset+blockDim.x]);
share_mem[thread_id] = result;
// printf("Result: %d\n", result);
// Sync Threads in a single Block
int delta = s_size - blockDim.x;
if (thread_id + delta > blockDim.x-1) {
share_mem[thread_id+delta] = INT_MAX;
}
__syncthreads();
// store result to shared memory
for (unsigned int s=s_size/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) {
g_odata[blockIdx.x+ gridDim.x*i] = result;
}
}
} | /*
* dijkstras-test.cu
*
* Created on: Apr 20, 2015
* Author: luke
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <climits>
#include <stdint.h>
#include <ctime>
void CudaMallocErrorCheck(void** ptr, int size);
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e);
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex);
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source);
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src);
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e);
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e);
__global__ void Update(int *U, int *F, int *sigma, int delta, int size);
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma);
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma);
uint32_t NearestPowerTwo(uint32_t N);
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power);
// Generate V_a, E_a, Start_a, End_a, Weight_a
int main(int argc, char **argv) {
// Initialize graph
int V[] = {0, 1, 5, 7, 9};
int E[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int Sv[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4};
int Ev[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int We[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
// Initialize Unsettled, Frontier, Sigma function
int sigma[]= {0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; // -1 = inf
int F[] = {1, 0, 0, 0, 0};
int U[] = {0, 1, 1, 1, 1};
DijkstrasSetupCuda(V, E, We, sigma, F, U, 5, 12);
}
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e) {
int extrema_vertex;
Extremas(V, E, num_v, num_e, &extrema_vertex, 0);
}
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex) {
// Define Unsettled sigma and Frontier nodes
int *dev_U, *dev_sigma, *dev_F, *dev_V, *dev_E, *dev_src, *dev_dest;
int delta = 0;
float elapsedTime=0;
// Initialize reduce function mem
CudaMallocErrorCheck((void**)&dev_src, num_v*sizeof(int));
CudaMallocErrorCheck((void**)&dev_dest, num_v*sizeof(int));
Initialize(V, E, num_v, num_e, &dev_V, &dev_E, &dev_U, &dev_F, &dev_sigma, source_vertex);
// Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
// int test = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
// Update<<<1,5>>>(dev_U, dev_F, dev_sigma, test, num_v);
// printf("Test: %d\n", test);
//
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
while (delta != INT_MAX) {
Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
delta = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
Update<<<1, 5>>>(dev_U, dev_F, dev_sigma, delta, num_v);
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&elapsedTime, start, end);
printf("Elapsed Time: %f\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(end);
int sigma[num_v];
// int V_t[num_v];
// int U_t[num_v];
hipMemcpy(sigma, dev_sigma, num_v*sizeof(int), hipMemcpyDeviceToHost);
// cudaMemcpy(V_t, dev_F, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(U_t, dev_U, num_v*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_v; ++i) {
printf("Sigma[%d] : %d\n", i, sigma[i]);
// printf("Frontier[%d] : %d\n", i, V_t[i]);
// printf("Unsettled[%d]: %d\n", i, U_t[i]);
}
}
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source) {
// Allocate the device memory
CudaMallocErrorCheck((void**)dev_V, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_E, num_e*sizeof(int));
CudaMallocErrorCheck((void**)dev_U, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_F, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_sigma, num_v*sizeof(int));
// copy graph to device
hipMemcpy(*dev_V, V, num_v*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(*dev_E, E, num_e*sizeof(int), hipMemcpyHostToDevice);
// initialize Frontier
// Initialize Unselttled
// Initialize Sigma distance function
int threads_per_block, blocks_per_dim;
blocks_per_dim = num_v / 1024 + 1;
threads_per_block = num_v / blocks_per_dim;
InitializeGPU<<<blocks_per_dim, threads_per_block>>>(*dev_V, *dev_E, *dev_U, *dev_F, *dev_sigma, source, num_e, num_v);
}
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
int U_t, F_t, sigma_t;
if (offset < size_v) {
U_t = 1;
F_t = 0;
sigma_t = INT_MAX - 1;
if (offset == src) {
U_t = 0;
F_t = 1;
sigma_t = 0;
}
U[offset] = U_t;
F[offset] = F_t;
sigma[offset] = sigma_t;
}
}
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < num_v) {
if (F[offset] == 1) {
for (int i = V[offset]; i < V[offset+1] && i < num_e; ++i) {
if (U[E[i]] == 1) {
atomicMin(&sigma[E[i]], sigma[offset] + 1);
}
}
}
}
}
__global__ void Update(int *U, int *F, int *sigma, int delta, int size) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < size){
F[offset] = 0;
if (U[offset] == 1 && sigma[offset] <= delta) {
U[offset] = 0;
F[offset] = 1;
}
}
}
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src) {
uint32_t blocks = (num_v+1) / 1024 + 1;
uint32_t threads = (num_v+1) / blocks / 2;
uint32_t loops;
uint32_t n_multiple = NearestPowerBase(num_v, threads * blocks * 2, loops);
uint32_t dev_dest_size = NearestPowerTwo(blocks*loops);
uint32_t share = NearestPowerTwo(threads);
// printf("Blocks: %d, Threads:%d\n", blocks, threads);
reduce_fix<<<blocks, threads, share*sizeof(int)>>>(V, dev_dest, n_multiple,
share, loops, U, sigma);
// Recall GPU function: Assumption Destination is power of 2. calculate block
// and threads for each call.
// GPU Call loop until Threshold
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
while (dev_dest_size > 1) {
int * temp = dev_dest;
dev_dest = dev_src;
dev_src = temp;
reduce<<<blocks, threads, threads*sizeof(int)>>>(dev_src, dev_dest,
dev_dest_size, U, sigma);
dev_dest_size = blocks;
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
}
int result;
hipMemcpy(&result, dev_dest, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
void CudaMallocErrorCheck(void** ptr, int size) {
hipError_t err = hipMalloc(ptr, size);
if (err != hipSuccess) {
printf("Error: %s", hipGetErrorString(err));
exit(1);
}
}
uint32_t NearestPowerTwo(uint32_t N) {
uint32_t result = 1;
while (result < N) {
result <<= 1;
}
return result;
}
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power) {
uint32_t result = base;
power = 1;
while (result < N) {
result += base;
power++;
}
return result;
}
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
unsigned int block_id = blockIdx.x;
unsigned int block_dim = blockDim.x;
unsigned int offset = block_id*block_dim*2 + thread_id;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + block_dim < n && U[offset + block_dim] == 1)
result = min(result, g_idata[offset+block_dim]);
share_mem[thread_id] = result;
// Sync Threads in a single Block
__syncthreads();
// store result to shared memory
for (unsigned int s=block_dim/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) g_odata[block_id] = result;
}
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
for (int i = 0; i < loops; ++i) {
unsigned int offset = blockIdx.x*blockDim.x*2 + threadIdx.x + blockDim.x * 2 * gridDim.x * i;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + blockDim.x < n && U[offset + blockDim.x] == 1)
result = min(result, g_idata[offset+blockDim.x]);
share_mem[thread_id] = result;
// printf("Result: %d\n", result);
// Sync Threads in a single Block
int delta = s_size - blockDim.x;
if (thread_id + delta > blockDim.x-1) {
share_mem[thread_id+delta] = INT_MAX;
}
__syncthreads();
// store result to shared memory
for (unsigned int s=s_size/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) {
g_odata[blockIdx.x+ gridDim.x*i] = result;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* dijkstras-test.cu
*
* Created on: Apr 20, 2015
* Author: luke
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <climits>
#include <stdint.h>
#include <ctime>
void CudaMallocErrorCheck(void** ptr, int size);
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e);
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex);
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source);
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src);
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e);
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e);
__global__ void Update(int *U, int *F, int *sigma, int delta, int size);
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma);
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma);
uint32_t NearestPowerTwo(uint32_t N);
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power);
// Generate V_a, E_a, Start_a, End_a, Weight_a
int main(int argc, char **argv) {
// Initialize graph
int V[] = {0, 1, 5, 7, 9};
int E[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int Sv[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4};
int Ev[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int We[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
// Initialize Unsettled, Frontier, Sigma function
int sigma[]= {0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; // -1 = inf
int F[] = {1, 0, 0, 0, 0};
int U[] = {0, 1, 1, 1, 1};
DijkstrasSetupCuda(V, E, We, sigma, F, U, 5, 12);
}
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e) {
int extrema_vertex;
Extremas(V, E, num_v, num_e, &extrema_vertex, 0);
}
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex) {
// Define Unsettled sigma and Frontier nodes
int *dev_U, *dev_sigma, *dev_F, *dev_V, *dev_E, *dev_src, *dev_dest;
int delta = 0;
float elapsedTime=0;
// Initialize reduce function mem
CudaMallocErrorCheck((void**)&dev_src, num_v*sizeof(int));
CudaMallocErrorCheck((void**)&dev_dest, num_v*sizeof(int));
Initialize(V, E, num_v, num_e, &dev_V, &dev_E, &dev_U, &dev_F, &dev_sigma, source_vertex);
// Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
// int test = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
// Update<<<1,5>>>(dev_U, dev_F, dev_sigma, test, num_v);
// printf("Test: %d\n", test);
//
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
while (delta != INT_MAX) {
Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
delta = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
Update<<<1, 5>>>(dev_U, dev_F, dev_sigma, delta, num_v);
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&elapsedTime, start, end);
printf("Elapsed Time: %f\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(end);
int sigma[num_v];
// int V_t[num_v];
// int U_t[num_v];
hipMemcpy(sigma, dev_sigma, num_v*sizeof(int), hipMemcpyDeviceToHost);
// cudaMemcpy(V_t, dev_F, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(U_t, dev_U, num_v*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_v; ++i) {
printf("Sigma[%d] : %d\n", i, sigma[i]);
// printf("Frontier[%d] : %d\n", i, V_t[i]);
// printf("Unsettled[%d]: %d\n", i, U_t[i]);
}
}
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source) {
// Allocate the device memory
CudaMallocErrorCheck((void**)dev_V, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_E, num_e*sizeof(int));
CudaMallocErrorCheck((void**)dev_U, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_F, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_sigma, num_v*sizeof(int));
// copy graph to device
hipMemcpy(*dev_V, V, num_v*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(*dev_E, E, num_e*sizeof(int), hipMemcpyHostToDevice);
// initialize Frontier
// Initialize Unselttled
// Initialize Sigma distance function
int threads_per_block, blocks_per_dim;
blocks_per_dim = num_v / 1024 + 1;
threads_per_block = num_v / blocks_per_dim;
InitializeGPU<<<blocks_per_dim, threads_per_block>>>(*dev_V, *dev_E, *dev_U, *dev_F, *dev_sigma, source, num_e, num_v);
}
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
int U_t, F_t, sigma_t;
if (offset < size_v) {
U_t = 1;
F_t = 0;
sigma_t = INT_MAX - 1;
if (offset == src) {
U_t = 0;
F_t = 1;
sigma_t = 0;
}
U[offset] = U_t;
F[offset] = F_t;
sigma[offset] = sigma_t;
}
}
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < num_v) {
if (F[offset] == 1) {
for (int i = V[offset]; i < V[offset+1] && i < num_e; ++i) {
if (U[E[i]] == 1) {
atomicMin(&sigma[E[i]], sigma[offset] + 1);
}
}
}
}
}
__global__ void Update(int *U, int *F, int *sigma, int delta, int size) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < size){
F[offset] = 0;
if (U[offset] == 1 && sigma[offset] <= delta) {
U[offset] = 0;
F[offset] = 1;
}
}
}
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src) {
uint32_t blocks = (num_v+1) / 1024 + 1;
uint32_t threads = (num_v+1) / blocks / 2;
uint32_t loops;
uint32_t n_multiple = NearestPowerBase(num_v, threads * blocks * 2, loops);
uint32_t dev_dest_size = NearestPowerTwo(blocks*loops);
uint32_t share = NearestPowerTwo(threads);
// printf("Blocks: %d, Threads:%d\n", blocks, threads);
reduce_fix<<<blocks, threads, share*sizeof(int)>>>(V, dev_dest, n_multiple,
share, loops, U, sigma);
// Recall GPU function: Assumption Destination is power of 2. calculate block
// and threads for each call.
// GPU Call loop until Threshold
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
while (dev_dest_size > 1) {
int * temp = dev_dest;
dev_dest = dev_src;
dev_src = temp;
reduce<<<blocks, threads, threads*sizeof(int)>>>(dev_src, dev_dest,
dev_dest_size, U, sigma);
dev_dest_size = blocks;
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
}
int result;
hipMemcpy(&result, dev_dest, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
void CudaMallocErrorCheck(void** ptr, int size) {
hipError_t err = hipMalloc(ptr, size);
if (err != hipSuccess) {
printf("Error: %s", hipGetErrorString(err));
exit(1);
}
}
uint32_t NearestPowerTwo(uint32_t N) {
uint32_t result = 1;
while (result < N) {
result <<= 1;
}
return result;
}
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power) {
uint32_t result = base;
power = 1;
while (result < N) {
result += base;
power++;
}
return result;
}
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
unsigned int block_id = blockIdx.x;
unsigned int block_dim = blockDim.x;
unsigned int offset = block_id*block_dim*2 + thread_id;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + block_dim < n && U[offset + block_dim] == 1)
result = min(result, g_idata[offset+block_dim]);
share_mem[thread_id] = result;
// Sync Threads in a single Block
__syncthreads();
// store result to shared memory
for (unsigned int s=block_dim/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) g_odata[block_id] = result;
}
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
for (int i = 0; i < loops; ++i) {
unsigned int offset = blockIdx.x*blockDim.x*2 + threadIdx.x + blockDim.x * 2 * gridDim.x * i;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + blockDim.x < n && U[offset + blockDim.x] == 1)
result = min(result, g_idata[offset+blockDim.x]);
share_mem[thread_id] = result;
// printf("Result: %d\n", result);
// Sync Threads in a single Block
int delta = s_size - blockDim.x;
if (thread_id + delta > blockDim.x-1) {
share_mem[thread_id+delta] = INT_MAX;
}
__syncthreads();
// store result to shared memory
for (unsigned int s=s_size/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) {
g_odata[blockIdx.x+ gridDim.x*i] = result;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13InitializeGPUPiS_S_S_S_iii
.globl _Z13InitializeGPUPiS_S_S_S_iii
.p2align 8
.type _Z13InitializeGPUPiS_S_S_S_iii,@function
_Z13InitializeGPUPiS_S_S_S_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s3, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s8, s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x20
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e64 s0, s8, v1
v_cmp_ne_u32_e32 vcc_lo, s8, v1
v_cndmask_b32_e64 v7, 0, 1, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s4, v2
v_add_co_ci_u32_e64 v1, s0, s5, v3, s0
v_add_co_u32 v4, s0, s6, v2
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cndmask_b32_e64 v8, 0, 0x7ffffffe, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e64 v5, s0, s7, v3, s0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v6, off
global_store_b32 v[4:5], v7, off
global_store_b32 v[2:3], v8, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13InitializeGPUPiS_S_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13InitializeGPUPiS_S_S_S_iii, .Lfunc_end0-_Z13InitializeGPUPiS_S_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5RelaxPiS_S_S_S_ii
.globl _Z5RelaxPiS_S_S_S_ii
.p2align 8
.type _Z5RelaxPiS_S_S_S_ii,@function
_Z5RelaxPiS_S_S_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB1_7
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b64 v[4:5], v[0:1], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v5, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v5, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_nc_u32_e32 v8, 1, v4
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v6, v[0:1], off offset:4
v_add_co_u32 v4, s0, v4, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_waitcnt vmcnt(0)
v_min_i32_e32 v6, s6, v6
v_cmp_le_i32_e32 vcc_lo, v6, v8
v_add_nc_u32_e32 v8, 1, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB1_7
.LBB1_5:
global_load_b32 v6, v[4:5], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v9, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v7, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v9
s_cbranch_execz .LBB1_4
global_load_b32 v9, v[2:3], off
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v9, 1, v9
global_atomic_min_i32 v[6:7], v9, off
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5RelaxPiS_S_S_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5RelaxPiS_S_S_S_ii, .Lfunc_end1-_Z5RelaxPiS_S_S_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6UpdatePiS_S_ii
.globl _Z6UpdatePiS_S_ii
.p2align 8
.type _Z6UpdatePiS_S_ii,@function
_Z6UpdatePiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_4
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
global_store_b32 v[0:1], v6, off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s0, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 1
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6UpdatePiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6UpdatePiS_S_ii, .Lfunc_end2-_Z6UpdatePiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6reducePiS_jS_S_
.globl _Z6reducePiS_jS_S_
.p2align 8
.type _Z6reducePiS_jS_S_,@function
_Z6reducePiS_jS_S_:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
v_bfrev_b32_e32 v4, -2
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s9, s15, s3
v_lshl_add_u32 v1, s9, 1, v0
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB3_4
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v4
v_bfrev_b32_e32 v4, -2
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB3_3
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v4, v[2:3], off
.LBB3_3:
s_or_b32 exec_lo, exec_lo, s10
.LBB3_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v1, s3, v1
v_cmp_gt_u32_e32 vcc_lo, s8, v1
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB3_8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v5, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
s_mov_b32 s6, exec_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v3
s_cbranch_execz .LBB3_7
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v4, v4, v1
.LBB3_7:
s_or_b32 exec_lo, exec_lo, s6
.LBB3_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_13
.p2align 6
.LBB3_9:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB3_11
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v4, v4, v2
ds_store_b32 v1, v4
.LBB3_11:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB3_13
s_mov_b32 s3, s4
s_branch .LBB3_9
.LBB3_13:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB3_15
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v4, s[0:1]
.LBB3_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6reducePiS_jS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z6reducePiS_jS_S_, .Lfunc_end3-_Z6reducePiS_jS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10reduce_fixPiS_jjjS_S_
.globl _Z10reduce_fixPiS_jjjS_S_
.p2align 8
.type _Z10reduce_fixPiS_jjjS_S_,@function
_Z10reduce_fixPiS_jjjS_S_:
s_load_b32 s12, s[0:1], 0x18
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB4_20
s_clause 0x4
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x30
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v6, v0, 2, 0
v_cmp_eq_u32_e64 s0, 0, v0
v_bfrev_b32_e32 v7, -2
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_sub_i32 s1, s9, s14
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v1, s1, v0
s_add_i32 s1, s14, -1
s_lshl_b32 s16, s14, 1
s_cmp_gt_u32 s9, 1
s_cselect_b32 s17, -1, 0
v_cmp_lt_u32_e64 s1, s1, v1
v_lshl_add_u32 v8, v1, 2, 0
s_branch .LBB4_3
.LBB4_2:
s_or_b32 exec_lo, exec_lo, s19
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s12
s_cbranch_scc1 .LBB4_20
.LBB4_3:
s_mul_i32 s2, s13, s18
v_bfrev_b32_e32 v9, -2
s_add_i32 s2, s2, s15
s_mov_b32 s19, exec_lo
v_mad_u64_u32 v[3:4], null, s16, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v3
s_cbranch_execz .LBB4_7
v_mov_b32_e32 v4, v2
s_mov_b32 s20, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v9, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v5, vcc_lo
global_load_b32 v1, v[9:10], off
v_bfrev_b32_e32 v9, -2
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v1
s_cbranch_execz .LBB4_6
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
global_load_b32 v9, v[4:5], off
.LBB4_6:
s_or_b32 exec_lo, exec_lo, s20
.LBB4_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v1, s14, v3
s_mov_b32 s19, exec_lo
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB4_11
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s20, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v4, vcc_lo
global_load_b32 v1, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e32 1, v1
s_cbranch_execz .LBB4_10
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_min_i32_e32 v9, v9, v1
.LBB4_10:
s_or_b32 exec_lo, exec_lo, s20
.LBB4_11:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s19
s_waitcnt vmcnt(0)
ds_store_b32 v6, v9
s_and_saveexec_b32 s19, s1
s_cbranch_execz .LBB4_13
ds_store_b32 v8, v7
.LBB4_13:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s17
s_mov_b32 s19, s9
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB4_18
.p2align 6
.LBB4_14:
s_lshr_b32 s20, s19, 1
s_mov_b32 s21, exec_lo
v_cmpx_gt_u32_e64 s20, v0
s_cbranch_execz .LBB4_16
v_add_nc_u32_e32 v1, s20, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v9, v9, v1
ds_store_b32 v6, v9
.LBB4_16:
s_or_b32 exec_lo, exec_lo, s21
s_cmp_lt_u32 s19, 4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB4_18
s_mov_b32 s19, s20
s_branch .LBB4_14
.LBB4_18:
s_and_saveexec_b32 s19, s0
s_cbranch_execz .LBB4_2
s_lshl_b64 s[20:21], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s6, s20
s_addc_u32 s21, s7, s21
global_store_b32 v2, v9, s[20:21]
s_branch .LBB4_2
.LBB4_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10reduce_fixPiS_jjjS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z10reduce_fixPiS_jjjS_S_, .Lfunc_end4-_Z10reduce_fixPiS_jjjS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13InitializeGPUPiS_S_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13InitializeGPUPiS_S_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5RelaxPiS_S_S_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5RelaxPiS_S_S_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
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.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
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.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6UpdatePiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6UpdatePiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
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.size: 8
.value_kind: global_buffer
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.size: 2
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.value_kind: hidden_global_offset_y
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.size: 8
.value_kind: hidden_global_offset_z
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.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6reducePiS_jS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6reducePiS_jS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
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.size: 4
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.size: 4
.value_kind: hidden_block_count_y
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.size: 4
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.size: 2
.value_kind: hidden_group_size_x
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.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
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.size: 2
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.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10reduce_fixPiS_jjjS_S_
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z10reduce_fixPiS_jjjS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* dijkstras-test.cu
*
* Created on: Apr 20, 2015
* Author: luke
*/
#include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <climits>
#include <stdint.h>
#include <ctime>
void CudaMallocErrorCheck(void** ptr, int size);
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e);
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex);
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source);
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src);
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e);
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e);
__global__ void Update(int *U, int *F, int *sigma, int delta, int size);
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma);
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma);
uint32_t NearestPowerTwo(uint32_t N);
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power);
// Generate V_a, E_a, Start_a, End_a, Weight_a
int main(int argc, char **argv) {
// Initialize graph
int V[] = {0, 1, 5, 7, 9};
int E[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int Sv[] = {0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 4};
int Ev[] = {1, 0, 2, 3, 4, 1, 4, 1, 4, 1, 2, 3};
int We[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
// Initialize Unsettled, Frontier, Sigma function
int sigma[]= {0,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1}; // -1 = inf
int F[] = {1, 0, 0, 0, 0};
int U[] = {0, 1, 1, 1, 1};
DijkstrasSetupCuda(V, E, We, sigma, F, U, 5, 12);
}
void DijkstrasSetupCuda(int *V, int *E, int *We, int *sigma, int *F, int *U, int num_v, int num_e) {
int extrema_vertex;
Extremas(V, E, num_v, num_e, &extrema_vertex, 0);
}
void Extremas(int *V, int *E, int num_v, int num_e, int *extrema_vertex, int source_vertex) {
// Define Unsettled sigma and Frontier nodes
int *dev_U, *dev_sigma, *dev_F, *dev_V, *dev_E, *dev_src, *dev_dest;
int delta = 0;
float elapsedTime=0;
// Initialize reduce function mem
CudaMallocErrorCheck((void**)&dev_src, num_v*sizeof(int));
CudaMallocErrorCheck((void**)&dev_dest, num_v*sizeof(int));
Initialize(V, E, num_v, num_e, &dev_V, &dev_E, &dev_U, &dev_F, &dev_sigma, source_vertex);
// Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
// int test = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
// Update<<<1,5>>>(dev_U, dev_F, dev_sigma, test, num_v);
// printf("Test: %d\n", test);
//
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start, 0);
while (delta != INT_MAX) {
Relax<<<1, 5>>>(dev_U, dev_F, dev_sigma, dev_V, dev_E, num_v, num_e);
delta = Minimum(dev_U, dev_sigma, dev_V, dev_E, num_v, num_e, dev_dest, dev_src);
Update<<<1, 5>>>(dev_U, dev_F, dev_sigma, delta, num_v);
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&elapsedTime, start, end);
printf("Elapsed Time: %f\n", elapsedTime);
hipEventDestroy(start);
hipEventDestroy(end);
int sigma[num_v];
// int V_t[num_v];
// int U_t[num_v];
hipMemcpy(sigma, dev_sigma, num_v*sizeof(int), hipMemcpyDeviceToHost);
// cudaMemcpy(V_t, dev_F, num_v*sizeof(int), cudaMemcpyDeviceToHost);
// cudaMemcpy(U_t, dev_U, num_v*sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < num_v; ++i) {
printf("Sigma[%d] : %d\n", i, sigma[i]);
// printf("Frontier[%d] : %d\n", i, V_t[i]);
// printf("Unsettled[%d]: %d\n", i, U_t[i]);
}
}
void Initialize(int *V, int *E, int num_v, int num_e, int **dev_V, int **dev_E, int **dev_U, int **dev_F, int **dev_sigma, int source) {
// Allocate the device memory
CudaMallocErrorCheck((void**)dev_V, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_E, num_e*sizeof(int));
CudaMallocErrorCheck((void**)dev_U, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_F, num_v*sizeof(int));
CudaMallocErrorCheck((void**)dev_sigma, num_v*sizeof(int));
// copy graph to device
hipMemcpy(*dev_V, V, num_v*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(*dev_E, E, num_e*sizeof(int), hipMemcpyHostToDevice);
// initialize Frontier
// Initialize Unselttled
// Initialize Sigma distance function
int threads_per_block, blocks_per_dim;
blocks_per_dim = num_v / 1024 + 1;
threads_per_block = num_v / blocks_per_dim;
InitializeGPU<<<blocks_per_dim, threads_per_block>>>(*dev_V, *dev_E, *dev_U, *dev_F, *dev_sigma, source, num_e, num_v);
}
__global__ void InitializeGPU(int *V, int *E, int *U, int *F, int *sigma, int src, int size_v, int size_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
int U_t, F_t, sigma_t;
if (offset < size_v) {
U_t = 1;
F_t = 0;
sigma_t = INT_MAX - 1;
if (offset == src) {
U_t = 0;
F_t = 1;
sigma_t = 0;
}
U[offset] = U_t;
F[offset] = F_t;
sigma[offset] = sigma_t;
}
}
__global__ void Relax(int *U, int *F, int *sigma, int *V, int *E, int num_v, int num_e) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < num_v) {
if (F[offset] == 1) {
for (int i = V[offset]; i < V[offset+1] && i < num_e; ++i) {
if (U[E[i]] == 1) {
atomicMin(&sigma[E[i]], sigma[offset] + 1);
}
}
}
}
}
__global__ void Update(int *U, int *F, int *sigma, int delta, int size) {
int offset = blockDim.x * blockIdx.x + threadIdx.x;
if (offset < size){
F[offset] = 0;
if (U[offset] == 1 && sigma[offset] <= delta) {
U[offset] = 0;
F[offset] = 1;
}
}
}
int Minimum(int *U, int *sigma, int *V, int *E, int num_v, int num_e, int *dev_dest, int *dev_src) {
uint32_t blocks = (num_v+1) / 1024 + 1;
uint32_t threads = (num_v+1) / blocks / 2;
uint32_t loops;
uint32_t n_multiple = NearestPowerBase(num_v, threads * blocks * 2, loops);
uint32_t dev_dest_size = NearestPowerTwo(blocks*loops);
uint32_t share = NearestPowerTwo(threads);
// printf("Blocks: %d, Threads:%d\n", blocks, threads);
reduce_fix<<<blocks, threads, share*sizeof(int)>>>(V, dev_dest, n_multiple,
share, loops, U, sigma);
// Recall GPU function: Assumption Destination is power of 2. calculate block
// and threads for each call.
// GPU Call loop until Threshold
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
while (dev_dest_size > 1) {
int * temp = dev_dest;
dev_dest = dev_src;
dev_src = temp;
reduce<<<blocks, threads, threads*sizeof(int)>>>(dev_src, dev_dest,
dev_dest_size, U, sigma);
dev_dest_size = blocks;
if (dev_dest_size > 1024) {
threads = 512;
blocks = dev_dest_size / threads / 2;
} else {
threads = dev_dest_size / 2;
blocks = 1;
}
}
int result;
hipMemcpy(&result, dev_dest, sizeof(int), hipMemcpyDeviceToHost);
return result;
}
void CudaMallocErrorCheck(void** ptr, int size) {
hipError_t err = hipMalloc(ptr, size);
if (err != hipSuccess) {
printf("Error: %s", hipGetErrorString(err));
exit(1);
}
}
uint32_t NearestPowerTwo(uint32_t N) {
uint32_t result = 1;
while (result < N) {
result <<= 1;
}
return result;
}
uint32_t NearestPowerBase(uint32_t N, uint32_t base, uint32_t &power) {
uint32_t result = base;
power = 1;
while (result < N) {
result += base;
power++;
}
return result;
}
__global__ void reduce(int *g_idata, int *g_odata, unsigned int n, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
unsigned int block_id = blockIdx.x;
unsigned int block_dim = blockDim.x;
unsigned int offset = block_id*block_dim*2 + thread_id;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + block_dim < n && U[offset + block_dim] == 1)
result = min(result, g_idata[offset+block_dim]);
share_mem[thread_id] = result;
// Sync Threads in a single Block
__syncthreads();
// store result to shared memory
for (unsigned int s=block_dim/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) g_odata[block_id] = result;
}
__global__ void reduce_fix(int *g_idata, int *g_odata, unsigned int n, unsigned int s_size, unsigned int loops, int *U, int *sigma) {
// Pointer to shared memory
extern __shared__ int share_mem[];
unsigned int thread_id = threadIdx.x;
for (int i = 0; i < loops; ++i) {
unsigned int offset = blockIdx.x*blockDim.x*2 + threadIdx.x + blockDim.x * 2 * gridDim.x * i;
// Temp result float
int result = (offset < n && U[offset] == 1) ? g_idata[offset] : INT_MAX;
// Perform summation
if (offset + blockDim.x < n && U[offset + blockDim.x] == 1)
result = min(result, g_idata[offset+blockDim.x]);
share_mem[thread_id] = result;
// printf("Result: %d\n", result);
// Sync Threads in a single Block
int delta = s_size - blockDim.x;
if (thread_id + delta > blockDim.x-1) {
share_mem[thread_id+delta] = INT_MAX;
}
__syncthreads();
// store result to shared memory
for (unsigned int s=s_size/2; s>0; s>>=1) {
if (thread_id < s) {
share_mem[thread_id] = result = min(result, share_mem[thread_id + s]);
}
__syncthreads();
}
// Store result to output data pointer
if (thread_id == 0) {
g_odata[blockIdx.x+ gridDim.x*i] = result;
}
}
} | .text
.file "dijkstra-test.hip"
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI0_0:
.long 0 # 0x0
.long 1 # 0x1
.long 5 # 0x5
.long 7 # 0x7
.LCPI0_1:
.long 1 # 0x1
.long 0 # 0x0
.long 2 # 0x2
.long 3 # 0x3
.LCPI0_2:
.long 4 # 0x4
.long 1 # 0x1
.long 4 # 0x4
.long 1 # 0x1
.LCPI0_3:
.long 4 # 0x4
.long 1 # 0x1
.long 2 # 0x2
.long 3 # 0x3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movaps .LCPI0_0(%rip), %xmm0 # xmm0 = [0,1,5,7]
movaps %xmm0, (%rsp)
movl $9, 16(%rsp)
movaps .LCPI0_1(%rip), %xmm0 # xmm0 = [1,0,2,3]
movaps %xmm0, 32(%rsp)
movaps .LCPI0_2(%rip), %xmm0 # xmm0 = [4,1,4,1]
movaps %xmm0, 48(%rsp)
movaps .LCPI0_3(%rip), %xmm0 # xmm0 = [4,1,2,3]
movaps %xmm0, 64(%rsp)
movq %rsp, %rdi
leaq 32(%rsp), %rsi
movl $5, %edx
movl $12, %ecx
xorl %r9d, %r9d
callq _Z8ExtremasPiS_iiS_i
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii # -- Begin function _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii
.p2align 4, 0x90
.type _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii,@function
_Z18DijkstrasSetupCudaPiS_S_S_S_S_ii: # @_Z18DijkstrasSetupCudaPiS_S_S_S_S_ii
.cfi_startproc
# %bb.0:
movl 8(%rsp), %edx
movl 16(%rsp), %ecx
xorl %r9d, %r9d
jmp _Z8ExtremasPiS_iiS_i # TAILCALL
.Lfunc_end1:
.size _Z18DijkstrasSetupCudaPiS_S_S_S_S_ii, .Lfunc_end1-_Z18DijkstrasSetupCudaPiS_S_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z8ExtremasPiS_iiS_i # -- Begin function _Z8ExtremasPiS_iiS_i
.p2align 4, 0x90
.type _Z8ExtremasPiS_iiS_i,@function
_Z8ExtremasPiS_iiS_i: # @_Z8ExtremasPiS_iiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $248, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
# kill: def $r9d killed $r9d def $r9
movq %r9, -208(%rbp) # 8-byte Spill
movl %ecx, -44(%rbp) # 4-byte Spill
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r14
movl $0, -48(%rbp)
movslq %edx, %r13
movq %r13, %r12
shlq $34, %r12
sarq $32, %r12
leaq -224(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.1: # %_Z20CudaMallocErrorCheckPPvi.exit
leaq -216(%rbp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_12
# %bb.2: # %_Z20CudaMallocErrorCheckPPvi.exit31
leaq (,%r13,4), %rax
movq %rax, -200(%rbp) # 8-byte Spill
movabsq $4294967297, %r12 # imm = 0x100000001
leaq -64(%rbp), %rax
leaq -192(%rbp), %r10
leaq -80(%rbp), %r11
leaq -184(%rbp), %r8
leaq -232(%rbp), %r9
movq %r14, %rdi
movq %r15, %rsi
movl %r13d, %edx
movl -44(%rbp), %ecx # 4-byte Reload
pushq -208(%rbp) # 8-byte Folded Reload
pushq %rax
pushq %r10
pushq %r11
callq _Z10InitializePiS_iiPS_S0_S0_S0_S0_i
addq $32, %rsp
leaq -72(%rbp), %rdi
callq hipEventCreate
leaq -56(%rbp), %rdi
callq hipEventCreate
movq -72(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 4(%r12), %r13
leaq -288(%rbp), %r14
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=1
cmpl $2147483647, %r15d # imm = 0x7FFFFFFF
je .LBB2_8
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movq -80(%rbp), %rax
movq %rax, -168(%rbp)
movq -192(%rbp), %rax
movq %rax, -160(%rbp)
movq -64(%rbp), %rax
movq %rax, -152(%rbp)
movq -184(%rbp), %rax
movq %rax, -112(%rbp)
movq -232(%rbp), %rax
movq %rax, -104(%rbp)
movl %ebx, -176(%rbp)
movl -44(%rbp), %eax # 4-byte Reload
movl %eax, -172(%rbp)
leaq -168(%rbp), %rax
movq %rax, -288(%rbp)
leaq -160(%rbp), %rax
movq %rax, -280(%rbp)
leaq -152(%rbp), %rax
movq %rax, -272(%rbp)
leaq -112(%rbp), %rax
movq %rax, -264(%rbp)
leaq -104(%rbp), %rax
movq %rax, -256(%rbp)
leaq -176(%rbp), %rax
movq %rax, -248(%rbp)
leaq -172(%rbp), %rax
movq %rax, -240(%rbp)
leaq -144(%rbp), %rdi
leaq -128(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -128(%rbp), %rcx
movl -120(%rbp), %r8d
movl $_Z5RelaxPiS_S_S_S_ii, %edi
movq %r14, %r9
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
movq -80(%rbp), %rdi
movq -64(%rbp), %rsi
movq -184(%rbp), %rdx
movl %ebx, %r8d
pushq -224(%rbp)
pushq -216(%rbp)
callq _Z7MinimumPiS_S_S_iiS_S_
addq $16, %rsp
movl %eax, %r15d
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_3 Depth=1
movq -80(%rbp), %rax
movq -192(%rbp), %rcx
movq -64(%rbp), %rdx
movq %rax, -168(%rbp)
movq %rcx, -160(%rbp)
movq %rdx, -152(%rbp)
movl %r15d, -96(%rbp)
movl %ebx, -88(%rbp)
leaq -168(%rbp), %rax
movq %rax, -288(%rbp)
leaq -160(%rbp), %rax
movq %rax, -280(%rbp)
leaq -152(%rbp), %rax
movq %rax, -272(%rbp)
leaq -96(%rbp), %rax
movq %rax, -264(%rbp)
leaq -88(%rbp), %rax
movq %rax, -256(%rbp)
leaq -144(%rbp), %rdi
leaq -128(%rbp), %rsi
leaq -112(%rbp), %rdx
leaq -104(%rbp), %rcx
callq __hipPopCallConfiguration
movq -144(%rbp), %rsi
movl -136(%rbp), %edx
movq -128(%rbp), %rcx
movl -120(%rbp), %r8d
movl $_Z6UpdatePiS_S_ii, %edi
movq %r14, %r9
pushq -104(%rbp)
pushq -112(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB2_7
.LBB2_8:
movq -56(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rdi
callq hipEventSynchronize
movq -72(%rbp), %rsi
movq -56(%rbp), %rdx
leaq -48(%rbp), %rdi
callq hipEventElapsedTime
movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq -72(%rbp), %rdi
callq hipEventDestroy
movq -56(%rbp), %rdi
callq hipEventDestroy
movq %rsp, %r15
movl %ebx, %r12d
movq %rsp, %r14
leaq 15(,%r12,4), %rax
andq $-16, %rax
subq %rax, %r14
movq %r14, %rsp
movq -64(%rbp), %rsi
movq %r14, %rdi
movq -200(%rbp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %ebx, %ebx
jle .LBB2_11
# %bb.9: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq %rbx, %r12
jne .LBB2_10
.LBB2_11: # %._crit_edge
movq %r15, %rsp
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_12:
.cfi_def_cfa %rbp, 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z8ExtremasPiS_iiS_i, .Lfunc_end2-_Z8ExtremasPiS_iiS_i
.cfi_endproc
# -- End function
.globl _Z20CudaMallocErrorCheckPPvi # -- Begin function _Z20CudaMallocErrorCheckPPvi
.p2align 4, 0x90
.type _Z20CudaMallocErrorCheckPPvi,@function
_Z20CudaMallocErrorCheckPPvi: # @_Z20CudaMallocErrorCheckPPvi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %esi, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_2
# %bb.1:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size _Z20CudaMallocErrorCheckPPvi, .Lfunc_end3-_Z20CudaMallocErrorCheckPPvi
.cfi_endproc
# -- End function
.globl _Z10InitializePiS_iiPS_S0_S0_S0_S0_i # -- Begin function _Z10InitializePiS_iiPS_S0_S0_S0_S0_i
.p2align 4, 0x90
.type _Z10InitializePiS_iiPS_S0_S0_S0_S0_i,@function
_Z10InitializePiS_iiPS_S0_S0_S0_S0_i: # @_Z10InitializePiS_iiPS_S0_S0_S0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r14
movq %r8, %r15
movl %ecx, %r12d
movq %rsi, 32(%rsp) # 8-byte Spill
movq %rdi, %rbp
movl %edx, 16(%rsp) # 4-byte Spill
movslq %edx, %rbx
movq %rbx, %r13
shlq $34, %r13
sarq $32, %r13
movq %r8, %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_8
# %bb.1: # %_Z20CudaMallocErrorCheckPPvi.exit
movl %r12d, 12(%rsp) # 4-byte Spill
movslq %r12d, %r12
movq %r12, %rsi
shlq $34, %rsi
sarq $32, %rsi
movq %r14, %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB4_8
# %bb.2: # %_Z20CudaMallocErrorCheckPPvi.exit31
movq 256(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_8
# %bb.3: # %_Z20CudaMallocErrorCheckPPvi.exit33
movq 264(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_8
# %bb.4: # %_Z20CudaMallocErrorCheckPPvi.exit35
movq 272(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_8
# %bb.5: # %_Z20CudaMallocErrorCheckPPvi.exit37
leaq (,%rbx,4), %rdx
shlq $2, %r12
movq (%r15), %rdi
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%r14), %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal 1023(%rbx), %edi
testl %ebx, %ebx
movl 16(%rsp), %ebp # 4-byte Reload
cmovnsl %ebp, %edi
sarl $10, %edi
incl %edi
movl %ebx, %eax
cltd
idivl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_7
# %bb.6:
movl 280(%rsp), %eax
movq (%r15), %rcx
movq (%r14), %rdx
movq 256(%rsp), %rsi
movq (%rsi), %rsi
movq 264(%rsp), %rdi
movq (%rdi), %rdi
movq 272(%rsp), %r8
movq (%r8), %r8
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movq %rdi, 96(%rsp)
movq %r8, 88(%rsp)
movl %eax, 28(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 24(%rsp)
movl %ebp, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z13InitializeGPUPiS_S_S_S_iii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_7:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 256
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z10InitializePiS_iiPS_S0_S0_S0_S0_i, .Lfunc_end4-_Z10InitializePiS_iiPS_S0_S0_S0_S0_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__RelaxPiS_S_S_S_ii # -- Begin function _Z20__device_stub__RelaxPiS_S_S_S_ii
.p2align 4, 0x90
.type _Z20__device_stub__RelaxPiS_S_S_S_ii,@function
_Z20__device_stub__RelaxPiS_S_S_S_ii: # @_Z20__device_stub__RelaxPiS_S_S_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5RelaxPiS_S_S_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z20__device_stub__RelaxPiS_S_S_S_ii, .Lfunc_end5-_Z20__device_stub__RelaxPiS_S_S_S_ii
.cfi_endproc
# -- End function
.globl _Z7MinimumPiS_S_S_iiS_S_ # -- Begin function _Z7MinimumPiS_S_S_iiS_S_
.p2align 4, 0x90
.type _Z7MinimumPiS_S_S_iiS_S_,@function
_Z7MinimumPiS_S_S_iiS_S_: # @_Z7MinimumPiS_S_S_iiS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r8d killed $r8d def $r8
movq %rdx, 176(%rsp) # 8-byte Spill
movq %rdi, 96(%rsp) # 8-byte Spill
leal 1(%r8), %eax
leal 1024(%r8), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $10, %ecx
incl %ecx
xorl %edx, %edx
divl %ecx
shrl %eax
movl %ecx, %edi
imull %eax, %edi
addl %edi, %edi
movl $1, %edx
movl $1, %r15d
cmpl %r8d, %edi
jae .LBB6_1
# %bb.2: # %.lr.ph.i.preheader
movl %edi, %ebx
.p2align 4, 0x90
.LBB6_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl %edi, %ebx
incl %r15d
cmpl %r8d, %ebx
jb .LBB6_3
jmp .LBB6_4
.LBB6_1:
movl %edi, %ebx
.LBB6_4: # %_Z16NearestPowerBasejjRj.exit
movq %rsi, 104(%rsp) # 8-byte Spill
movq 248(%rsp), %rbp
movq 240(%rsp), %r14
movl %r15d, %esi
imull %ecx, %esi
.p2align 4, 0x90
.LBB6_5: # =>This Inner Loop Header: Depth=1
movl %edx, %r13d
leal (,%r13,2), %edx
cmpl %esi, %r13d
jb .LBB6_5
# %bb.6: # %_Z15NearestPowerTwoj.exit.preheader
movl $1, %edx
.p2align 4, 0x90
.LBB6_7: # %_Z15NearestPowerTwoj.exit
# =>This Inner Loop Header: Depth=1
movl %edx, %r12d
leal (%r12,%r12), %edx
cmpl %eax, %r12d
jb .LBB6_7
# %bb.8: # %_Z15NearestPowerTwoj.exit54
movabsq $4294967296, %rsi # imm = 0x100000000
movl %r12d, %r8d
shlq $2, %r8
movl %ecx, %edi
orq %rsi, %rdi
movl %eax, %edx
orq %rsi, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB6_9
# %bb.10:
cmpl $2, %r13d
jb .LBB6_11
.LBB6_12: # %.lr.ph
movl %r13d, %eax
shrl $10, %eax
movl %r13d, %ecx
shrl %ecx
cmpl $1025, %r13d # imm = 0x401
movl $1, %edx
cmovbl %edx, %eax
movl $512, %edx # imm = 0x200
movl $512, %r12d # imm = 0x200
cmovael %edx, %ecx
jmp .LBB6_13
.p2align 4, 0x90
.LBB6_15: # in Loop: Header=BB6_13 Depth=1
movl %ebx, %eax
shrl $10, %eax
movl %ebx, %ecx
shrl %ecx
cmpl $1025, %ebx # imm = 0x401
cmovael %r12d, %ecx
movl $1, %edx
cmovbl %edx, %eax
movq %r15, %r14
movl %ebx, %r13d
cmpl $1, %ebx
jbe .LBB6_16
.LBB6_13: # =>This Inner Loop Header: Depth=1
movl %eax, %ebx
movq %rbp, %r15
movq %r14, %rbp
movl %ecx, %edx
leaq (,%rdx,4), %r8
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_15
# %bb.14: # in Loop: Header=BB6_13 Depth=1
movq %rbp, 80(%rsp)
movq %r15, 72(%rsp)
movl %r13d, 4(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z6reducePiS_jS_S_, %edi
leaq 112(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB6_15
.LBB6_9:
movq 176(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebx, 4(%rsp)
movl %r12d, 92(%rsp)
movl %r15d, 88(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movq 104(%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 92(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10reduce_fixPiS_jjjS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $2, %r13d
jae .LBB6_12
.LBB6_11:
movq %r14, %r15
.LBB6_16: # %._crit_edge
leaq 112(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $2, %ecx
callq hipMemcpy
movl 112(%rsp), %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7MinimumPiS_S_S_iiS_S_, .Lfunc_end6-_Z7MinimumPiS_S_S_iiS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__UpdatePiS_S_ii # -- Begin function _Z21__device_stub__UpdatePiS_S_ii
.p2align 4, 0x90
.type _Z21__device_stub__UpdatePiS_S_ii,@function
_Z21__device_stub__UpdatePiS_S_ii: # @_Z21__device_stub__UpdatePiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6UpdatePiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z21__device_stub__UpdatePiS_S_ii, .Lfunc_end7-_Z21__device_stub__UpdatePiS_S_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__InitializeGPUPiS_S_S_S_iii # -- Begin function _Z28__device_stub__InitializeGPUPiS_S_S_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__InitializeGPUPiS_S_S_S_iii,@function
_Z28__device_stub__InitializeGPUPiS_S_S_S_iii: # @_Z28__device_stub__InitializeGPUPiS_S_S_S_iii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13InitializeGPUPiS_S_S_S_iii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end8:
.size _Z28__device_stub__InitializeGPUPiS_S_S_S_iii, .Lfunc_end8-_Z28__device_stub__InitializeGPUPiS_S_S_S_iii
.cfi_endproc
# -- End function
.globl _Z16NearestPowerBasejjRj # -- Begin function _Z16NearestPowerBasejjRj
.p2align 4, 0x90
.type _Z16NearestPowerBasejjRj,@function
_Z16NearestPowerBasejjRj: # @_Z16NearestPowerBasejjRj
.cfi_startproc
# %bb.0:
movl $1, %ecx
cmpl %edi, %esi
jae .LBB9_1
# %bb.2: # %.lr.ph.preheader
movl %esi, %eax
.p2align 4, 0x90
.LBB9_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl %esi, %eax
incl %ecx
cmpl %edi, %eax
jb .LBB9_3
# %bb.4: # %._crit_edge
movl %ecx, (%rdx)
retq
.LBB9_1:
movl %esi, %eax
movl %ecx, (%rdx)
retq
.Lfunc_end9:
.size _Z16NearestPowerBasejjRj, .Lfunc_end9-_Z16NearestPowerBasejjRj
.cfi_endproc
# -- End function
.globl _Z15NearestPowerTwoj # -- Begin function _Z15NearestPowerTwoj
.p2align 4, 0x90
.type _Z15NearestPowerTwoj,@function
_Z15NearestPowerTwoj: # @_Z15NearestPowerTwoj
.cfi_startproc
# %bb.0:
movl $1, %ecx
.p2align 4, 0x90
.LBB10_1: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
leal (%rax,%rax), %ecx
cmpl %edi, %eax
jb .LBB10_1
# %bb.2:
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end10:
.size _Z15NearestPowerTwoj, .Lfunc_end10-_Z15NearestPowerTwoj
.cfi_endproc
# -- End function
.globl _Z25__device_stub__reduce_fixPiS_jjjS_S_ # -- Begin function _Z25__device_stub__reduce_fixPiS_jjjS_S_
.p2align 4, 0x90
.type _Z25__device_stub__reduce_fixPiS_jjjS_S_,@function
_Z25__device_stub__reduce_fixPiS_jjjS_S_: # @_Z25__device_stub__reduce_fixPiS_jjjS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10reduce_fixPiS_jjjS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end11:
.size _Z25__device_stub__reduce_fixPiS_jjjS_S_, .Lfunc_end11-_Z25__device_stub__reduce_fixPiS_jjjS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__reducePiS_jS_S_ # -- Begin function _Z21__device_stub__reducePiS_jS_S_
.p2align 4, 0x90
.type _Z21__device_stub__reducePiS_jS_S_,@function
_Z21__device_stub__reducePiS_jS_S_: # @_Z21__device_stub__reducePiS_jS_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6reducePiS_jS_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end12:
.size _Z21__device_stub__reducePiS_jS_S_, .Lfunc_end12-_Z21__device_stub__reducePiS_jS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB13_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB13_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13InitializeGPUPiS_S_S_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5RelaxPiS_S_S_S_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6UpdatePiS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6reducePiS_jS_S_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10reduce_fixPiS_jjjS_S_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end13:
.size __hip_module_ctor, .Lfunc_end13-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB14_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB14_2:
retq
.Lfunc_end14:
.size __hip_module_dtor, .Lfunc_end14-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5RelaxPiS_S_S_S_ii,@object # @_Z5RelaxPiS_S_S_S_ii
.section .rodata,"a",@progbits
.globl _Z5RelaxPiS_S_S_S_ii
.p2align 3, 0x0
_Z5RelaxPiS_S_S_S_ii:
.quad _Z20__device_stub__RelaxPiS_S_S_S_ii
.size _Z5RelaxPiS_S_S_S_ii, 8
.type _Z6UpdatePiS_S_ii,@object # @_Z6UpdatePiS_S_ii
.globl _Z6UpdatePiS_S_ii
.p2align 3, 0x0
_Z6UpdatePiS_S_ii:
.quad _Z21__device_stub__UpdatePiS_S_ii
.size _Z6UpdatePiS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed Time: %f\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sigma[%d] : %d\n"
.size .L.str.1, 19
.type _Z13InitializeGPUPiS_S_S_S_iii,@object # @_Z13InitializeGPUPiS_S_S_S_iii
.section .rodata,"a",@progbits
.globl _Z13InitializeGPUPiS_S_S_S_iii
.p2align 3, 0x0
_Z13InitializeGPUPiS_S_S_S_iii:
.quad _Z28__device_stub__InitializeGPUPiS_S_S_S_iii
.size _Z13InitializeGPUPiS_S_S_S_iii, 8
.type _Z10reduce_fixPiS_jjjS_S_,@object # @_Z10reduce_fixPiS_jjjS_S_
.globl _Z10reduce_fixPiS_jjjS_S_
.p2align 3, 0x0
_Z10reduce_fixPiS_jjjS_S_:
.quad _Z25__device_stub__reduce_fixPiS_jjjS_S_
.size _Z10reduce_fixPiS_jjjS_S_, 8
.type _Z6reducePiS_jS_S_,@object # @_Z6reducePiS_jS_S_
.globl _Z6reducePiS_jS_S_
.p2align 3, 0x0
_Z6reducePiS_jS_S_:
.quad _Z21__device_stub__reducePiS_jS_S_
.size _Z6reducePiS_jS_S_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Error: %s"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13InitializeGPUPiS_S_S_S_iii"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5RelaxPiS_S_S_S_ii"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6UpdatePiS_S_ii"
.size .L__unnamed_3, 18
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z6reducePiS_jS_S_"
.size .L__unnamed_4, 19
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z10reduce_fixPiS_jjjS_S_"
.size .L__unnamed_5, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__RelaxPiS_S_S_S_ii
.addrsig_sym _Z21__device_stub__UpdatePiS_S_ii
.addrsig_sym _Z28__device_stub__InitializeGPUPiS_S_S_S_iii
.addrsig_sym _Z25__device_stub__reduce_fixPiS_jjjS_S_
.addrsig_sym _Z21__device_stub__reducePiS_jS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5RelaxPiS_S_S_S_ii
.addrsig_sym _Z6UpdatePiS_S_ii
.addrsig_sym _Z13InitializeGPUPiS_S_S_S_iii
.addrsig_sym _Z10reduce_fixPiS_jjjS_S_
.addrsig_sym _Z6reducePiS_jS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#include <unistd.h>
#include <png.h>
#include <cuda.h>
#include <math.h>
#define rel params[0]
#define img params[1]
#define scl params[2]
__device__ void writeHSV(uint8_t *pixel, int theta) {
unsigned char region, remainder, q, t;
region = theta / 43;
remainder = (theta - (region * 43)) * 6;
q = (255 * (255 - ((255 * remainder) >> 8))) >> 8;
t = (255 * (255 - ((255 * (255 - remainder)) >> 8))) >> 8;
switch (region) {
case 0:
*pixel++ = 255;
*pixel++ = t;
*pixel++ = 0;
return;
case 1:
*pixel++ = q;
*pixel++ = 255;
*pixel++ = 0;
return;
case 2:
*pixel++ = 0;
*pixel++ = 255;
*pixel++ = t;
return;
case 3:
*pixel++ = 0;
*pixel++ = q;
*pixel++ = 255;
return;
case 4:
*pixel++ = t;
*pixel++ = 0;
*pixel++ = 255;
return;
default:
*pixel++ = 255;
*pixel++ = 0;
*pixel++ = q;
return;
}
}
__global__ void euclid (uint8_t *gpu, double *params, int streamNumber ) {
int index, pos;
int c, t;
uint32_t x, y;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
x = (uint32_t) (((rel + 2.0) + (double) (.5 + (index % 1024)) * scl) * 1048576);
y = (uint32_t) (((img + 2.0) + (double) (.5 + (index / 1024)) * scl) * 1048576);
c = 0;
t = 1;
while (1) {
if (x > y) {
x -= y;
c++;
} else if (y > x) {
y -= x;
} else {
break;
}
t++;
if (t > 1000) break;
}
uint8_t *pixel = (gpu + index++ * 3);
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
}
}
__global__ void mandelbrot (uint8_t *gpu, double *params, int streamNumber ) {
int index, c, pos;
double cr, ci, zr, zi, t;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
c = 0;
cr = rel + (double) (.5 + (index % 1024)) * scl / 1024.0;
ci = img + (double) (.5 + (index / 1024)) * scl / 1024.0;
zr = cr;
zi = ci;
while (++c < 1000 && zr * zr + zi * zi < 4) {
t = zr;
zr = zr * zr - zi * zi + cr;
zi = 2 * t * zi + ci;
}
uint8_t *pixel = (gpu + index * 3);
if (c == 1000) {
*pixel++ = 0;
*pixel++ = 0;
*pixel++ = 0;
} else {
writeHSV(pixel, c);
}
index ++;
}
}
// GPU variables
double *gpu_params;
uint8_t *gpu;
// Host variables
cudaStream_t streams[16];
double params[3];
png_byte ** row_pointers;
void (*kernel) (uint8_t *, double *, int);
// reads parameters from stdin and writes them to params array
// initializes rel, img, and scl macros
void readParams() {
rel = -2.0;
img = -2.0;
scl = 4.0;
char c = getchar();
switch (c) {
case 'm':
kernel = mandelbrot;
break;
default:
kernel = euclid;
}
while ((c = getchar()) != '@') {
scl /= 3.0;
switch (c) {
case '3':
case '6':
case '9':
rel += scl;
case '2':
case '5':
case '8':
rel += scl;
default:
break;
}
switch (c) {
case '7':
case '8':
case '9':
img += scl;
case '4':
case '5':
case '6':
img += scl;
default:
break;
}
}
}
// begins computation
void computeKernel() {
// setup params
cudaMemcpy( gpu_params, params, 3 * sizeof(double), cudaMemcpyHostToDevice);
// initialize streams
int i, r;
for (i = 0; i < 16; i++) {
cudaStreamCreate((streams + i));
}
// execute kernels in the streams
for (i = 0; i < 16; i++) {
kernel<<<1, 256, 0, streams[i]>>>( gpu, gpu_params, i );
}
// setup asynchronous memory copy after completion
for (i = 0; i < 16; i++) {
for (r = 0; r < 64; r++) {
cudaMemcpyAsync(row_pointers[64 * i + r], (gpu + i * 65536 * 3 + r * 1024 * 3), sizeof(uint8_t) * 1024 * 3, cudaMemcpyDeviceToHost, streams[i]);
}
}
cudaDeviceSynchronize();
}
extern void writePngOutput();
int main(int argc, char **argv) {
// Initialize memory
cudaMalloc( (void**) &gpu, 1024 * 1024 * sizeof(uint8_t) * 3 );
cudaMalloc( (void**) &gpu_params, 3 * sizeof(double) );
row_pointers = (png_byte **) malloc (1024 * sizeof (png_byte *));
for (int y = 0; y < 1024; y++) {
row_pointers[y] = (png_byte *) malloc (sizeof (uint8_t) * 1024 * 3);
}
// do the process
while (1) {
readParams();
computeKernel();
writePngOutput();
}
}
size_t pngBufferFill = 0;
extern void writeFn(png_structp png_ptr, png_bytep data, uint32_t size);
extern void flushFn(png_structp png_ptr);
void writePngOutput() {
png_structp png_ptr = png_create_write_struct (PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
png_infop info_ptr = png_create_info_struct (png_ptr);
png_set_IHDR (png_ptr,
info_ptr,
1024, // width
1024, // height
8, // depth
PNG_COLOR_TYPE_RGB,
PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
png_set_write_fn(png_ptr, NULL, (png_rw_ptr) writeFn, (png_flush_ptr) flushFn);
png_init_io (png_ptr, stdout);
png_set_rows (png_ptr, info_ptr, row_pointers);
png_write_png (png_ptr, info_ptr, PNG_TRANSFORM_IDENTITY, NULL);
write(2, &pngBufferFill, 4);
pngBufferFill = 0;
png_destroy_write_struct (&png_ptr, &info_ptr);
}
void writeFn(png_structp png_ptr, png_bytep data, uint32_t size) {
write(1, data, size);
pngBufferFill += size;
}
void flushFn(png_structp png_ptr) {
fflush(stdout);
} | .file "tmpxft_00138b38_00000000-6_parallelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z7writeFnP14png_struct_defPhj
.type _Z7writeFnP14png_struct_defPhj, @function
_Z7writeFnP14png_struct_defPhj:
.LFB2075:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edx, %ebx
movq %rbx, %rdx
movl $1, %edi
call write@PLT
addq %rbx, pngBufferFill(%rip)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z7writeFnP14png_struct_defPhj, .-_Z7writeFnP14png_struct_defPhj
.globl _Z7flushFnP14png_struct_def
.type _Z7flushFnP14png_struct_def, @function
_Z7flushFnP14png_struct_def:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq stdout(%rip), %rdi
call fflush@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z7flushFnP14png_struct_def, .-_Z7flushFnP14png_struct_def
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8writeHSVPhi
.type _Z8writeHSVPhi, @function
_Z8writeHSVPhi:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z8writeHSVPhi, .-_Z8writeHSVPhi
.globl _Z10readParamsv
.type _Z10readParamsv, @function
_Z10readParamsv:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movsd .LC0(%rip), %xmm0
movsd %xmm0, params(%rip)
movsd %xmm0, 8+params(%rip)
movq .LC1(%rip), %rax
movq %rax, 16+params(%rip)
movq stdin(%rip), %rdi
call getc@PLT
cmpb $109, %al
leaq _Z6euclidPhPdi(%rip), %rax
leaq _Z10mandelbrotPhPdi(%rip), %rdx
cmove %rdx, %rax
movq %rax, kernel(%rip)
movabsq $82190693199511552, %rbp
movabsq $164381386399023104, %r12
jmp .L11
.L12:
cmpb $54, %cl
jle .L17
subl $55, %ecx
cmpb $2, %cl
ja .L17
.L20:
movapd %xmm0, %xmm1
addsd 8+params(%rip), %xmm1
movsd %xmm1, 8+params(%rip)
.L15:
addsd 8+params(%rip), %xmm0
movsd %xmm0, 8+params(%rip)
.L11:
movl $1, %ebx
.L17:
movq stdin(%rip), %rdi
call getc@PLT
movl %eax, %ecx
cmpb $64, %al
je .L26
movsd 16+params(%rip), %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 16+params(%rip)
cmpb $57, %cl
ja .L12
movq %rbx, %rax
salq %cl, %rax
testq %rbp, %rax
jne .L13
testq %r12, %rax
je .L14
movapd %xmm0, %xmm1
addsd params(%rip), %xmm1
movsd %xmm1, params(%rip)
.L13:
movapd %xmm0, %xmm1
addsd params(%rip), %xmm1
movsd %xmm1, params(%rip)
.L14:
cmpb $54, %cl
jg .L20
cmpb $51, %cl
jg .L15
jmp .L17
.L26:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10readParamsv, .-_Z10readParamsv
.globl _Z13computeKernelv
.type _Z13computeKernelv, @function
_Z13computeKernelv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl $1, %ecx
movl $24, %edx
leaq params(%rip), %rsi
movq gpu_params(%rip), %rdi
call cudaMemcpy@PLT
leaq streams(%rip), %rbp
leaq 128(%rbp), %r13
movq %rbp, %rbx
.L28:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L28
movl $0, %ebx
leaq streams(%rip), %r12
jmp .L30
.L29:
addq $1, %rbx
cmpq $16, %rbx
je .L38
.L30:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq (%r12,%rbx,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl %ebx, %edx
movq gpu_params(%rip), %rsi
movq gpu(%rip), %rdi
call *kernel(%rip)
jmp .L29
.L38:
movl $512, %r12d
.L31:
leaq -512(%r12), %rbx
.L32:
leaq (%rbx,%rbx,2), %rsi
salq $7, %rsi
addq gpu(%rip), %rsi
movq row_pointers(%rip), %rax
movq (%rax,%rbx), %rdi
movq 0(%rbp), %r8
movl $2, %ecx
movl $3072, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L32
addq $8, %rbp
addq $512, %r12
cmpq %r13, %rbp
jne .L31
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z13computeKernelv, .-_Z13computeKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "1.6.43"
.text
.globl _Z14writePngOutputv
.type _Z14writePngOutputv, @function
_Z14writePngOutputv:
.LFB2074:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %ecx
movl $0, %edx
movl $0, %esi
leaq .LC3(%rip), %rdi
call png_create_write_struct@PLT
movq %rax, %rdi
movq %rax, 8(%rsp)
call png_create_info_struct@PLT
movq %rax, %rsi
movq %rax, 16(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq $0
.cfi_def_cfa_offset 64
pushq $0
.cfi_def_cfa_offset 72
pushq $0
.cfi_def_cfa_offset 80
movl $2, %r9d
movl $8, %r8d
movl $1024, %ecx
movl $1024, %edx
movq 40(%rsp), %rdi
call png_set_IHDR@PLT
addq $32, %rsp
.cfi_def_cfa_offset 48
leaq _Z7flushFnP14png_struct_def(%rip), %rcx
leaq _Z7writeFnP14png_struct_defPhj(%rip), %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call png_set_write_fn@PLT
movq stdout(%rip), %rsi
movq 8(%rsp), %rdi
call png_init_io@PLT
movq row_pointers(%rip), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call png_set_rows@PLT
movl $0, %ecx
movl $0, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call png_write_png@PLT
movl $4, %edx
leaq pngBufferFill(%rip), %rsi
movl $2, %edi
call write@PLT
movq $0, pngBufferFill(%rip)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
call png_destroy_write_struct@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z14writePngOutputv, .-_Z14writePngOutputv
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $3145728, %esi
leaq gpu(%rip), %rdi
call cudaMalloc@PLT
movl $24, %esi
leaq gpu_params(%rip), %rdi
call cudaMalloc@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, row_pointers(%rip)
movl $0, %ebx
.L44:
movq %rbx, %rbp
addq row_pointers(%rip), %rbp
movl $3072, %edi
call malloc@PLT
movq %rax, 0(%rbp)
addq $8, %rbx
cmpq $8192, %rbx
jne .L44
.L45:
call _Z10readParamsv
call _Z13computeKernelv
call _Z14writePngOutputv
jmp .L45
.cfi_endproc
.LFE2073:
.size main, .-main
.globl _Z28__device_stub__Z6euclidPhPdiPhPdi
.type _Z28__device_stub__Z6euclidPhPdiPhPdi, @function
_Z28__device_stub__Z6euclidPhPdiPhPdi:
.LFB2101:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6euclidPhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2101:
.size _Z28__device_stub__Z6euclidPhPdiPhPdi, .-_Z28__device_stub__Z6euclidPhPdiPhPdi
.globl _Z6euclidPhPdi
.type _Z6euclidPhPdi, @function
_Z6euclidPhPdi:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6euclidPhPdiPhPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _Z6euclidPhPdi, .-_Z6euclidPhPdi
.globl _Z33__device_stub__Z10mandelbrotPhPdiPhPdi
.type _Z33__device_stub__Z10mandelbrotPhPdiPhPdi, @function
_Z33__device_stub__Z10mandelbrotPhPdiPhPdi:
.LFB2103:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mandelbrotPhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z33__device_stub__Z10mandelbrotPhPdiPhPdi, .-_Z33__device_stub__Z10mandelbrotPhPdiPhPdi
.globl _Z10mandelbrotPhPdi
.type _Z10mandelbrotPhPdi, @function
_Z10mandelbrotPhPdi:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mandelbrotPhPdiPhPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z10mandelbrotPhPdi, .-_Z10mandelbrotPhPdi
.section .rodata.str1.1
.LC4:
.string "_Z10mandelbrotPhPdi"
.LC5:
.string "_Z6euclidPhPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mandelbrotPhPdi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6euclidPhPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl pngBufferFill
.bss
.align 8
.type pngBufferFill, @object
.size pngBufferFill, 8
pngBufferFill:
.zero 8
.globl kernel
.align 8
.type kernel, @object
.size kernel, 8
kernel:
.zero 8
.globl row_pointers
.align 8
.type row_pointers, @object
.size row_pointers, 8
row_pointers:
.zero 8
.globl params
.align 16
.type params, @object
.size params, 24
params:
.zero 24
.globl streams
.align 32
.type streams, @object
.size streams, 128
streams:
.zero 128
.globl gpu
.align 8
.type gpu, @object
.size gpu, 8
gpu:
.zero 8
.globl gpu_params
.align 8
.type gpu_params, @object
.size gpu_params, 8
gpu_params:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1073741824
.align 8
.LC1:
.long 0
.long 1074790400
.align 8
.LC2:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <unistd.h>
#include <png.h>
#include <cuda.h>
#include <math.h>
#define rel params[0]
#define img params[1]
#define scl params[2]
__device__ void writeHSV(uint8_t *pixel, int theta) {
unsigned char region, remainder, q, t;
region = theta / 43;
remainder = (theta - (region * 43)) * 6;
q = (255 * (255 - ((255 * remainder) >> 8))) >> 8;
t = (255 * (255 - ((255 * (255 - remainder)) >> 8))) >> 8;
switch (region) {
case 0:
*pixel++ = 255;
*pixel++ = t;
*pixel++ = 0;
return;
case 1:
*pixel++ = q;
*pixel++ = 255;
*pixel++ = 0;
return;
case 2:
*pixel++ = 0;
*pixel++ = 255;
*pixel++ = t;
return;
case 3:
*pixel++ = 0;
*pixel++ = q;
*pixel++ = 255;
return;
case 4:
*pixel++ = t;
*pixel++ = 0;
*pixel++ = 255;
return;
default:
*pixel++ = 255;
*pixel++ = 0;
*pixel++ = q;
return;
}
}
__global__ void euclid (uint8_t *gpu, double *params, int streamNumber ) {
int index, pos;
int c, t;
uint32_t x, y;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
x = (uint32_t) (((rel + 2.0) + (double) (.5 + (index % 1024)) * scl) * 1048576);
y = (uint32_t) (((img + 2.0) + (double) (.5 + (index / 1024)) * scl) * 1048576);
c = 0;
t = 1;
while (1) {
if (x > y) {
x -= y;
c++;
} else if (y > x) {
y -= x;
} else {
break;
}
t++;
if (t > 1000) break;
}
uint8_t *pixel = (gpu + index++ * 3);
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
}
}
__global__ void mandelbrot (uint8_t *gpu, double *params, int streamNumber ) {
int index, c, pos;
double cr, ci, zr, zi, t;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
c = 0;
cr = rel + (double) (.5 + (index % 1024)) * scl / 1024.0;
ci = img + (double) (.5 + (index / 1024)) * scl / 1024.0;
zr = cr;
zi = ci;
while (++c < 1000 && zr * zr + zi * zi < 4) {
t = zr;
zr = zr * zr - zi * zi + cr;
zi = 2 * t * zi + ci;
}
uint8_t *pixel = (gpu + index * 3);
if (c == 1000) {
*pixel++ = 0;
*pixel++ = 0;
*pixel++ = 0;
} else {
writeHSV(pixel, c);
}
index ++;
}
}
// GPU variables
double *gpu_params;
uint8_t *gpu;
// Host variables
cudaStream_t streams[16];
double params[3];
png_byte ** row_pointers;
void (*kernel) (uint8_t *, double *, int);
// reads parameters from stdin and writes them to params array
// initializes rel, img, and scl macros
void readParams() {
rel = -2.0;
img = -2.0;
scl = 4.0;
char c = getchar();
switch (c) {
case 'm':
kernel = mandelbrot;
break;
default:
kernel = euclid;
}
while ((c = getchar()) != '@') {
scl /= 3.0;
switch (c) {
case '3':
case '6':
case '9':
rel += scl;
case '2':
case '5':
case '8':
rel += scl;
default:
break;
}
switch (c) {
case '7':
case '8':
case '9':
img += scl;
case '4':
case '5':
case '6':
img += scl;
default:
break;
}
}
}
// begins computation
void computeKernel() {
// setup params
cudaMemcpy( gpu_params, params, 3 * sizeof(double), cudaMemcpyHostToDevice);
// initialize streams
int i, r;
for (i = 0; i < 16; i++) {
cudaStreamCreate((streams + i));
}
// execute kernels in the streams
for (i = 0; i < 16; i++) {
kernel<<<1, 256, 0, streams[i]>>>( gpu, gpu_params, i );
}
// setup asynchronous memory copy after completion
for (i = 0; i < 16; i++) {
for (r = 0; r < 64; r++) {
cudaMemcpyAsync(row_pointers[64 * i + r], (gpu + i * 65536 * 3 + r * 1024 * 3), sizeof(uint8_t) * 1024 * 3, cudaMemcpyDeviceToHost, streams[i]);
}
}
cudaDeviceSynchronize();
}
extern void writePngOutput();
int main(int argc, char **argv) {
// Initialize memory
cudaMalloc( (void**) &gpu, 1024 * 1024 * sizeof(uint8_t) * 3 );
cudaMalloc( (void**) &gpu_params, 3 * sizeof(double) );
row_pointers = (png_byte **) malloc (1024 * sizeof (png_byte *));
for (int y = 0; y < 1024; y++) {
row_pointers[y] = (png_byte *) malloc (sizeof (uint8_t) * 1024 * 3);
}
// do the process
while (1) {
readParams();
computeKernel();
writePngOutput();
}
}
size_t pngBufferFill = 0;
extern void writeFn(png_structp png_ptr, png_bytep data, uint32_t size);
extern void flushFn(png_structp png_ptr);
void writePngOutput() {
png_structp png_ptr = png_create_write_struct (PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
png_infop info_ptr = png_create_info_struct (png_ptr);
png_set_IHDR (png_ptr,
info_ptr,
1024, // width
1024, // height
8, // depth
PNG_COLOR_TYPE_RGB,
PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
png_set_write_fn(png_ptr, NULL, (png_rw_ptr) writeFn, (png_flush_ptr) flushFn);
png_init_io (png_ptr, stdout);
png_set_rows (png_ptr, info_ptr, row_pointers);
png_write_png (png_ptr, info_ptr, PNG_TRANSFORM_IDENTITY, NULL);
write(2, &pngBufferFill, 4);
pngBufferFill = 0;
png_destroy_write_struct (&png_ptr, &info_ptr);
}
void writeFn(png_structp png_ptr, png_bytep data, uint32_t size) {
write(1, data, size);
pngBufferFill += size;
}
void flushFn(png_structp png_ptr) {
fflush(stdout);
} | #include <stdint.h>
#include <unistd.h>
#include <png.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define rel params[0]
#define img params[1]
#define scl params[2]
__device__ void writeHSV(uint8_t *pixel, int theta) {
unsigned char region, remainder, q, t;
region = theta / 43;
remainder = (theta - (region * 43)) * 6;
q = (255 * (255 - ((255 * remainder) >> 8))) >> 8;
t = (255 * (255 - ((255 * (255 - remainder)) >> 8))) >> 8;
switch (region) {
case 0:
*pixel++ = 255;
*pixel++ = t;
*pixel++ = 0;
return;
case 1:
*pixel++ = q;
*pixel++ = 255;
*pixel++ = 0;
return;
case 2:
*pixel++ = 0;
*pixel++ = 255;
*pixel++ = t;
return;
case 3:
*pixel++ = 0;
*pixel++ = q;
*pixel++ = 255;
return;
case 4:
*pixel++ = t;
*pixel++ = 0;
*pixel++ = 255;
return;
default:
*pixel++ = 255;
*pixel++ = 0;
*pixel++ = q;
return;
}
}
__global__ void euclid (uint8_t *gpu, double *params, int streamNumber ) {
int index, pos;
int c, t;
uint32_t x, y;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
x = (uint32_t) (((rel + 2.0) + (double) (.5 + (index % 1024)) * scl) * 1048576);
y = (uint32_t) (((img + 2.0) + (double) (.5 + (index / 1024)) * scl) * 1048576);
c = 0;
t = 1;
while (1) {
if (x > y) {
x -= y;
c++;
} else if (y > x) {
y -= x;
} else {
break;
}
t++;
if (t > 1000) break;
}
uint8_t *pixel = (gpu + index++ * 3);
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
}
}
__global__ void mandelbrot (uint8_t *gpu, double *params, int streamNumber ) {
int index, c, pos;
double cr, ci, zr, zi, t;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
c = 0;
cr = rel + (double) (.5 + (index % 1024)) * scl / 1024.0;
ci = img + (double) (.5 + (index / 1024)) * scl / 1024.0;
zr = cr;
zi = ci;
while (++c < 1000 && zr * zr + zi * zi < 4) {
t = zr;
zr = zr * zr - zi * zi + cr;
zi = 2 * t * zi + ci;
}
uint8_t *pixel = (gpu + index * 3);
if (c == 1000) {
*pixel++ = 0;
*pixel++ = 0;
*pixel++ = 0;
} else {
writeHSV(pixel, c);
}
index ++;
}
}
// GPU variables
double *gpu_params;
uint8_t *gpu;
// Host variables
hipStream_t streams[16];
double params[3];
png_byte ** row_pointers;
void (*kernel) (uint8_t *, double *, int);
// reads parameters from stdin and writes them to params array
// initializes rel, img, and scl macros
void readParams() {
rel = -2.0;
img = -2.0;
scl = 4.0;
char c = getchar();
switch (c) {
case 'm':
kernel = mandelbrot;
break;
default:
kernel = euclid;
}
while ((c = getchar()) != '@') {
scl /= 3.0;
switch (c) {
case '3':
case '6':
case '9':
rel += scl;
case '2':
case '5':
case '8':
rel += scl;
default:
break;
}
switch (c) {
case '7':
case '8':
case '9':
img += scl;
case '4':
case '5':
case '6':
img += scl;
default:
break;
}
}
}
// begins computation
void computeKernel() {
// setup params
hipMemcpy( gpu_params, params, 3 * sizeof(double), hipMemcpyHostToDevice);
// initialize streams
int i, r;
for (i = 0; i < 16; i++) {
hipStreamCreate((streams + i));
}
// execute kernels in the streams
for (i = 0; i < 16; i++) {
kernel<<<1, 256, 0, streams[i]>>>( gpu, gpu_params, i );
}
// setup asynchronous memory copy after completion
for (i = 0; i < 16; i++) {
for (r = 0; r < 64; r++) {
hipMemcpyAsync(row_pointers[64 * i + r], (gpu + i * 65536 * 3 + r * 1024 * 3), sizeof(uint8_t) * 1024 * 3, hipMemcpyDeviceToHost, streams[i]);
}
}
hipDeviceSynchronize();
}
extern void writePngOutput();
int main(int argc, char **argv) {
// Initialize memory
hipMalloc( (void**) &gpu, 1024 * 1024 * sizeof(uint8_t) * 3 );
hipMalloc( (void**) &gpu_params, 3 * sizeof(double) );
row_pointers = (png_byte **) malloc (1024 * sizeof (png_byte *));
for (int y = 0; y < 1024; y++) {
row_pointers[y] = (png_byte *) malloc (sizeof (uint8_t) * 1024 * 3);
}
// do the process
while (1) {
readParams();
computeKernel();
writePngOutput();
}
}
size_t pngBufferFill = 0;
extern void writeFn(png_structp png_ptr, png_bytep data, uint32_t size);
extern void flushFn(png_structp png_ptr);
void writePngOutput() {
png_structp png_ptr = png_create_write_struct (PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
png_infop info_ptr = png_create_info_struct (png_ptr);
png_set_IHDR (png_ptr,
info_ptr,
1024, // width
1024, // height
8, // depth
PNG_COLOR_TYPE_RGB,
PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
png_set_write_fn(png_ptr, NULL, (png_rw_ptr) writeFn, (png_flush_ptr) flushFn);
png_init_io (png_ptr, stdout);
png_set_rows (png_ptr, info_ptr, row_pointers);
png_write_png (png_ptr, info_ptr, PNG_TRANSFORM_IDENTITY, NULL);
write(2, &pngBufferFill, 4);
pngBufferFill = 0;
png_destroy_write_struct (&png_ptr, &info_ptr);
}
void writeFn(png_structp png_ptr, png_bytep data, uint32_t size) {
write(1, data, size);
pngBufferFill += size;
}
void flushFn(png_structp png_ptr) {
fflush(stdout);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdint.h>
#include <unistd.h>
#include <png.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define rel params[0]
#define img params[1]
#define scl params[2]
__device__ void writeHSV(uint8_t *pixel, int theta) {
unsigned char region, remainder, q, t;
region = theta / 43;
remainder = (theta - (region * 43)) * 6;
q = (255 * (255 - ((255 * remainder) >> 8))) >> 8;
t = (255 * (255 - ((255 * (255 - remainder)) >> 8))) >> 8;
switch (region) {
case 0:
*pixel++ = 255;
*pixel++ = t;
*pixel++ = 0;
return;
case 1:
*pixel++ = q;
*pixel++ = 255;
*pixel++ = 0;
return;
case 2:
*pixel++ = 0;
*pixel++ = 255;
*pixel++ = t;
return;
case 3:
*pixel++ = 0;
*pixel++ = q;
*pixel++ = 255;
return;
case 4:
*pixel++ = t;
*pixel++ = 0;
*pixel++ = 255;
return;
default:
*pixel++ = 255;
*pixel++ = 0;
*pixel++ = q;
return;
}
}
__global__ void euclid (uint8_t *gpu, double *params, int streamNumber ) {
int index, pos;
int c, t;
uint32_t x, y;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
x = (uint32_t) (((rel + 2.0) + (double) (.5 + (index % 1024)) * scl) * 1048576);
y = (uint32_t) (((img + 2.0) + (double) (.5 + (index / 1024)) * scl) * 1048576);
c = 0;
t = 1;
while (1) {
if (x > y) {
x -= y;
c++;
} else if (y > x) {
y -= x;
} else {
break;
}
t++;
if (t > 1000) break;
}
uint8_t *pixel = (gpu + index++ * 3);
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
}
}
__global__ void mandelbrot (uint8_t *gpu, double *params, int streamNumber ) {
int index, c, pos;
double cr, ci, zr, zi, t;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
c = 0;
cr = rel + (double) (.5 + (index % 1024)) * scl / 1024.0;
ci = img + (double) (.5 + (index / 1024)) * scl / 1024.0;
zr = cr;
zi = ci;
while (++c < 1000 && zr * zr + zi * zi < 4) {
t = zr;
zr = zr * zr - zi * zi + cr;
zi = 2 * t * zi + ci;
}
uint8_t *pixel = (gpu + index * 3);
if (c == 1000) {
*pixel++ = 0;
*pixel++ = 0;
*pixel++ = 0;
} else {
writeHSV(pixel, c);
}
index ++;
}
}
// GPU variables
double *gpu_params;
uint8_t *gpu;
// Host variables
hipStream_t streams[16];
double params[3];
png_byte ** row_pointers;
void (*kernel) (uint8_t *, double *, int);
// reads parameters from stdin and writes them to params array
// initializes rel, img, and scl macros
void readParams() {
rel = -2.0;
img = -2.0;
scl = 4.0;
char c = getchar();
switch (c) {
case 'm':
kernel = mandelbrot;
break;
default:
kernel = euclid;
}
while ((c = getchar()) != '@') {
scl /= 3.0;
switch (c) {
case '3':
case '6':
case '9':
rel += scl;
case '2':
case '5':
case '8':
rel += scl;
default:
break;
}
switch (c) {
case '7':
case '8':
case '9':
img += scl;
case '4':
case '5':
case '6':
img += scl;
default:
break;
}
}
}
// begins computation
void computeKernel() {
// setup params
hipMemcpy( gpu_params, params, 3 * sizeof(double), hipMemcpyHostToDevice);
// initialize streams
int i, r;
for (i = 0; i < 16; i++) {
hipStreamCreate((streams + i));
}
// execute kernels in the streams
for (i = 0; i < 16; i++) {
kernel<<<1, 256, 0, streams[i]>>>( gpu, gpu_params, i );
}
// setup asynchronous memory copy after completion
for (i = 0; i < 16; i++) {
for (r = 0; r < 64; r++) {
hipMemcpyAsync(row_pointers[64 * i + r], (gpu + i * 65536 * 3 + r * 1024 * 3), sizeof(uint8_t) * 1024 * 3, hipMemcpyDeviceToHost, streams[i]);
}
}
hipDeviceSynchronize();
}
extern void writePngOutput();
int main(int argc, char **argv) {
// Initialize memory
hipMalloc( (void**) &gpu, 1024 * 1024 * sizeof(uint8_t) * 3 );
hipMalloc( (void**) &gpu_params, 3 * sizeof(double) );
row_pointers = (png_byte **) malloc (1024 * sizeof (png_byte *));
for (int y = 0; y < 1024; y++) {
row_pointers[y] = (png_byte *) malloc (sizeof (uint8_t) * 1024 * 3);
}
// do the process
while (1) {
readParams();
computeKernel();
writePngOutput();
}
}
size_t pngBufferFill = 0;
extern void writeFn(png_structp png_ptr, png_bytep data, uint32_t size);
extern void flushFn(png_structp png_ptr);
void writePngOutput() {
png_structp png_ptr = png_create_write_struct (PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
png_infop info_ptr = png_create_info_struct (png_ptr);
png_set_IHDR (png_ptr,
info_ptr,
1024, // width
1024, // height
8, // depth
PNG_COLOR_TYPE_RGB,
PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
png_set_write_fn(png_ptr, NULL, (png_rw_ptr) writeFn, (png_flush_ptr) flushFn);
png_init_io (png_ptr, stdout);
png_set_rows (png_ptr, info_ptr, row_pointers);
png_write_png (png_ptr, info_ptr, PNG_TRANSFORM_IDENTITY, NULL);
write(2, &pngBufferFill, 4);
pngBufferFill = 0;
png_destroy_write_struct (&png_ptr, &info_ptr);
}
void writeFn(png_structp png_ptr, png_bytep data, uint32_t size) {
write(1, data, size);
pngBufferFill += size;
}
void flushFn(png_structp png_ptr) {
fflush(stdout);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6euclidPhPdi
.globl _Z6euclidPhPdi
.p2align 8
.type _Z6euclidPhPdi,@function
_Z6euclidPhPdi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 8, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, s4, 16, v0
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
s_branch .LBB0_2
.LBB0_1:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
v_cvt_f32_u32_e32 v3, v5
v_mul_lo_u32 v2, v2, 0xff
v_sub_nc_u32_e32 v4, 0, v5
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
s_cmpk_lg_i32 s4, 0x100
v_rcp_iflag_f32_e32 v3, v3
v_ashrrev_i32_e32 v6, 31, v2
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v3, 0x4f7ffffe, v3 :: v_dual_add_nc_u32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, v2, v6
v_cvt_u32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v4, v3
v_mul_hi_u32 v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v3, v4
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v3, v5
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v2, v5
v_cmp_ge_u32_e32 vcc_lo, v2, v5
v_dual_cndmask_b32 v2, v2, v7 :: v_dual_cndmask_b32 v3, v3, v4
v_lshl_add_u32 v7, v1, 1, v1
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v2, v5
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
v_ashrrev_i32_e32 v3, 31, v7
v_xor_b32_e32 v4, v2, v6
v_add_co_u32 v2, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_sub_nc_u32_e32 v4, v4, v6
s_clause 0x2
global_store_b8 v[2:3], v4, off
global_store_b8 v[2:3], v4, off offset:1
global_store_b8 v[2:3], v4, off offset:2
s_cbranch_scc0 .LBB0_12
.LBB0_2:
s_clause 0x1
global_load_b128 v[2:5], v0, s[2:3]
global_load_b64 v[6:7], v0, s[2:3] offset:16
v_ashrrev_i32_e32 v8, 31, v1
s_mov_b32 s5, 0
s_mov_b32 s6, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v8, 22, v8
v_add_nc_u32_e32 v8, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 10, v8
v_mul_i32_i24_e32 v9, 0x400, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v1, v9
v_cvt_f64_i32_e32 v[8:9], v8
v_cvt_f64_i32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], 0.5
v_add_f64 v[10:11], v[10:11], 0.5
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], 2.0
v_add_f64 v[4:5], v[4:5], 2.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[2:3], v[10:11], v[6:7], v[2:3]
v_fma_f64 v[4:5], v[8:9], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[2:3], v[2:3], 20
v_ldexp_f64 v[4:5], v[4:5], 20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f64_e32 v3, v[2:3]
v_cvt_u32_f64_e32 v4, v[4:5]
v_mov_b32_e32 v2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s7, exec_lo, s8
s_or_b32 s5, s7, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_1
.LBB0_4:
s_mov_b32 s7, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_le_u32_e64 v3, v4
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB0_8
s_mov_b32 s9, exec_lo
v_cmpx_gt_u32_e64 v4, v3
s_xor_b32 s9, exec_lo, s9
s_mov_b32 s7, exec_lo
v_sub_nc_u32_e32 v4, v4, v3
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s7, s7, exec_lo
.LBB0_8:
s_and_not1_saveexec_b32 s8, s8
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v2, 1, v2
s_or_b32 s7, s7, exec_lo
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v5, s6
s_mov_b32 s8, -1
s_and_saveexec_b32 s9, s7
s_cbranch_execz .LBB0_3
s_add_i32 s6, s6, 1
v_mov_b32_e32 v5, 0x3e9
s_cmpk_eq_i32 s6, 0x3e9
s_cselect_b32 s7, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s8, s7, exec_lo
s_branch .LBB0_3
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6euclidPhPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6euclidPhPdi, .Lfunc_end0-_Z6euclidPhPdi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10mandelbrotPhPdi
.globl _Z10mandelbrotPhPdi
.p2align 8
.type _Z10mandelbrotPhPdi,@function
_Z10mandelbrotPhPdi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 8, v0
v_mov_b32_e32 v12, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v11, s4, 16, v0
s_mov_b32 s4, 0
s_branch .LBB1_2
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v11, 1, v11
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s4, 0x100
s_cbranch_scc0 .LBB1_30
.LBB1_2:
s_clause 0x1
global_load_b64 v[0:1], v12, s[2:3] offset:16
global_load_b128 v[2:5], v12, s[2:3]
v_ashrrev_i32_e32 v6, 31, v11
s_mov_b32 s5, 0
s_mov_b32 s6, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v6, 22, v6
v_add_nc_u32_e32 v6, v11, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 10, v6
v_mul_i32_i24_e32 v7, 0x400, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v11, v7
v_cvt_f64_i32_e32 v[6:7], v6
v_cvt_f64_i32_e32 v[8:9], v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], v[6:7], 0.5
v_add_f64 v[8:9], v[8:9], 0.5
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[6:7], v[6:7], v[0:1]
v_mul_f64 v[8:9], v[8:9], v[0:1]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[0:1], v[6:7], 0x3f500000, v[4:5]
v_fma_f64 v[2:3], v[8:9], 0x3f500000, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v8, v3
v_dual_mov_b32 v4, v0 :: v_dual_mov_b32 v7, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_4
.p2align 6
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, exec_lo, s7
s_or_b32 s5, s8, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_6
.LBB1_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[9:10], v[4:5], v[4:5]
v_mov_b32_e32 v6, s6
s_or_b32 s7, s7, exec_lo
s_mov_b32 s8, exec_lo
v_fma_f64 v[13:14], v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f64_e32 4.0, v[13:14]
s_cbranch_execz .LBB1_3
v_mul_f64 v[13:14], v[7:8], v[7:8]
v_add_f64 v[6:7], v[7:8], v[7:8]
s_add_i32 s6, s6, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmpk_eq_i32 s6, 0x3e8
s_cselect_b32 s9, -1, 0
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s9, s9, exec_lo
s_or_b32 s7, s7, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[9:10], v[13:14], -v[9:10]
v_fma_f64 v[4:5], v[6:7], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[2:3], v[9:10]
v_dual_mov_b32 v6, 0x3e8 :: v_dual_mov_b32 v7, v8
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v8, v9
s_branch .LBB1_3
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v0, v11, 1, v11
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_cmpx_ne_u32_e32 0x3e8, v6
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB1_28
v_mul_hi_u32 v2, v6, 0x2fa0be83
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 3, v2
v_mad_u64_u32 v[2:3], null, v4, 0xd5, v[6:7]
v_and_b32_e32 v4, 0xff, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v2, 6
v_and_b32_e32 v2, 0xfe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v3, 0xff, v2
v_mul_u32_u24_e32 v2, 0xff, v2
v_mul_u32_u24_e32 v3, 0xff, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 8, v2
v_lshrrev_b32_e32 v3, 8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v2, 0xff, v2
v_xor_b32_e32 v5, 0xff, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_u32_u24_e32 v3, 0xff, v2
v_mul_u32_u24_e32 v2, 0xff, v5
v_cmpx_lt_i16_e32 1, v4
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB1_21
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 2, v4
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_18
s_mov_b32 s8, exec_lo
v_cmpx_lt_i16_e32 3, v4
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB1_15
s_mov_b32 s9, exec_lo
v_cmpx_ne_u16_e32 4, v4
s_xor_b32 s9, exec_lo, s9
v_mov_b32_e32 v2, 0xff
v_lshrrev_b32_e32 v3, 8, v3
s_clause 0x1
global_store_b16 v[0:1], v2, off
global_store_b8 v[0:1], v3, off offset:2
s_and_not1_saveexec_b32 s9, s9
v_lshrrev_b32_e32 v2, 8, v2
v_mov_b32_e32 v3, 0xffffff00
s_clause 0x1
global_store_b8 v[0:1], v2, off
global_store_b16 v[0:1], v3, off offset:1
s_or_b32 exec_lo, exec_lo, s9
.LBB1_15:
s_and_not1_saveexec_b32 s8, s8
v_mov_b32_e32 v2, 0
v_lshrrev_b32_e32 v3, 8, v3
v_mov_b32_e32 v4, 0xff
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v3, off offset:1
global_store_b8 v[0:1], v4, off offset:2
s_or_b32 exec_lo, exec_lo, s8
.LBB1_18:
s_and_not1_saveexec_b32 s7, s7
v_mov_b32_e32 v3, 0xffffff00
v_lshrrev_b32_e32 v2, 8, v2
s_clause 0x1
global_store_b16 v[0:1], v3, off
global_store_b8 v[0:1], v2, off offset:2
s_or_b32 exec_lo, exec_lo, s7
.LBB1_21:
s_and_not1_saveexec_b32 s6, s6
s_cbranch_execz .LBB1_27
s_mov_b32 s7, exec_lo
v_cmpx_lt_i16_e32 0, v4
s_xor_b32 s7, exec_lo, s7
v_lshrrev_b32_e32 v2, 8, v3
v_mov_b32_e32 v3, 0xff
s_clause 0x1
global_store_b8 v[0:1], v2, off
global_store_b16 v[0:1], v3, off offset:1
s_and_not1_saveexec_b32 s7, s7
v_dual_mov_b32 v3, 0xff :: v_dual_mov_b32 v4, 0
v_lshrrev_b32_e32 v2, 8, v2
s_clause 0x2
global_store_b8 v[0:1], v3, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v4, off offset:2
s_or_b32 exec_lo, exec_lo, s7
.LBB1_27:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
.LBB1_28:
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB1_1
v_mov_b32_e32 v2, 0
s_clause 0x1
global_store_b16 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:2
s_branch .LBB1_1
.LBB1_30:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10mandelbrotPhPdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10mandelbrotPhPdi, .Lfunc_end1-_Z10mandelbrotPhPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6euclidPhPdi
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z6euclidPhPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10mandelbrotPhPdi
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10mandelbrotPhPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdint.h>
#include <unistd.h>
#include <png.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define rel params[0]
#define img params[1]
#define scl params[2]
__device__ void writeHSV(uint8_t *pixel, int theta) {
unsigned char region, remainder, q, t;
region = theta / 43;
remainder = (theta - (region * 43)) * 6;
q = (255 * (255 - ((255 * remainder) >> 8))) >> 8;
t = (255 * (255 - ((255 * (255 - remainder)) >> 8))) >> 8;
switch (region) {
case 0:
*pixel++ = 255;
*pixel++ = t;
*pixel++ = 0;
return;
case 1:
*pixel++ = q;
*pixel++ = 255;
*pixel++ = 0;
return;
case 2:
*pixel++ = 0;
*pixel++ = 255;
*pixel++ = t;
return;
case 3:
*pixel++ = 0;
*pixel++ = q;
*pixel++ = 255;
return;
case 4:
*pixel++ = t;
*pixel++ = 0;
*pixel++ = 255;
return;
default:
*pixel++ = 255;
*pixel++ = 0;
*pixel++ = q;
return;
}
}
__global__ void euclid (uint8_t *gpu, double *params, int streamNumber ) {
int index, pos;
int c, t;
uint32_t x, y;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
x = (uint32_t) (((rel + 2.0) + (double) (.5 + (index % 1024)) * scl) * 1048576);
y = (uint32_t) (((img + 2.0) + (double) (.5 + (index / 1024)) * scl) * 1048576);
c = 0;
t = 1;
while (1) {
if (x > y) {
x -= y;
c++;
} else if (y > x) {
y -= x;
} else {
break;
}
t++;
if (t > 1000) break;
}
uint8_t *pixel = (gpu + index++ * 3);
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
*pixel++ = (255 * c) / t;
}
}
__global__ void mandelbrot (uint8_t *gpu, double *params, int streamNumber ) {
int index, c, pos;
double cr, ci, zr, zi, t;
index = streamNumber * 65536 + threadIdx.x * 256;
for (pos = 0; pos < 256; pos++) {
c = 0;
cr = rel + (double) (.5 + (index % 1024)) * scl / 1024.0;
ci = img + (double) (.5 + (index / 1024)) * scl / 1024.0;
zr = cr;
zi = ci;
while (++c < 1000 && zr * zr + zi * zi < 4) {
t = zr;
zr = zr * zr - zi * zi + cr;
zi = 2 * t * zi + ci;
}
uint8_t *pixel = (gpu + index * 3);
if (c == 1000) {
*pixel++ = 0;
*pixel++ = 0;
*pixel++ = 0;
} else {
writeHSV(pixel, c);
}
index ++;
}
}
// GPU variables
double *gpu_params;
uint8_t *gpu;
// Host variables
hipStream_t streams[16];
double params[3];
png_byte ** row_pointers;
void (*kernel) (uint8_t *, double *, int);
// reads parameters from stdin and writes them to params array
// initializes rel, img, and scl macros
void readParams() {
rel = -2.0;
img = -2.0;
scl = 4.0;
char c = getchar();
switch (c) {
case 'm':
kernel = mandelbrot;
break;
default:
kernel = euclid;
}
while ((c = getchar()) != '@') {
scl /= 3.0;
switch (c) {
case '3':
case '6':
case '9':
rel += scl;
case '2':
case '5':
case '8':
rel += scl;
default:
break;
}
switch (c) {
case '7':
case '8':
case '9':
img += scl;
case '4':
case '5':
case '6':
img += scl;
default:
break;
}
}
}
// begins computation
void computeKernel() {
// setup params
hipMemcpy( gpu_params, params, 3 * sizeof(double), hipMemcpyHostToDevice);
// initialize streams
int i, r;
for (i = 0; i < 16; i++) {
hipStreamCreate((streams + i));
}
// execute kernels in the streams
for (i = 0; i < 16; i++) {
kernel<<<1, 256, 0, streams[i]>>>( gpu, gpu_params, i );
}
// setup asynchronous memory copy after completion
for (i = 0; i < 16; i++) {
for (r = 0; r < 64; r++) {
hipMemcpyAsync(row_pointers[64 * i + r], (gpu + i * 65536 * 3 + r * 1024 * 3), sizeof(uint8_t) * 1024 * 3, hipMemcpyDeviceToHost, streams[i]);
}
}
hipDeviceSynchronize();
}
extern void writePngOutput();
int main(int argc, char **argv) {
// Initialize memory
hipMalloc( (void**) &gpu, 1024 * 1024 * sizeof(uint8_t) * 3 );
hipMalloc( (void**) &gpu_params, 3 * sizeof(double) );
row_pointers = (png_byte **) malloc (1024 * sizeof (png_byte *));
for (int y = 0; y < 1024; y++) {
row_pointers[y] = (png_byte *) malloc (sizeof (uint8_t) * 1024 * 3);
}
// do the process
while (1) {
readParams();
computeKernel();
writePngOutput();
}
}
size_t pngBufferFill = 0;
extern void writeFn(png_structp png_ptr, png_bytep data, uint32_t size);
extern void flushFn(png_structp png_ptr);
void writePngOutput() {
png_structp png_ptr = png_create_write_struct (PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
png_infop info_ptr = png_create_info_struct (png_ptr);
png_set_IHDR (png_ptr,
info_ptr,
1024, // width
1024, // height
8, // depth
PNG_COLOR_TYPE_RGB,
PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_DEFAULT,
PNG_FILTER_TYPE_DEFAULT);
png_set_write_fn(png_ptr, NULL, (png_rw_ptr) writeFn, (png_flush_ptr) flushFn);
png_init_io (png_ptr, stdout);
png_set_rows (png_ptr, info_ptr, row_pointers);
png_write_png (png_ptr, info_ptr, PNG_TRANSFORM_IDENTITY, NULL);
write(2, &pngBufferFill, 4);
pngBufferFill = 0;
png_destroy_write_struct (&png_ptr, &info_ptr);
}
void writeFn(png_structp png_ptr, png_bytep data, uint32_t size) {
write(1, data, size);
pngBufferFill += size;
}
void flushFn(png_structp png_ptr) {
fflush(stdout);
} | .text
.file "parallelbrot.hip"
.globl _Z21__device_stub__euclidPhPdi # -- Begin function _Z21__device_stub__euclidPhPdi
.p2align 4, 0x90
.type _Z21__device_stub__euclidPhPdi,@function
_Z21__device_stub__euclidPhPdi: # @_Z21__device_stub__euclidPhPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6euclidPhPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__euclidPhPdi, .Lfunc_end0-_Z21__device_stub__euclidPhPdi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mandelbrotPhPdi # -- Begin function _Z25__device_stub__mandelbrotPhPdi
.p2align 4, 0x90
.type _Z25__device_stub__mandelbrotPhPdi,@function
_Z25__device_stub__mandelbrotPhPdi: # @_Z25__device_stub__mandelbrotPhPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mandelbrotPhPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__mandelbrotPhPdi, .Lfunc_end1-_Z25__device_stub__mandelbrotPhPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10readParamsv
.LCPI2_0:
.quad 0x4008000000000000 # double 3
.text
.globl _Z10readParamsv
.p2align 4, 0x90
.type _Z10readParamsv,@function
_Z10readParamsv: # @_Z10readParamsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $-4611686018427387904, %rax # imm = 0xC000000000000000
movq %rax, params(%rip)
movq %rax, params+8(%rip)
movabsq $4616189618054758400, %rax # imm = 0x4010000000000000
movq %rax, params+16(%rip)
movq stdin(%rip), %rdi
callq getc
cmpb $109, %al
movl $_Z10mandelbrotPhPdi, %eax
movl $_Z6euclidPhPdi, %ecx
cmoveq %rax, %rcx
movq %rcx, kernel(%rip)
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
movsd params+8(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params+8(%rip)
.LBB2_8: # in Loop: Header=BB2_1 Depth=1
addsd params+8(%rip), %xmm0
movsd %xmm0, params+8(%rip)
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
callq getc
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $1073741824, %eax # imm = 0x40000000
je .LBB2_9
# %bb.2: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
sarl $24, %eax
movsd params+16(%rip), %xmm0 # xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, params+16(%rip)
leal -50(%rax), %ecx
cmpl $7, %ecx
ja .LBB2_1
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
jmpq *.LJTI2_0(,%rcx,8)
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movsd params(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params(%rip)
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
movsd params(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params(%rip)
leal -52(%rax), %ecx
cmpl $3, %ecx
jb .LBB2_8
# %bb.6: # in Loop: Header=BB2_1 Depth=1
addl $-55, %eax
cmpl $2, %eax
jbe .LBB2_7
jmp .LBB2_1
.LBB2_9: # %._crit_edge
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10readParamsv, .Lfunc_end2-_Z10readParamsv
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI2_0:
.quad .LBB2_5
.quad .LBB2_4
.quad .LBB2_8
.quad .LBB2_5
.quad .LBB2_4
.quad .LBB2_7
.quad .LBB2_5
.quad .LBB2_4
# -- End function
.text
.globl _Z13computeKernelv # -- Begin function _Z13computeKernelv
.p2align 4, 0x90
.type _Z13computeKernelv,@function
_Z13computeKernelv: # @_Z13computeKernelv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq gpu_params(%rip), %rdi
movl $params, %esi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq streams(%rbx), %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $128, %rbx
jne .LBB3_1
# %bb.2: # %.preheader23.preheader
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 255(%rbx), %r15
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
incq %r14
cmpq $16, %r14
je .LBB3_6
.LBB3_3: # %.preheader23
# =>This Inner Loop Header: Depth=1
movq streams(,%r14,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq kernel(%rip), %rax
movq gpu(%rip), %rdi
movq gpu_params(%rip), %rsi
movl %r14d, %edx
callq *(%rax)
jmp .LBB3_5
.LBB3_6: # %.preheader.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq row_pointers(%rip), %rax
addq %r14, %rax
movq (%rax,%r13,8), %rdi
movq gpu(%rip), %rsi
addq %r12, %rsi
movq streams(,%r15,8), %r8
movl $3072, %edx # imm = 0xC00
movl $2, %ecx
callq hipMemcpyAsync
incq %r13
addq $3072, %r12 # imm = 0xC00
cmpq $64, %r13
jne .LBB3_8
# %bb.9: # in Loop: Header=BB3_7 Depth=1
incq %r15
addq $512, %r14 # imm = 0x200
addq $196608, %rbx # imm = 0x30000
cmpq $16, %r15
jne .LBB3_7
# %bb.10:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipDeviceSynchronize # TAILCALL
.Lfunc_end3:
.size _Z13computeKernelv, .Lfunc_end3-_Z13computeKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $gpu, %edi
movl $3145728, %esi # imm = 0x300000
callq hipMalloc
movl $gpu_params, %edi
movl $24, %esi
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, row_pointers(%rip)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $3072, %edi # imm = 0xC00
callq malloc
movq row_pointers(%rip), %rcx
movq %rax, (%rcx,%rbx,8)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_1
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
callq _Z10readParamsv
callq _Z13computeKernelv
callq _Z14writePngOutputv
jmp .LBB4_2
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z14writePngOutputv # -- Begin function _Z14writePngOutputv
.p2align 4, 0x90
.type _Z14writePngOutputv,@function
_Z14writePngOutputv: # @_Z14writePngOutputv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.L.str, %edi
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq png_create_write_struct
movq %rax, 8(%rsp)
movq %rax, %rdi
callq png_create_info_struct
movq %rax, 16(%rsp)
movq 8(%rsp), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %rax, %rsi
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
movl $8, %r8d
movl $2, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq png_set_IHDR
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq 8(%rsp), %rdi
movl $_Z7writeFnP14png_struct_defPhj, %edx
movl $_Z7flushFnP14png_struct_def, %ecx
xorl %esi, %esi
callq png_set_write_fn
movq 8(%rsp), %rdi
movq stdout(%rip), %rsi
callq png_init_io
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq row_pointers(%rip), %rdx
callq png_set_rows
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
xorl %edx, %edx
xorl %ecx, %ecx
callq png_write_png
movl $pngBufferFill, %esi
movl $4, %edx
movl $2, %edi
callq write
movq $0, pngBufferFill(%rip)
leaq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
callq png_destroy_write_struct
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z14writePngOutputv, .Lfunc_end5-_Z14writePngOutputv
.cfi_endproc
# -- End function
.globl _Z7writeFnP14png_struct_defPhj # -- Begin function _Z7writeFnP14png_struct_defPhj
.p2align 4, 0x90
.type _Z7writeFnP14png_struct_defPhj,@function
_Z7writeFnP14png_struct_defPhj: # @_Z7writeFnP14png_struct_defPhj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %ebx
movl $1, %edi
movq %rbx, %rdx
callq write
addq %rbx, pngBufferFill(%rip)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7writeFnP14png_struct_defPhj, .Lfunc_end6-_Z7writeFnP14png_struct_defPhj
.cfi_endproc
# -- End function
.globl _Z7flushFnP14png_struct_def # -- Begin function _Z7flushFnP14png_struct_def
.p2align 4, 0x90
.type _Z7flushFnP14png_struct_def,@function
_Z7flushFnP14png_struct_def: # @_Z7flushFnP14png_struct_def
.cfi_startproc
# %bb.0:
movq stdout(%rip), %rdi
jmp fflush # TAILCALL
.Lfunc_end7:
.size _Z7flushFnP14png_struct_def, .Lfunc_end7-_Z7flushFnP14png_struct_def
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6euclidPhPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mandelbrotPhPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6euclidPhPdi,@object # @_Z6euclidPhPdi
.section .rodata,"a",@progbits
.globl _Z6euclidPhPdi
.p2align 3, 0x0
_Z6euclidPhPdi:
.quad _Z21__device_stub__euclidPhPdi
.size _Z6euclidPhPdi, 8
.type _Z10mandelbrotPhPdi,@object # @_Z10mandelbrotPhPdi
.globl _Z10mandelbrotPhPdi
.p2align 3, 0x0
_Z10mandelbrotPhPdi:
.quad _Z25__device_stub__mandelbrotPhPdi
.size _Z10mandelbrotPhPdi, 8
.type gpu_params,@object # @gpu_params
.bss
.globl gpu_params
.p2align 3, 0x0
gpu_params:
.quad 0
.size gpu_params, 8
.type gpu,@object # @gpu
.globl gpu
.p2align 3, 0x0
gpu:
.quad 0
.size gpu, 8
.type streams,@object # @streams
.globl streams
.p2align 4, 0x0
streams:
.zero 128
.size streams, 128
.type params,@object # @params
.globl params
.p2align 4, 0x0
params:
.zero 24
.size params, 24
.type row_pointers,@object # @row_pointers
.globl row_pointers
.p2align 3, 0x0
row_pointers:
.quad 0
.size row_pointers, 8
.type kernel,@object # @kernel
.globl kernel
.p2align 3, 0x0
kernel:
.quad 0
.size kernel, 8
.type pngBufferFill,@object # @pngBufferFill
.globl pngBufferFill
.p2align 3, 0x0
pngBufferFill:
.quad 0 # 0x0
.size pngBufferFill, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "1.6.43"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6euclidPhPdi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10mandelbrotPhPdi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__euclidPhPdi
.addrsig_sym _Z25__device_stub__mandelbrotPhPdi
.addrsig_sym _Z7writeFnP14png_struct_defPhj
.addrsig_sym _Z7flushFnP14png_struct_def
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6euclidPhPdi
.addrsig_sym _Z10mandelbrotPhPdi
.addrsig_sym gpu_params
.addrsig_sym gpu
.addrsig_sym streams
.addrsig_sym params
.addrsig_sym pngBufferFill
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138b38_00000000-6_parallelbrot.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z7writeFnP14png_struct_defPhj
.type _Z7writeFnP14png_struct_defPhj, @function
_Z7writeFnP14png_struct_defPhj:
.LFB2075:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edx, %ebx
movq %rbx, %rdx
movl $1, %edi
call write@PLT
addq %rbx, pngBufferFill(%rip)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z7writeFnP14png_struct_defPhj, .-_Z7writeFnP14png_struct_defPhj
.globl _Z7flushFnP14png_struct_def
.type _Z7flushFnP14png_struct_def, @function
_Z7flushFnP14png_struct_def:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq stdout(%rip), %rdi
call fflush@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z7flushFnP14png_struct_def, .-_Z7flushFnP14png_struct_def
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2079:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8writeHSVPhi
.type _Z8writeHSVPhi, @function
_Z8writeHSVPhi:
.LFB2070:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z8writeHSVPhi, .-_Z8writeHSVPhi
.globl _Z10readParamsv
.type _Z10readParamsv, @function
_Z10readParamsv:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movsd .LC0(%rip), %xmm0
movsd %xmm0, params(%rip)
movsd %xmm0, 8+params(%rip)
movq .LC1(%rip), %rax
movq %rax, 16+params(%rip)
movq stdin(%rip), %rdi
call getc@PLT
cmpb $109, %al
leaq _Z6euclidPhPdi(%rip), %rax
leaq _Z10mandelbrotPhPdi(%rip), %rdx
cmove %rdx, %rax
movq %rax, kernel(%rip)
movabsq $82190693199511552, %rbp
movabsq $164381386399023104, %r12
jmp .L11
.L12:
cmpb $54, %cl
jle .L17
subl $55, %ecx
cmpb $2, %cl
ja .L17
.L20:
movapd %xmm0, %xmm1
addsd 8+params(%rip), %xmm1
movsd %xmm1, 8+params(%rip)
.L15:
addsd 8+params(%rip), %xmm0
movsd %xmm0, 8+params(%rip)
.L11:
movl $1, %ebx
.L17:
movq stdin(%rip), %rdi
call getc@PLT
movl %eax, %ecx
cmpb $64, %al
je .L26
movsd 16+params(%rip), %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, 16+params(%rip)
cmpb $57, %cl
ja .L12
movq %rbx, %rax
salq %cl, %rax
testq %rbp, %rax
jne .L13
testq %r12, %rax
je .L14
movapd %xmm0, %xmm1
addsd params(%rip), %xmm1
movsd %xmm1, params(%rip)
.L13:
movapd %xmm0, %xmm1
addsd params(%rip), %xmm1
movsd %xmm1, params(%rip)
.L14:
cmpb $54, %cl
jg .L20
cmpb $51, %cl
jg .L15
jmp .L17
.L26:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10readParamsv, .-_Z10readParamsv
.globl _Z13computeKernelv
.type _Z13computeKernelv, @function
_Z13computeKernelv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl $1, %ecx
movl $24, %edx
leaq params(%rip), %rsi
movq gpu_params(%rip), %rdi
call cudaMemcpy@PLT
leaq streams(%rip), %rbp
leaq 128(%rbp), %r13
movq %rbp, %rbx
.L28:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L28
movl $0, %ebx
leaq streams(%rip), %r12
jmp .L30
.L29:
addq $1, %rbx
cmpq $16, %rbx
je .L38
.L30:
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq (%r12,%rbx,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L29
movl %ebx, %edx
movq gpu_params(%rip), %rsi
movq gpu(%rip), %rdi
call *kernel(%rip)
jmp .L29
.L38:
movl $512, %r12d
.L31:
leaq -512(%r12), %rbx
.L32:
leaq (%rbx,%rbx,2), %rsi
salq $7, %rsi
addq gpu(%rip), %rsi
movq row_pointers(%rip), %rax
movq (%rax,%rbx), %rdi
movq 0(%rbp), %r8
movl $2, %ecx
movl $3072, %edx
call cudaMemcpyAsync@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L32
addq $8, %rbp
addq $512, %r12
cmpq %r13, %rbp
jne .L31
call cudaDeviceSynchronize@PLT
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z13computeKernelv, .-_Z13computeKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "1.6.43"
.text
.globl _Z14writePngOutputv
.type _Z14writePngOutputv, @function
_Z14writePngOutputv:
.LFB2074:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %ecx
movl $0, %edx
movl $0, %esi
leaq .LC3(%rip), %rdi
call png_create_write_struct@PLT
movq %rax, %rdi
movq %rax, 8(%rsp)
call png_create_info_struct@PLT
movq %rax, %rsi
movq %rax, 16(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 56
pushq $0
.cfi_def_cfa_offset 64
pushq $0
.cfi_def_cfa_offset 72
pushq $0
.cfi_def_cfa_offset 80
movl $2, %r9d
movl $8, %r8d
movl $1024, %ecx
movl $1024, %edx
movq 40(%rsp), %rdi
call png_set_IHDR@PLT
addq $32, %rsp
.cfi_def_cfa_offset 48
leaq _Z7flushFnP14png_struct_def(%rip), %rcx
leaq _Z7writeFnP14png_struct_defPhj(%rip), %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call png_set_write_fn@PLT
movq stdout(%rip), %rsi
movq 8(%rsp), %rdi
call png_init_io@PLT
movq row_pointers(%rip), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call png_set_rows@PLT
movl $0, %ecx
movl $0, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call png_write_png@PLT
movl $4, %edx
leaq pngBufferFill(%rip), %rsi
movl $2, %edi
call write@PLT
movq $0, pngBufferFill(%rip)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
call png_destroy_write_struct@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2074:
.size _Z14writePngOutputv, .-_Z14writePngOutputv
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $3145728, %esi
leaq gpu(%rip), %rdi
call cudaMalloc@PLT
movl $24, %esi
leaq gpu_params(%rip), %rdi
call cudaMalloc@PLT
movl $8192, %edi
call malloc@PLT
movq %rax, row_pointers(%rip)
movl $0, %ebx
.L44:
movq %rbx, %rbp
addq row_pointers(%rip), %rbp
movl $3072, %edi
call malloc@PLT
movq %rax, 0(%rbp)
addq $8, %rbx
cmpq $8192, %rbx
jne .L44
.L45:
call _Z10readParamsv
call _Z13computeKernelv
call _Z14writePngOutputv
jmp .L45
.cfi_endproc
.LFE2073:
.size main, .-main
.globl _Z28__device_stub__Z6euclidPhPdiPhPdi
.type _Z28__device_stub__Z6euclidPhPdiPhPdi, @function
_Z28__device_stub__Z6euclidPhPdiPhPdi:
.LFB2101:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L52
.L48:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6euclidPhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L48
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2101:
.size _Z28__device_stub__Z6euclidPhPdiPhPdi, .-_Z28__device_stub__Z6euclidPhPdiPhPdi
.globl _Z6euclidPhPdi
.type _Z6euclidPhPdi, @function
_Z6euclidPhPdi:
.LFB2102:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6euclidPhPdiPhPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2102:
.size _Z6euclidPhPdi, .-_Z6euclidPhPdi
.globl _Z33__device_stub__Z10mandelbrotPhPdiPhPdi
.type _Z33__device_stub__Z10mandelbrotPhPdiPhPdi, @function
_Z33__device_stub__Z10mandelbrotPhPdiPhPdi:
.LFB2103:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10mandelbrotPhPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z33__device_stub__Z10mandelbrotPhPdiPhPdi, .-_Z33__device_stub__Z10mandelbrotPhPdiPhPdi
.globl _Z10mandelbrotPhPdi
.type _Z10mandelbrotPhPdi, @function
_Z10mandelbrotPhPdi:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mandelbrotPhPdiPhPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z10mandelbrotPhPdi, .-_Z10mandelbrotPhPdi
.section .rodata.str1.1
.LC4:
.string "_Z10mandelbrotPhPdi"
.LC5:
.string "_Z6euclidPhPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2106:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mandelbrotPhPdi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6euclidPhPdi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl pngBufferFill
.bss
.align 8
.type pngBufferFill, @object
.size pngBufferFill, 8
pngBufferFill:
.zero 8
.globl kernel
.align 8
.type kernel, @object
.size kernel, 8
kernel:
.zero 8
.globl row_pointers
.align 8
.type row_pointers, @object
.size row_pointers, 8
row_pointers:
.zero 8
.globl params
.align 16
.type params, @object
.size params, 24
params:
.zero 24
.globl streams
.align 32
.type streams, @object
.size streams, 128
streams:
.zero 128
.globl gpu
.align 8
.type gpu, @object
.size gpu, 8
gpu:
.zero 8
.globl gpu_params
.align 8
.type gpu_params, @object
.size gpu_params, 8
gpu_params:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long -1073741824
.align 8
.LC1:
.long 0
.long 1074790400
.align 8
.LC2:
.long 0
.long 1074266112
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallelbrot.hip"
.globl _Z21__device_stub__euclidPhPdi # -- Begin function _Z21__device_stub__euclidPhPdi
.p2align 4, 0x90
.type _Z21__device_stub__euclidPhPdi,@function
_Z21__device_stub__euclidPhPdi: # @_Z21__device_stub__euclidPhPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6euclidPhPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__euclidPhPdi, .Lfunc_end0-_Z21__device_stub__euclidPhPdi
.cfi_endproc
# -- End function
.globl _Z25__device_stub__mandelbrotPhPdi # -- Begin function _Z25__device_stub__mandelbrotPhPdi
.p2align 4, 0x90
.type _Z25__device_stub__mandelbrotPhPdi,@function
_Z25__device_stub__mandelbrotPhPdi: # @_Z25__device_stub__mandelbrotPhPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10mandelbrotPhPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__mandelbrotPhPdi, .Lfunc_end1-_Z25__device_stub__mandelbrotPhPdi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10readParamsv
.LCPI2_0:
.quad 0x4008000000000000 # double 3
.text
.globl _Z10readParamsv
.p2align 4, 0x90
.type _Z10readParamsv,@function
_Z10readParamsv: # @_Z10readParamsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $-4611686018427387904, %rax # imm = 0xC000000000000000
movq %rax, params(%rip)
movq %rax, params+8(%rip)
movabsq $4616189618054758400, %rax # imm = 0x4010000000000000
movq %rax, params+16(%rip)
movq stdin(%rip), %rdi
callq getc
cmpb $109, %al
movl $_Z10mandelbrotPhPdi, %eax
movl $_Z6euclidPhPdi, %ecx
cmoveq %rax, %rcx
movq %rcx, kernel(%rip)
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_1 Depth=1
movsd params+8(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params+8(%rip)
.LBB2_8: # in Loop: Header=BB2_1 Depth=1
addsd params+8(%rip), %xmm0
movsd %xmm0, params+8(%rip)
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq stdin(%rip), %rdi
callq getc
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $1073741824, %eax # imm = 0x40000000
je .LBB2_9
# %bb.2: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
sarl $24, %eax
movsd params+16(%rip), %xmm0 # xmm0 = mem[0],zero
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, params+16(%rip)
leal -50(%rax), %ecx
cmpl $7, %ecx
ja .LBB2_1
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_1 Depth=1
jmpq *.LJTI2_0(,%rcx,8)
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movsd params(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params(%rip)
.LBB2_5: # in Loop: Header=BB2_1 Depth=1
movsd params(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, params(%rip)
leal -52(%rax), %ecx
cmpl $3, %ecx
jb .LBB2_8
# %bb.6: # in Loop: Header=BB2_1 Depth=1
addl $-55, %eax
cmpl $2, %eax
jbe .LBB2_7
jmp .LBB2_1
.LBB2_9: # %._crit_edge
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10readParamsv, .Lfunc_end2-_Z10readParamsv
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI2_0:
.quad .LBB2_5
.quad .LBB2_4
.quad .LBB2_8
.quad .LBB2_5
.quad .LBB2_4
.quad .LBB2_7
.quad .LBB2_5
.quad .LBB2_4
# -- End function
.text
.globl _Z13computeKernelv # -- Begin function _Z13computeKernelv
.p2align 4, 0x90
.type _Z13computeKernelv,@function
_Z13computeKernelv: # @_Z13computeKernelv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq gpu_params(%rip), %rdi
movl $params, %esi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq streams(%rbx), %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $128, %rbx
jne .LBB3_1
# %bb.2: # %.preheader23.preheader
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 255(%rbx), %r15
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
incq %r14
cmpq $16, %r14
je .LBB3_6
.LBB3_3: # %.preheader23
# =>This Inner Loop Header: Depth=1
movq streams(,%r14,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq kernel(%rip), %rax
movq gpu(%rip), %rdi
movq gpu_params(%rip), %rsi
movl %r14d, %edx
callq *(%rax)
jmp .LBB3_5
.LBB3_6: # %.preheader.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
movq row_pointers(%rip), %rax
addq %r14, %rax
movq (%rax,%r13,8), %rdi
movq gpu(%rip), %rsi
addq %r12, %rsi
movq streams(,%r15,8), %r8
movl $3072, %edx # imm = 0xC00
movl $2, %ecx
callq hipMemcpyAsync
incq %r13
addq $3072, %r12 # imm = 0xC00
cmpq $64, %r13
jne .LBB3_8
# %bb.9: # in Loop: Header=BB3_7 Depth=1
incq %r15
addq $512, %r14 # imm = 0x200
addq $196608, %rbx # imm = 0x30000
cmpq $16, %r15
jne .LBB3_7
# %bb.10:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipDeviceSynchronize # TAILCALL
.Lfunc_end3:
.size _Z13computeKernelv, .Lfunc_end3-_Z13computeKernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $gpu, %edi
movl $3145728, %esi # imm = 0x300000
callq hipMalloc
movl $gpu_params, %edi
movl $24, %esi
callq hipMalloc
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, row_pointers(%rip)
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $3072, %edi # imm = 0xC00
callq malloc
movq row_pointers(%rip), %rcx
movq %rax, (%rcx,%rbx,8)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB4_1
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
callq _Z10readParamsv
callq _Z13computeKernelv
callq _Z14writePngOutputv
jmp .LBB4_2
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.globl _Z14writePngOutputv # -- Begin function _Z14writePngOutputv
.p2align 4, 0x90
.type _Z14writePngOutputv,@function
_Z14writePngOutputv: # @_Z14writePngOutputv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.L.str, %edi
xorl %esi, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq png_create_write_struct
movq %rax, 8(%rsp)
movq %rax, %rdi
callq png_create_info_struct
movq %rax, 16(%rsp)
movq 8(%rsp), %rdi
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %rax, %rsi
movl $1024, %edx # imm = 0x400
movl $1024, %ecx # imm = 0x400
movl $8, %r8d
movl $2, %r9d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq png_set_IHDR
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movq 8(%rsp), %rdi
movl $_Z7writeFnP14png_struct_defPhj, %edx
movl $_Z7flushFnP14png_struct_def, %ecx
xorl %esi, %esi
callq png_set_write_fn
movq 8(%rsp), %rdi
movq stdout(%rip), %rsi
callq png_init_io
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
movq row_pointers(%rip), %rdx
callq png_set_rows
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
xorl %edx, %edx
xorl %ecx, %ecx
callq png_write_png
movl $pngBufferFill, %esi
movl $4, %edx
movl $2, %edi
callq write
movq $0, pngBufferFill(%rip)
leaq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
callq png_destroy_write_struct
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z14writePngOutputv, .Lfunc_end5-_Z14writePngOutputv
.cfi_endproc
# -- End function
.globl _Z7writeFnP14png_struct_defPhj # -- Begin function _Z7writeFnP14png_struct_defPhj
.p2align 4, 0x90
.type _Z7writeFnP14png_struct_defPhj,@function
_Z7writeFnP14png_struct_defPhj: # @_Z7writeFnP14png_struct_defPhj
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %ebx
movl $1, %edi
movq %rbx, %rdx
callq write
addq %rbx, pngBufferFill(%rip)
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z7writeFnP14png_struct_defPhj, .Lfunc_end6-_Z7writeFnP14png_struct_defPhj
.cfi_endproc
# -- End function
.globl _Z7flushFnP14png_struct_def # -- Begin function _Z7flushFnP14png_struct_def
.p2align 4, 0x90
.type _Z7flushFnP14png_struct_def,@function
_Z7flushFnP14png_struct_def: # @_Z7flushFnP14png_struct_def
.cfi_startproc
# %bb.0:
movq stdout(%rip), %rdi
jmp fflush # TAILCALL
.Lfunc_end7:
.size _Z7flushFnP14png_struct_def, .Lfunc_end7-_Z7flushFnP14png_struct_def
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6euclidPhPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10mandelbrotPhPdi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6euclidPhPdi,@object # @_Z6euclidPhPdi
.section .rodata,"a",@progbits
.globl _Z6euclidPhPdi
.p2align 3, 0x0
_Z6euclidPhPdi:
.quad _Z21__device_stub__euclidPhPdi
.size _Z6euclidPhPdi, 8
.type _Z10mandelbrotPhPdi,@object # @_Z10mandelbrotPhPdi
.globl _Z10mandelbrotPhPdi
.p2align 3, 0x0
_Z10mandelbrotPhPdi:
.quad _Z25__device_stub__mandelbrotPhPdi
.size _Z10mandelbrotPhPdi, 8
.type gpu_params,@object # @gpu_params
.bss
.globl gpu_params
.p2align 3, 0x0
gpu_params:
.quad 0
.size gpu_params, 8
.type gpu,@object # @gpu
.globl gpu
.p2align 3, 0x0
gpu:
.quad 0
.size gpu, 8
.type streams,@object # @streams
.globl streams
.p2align 4, 0x0
streams:
.zero 128
.size streams, 128
.type params,@object # @params
.globl params
.p2align 4, 0x0
params:
.zero 24
.size params, 24
.type row_pointers,@object # @row_pointers
.globl row_pointers
.p2align 3, 0x0
row_pointers:
.quad 0
.size row_pointers, 8
.type kernel,@object # @kernel
.globl kernel
.p2align 3, 0x0
kernel:
.quad 0
.size kernel, 8
.type pngBufferFill,@object # @pngBufferFill
.globl pngBufferFill
.p2align 3, 0x0
pngBufferFill:
.quad 0 # 0x0
.size pngBufferFill, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "1.6.43"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6euclidPhPdi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10mandelbrotPhPdi"
.size .L__unnamed_2, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__euclidPhPdi
.addrsig_sym _Z25__device_stub__mandelbrotPhPdi
.addrsig_sym _Z7writeFnP14png_struct_defPhj
.addrsig_sym _Z7flushFnP14png_struct_def
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6euclidPhPdi
.addrsig_sym _Z10mandelbrotPhPdi
.addrsig_sym gpu_params
.addrsig_sym gpu
.addrsig_sym streams
.addrsig_sym params
.addrsig_sym pngBufferFill
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} | code for sm_80
Function : _Z7sfilterPfS_lfffffffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR8, SR_CTAID.Y ; /* 0x00000000000879c3 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR12, c[0x0][0x170] ; /* 0x00005c00000c7ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULDC.64 UR14, c[0x0][0x160] ; /* 0x00005800000e7ab9 */
/* 0x000fe40000000a00 */
/*0040*/ UMOV UR11, UR12 ; /* 0x0000000c000b7c82 */
/* 0x000fc60008000000 */
/*0050*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0060*/ UIADD3 UR9, UP0, UR8, -0x1, URZ ; /* 0xffffffff08097890 */
/* 0x001fc8000ff1e03f */
/*0070*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fc800087fe43f */
/*0080*/ UIMAD UR10, UR5, UR12, URZ ; /* 0x0000000c050a72a4 */
/* 0x000fc6000f8e023f */
/*0090*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*00a0*/ UIMAD.WIDE.U32 UR6, UR9, UR12, UR4 ; /* 0x0000000c090672a5 */
/* 0x002fe4000f8e0004 */
/*00b0*/ UIMAD UR9, UR9, UR13, UR10 ; /* 0x0000000d090972a4 */
/* 0x000fe4000f8e020a */
/*00c0*/ ULEA UR10, UP0, UR6, UR14, 0x2 ; /* 0x0000000e060a7291 */
/* 0x000fe4000f80103f */
/*00d0*/ UIADD3 UR9, UR7, UR9, URZ ; /* 0x0000000907097290 */
/* 0x000fe4000fffe03f */
/*00e0*/ USHF.L.U32 UR7, UR11, 0x2, URZ ; /* 0x000000020b077899 */
/* 0x000fc4000800063f */
/*00f0*/ ULEA.HI.X UR9, UR6, UR15, UR9, 0x2, UP0 ; /* 0x0000000f06097291 */
/* 0x000fe200080f1409 */
/*0100*/ MOV R2, UR10 ; /* 0x0000000a00027c02 */
/* 0x000fe20008000f00 */
/*0110*/ UIADD3 UR14, UP0, UR7, UR10, URZ ; /* 0x0000000a070e7290 */
/* 0x000fe4000ff1e03f */
/*0120*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe40000000000 */
/*0130*/ MOV R3, UR9 ; /* 0x0000000900037c02 */
/* 0x000fe20008000f00 */
/*0140*/ USHF.L.U64.HI UR6, UR11, UR6, UR13 ; /* 0x000000060b067299 */
/* 0x000fc6000801020d */
/*0150*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0160*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x0000a2000c1e1900 */
/*0170*/ UIADD3.X UR9, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906097290 */
/* 0x000fc600087fe43f */
/*0180*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0a02007981 */
/* 0x0000e2000c1e1900 */
/*0190*/ MOV R4, UR14 ; /* 0x0000000e00047c02 */
/* 0x000fe40008000f00 */
/*01a0*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fe20008000f00 */
/*01b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040a020a7981 */
/* 0x000122000c1e1900 */
/*01c0*/ UIADD3 UR7, UP0, UR7, UR14, URZ ; /* 0x0000000e07077290 */
/* 0x000fc6000ff1e03f */
/*01d0*/ LDG.E R11, [R4.64+-0x4] ; /* 0xfffffc0a040b7981 */
/* 0x000f62000c1e1900 */
/*01e0*/ UIADD3.X UR6, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906067290 */
/* 0x000fc600087fe43f */
/*01f0*/ LDG.E R12, [R4.64] ; /* 0x0000000a040c7981 */
/* 0x000f62000c1e1900 */
/*0200*/ MOV R6, UR7 ; /* 0x0000000700067c02 */
/* 0x000fe40008000f00 */
/*0210*/ MOV R7, UR6 ; /* 0x0000000600077c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R13, [R4.64+0x4] ; /* 0x0000040a040d7981 */
/* 0x000f62000c1e1900 */
/*0230*/ UIMAD.WIDE.U32 UR4, UR8, UR12, UR4 ; /* 0x0000000c080472a5 */
/* 0x000fe4000f8e0004 */
/*0240*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0250*/ LDG.E R14, [R6.64+-0x4] ; /* 0xfffffc0a060e7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R15, [R6.64] ; /* 0x0000000a060f7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040a06107981 */
/* 0x000f62000c1e1900 */
/*0280*/ UIMAD UR8, UR8, UR13, UR5 ; /* 0x0000000d080872a4 */
/* 0x000fc4000f8e0205 */
/*0290*/ ULEA UR5, UP0, UR4, UR6, 0x2 ; /* 0x0000000604057291 */
/* 0x000fc8000f80103f */
/*02a0*/ ULEA.HI.X UR4, UR4, UR7, UR8, 0x2, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f1408 */
/*02b0*/ MOV R2, UR5 ; /* 0x0000000500027c02 */
/* 0x001fc80008000f00 */
/*02c0*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*02d0*/ FMUL R9, R8, c[0x0][0x17c] ; /* 0x00005f0008097a20 */
/* 0x004fc80000400000 */
/*02e0*/ FFMA R9, R0, c[0x0][0x178], R9 ; /* 0x00005e0000097a23 */
/* 0x008fc80000000009 */
/*02f0*/ FFMA R10, R10, c[0x0][0x180], R9 ; /* 0x000060000a0a7a23 */
/* 0x010fc80000000009 */
/*0300*/ FFMA R11, R11, c[0x0][0x184], R10 ; /* 0x000061000b0b7a23 */
/* 0x020fc8000000000a */
/*0310*/ FFMA R12, R12, c[0x0][0x188], R11 ; /* 0x000062000c0c7a23 */
/* 0x000fc8000000000b */
/*0320*/ FFMA R13, R13, c[0x0][0x18c], R12 ; /* 0x000063000d0d7a23 */
/* 0x000fc8000000000c */
/*0330*/ FFMA R14, R14, c[0x0][0x190], R13 ; /* 0x000064000e0e7a23 */
/* 0x000fc8000000000d */
/*0340*/ FFMA R15, R15, c[0x0][0x194], R14 ; /* 0x000065000f0f7a23 */
/* 0x000fc8000000000e */
/*0350*/ FFMA R15, R16, c[0x0][0x198], R15 ; /* 0x00006600100f7a23 */
/* 0x000fca000000000f */
/*0360*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c10190a */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} | .file "tmpxft_00168dfb_00000000-6_sfilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
.type _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff, @function
_Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 256(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7sfilterPfS_lfffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff, .-_Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
.globl _Z7sfilterPfS_lfffffffff
.type _Z7sfilterPfS_lfffffffff, @function
_Z7sfilterPfS_lfffffffff:
.LFB2052:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sfilterPfS_lfffffffff, .-_Z7sfilterPfS_lfffffffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sfilterPfS_lfffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sfilterPfS_lfffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} | #include <hip/hip_runtime.h>
// m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sfilterPfS_lfffffffff
.globl _Z7sfilterPfS_lfffffffff
.p2align 8
.type _Z7sfilterPfS_lfffffffff,@function
_Z7sfilterPfS_lfffffffff:
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s15, 0
s_add_u32 s3, s2, -1
s_addc_u32 s16, 0, -1
s_lshl_b64 s[12:13], s[14:15], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s3, s9
s_mul_hi_u32 s17, s3, s8
s_mul_i32 s18, s16, s8
s_add_i32 s15, s17, s15
s_mul_i32 s16, s3, s8
s_add_i32 s17, s15, s18
s_add_u32 s28, s4, s12
s_addc_u32 s29, s5, s13
s_add_u32 s30, s28, -4
s_addc_u32 s31, s29, -1
s_lshl_b64 s[12:13], s[16:17], 2
s_mul_i32 s3, s2, s9
s_add_u32 s18, s30, s12
s_addc_u32 s19, s31, s13
s_add_u32 s20, s28, s12
s_addc_u32 s21, s29, s13
s_add_u32 s33, s28, 4
s_mul_hi_u32 s24, s2, s8
s_addc_u32 s34, s29, 0
s_add_u32 s22, s33, s12
s_mul_i32 s16, s2, s8
s_addc_u32 s23, s34, s13
s_add_i32 s17, s24, s3
s_clause 0x1
s_load_b32 s35, s[18:19], 0x0
s_load_b32 s20, s[20:21], 0x0
s_lshl_b64 s[12:13], s[16:17], 2
s_load_b32 s21, s[22:23], 0x0
s_add_u32 s24, s30, s12
s_addc_u32 s25, s31, s13
s_add_u32 s14, s16, s14
s_addc_u32 s15, s17, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[14:15], 2
s_add_u32 s4, s4, s16
s_addc_u32 s5, s5, s17
s_add_u32 s26, s33, s12
s_addc_u32 s27, s34, s13
s_add_u32 s2, s2, 1
s_addc_u32 s3, 0, 0
s_mul_i32 s9, s2, s9
s_mul_hi_u32 s12, s2, s8
s_mul_i32 s3, s3, s8
s_add_i32 s9, s12, s9
s_load_b128 s[12:15], s[0:1], 0x20
s_mul_i32 s2, s2, s8
s_add_i32 s3, s9, s3
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, s20, s11
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s30, s2
s_addc_u32 s9, s31, s3
s_add_u32 s18, s28, s2
s_addc_u32 s19, s29, s3
s_clause 0x4
s_load_b32 s22, s[24:25], 0x0
s_load_b32 s23, s[4:5], 0x0
s_load_b32 s24, s[26:27], 0x0
s_load_b32 s8, s[8:9], 0x0
s_load_b32 s9, s[18:19], 0x0
s_load_b64 s[4:5], s[0:1], 0x30
v_fmac_f32_e64 v0, s35, s10
s_add_u32 s2, s33, s2
s_addc_u32 s3, s34, s3
s_load_b32 s0, s[0:1], 0x38
s_load_b32 s1, s[2:3], 0x0
v_fmac_f32_e64 v0, s21, s12
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s22, s13
v_fmac_f32_e64 v0, s23, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s24, s15
v_fmac_f32_e64 v0, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s9, s5
v_fmac_f32_e64 v0, s1, s0
s_add_u32 s0, s6, s16
s_addc_u32 s1, s7, s17
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sfilterPfS_lfffffffff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 36
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sfilterPfS_lfffffffff, .Lfunc_end0-_Z7sfilterPfS_lfffffffff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sfilterPfS_lfffffffff
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z7sfilterPfS_lfffffffff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// m0 m1 m2
// m3 m4 m5
// m6 m7 m8
__global__ void sfilter(float *src, float *dst, long ldc,
float m0, float m1, float m2, float m3, float m4, float m5, float m6, float m7, float m8)
{
long x = blockIdx.x;
long y = blockIdx.y;
float i0 = src[(x-1)+(y-1)*ldc]*m0;
float i1 = src[(x) +(y-1)*ldc]*m1;
float i2 = src[(x+1)+(y-1)*ldc]*m2;
float i3 = src[(x-1)+(y) *ldc]*m3;
float i4 = src[(x) + y * ldc]*m4;
float i5 = src[(x+1)+(y) *ldc]*m5;
float i6 = src[(x-1)+(y+1)*ldc]*m6;
float i7 = src[(x) +(y+1)*ldc]*m7;
float i8 = src[(x+1)+(y+1)*ldc]*m8;
dst[x+y*ldc] = i0 + i1 + i2 + i3 + i4 + i5 + i6 + i7 + i8;
} | .text
.file "sfilter.hip"
.globl _Z22__device_stub__sfilterPfS_lfffffffff # -- Begin function _Z22__device_stub__sfilterPfS_lfffffffff
.p2align 4, 0x90
.type _Z22__device_stub__sfilterPfS_lfffffffff,@function
_Z22__device_stub__sfilterPfS_lfffffffff: # @_Z22__device_stub__sfilterPfS_lfffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 224(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7sfilterPfS_lfffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__sfilterPfS_lfffffffff, .Lfunc_end0-_Z22__device_stub__sfilterPfS_lfffffffff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sfilterPfS_lfffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sfilterPfS_lfffffffff,@object # @_Z7sfilterPfS_lfffffffff
.section .rodata,"a",@progbits
.globl _Z7sfilterPfS_lfffffffff
.p2align 3, 0x0
_Z7sfilterPfS_lfffffffff:
.quad _Z22__device_stub__sfilterPfS_lfffffffff
.size _Z7sfilterPfS_lfffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sfilterPfS_lfffffffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sfilterPfS_lfffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sfilterPfS_lfffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sfilterPfS_lfffffffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR8, SR_CTAID.Y ; /* 0x00000000000879c3 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR12, c[0x0][0x170] ; /* 0x00005c00000c7ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULDC.64 UR14, c[0x0][0x160] ; /* 0x00005800000e7ab9 */
/* 0x000fe40000000a00 */
/*0040*/ UMOV UR11, UR12 ; /* 0x0000000c000b7c82 */
/* 0x000fc60008000000 */
/*0050*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e620000002500 */
/*0060*/ UIADD3 UR9, UP0, UR8, -0x1, URZ ; /* 0xffffffff08097890 */
/* 0x001fc8000ff1e03f */
/*0070*/ UIADD3.X UR5, URZ, -0x1, URZ, UP0, !UPT ; /* 0xffffffff3f057890 */
/* 0x000fc800087fe43f */
/*0080*/ UIMAD UR10, UR5, UR12, URZ ; /* 0x0000000c050a72a4 */
/* 0x000fc6000f8e023f */
/*0090*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*00a0*/ UIMAD.WIDE.U32 UR6, UR9, UR12, UR4 ; /* 0x0000000c090672a5 */
/* 0x002fe4000f8e0004 */
/*00b0*/ UIMAD UR9, UR9, UR13, UR10 ; /* 0x0000000d090972a4 */
/* 0x000fe4000f8e020a */
/*00c0*/ ULEA UR10, UP0, UR6, UR14, 0x2 ; /* 0x0000000e060a7291 */
/* 0x000fe4000f80103f */
/*00d0*/ UIADD3 UR9, UR7, UR9, URZ ; /* 0x0000000907097290 */
/* 0x000fe4000fffe03f */
/*00e0*/ USHF.L.U32 UR7, UR11, 0x2, URZ ; /* 0x000000020b077899 */
/* 0x000fc4000800063f */
/*00f0*/ ULEA.HI.X UR9, UR6, UR15, UR9, 0x2, UP0 ; /* 0x0000000f06097291 */
/* 0x000fe200080f1409 */
/*0100*/ MOV R2, UR10 ; /* 0x0000000a00027c02 */
/* 0x000fe20008000f00 */
/*0110*/ UIADD3 UR14, UP0, UR7, UR10, URZ ; /* 0x0000000a070e7290 */
/* 0x000fe4000ff1e03f */
/*0120*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe40000000000 */
/*0130*/ MOV R3, UR9 ; /* 0x0000000900037c02 */
/* 0x000fe20008000f00 */
/*0140*/ USHF.L.U64.HI UR6, UR11, UR6, UR13 ; /* 0x000000060b067299 */
/* 0x000fc6000801020d */
/*0150*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0160*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x0000a2000c1e1900 */
/*0170*/ UIADD3.X UR9, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906097290 */
/* 0x000fc600087fe43f */
/*0180*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0a02007981 */
/* 0x0000e2000c1e1900 */
/*0190*/ MOV R4, UR14 ; /* 0x0000000e00047c02 */
/* 0x000fe40008000f00 */
/*01a0*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fe20008000f00 */
/*01b0*/ LDG.E R10, [R2.64+0x4] ; /* 0x0000040a020a7981 */
/* 0x000122000c1e1900 */
/*01c0*/ UIADD3 UR7, UP0, UR7, UR14, URZ ; /* 0x0000000e07077290 */
/* 0x000fc6000ff1e03f */
/*01d0*/ LDG.E R11, [R4.64+-0x4] ; /* 0xfffffc0a040b7981 */
/* 0x000f62000c1e1900 */
/*01e0*/ UIADD3.X UR6, UR6, UR9, URZ, UP0, !UPT ; /* 0x0000000906067290 */
/* 0x000fc600087fe43f */
/*01f0*/ LDG.E R12, [R4.64] ; /* 0x0000000a040c7981 */
/* 0x000f62000c1e1900 */
/*0200*/ MOV R6, UR7 ; /* 0x0000000700067c02 */
/* 0x000fe40008000f00 */
/*0210*/ MOV R7, UR6 ; /* 0x0000000600077c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R13, [R4.64+0x4] ; /* 0x0000040a040d7981 */
/* 0x000f62000c1e1900 */
/*0230*/ UIMAD.WIDE.U32 UR4, UR8, UR12, UR4 ; /* 0x0000000c080472a5 */
/* 0x000fe4000f8e0004 */
/*0240*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0250*/ LDG.E R14, [R6.64+-0x4] ; /* 0xfffffc0a060e7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R15, [R6.64] ; /* 0x0000000a060f7981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040a06107981 */
/* 0x000f62000c1e1900 */
/*0280*/ UIMAD UR8, UR8, UR13, UR5 ; /* 0x0000000d080872a4 */
/* 0x000fc4000f8e0205 */
/*0290*/ ULEA UR5, UP0, UR4, UR6, 0x2 ; /* 0x0000000604057291 */
/* 0x000fc8000f80103f */
/*02a0*/ ULEA.HI.X UR4, UR4, UR7, UR8, 0x2, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f1408 */
/*02b0*/ MOV R2, UR5 ; /* 0x0000000500027c02 */
/* 0x001fc80008000f00 */
/*02c0*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*02d0*/ FMUL R9, R8, c[0x0][0x17c] ; /* 0x00005f0008097a20 */
/* 0x004fc80000400000 */
/*02e0*/ FFMA R9, R0, c[0x0][0x178], R9 ; /* 0x00005e0000097a23 */
/* 0x008fc80000000009 */
/*02f0*/ FFMA R10, R10, c[0x0][0x180], R9 ; /* 0x000060000a0a7a23 */
/* 0x010fc80000000009 */
/*0300*/ FFMA R11, R11, c[0x0][0x184], R10 ; /* 0x000061000b0b7a23 */
/* 0x020fc8000000000a */
/*0310*/ FFMA R12, R12, c[0x0][0x188], R11 ; /* 0x000062000c0c7a23 */
/* 0x000fc8000000000b */
/*0320*/ FFMA R13, R13, c[0x0][0x18c], R12 ; /* 0x000063000d0d7a23 */
/* 0x000fc8000000000c */
/*0330*/ FFMA R14, R14, c[0x0][0x190], R13 ; /* 0x000064000e0e7a23 */
/* 0x000fc8000000000d */
/*0340*/ FFMA R15, R15, c[0x0][0x194], R14 ; /* 0x000065000f0f7a23 */
/* 0x000fc8000000000e */
/*0350*/ FFMA R15, R16, c[0x0][0x198], R15 ; /* 0x00006600100f7a23 */
/* 0x000fca000000000f */
/*0360*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe2000c10190a */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ BRA 0x380; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sfilterPfS_lfffffffff
.globl _Z7sfilterPfS_lfffffffff
.p2align 8
.type _Z7sfilterPfS_lfffffffff,@function
_Z7sfilterPfS_lfffffffff:
s_load_b256 s[4:11], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s15, 0
s_add_u32 s3, s2, -1
s_addc_u32 s16, 0, -1
s_lshl_b64 s[12:13], s[14:15], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s3, s9
s_mul_hi_u32 s17, s3, s8
s_mul_i32 s18, s16, s8
s_add_i32 s15, s17, s15
s_mul_i32 s16, s3, s8
s_add_i32 s17, s15, s18
s_add_u32 s28, s4, s12
s_addc_u32 s29, s5, s13
s_add_u32 s30, s28, -4
s_addc_u32 s31, s29, -1
s_lshl_b64 s[12:13], s[16:17], 2
s_mul_i32 s3, s2, s9
s_add_u32 s18, s30, s12
s_addc_u32 s19, s31, s13
s_add_u32 s20, s28, s12
s_addc_u32 s21, s29, s13
s_add_u32 s33, s28, 4
s_mul_hi_u32 s24, s2, s8
s_addc_u32 s34, s29, 0
s_add_u32 s22, s33, s12
s_mul_i32 s16, s2, s8
s_addc_u32 s23, s34, s13
s_add_i32 s17, s24, s3
s_clause 0x1
s_load_b32 s35, s[18:19], 0x0
s_load_b32 s20, s[20:21], 0x0
s_lshl_b64 s[12:13], s[16:17], 2
s_load_b32 s21, s[22:23], 0x0
s_add_u32 s24, s30, s12
s_addc_u32 s25, s31, s13
s_add_u32 s14, s16, s14
s_addc_u32 s15, s17, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[16:17], s[14:15], 2
s_add_u32 s4, s4, s16
s_addc_u32 s5, s5, s17
s_add_u32 s26, s33, s12
s_addc_u32 s27, s34, s13
s_add_u32 s2, s2, 1
s_addc_u32 s3, 0, 0
s_mul_i32 s9, s2, s9
s_mul_hi_u32 s12, s2, s8
s_mul_i32 s3, s3, s8
s_add_i32 s9, s12, s9
s_load_b128 s[12:15], s[0:1], 0x20
s_mul_i32 s2, s2, s8
s_add_i32 s3, s9, s3
s_waitcnt lgkmcnt(0)
v_mul_f32_e64 v0, s20, s11
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s30, s2
s_addc_u32 s9, s31, s3
s_add_u32 s18, s28, s2
s_addc_u32 s19, s29, s3
s_clause 0x4
s_load_b32 s22, s[24:25], 0x0
s_load_b32 s23, s[4:5], 0x0
s_load_b32 s24, s[26:27], 0x0
s_load_b32 s8, s[8:9], 0x0
s_load_b32 s9, s[18:19], 0x0
s_load_b64 s[4:5], s[0:1], 0x30
v_fmac_f32_e64 v0, s35, s10
s_add_u32 s2, s33, s2
s_addc_u32 s3, s34, s3
s_load_b32 s0, s[0:1], 0x38
s_load_b32 s1, s[2:3], 0x0
v_fmac_f32_e64 v0, s21, s12
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s22, s13
v_fmac_f32_e64 v0, s23, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s24, s15
v_fmac_f32_e64 v0, s8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e64 v0, s9, s5
v_fmac_f32_e64 v0, s1, s0
s_add_u32 s0, s6, s16
s_addc_u32 s1, s7, s17
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7sfilterPfS_lfffffffff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 60
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 36
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7sfilterPfS_lfffffffff, .Lfunc_end0-_Z7sfilterPfS_lfffffffff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 60
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7sfilterPfS_lfffffffff
.private_segment_fixed_size: 0
.sgpr_count: 36
.sgpr_spill_count: 0
.symbol: _Z7sfilterPfS_lfffffffff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168dfb_00000000-6_sfilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
.type _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff, @function
_Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff:
.LFB2051:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 20(%rsp), %rax
movq %rax, 184(%rsp)
leaq 16(%rsp), %rax
movq %rax, 192(%rsp)
leaq 12(%rsp), %rax
movq %rax, 200(%rsp)
leaq 8(%rsp), %rax
movq %rax, 208(%rsp)
leaq 256(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7sfilterPfS_lfffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff, .-_Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
.globl _Z7sfilterPfS_lfffffffff
.type _Z7sfilterPfS_lfffffffff, @function
_Z7sfilterPfS_lfffffffff:
.LFB2052:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movss 32(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z38__device_stub__Z7sfilterPfS_lfffffffffPfS_lfffffffff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7sfilterPfS_lfffffffff, .-_Z7sfilterPfS_lfffffffff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7sfilterPfS_lfffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7sfilterPfS_lfffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sfilter.hip"
.globl _Z22__device_stub__sfilterPfS_lfffffffff # -- Begin function _Z22__device_stub__sfilterPfS_lfffffffff
.p2align 4, 0x90
.type _Z22__device_stub__sfilterPfS_lfffffffff,@function
_Z22__device_stub__sfilterPfS_lfffffffff: # @_Z22__device_stub__sfilterPfS_lfffffffff
.cfi_startproc
# %bb.0:
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movss %xmm4, 20(%rsp)
movss %xmm5, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 28(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 20(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
leaq 224(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7sfilterPfS_lfffffffff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $232, %rsp
.cfi_adjust_cfa_offset -232
retq
.Lfunc_end0:
.size _Z22__device_stub__sfilterPfS_lfffffffff, .Lfunc_end0-_Z22__device_stub__sfilterPfS_lfffffffff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7sfilterPfS_lfffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7sfilterPfS_lfffffffff,@object # @_Z7sfilterPfS_lfffffffff
.section .rodata,"a",@progbits
.globl _Z7sfilterPfS_lfffffffff
.p2align 3, 0x0
_Z7sfilterPfS_lfffffffff:
.quad _Z22__device_stub__sfilterPfS_lfffffffff
.size _Z7sfilterPfS_lfffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7sfilterPfS_lfffffffff"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__sfilterPfS_lfffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7sfilterPfS_lfffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
cudaMalloc((void **)&da, sizeof(int));
cudaMalloc((void **)&db, sizeof(int));
cudaMalloc((void **)&dc, sizeof(int));
// ... move data ...
cudaMemcpy(da, &a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, &b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
cudaMemcpy(&c, dc, sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
cudaFree(da); cudaFree(db); cudaFree(dc);
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
cudaMalloc((void **)&da, sizeof(int));
cudaMalloc((void **)&db, sizeof(int));
cudaMalloc((void **)&dc, sizeof(int));
// ... move data ...
cudaMemcpy(da, &a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, &b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
cudaMemcpy(&c, dc, sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
cudaFree(da); cudaFree(db); cudaFree(dc);
} | .file "tmpxft_0007e6ff_00000000-6_add_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d -> %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
cudaMalloc((void **)&da, sizeof(int));
cudaMalloc((void **)&db, sizeof(int));
cudaMalloc((void **)&dc, sizeof(int));
// ... move data ...
cudaMemcpy(da, &a, sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(db, &b, sizeof(int), cudaMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
cudaMemcpy(&c, dc, sizeof(int), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
cudaFree(da); cudaFree(db); cudaFree(dc);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
hipMalloc((void **)&da, sizeof(int));
hipMalloc((void **)&db, sizeof(int));
hipMalloc((void **)&dc, sizeof(int));
// ... move data ...
hipMemcpy(da, &a, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, &b, sizeof(int), hipMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
hipMemcpy(&c, dc, sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
hipFree(da); hipFree(db); hipFree(dc);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
hipMalloc((void **)&da, sizeof(int));
hipMalloc((void **)&db, sizeof(int));
hipMalloc((void **)&dc, sizeof(int));
// ... move data ...
hipMemcpy(da, &a, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, &b, sizeof(int), hipMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
hipMemcpy(&c, dc, sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
hipFree(da); hipFree(db); hipFree(dc);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
// ... define function 'add' ...
__global__ void add(int *da, int *db, int *dc) {
*dc = *da + *db;
}
int main(int argc, char **argv) {
int a, b, c; // We've chosen static allocation here for host storage..
int *da, *db, *dc; // ...but device storage must be dynamically allocated
a = atoi(argv[1]); // Read the addends from the command line args
b = atoi(argv[2]);
// ... manage memory ...
hipMalloc((void **)&da, sizeof(int));
hipMalloc((void **)&db, sizeof(int));
hipMalloc((void **)&dc, sizeof(int));
// ... move data ...
hipMemcpy(da, &a, sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(db, &b, sizeof(int), hipMemcpyHostToDevice);
add<<<1,1>>>(da, db, dc);
// ... move data ...
hipMemcpy(&c, dc, sizeof(int), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
printf("%d + %d -> %d\n", a, b, c);
// ... manage memory ...
hipFree(da); hipFree(db); hipFree(dc);
} | .text
.file "add_solution.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d -> %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007e6ff_00000000-6_add_solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d -> %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, (%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_solution.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, (%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d -> %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include "cuda_runtime.h"
#include <device_launch_parameters.h>
#include <device_functions.h>
#include <time.h>
#include <cuda_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
cudaMalloc((void**)&d_vec, ARRAY_BYTES);
cudaMalloc((void**)&d_mat, MATRIX_BYTES);
cudaMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
cudaMemcpy(d_vec, h_vec, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat, h_mat, MATRIX_BYTES, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
cudaEventRecord(stop, 0);
//trasfer the results from GPU to CPU
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
cudaFree(d_vec);
cudaFree(d_mat);
cudaFree(d_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ | code for sm_80
Function : _Z18vector_matrix_multPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe400000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xb70 ; /* 0x00000ac000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0100*/ @!P0 BRA 0xa60 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R4, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe20000000f00 */
/*0140*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f04270 */
/*0160*/ MOV R12, c[0x0][0x160] ; /* 0x00005800000c7a02 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R13, c[0x0][0x164] ; /* 0x00005900000d7a02 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD.WIDE R18, R0, R5, c[0x0][0x168] ; /* 0x00005a0000127625 */
/* 0x000fcc00078e0205 */
/*0190*/ @!P0 BRA 0x8e0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x640 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a2000c1e1900 */
/*01f0*/ IMAD.WIDE R24, R5, c[0x0][0x17c], R18 ; /* 0x00005f0005187a25 */
/* 0x000fc600078e0212 */
/*0200*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R7, [R12.64+0x8] ; /* 0x000008040c077981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R24, R5, c[0x0][0x17c], R24 ; /* 0x00005f0005187a25 */
/* 0x002fc600078e0218 */
/*0250*/ LDG.E R8, [R12.64+0xc] ; /* 0x00000c040c087981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x000322000c1e1900 */
/*0270*/ IMAD.WIDE R26, R5, c[0x0][0x17c], R24 ; /* 0x00005f00051a7a25 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R11, [R12.64+0x10] ; /* 0x000010040c0b7981 */
/* 0x000f66000c1e1900 */
/*0290*/ IMAD.WIDE R22, R5.reuse, c[0x0][0x17c], R26 ; /* 0x00005f0005167a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000368000c1e1900 */
/*02b0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000362000c1e1900 */
/*02c0*/ IMAD.WIDE R20, R5, c[0x0][0x17c], R22 ; /* 0x00005f0005147a25 */
/* 0x000fc600078e0216 */
/*02d0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x001f68000c1e1900 */
/*02e0*/ LDG.E R19, [R20.64] ; /* 0x0000000414137981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R24, [R12.64+0x18] ; /* 0x000018040c187981 */
/* 0x002f68000c1e1900 */
/*0300*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*0310*/ IMAD.WIDE R20, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005147a25 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R29, [R12.64+0x28] ; /* 0x000028040c1d7981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005167a25 */
/* 0x000fe200078e0214 */
/*0340*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x002362000c1e1900 */
/*0370*/ FFMA R28, R15, R14, R28 ; /* 0x0000000e0f1c7223 */
/* 0x004fc4000000001c */
/*0380*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x17c], R22 ; /* 0x00005f00050e7a25 */
/* 0x040fe400078e0216 */
/*0390*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x0012a4000c1e1900 */
/*03a0*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x008fe4000000001c */
/*03b0*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R14 ; /* 0x00005f0005107a25 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e4000c1e1900 */
/*03d0*/ FFMA R28, R6, R7, R28 ; /* 0x00000007061c7223 */
/* 0x010fc4000000001c */
/*03e0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R16 ; /* 0x00005f0005067a25 */
/* 0x000fe200078e0210 */
/*03f0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001328000c1e1900 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000a2000c1e1900 */
/*0410*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*0420*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0206 */
/*0430*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000b26000c1e1900 */
/*0440*/ FFMA R28, R10, R11, R28 ; /* 0x0000000b0a1c7223 */
/* 0x000fe2000000001c */
/*0450*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000322000c1e1900 */
/*0460*/ IMAD.WIDE R10, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050a7a25 */
/* 0x000fc600078e0208 */
/*0470*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x001122000c1e1900 */
/*0480*/ FFMA R28, R19, R18, R28 ; /* 0x00000012131c7223 */
/* 0x000fe4000000001c */
/*0490*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x17c], R10 ; /* 0x00005f0005127a25 */
/* 0x040fe400078e020a */
/*04a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000128000c1e1900 */
/*04b0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R18 ; /* 0x00005f0005067a25 */
/* 0x020fc800078e0212 */
/*04c0*/ FFMA R28, R25, R24, R28 ; /* 0x00000018191c7223 */
/* 0x000fe4000000001c */
/*04d0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000b22000c1e1900 */
/*04e0*/ IMAD.WIDE R8, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x002fc600078e0206 */
/*04f0*/ LDG.E R25, [R12.64+0x34] ; /* 0x000034040c197981 */
/* 0x000328000c1e1900 */
/*0500*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x001f22000c1e1900 */
/*0510*/ FFMA R18, R27, R26, R28 ; /* 0x0000001a1b127223 */
/* 0x020fc6000000001c */
/*0520*/ LDG.E R27, [R12.64+0x38] ; /* 0x000038040c1b7981 */
/* 0x000368000c1e1900 */
/*0530*/ LDG.E R26, [R6.64] ; /* 0x00000004061a7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R28, [R12.64+0x3c] ; /* 0x00003c040c1c7981 */
/* 0x000362000c1e1900 */
/*0550*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0570*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f5e0ff */
/*0580*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05a0*/ FFMA R14, R14, R21, R18 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000012 */
/*05b0*/ FFMA R14, R16, R23, R14 ; /* 0x00000017100e7223 */
/* 0x004fc8000000000e */
/*05c0*/ FFMA R14, R20, R29, R14 ; /* 0x0000001d140e7223 */
/* 0x010fc8000000000e */
/*05d0*/ FFMA R14, R22, R15, R14 ; /* 0x0000000f160e7223 */
/* 0x000fc8000000000e */
/*05e0*/ FFMA R10, R10, R17, R14 ; /* 0x000000110a0a7223 */
/* 0x000fe4000000000e */
/*05f0*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R8 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0208 */
/*0600*/ FFMA R10, R24, R25, R10 ; /* 0x00000019180a7223 */
/* 0x000fc8000000000a */
/*0610*/ FFMA R10, R26, R27, R10 ; /* 0x0000001b1a0a7223 */
/* 0x020fc8000000000a */
/*0620*/ FFMA R28, R11, R28, R10 ; /* 0x0000001c0b1c7223 */
/* 0x000fe2000000000a */
/*0630*/ @P1 BRA 0x1e0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8c0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x17c], R18 ; /* 0x00005f0005147a25 */
/* 0x040fe200078e0212 */
/*0670*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000ea8000c1e1900 */
/*0680*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x0000e2000c1e1900 */
/*0690*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005107a25 */
/* 0x000fc600078e0214 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000326000c1e1900 */
/*06b0*/ IMAD.WIDE R10, R5.reuse, c[0x0][0x17c], R16 ; /* 0x00005f00050a7a25 */
/* 0x040fe200078e0210 */
/*06c0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000aa8000c1e1900 */
/*06d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x001ee2000c1e1900 */
/*06e0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R10 ; /* 0x00005f0005067a25 */
/* 0x000fc600078e020a */
/*06f0*/ LDG.E R21, [R12.64+0x4] ; /* 0x000004040c157981 */
/* 0x002f26000c1e1900 */
/*0700*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0206 */
/*0710*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a8000c1e1900 */
/*0720*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD.WIDE R14, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050e7a25 */
/* 0x000fc600078e0208 */
/*0740*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R14 ; /* 0x00005f0005107a25 */
/* 0x020fc600078e020e */
/*0770*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*0780*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R26, [R12.64+0x18] ; /* 0x000018040c1a7981 */
/* 0x000f68000c1e1900 */
/*07b0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x001f68000c1e1900 */
/*07c0*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x002162000c1e1900 */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*07e0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0800*/ FFMA R18, R19, R18, R28 ; /* 0x0000001213127223 */
/* 0x008fc8000000001c */
/*0810*/ FFMA R18, R20, R21, R18 ; /* 0x0000001514127223 */
/* 0x010fc80000000012 */
/*0820*/ FFMA R18, R22, R23, R18 ; /* 0x0000001716127223 */
/* 0x004fc80000000012 */
/*0830*/ FFMA R10, R10, R25, R18 ; /* 0x000000190a0a7223 */
/* 0x000fc80000000012 */
/*0840*/ FFMA R6, R6, R27, R10 ; /* 0x0000001b06067223 */
/* 0x000fc8000000000a */
/*0850*/ FFMA R29, R8, R29, R6 ; /* 0x0000001d081d7223 */
/* 0x020fe20000000006 */
/*0860*/ IADD3 R6, P1, R12, 0x20, RZ ; /* 0x000000200c067810 */
/* 0x000fe20007f3e0ff */
/*0870*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R16 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0210 */
/*0880*/ FFMA R24, R24, R26, R29 ; /* 0x0000001a18187223 */
/* 0x000fe2000000001d */
/*0890*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x001fe40000ffe4ff */
/*08a0*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fe20000000f00 */
/*08b0*/ FFMA R28, R11, R14, R24 ; /* 0x0000000e0b1c7223 */
/* 0x000fe40000000018 */
/*08c0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0xa60 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R18 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0212 */
/*08f0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0000a8000c1e1900 */
/*0900*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R10, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050a7a25 */
/* 0x000fc600078e0208 */
/*0920*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x0002e8000c1e1900 */
/*0930*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x0000e2000c1e1900 */
/*0940*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R10 ; /* 0x00005f0005067a25 */
/* 0x000fc600078e020a */
/*0950*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000128000c1e1900 */
/*0960*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000168000c1e1900 */
/*0980*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000f62000c1e1900 */
/*0990*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*09b0*/ IADD3 R8, P1, R12, 0x10, RZ ; /* 0x000000100c087810 */
/* 0x002fc80007f3e0ff */
/*09c0*/ IADD3.X R9, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff097210 */
/* 0x000fe40000ffe4ff */
/*09d0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x001fe40000000f00 */
/*09f0*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe20000000f00 */
/*0a00*/ FFMA R14, R19, R14, R28 ; /* 0x0000000e130e7223 */
/* 0x004fc8000000001c */
/*0a10*/ FFMA R14, R15, R16, R14 ; /* 0x000000100f0e7223 */
/* 0x008fe4000000000e */
/*0a20*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0206 */
/*0a30*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x010fc8000000000e */
/*0a40*/ FFMA R28, R21, R22, R14 ; /* 0x00000016151c7223 */
/* 0x020fe2000000000e */
/*0a50*/ @P0 BRA 0x8e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0a70*/ @!P0 BRA 0xb70 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R6, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003067a24 */
/* 0x000fd200078e0200 */
/*0aa0*/ IMAD.WIDE R4, R3, R9, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0209 */
/*0ab0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0ac0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*0ad0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0ae0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0000aa000c1e1900 */
/*0af0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0b00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f3e0ff */
/*0b20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0b30*/ IMAD.WIDE R6, R9, c[0x0][0x17c], R6 ; /* 0x00005f0009067a25 */
/* 0x001fe200078e0206 */
/*0b40*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x002fc60000ffe4ff */
/*0b50*/ FFMA R28, R3, R4, R28 ; /* 0x00000004031c7223 */
/* 0x004fd0000000001c */
/*0b60*/ @P0 BRA 0xad0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0b70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0b80*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0b90*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include "cuda_runtime.h"
#include <device_launch_parameters.h>
#include <device_functions.h>
#include <time.h>
#include <cuda_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
cudaMalloc((void**)&d_vec, ARRAY_BYTES);
cudaMalloc((void**)&d_mat, MATRIX_BYTES);
cudaMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
cudaMemcpy(d_vec, h_vec, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat, h_mat, MATRIX_BYTES, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
cudaEventRecord(stop, 0);
//trasfer the results from GPU to CPU
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
cudaFree(d_vec);
cudaFree(d_mat);
cudaFree(d_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ | .file "tmpxft_0018f672_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
.type _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii, @function
_Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vector_matrix_multPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii, .-_Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
.globl _Z18vector_matrix_multPfS_S_ii
.type _Z18vector_matrix_multPfS_S_ii, @function
_Z18vector_matrix_multPfS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18vector_matrix_multPfS_S_ii, .-_Z18vector_matrix_multPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f"
.LC6:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "The GPU time elapsed is %.6f ms \""
.section .rodata.str1.1
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0x00000000, 12(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movss .LC1(%rip), %xmm0
movss %xmm0, 80(%rsp)
movss .LC2(%rip), %xmm1
movss %xmm1, 84(%rsp)
movss %xmm1, 88(%rsp)
movss %xmm1, 92(%rsp)
movss %xmm0, 112(%rsp)
movss %xmm0, 116(%rsp)
movss .LC3(%rip), %xmm3
movss %xmm3, 120(%rsp)
movss .LC4(%rip), %xmm2
movss %xmm2, 124(%rsp)
movss %xmm1, 128(%rsp)
movss %xmm0, 132(%rsp)
movss %xmm3, 136(%rsp)
movss %xmm2, 140(%rsp)
movss %xmm1, 144(%rsp)
movss %xmm0, 148(%rsp)
movss %xmm3, 152(%rsp)
movss %xmm2, 156(%rsp)
movss %xmm1, 160(%rsp)
movss %xmm0, 164(%rsp)
movss %xmm3, 168(%rsp)
movss %xmm2, 172(%rsp)
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %ebx
leaq 96(%rsp), %r12
leaq .LC5(%rip), %rbp
leaq .LC6(%rip), %r13
jmp .L14
.L20:
movl $4, %r8d
movl $4, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
jmp .L12
.L21:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
je .L15
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
jne .L21
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z18vector_matrix_multPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vector_matrix_multPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include "cuda_runtime.h"
#include <device_launch_parameters.h>
#include <device_functions.h>
#include <time.h>
#include <cuda_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
cudaMalloc((void**)&d_vec, ARRAY_BYTES);
cudaMalloc((void**)&d_mat, MATRIX_BYTES);
cudaMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
cudaMemcpy(d_vec, h_vec, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat, h_mat, MATRIX_BYTES, cudaMemcpyHostToDevice);
cudaEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
cudaEventRecord(stop, 0);
//trasfer the results from GPU to CPU
cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
cudaFree(d_vec);
cudaFree(d_mat);
cudaFree(d_out);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ | #include <stdio.h>
#include <iostream>
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <time.h>
#include <hip/hip_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
hipMalloc((void**)&d_vec, ARRAY_BYTES);
hipMalloc((void**)&d_mat, MATRIX_BYTES);
hipMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
hipMemcpy(d_vec, h_vec, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_mat, h_mat, MATRIX_BYTES, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
hipEventRecord(stop, 0);
//trasfer the results from GPU to CPU
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
hipFree(d_vec);
hipFree(d_mat);
hipFree(d_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <iostream>
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <time.h>
#include <hip/hip_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
hipMalloc((void**)&d_vec, ARRAY_BYTES);
hipMalloc((void**)&d_mat, MATRIX_BYTES);
hipMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
hipMemcpy(d_vec, h_vec, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_mat, h_mat, MATRIX_BYTES, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
hipEventRecord(stop, 0);
//trasfer the results from GPU to CPU
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
hipFree(d_vec);
hipFree(d_mat);
hipFree(d_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vector_matrix_multPfS_S_ii
.globl _Z18vector_matrix_multPfS_S_ii
.p2align 8
.type _Z18vector_matrix_multPfS_S_ii,@function
_Z18vector_matrix_multPfS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vector_matrix_multPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vector_matrix_multPfS_S_ii, .Lfunc_end0-_Z18vector_matrix_multPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vector_matrix_multPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vector_matrix_multPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include "hip/hip_runtime.h"
#include <hip/device_functions.h>
#include <time.h>
#include <hip/hip_runtime_api.h>
/*Realization of the multiplication between a vector and a matrix, on the GPU.
It realizes multiplication between a vector of 4 element and a matrix (4x4),
so as result is expected a vector of 4 element.
We initialized the input array on the host (CPU) and trasferred to device (GPU).
Then, CPU launches the kernel which is elaborated on GPU.
Finally, the results is trasferred from GPU to CPU and printed out*/
__global__ void vector_matrix_mult(float *d_vec, float *d_mat, float *d_out, const int N, const int M)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
float sum = 0;
if (tid < M) {
for (int i = 0; i < N; i++)
sum += d_vec[i] * d_mat[(i*M) + tid];
d_out[tid] = sum;
}
}
int main(int argc, char ** argv) {
float elapsed = 0;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
const int N = 4;
const int M = N;
const int ARRAY_SIZE = N;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
const int MATRIX_SIZE = ARRAY_SIZE*ARRAY_SIZE;
const int MATRIX_BYTES = MATRIX_SIZE * sizeof(float);
// generate the input vector and input matrix on the host
float h_vec[ARRAY_SIZE] = { 2, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 2, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float * d_vec;
float * d_mat;
float * d_out;
//allocate GPU memory
hipMalloc((void**)&d_vec, ARRAY_BYTES);
hipMalloc((void**)&d_mat, MATRIX_BYTES);
hipMalloc((void**)&d_out, ARRAY_BYTES);
//transfer the input from CPU to GPU
hipMemcpy(d_vec, h_vec, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_mat, h_mat, MATRIX_BYTES, hipMemcpyHostToDevice);
hipEventRecord(start, 0);
//launch the kernel
vector_matrix_mult <<<1, ARRAY_SIZE>>> (d_vec, d_mat, d_out, N, M);
hipEventRecord(stop, 0);
//trasfer the results from GPU to CPU
hipMemcpy(h_out, d_out, ARRAY_BYTES, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
//print out the resulting array
for (int i = 0; i < ARRAY_SIZE; i++) {
printf("%f", h_out[i]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
printf("The GPU time elapsed is %.6f ms \"", elapsed);
//free GPU location memory
hipFree(d_vec);
hipFree(d_mat);
hipFree(d_out);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
}
/*Realization though CPU*/
/*
#include <time.h>
int main(int argc, char ** argv) {
clock_t cpu_startTime, cpu_stopTime;
double cpu_elapsedTime = 0;
cpu_startTime = clock();
const int ARRAY_SIZE = 4;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_vec[ARRAY_SIZE] = { 1, 1, 1, 1 };
float h_mat[ARRAY_SIZE][ARRAY_SIZE] = { 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 };
float risultato[ARRAY_SIZE];
float h_out[ARRAY_SIZE];
float tot = 0;
int i, j;
for (j = 0; j < ARRAY_SIZE; j++){
for (i = 0; i < ARRAY_SIZE; i++) {
risultato[i] = h_vec[i] * h_mat[i][j];
tot += risultato[i];
}
h_out[j] = tot;
tot = 0;
printf("%f", h_out[j]);
printf(((i % 4) != 3) ? "\t" : "\n");
}
cpu_stopTime = clock();
cpu_elapsedTime = ((cpu_startTime - cpu_stopTime) / CLOCKS_PER_SEC);
printf("The CPU elapsed time is %.6f ms \"", cpu_elapsedTime);
return 0;
}
*/ | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__vector_matrix_multPfS_S_ii # -- Begin function _Z33__device_stub__vector_matrix_multPfS_S_ii
.p2align 4, 0x90
.type _Z33__device_stub__vector_matrix_multPfS_S_ii,@function
_Z33__device_stub__vector_matrix_multPfS_S_ii: # @_Z33__device_stub__vector_matrix_multPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vector_matrix_multPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__vector_matrix_multPfS_S_ii, .Lfunc_end0-_Z33__device_stub__vector_matrix_multPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x40000000 # float 2
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI1_2:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2.0E+0,1.0E+0,1.0E+0,1.0E+0]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [2.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 192(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 208(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 240(%rsp)
leaq 32(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $4, 52(%rsp)
movl $4, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z18vector_matrix_multPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $3, %r14
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB1_3
# %bb.4:
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vector_matrix_multPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vector_matrix_multPfS_S_ii,@object # @_Z18vector_matrix_multPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z18vector_matrix_multPfS_S_ii
.p2align 3, 0x0
_Z18vector_matrix_multPfS_S_ii:
.quad _Z33__device_stub__vector_matrix_multPfS_S_ii
.size _Z18vector_matrix_multPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The GPU time elapsed is %.6f ms \""
.size .L.str.3, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18vector_matrix_multPfS_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vector_matrix_multPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vector_matrix_multPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18vector_matrix_multPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe400000001ff */
/*0090*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00a0*/ @!P0 BRA 0xb70 ; /* 0x00000ac000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0100*/ @!P0 BRA 0xa60 ; /* 0x0000095000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R4, -R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe20000000f00 */
/*0140*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f04270 */
/*0160*/ MOV R12, c[0x0][0x160] ; /* 0x00005800000c7a02 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R13, c[0x0][0x164] ; /* 0x00005900000d7a02 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD.WIDE R18, R0, R5, c[0x0][0x168] ; /* 0x00005a0000127625 */
/* 0x000fcc00078e0205 */
/*0190*/ @!P0 BRA 0x8e0 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x640 ; /* 0x0000047000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a2000c1e1900 */
/*01f0*/ IMAD.WIDE R24, R5, c[0x0][0x17c], R18 ; /* 0x00005f0005187a25 */
/* 0x000fc600078e0212 */
/*0200*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0002e8000c1e1900 */
/*0220*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R7, [R12.64+0x8] ; /* 0x000008040c077981 */
/* 0x000f22000c1e1900 */
/*0240*/ IMAD.WIDE R24, R5, c[0x0][0x17c], R24 ; /* 0x00005f0005187a25 */
/* 0x002fc600078e0218 */
/*0250*/ LDG.E R8, [R12.64+0xc] ; /* 0x00000c040c087981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x000322000c1e1900 */
/*0270*/ IMAD.WIDE R26, R5, c[0x0][0x17c], R24 ; /* 0x00005f00051a7a25 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R11, [R12.64+0x10] ; /* 0x000010040c0b7981 */
/* 0x000f66000c1e1900 */
/*0290*/ IMAD.WIDE R22, R5.reuse, c[0x0][0x17c], R26 ; /* 0x00005f0005167a25 */
/* 0x040fe200078e021a */
/*02a0*/ LDG.E R9, [R26.64] ; /* 0x000000041a097981 */
/* 0x000368000c1e1900 */
/*02b0*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000362000c1e1900 */
/*02c0*/ IMAD.WIDE R20, R5, c[0x0][0x17c], R22 ; /* 0x00005f0005147a25 */
/* 0x000fc600078e0216 */
/*02d0*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x001f68000c1e1900 */
/*02e0*/ LDG.E R19, [R20.64] ; /* 0x0000000414137981 */
/* 0x000168000c1e1900 */
/*02f0*/ LDG.E R24, [R12.64+0x18] ; /* 0x000018040c187981 */
/* 0x002f68000c1e1900 */
/*0300*/ LDG.E R26, [R12.64+0x1c] ; /* 0x00001c040c1a7981 */
/* 0x000f62000c1e1900 */
/*0310*/ IMAD.WIDE R20, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005147a25 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R29, [R12.64+0x28] ; /* 0x000028040c1d7981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005167a25 */
/* 0x000fe200078e0214 */
/*0340*/ LDG.E R25, [R20.64] ; /* 0x0000000414197981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R27, [R22.64] ; /* 0x00000004161b7981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x002362000c1e1900 */
/*0370*/ FFMA R28, R15, R14, R28 ; /* 0x0000000e0f1c7223 */
/* 0x004fc4000000001c */
/*0380*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x17c], R22 ; /* 0x00005f00050e7a25 */
/* 0x040fe400078e0216 */
/*0390*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x0012a4000c1e1900 */
/*03a0*/ FFMA R28, R16, R17, R28 ; /* 0x00000011101c7223 */
/* 0x008fe4000000001c */
/*03b0*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R14 ; /* 0x00005f0005107a25 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e4000c1e1900 */
/*03d0*/ FFMA R28, R6, R7, R28 ; /* 0x00000007061c7223 */
/* 0x010fc4000000001c */
/*03e0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R16 ; /* 0x00005f0005067a25 */
/* 0x000fe200078e0210 */
/*03f0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001328000c1e1900 */
/*0400*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0000a2000c1e1900 */
/*0410*/ FFMA R28, R9, R8, R28 ; /* 0x00000008091c7223 */
/* 0x020fe4000000001c */
/*0420*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0206 */
/*0430*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000b26000c1e1900 */
/*0440*/ FFMA R28, R10, R11, R28 ; /* 0x0000000b0a1c7223 */
/* 0x000fe2000000001c */
/*0450*/ LDG.E R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000322000c1e1900 */
/*0460*/ IMAD.WIDE R10, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050a7a25 */
/* 0x000fc600078e0208 */
/*0470*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x001122000c1e1900 */
/*0480*/ FFMA R28, R19, R18, R28 ; /* 0x00000012131c7223 */
/* 0x000fe4000000001c */
/*0490*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x17c], R10 ; /* 0x00005f0005127a25 */
/* 0x040fe400078e020a */
/*04a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000128000c1e1900 */
/*04b0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R18 ; /* 0x00005f0005067a25 */
/* 0x020fc800078e0212 */
/*04c0*/ FFMA R28, R25, R24, R28 ; /* 0x00000018191c7223 */
/* 0x000fe4000000001c */
/*04d0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000b22000c1e1900 */
/*04e0*/ IMAD.WIDE R8, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x002fc600078e0206 */
/*04f0*/ LDG.E R25, [R12.64+0x34] ; /* 0x000034040c197981 */
/* 0x000328000c1e1900 */
/*0500*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x001f22000c1e1900 */
/*0510*/ FFMA R18, R27, R26, R28 ; /* 0x0000001a1b127223 */
/* 0x020fc6000000001c */
/*0520*/ LDG.E R27, [R12.64+0x38] ; /* 0x000038040c1b7981 */
/* 0x000368000c1e1900 */
/*0530*/ LDG.E R26, [R6.64] ; /* 0x00000004061a7981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R28, [R12.64+0x3c] ; /* 0x00003c040c1c7981 */
/* 0x000362000c1e1900 */
/*0550*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc80007ffe0ff */
/*0560*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0570*/ IADD3 R12, P2, R12, 0x40, RZ ; /* 0x000000400c0c7810 */
/* 0x002fe40007f5e0ff */
/*0580*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0590*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fe200017fe4ff */
/*05a0*/ FFMA R14, R14, R21, R18 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000012 */
/*05b0*/ FFMA R14, R16, R23, R14 ; /* 0x00000017100e7223 */
/* 0x004fc8000000000e */
/*05c0*/ FFMA R14, R20, R29, R14 ; /* 0x0000001d140e7223 */
/* 0x010fc8000000000e */
/*05d0*/ FFMA R14, R22, R15, R14 ; /* 0x0000000f160e7223 */
/* 0x000fc8000000000e */
/*05e0*/ FFMA R10, R10, R17, R14 ; /* 0x000000110a0a7223 */
/* 0x000fe4000000000e */
/*05f0*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R8 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0208 */
/*0600*/ FFMA R10, R24, R25, R10 ; /* 0x00000019180a7223 */
/* 0x000fc8000000000a */
/*0610*/ FFMA R10, R26, R27, R10 ; /* 0x0000001b1a0a7223 */
/* 0x020fc8000000000a */
/*0620*/ FFMA R28, R11, R28, R10 ; /* 0x0000001c0b1c7223 */
/* 0x000fe2000000000a */
/*0630*/ @P1 BRA 0x1e0 ; /* 0xfffffba000001947 */
/* 0x000fea000383ffff */
/*0640*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0650*/ @!P1 BRA 0x8c0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0660*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x17c], R18 ; /* 0x00005f0005147a25 */
/* 0x040fe200078e0212 */
/*0670*/ LDG.E R23, [R12.64+0x8] ; /* 0x000008040c177981 */
/* 0x000ea8000c1e1900 */
/*0680*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x0000e2000c1e1900 */
/*0690*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R20 ; /* 0x00005f0005107a25 */
/* 0x000fc600078e0214 */
/*06a0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000326000c1e1900 */
/*06b0*/ IMAD.WIDE R10, R5.reuse, c[0x0][0x17c], R16 ; /* 0x00005f00050a7a25 */
/* 0x040fe200078e0210 */
/*06c0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000aa8000c1e1900 */
/*06d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x001ee2000c1e1900 */
/*06e0*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R10 ; /* 0x00005f0005067a25 */
/* 0x000fc600078e020a */
/*06f0*/ LDG.E R21, [R12.64+0x4] ; /* 0x000004040c157981 */
/* 0x002f26000c1e1900 */
/*0700*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R6 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0206 */
/*0710*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a8000c1e1900 */
/*0720*/ LDG.E R25, [R12.64+0xc] ; /* 0x00000c040c197981 */
/* 0x000ea2000c1e1900 */
/*0730*/ IMAD.WIDE R14, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050e7a25 */
/* 0x000fc600078e0208 */
/*0740*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0750*/ LDG.E R27, [R12.64+0x10] ; /* 0x000010040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD.WIDE R16, R5, c[0x0][0x17c], R14 ; /* 0x00005f0005107a25 */
/* 0x020fc600078e020e */
/*0770*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f68000c1e1900 */
/*0780*/ LDG.E R29, [R12.64+0x14] ; /* 0x000014040c1d7981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R26, [R12.64+0x18] ; /* 0x000018040c1a7981 */
/* 0x000f68000c1e1900 */
/*07b0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x001f68000c1e1900 */
/*07c0*/ LDG.E R14, [R12.64+0x1c] ; /* 0x00001c040c0e7981 */
/* 0x002162000c1e1900 */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*07e0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0800*/ FFMA R18, R19, R18, R28 ; /* 0x0000001213127223 */
/* 0x008fc8000000001c */
/*0810*/ FFMA R18, R20, R21, R18 ; /* 0x0000001514127223 */
/* 0x010fc80000000012 */
/*0820*/ FFMA R18, R22, R23, R18 ; /* 0x0000001716127223 */
/* 0x004fc80000000012 */
/*0830*/ FFMA R10, R10, R25, R18 ; /* 0x000000190a0a7223 */
/* 0x000fc80000000012 */
/*0840*/ FFMA R6, R6, R27, R10 ; /* 0x0000001b06067223 */
/* 0x000fc8000000000a */
/*0850*/ FFMA R29, R8, R29, R6 ; /* 0x0000001d081d7223 */
/* 0x020fe20000000006 */
/*0860*/ IADD3 R6, P1, R12, 0x20, RZ ; /* 0x000000200c067810 */
/* 0x000fe20007f3e0ff */
/*0870*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R16 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0210 */
/*0880*/ FFMA R24, R24, R26, R29 ; /* 0x0000001a18187223 */
/* 0x000fe2000000001d */
/*0890*/ IADD3.X R13, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff0d7210 */
/* 0x001fe40000ffe4ff */
/*08a0*/ MOV R12, R6 ; /* 0x00000006000c7202 */
/* 0x000fe20000000f00 */
/*08b0*/ FFMA R28, R11, R14, R24 ; /* 0x0000000e0b1c7223 */
/* 0x000fe40000000018 */
/*08c0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*08d0*/ @!P0 BRA 0xa60 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x17c], R18 ; /* 0x00005f0005087a25 */
/* 0x040fe200078e0212 */
/*08f0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x0000a8000c1e1900 */
/*0900*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R10, R5, c[0x0][0x17c], R8 ; /* 0x00005f00050a7a25 */
/* 0x000fc600078e0208 */
/*0920*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x0002e8000c1e1900 */
/*0930*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x0000e2000c1e1900 */
/*0940*/ IMAD.WIDE R6, R5, c[0x0][0x17c], R10 ; /* 0x00005f0005067a25 */
/* 0x000fc600078e020a */
/*0950*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000128000c1e1900 */
/*0960*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000168000c1e1900 */
/*0980*/ LDG.E R21, [R6.64] ; /* 0x0000000406157981 */
/* 0x000f62000c1e1900 */
/*0990*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fc80007ffe0ff */
/*09a0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*09b0*/ IADD3 R8, P1, R12, 0x10, RZ ; /* 0x000000100c087810 */
/* 0x002fc80007f3e0ff */
/*09c0*/ IADD3.X R9, RZ, R13, RZ, P1, !PT ; /* 0x0000000dff097210 */
/* 0x000fe40000ffe4ff */
/*09d0*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R12, R8 ; /* 0x00000008000c7202 */
/* 0x001fe40000000f00 */
/*09f0*/ MOV R13, R9 ; /* 0x00000009000d7202 */
/* 0x000fe20000000f00 */
/*0a00*/ FFMA R14, R19, R14, R28 ; /* 0x0000000e130e7223 */
/* 0x004fc8000000001c */
/*0a10*/ FFMA R14, R15, R16, R14 ; /* 0x000000100f0e7223 */
/* 0x008fe4000000000e */
/*0a20*/ IMAD.WIDE R18, R5, c[0x0][0x17c], R6 ; /* 0x00005f0005127a25 */
/* 0x000fc800078e0206 */
/*0a30*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x010fc8000000000e */
/*0a40*/ FFMA R28, R21, R22, R14 ; /* 0x00000016151c7223 */
/* 0x020fe2000000000e */
/*0a50*/ @P0 BRA 0x8e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0a60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0a70*/ @!P0 BRA 0xb70 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R6, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003067a24 */
/* 0x000fd200078e0200 */
/*0aa0*/ IMAD.WIDE R4, R3, R9, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0209 */
/*0ab0*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0209 */
/*0ac0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*0ad0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fe20000000f00 */
/*0ae0*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0000aa000c1e1900 */
/*0af0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0b00*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fc40007f3e0ff */
/*0b20*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0b30*/ IMAD.WIDE R6, R9, c[0x0][0x17c], R6 ; /* 0x00005f0009067a25 */
/* 0x001fe200078e0206 */
/*0b40*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x002fc60000ffe4ff */
/*0b50*/ FFMA R28, R3, R4, R28 ; /* 0x00000004031c7223 */
/* 0x004fd0000000001c */
/*0b60*/ @P0 BRA 0xad0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0b70*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0b80*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*0b90*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0ba0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bb0*/ BRA 0xbb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18vector_matrix_multPfS_S_ii
.globl _Z18vector_matrix_multPfS_S_ii
.p2align 8
.type _Z18vector_matrix_multPfS_S_ii,@function
_Z18vector_matrix_multPfS_S_ii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18vector_matrix_multPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18vector_matrix_multPfS_S_ii, .Lfunc_end0-_Z18vector_matrix_multPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18vector_matrix_multPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18vector_matrix_multPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f672_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
.type _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii, @function
_Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18vector_matrix_multPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii, .-_Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
.globl _Z18vector_matrix_multPfS_S_ii
.type _Z18vector_matrix_multPfS_S_ii, @function
_Z18vector_matrix_multPfS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18vector_matrix_multPfS_S_ii, .-_Z18vector_matrix_multPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "%f"
.LC6:
.string "\t"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "The GPU time elapsed is %.6f ms \""
.section .rodata.str1.1
.LC8:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movl $0x00000000, 12(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movss .LC1(%rip), %xmm0
movss %xmm0, 80(%rsp)
movss .LC2(%rip), %xmm1
movss %xmm1, 84(%rsp)
movss %xmm1, 88(%rsp)
movss %xmm1, 92(%rsp)
movss %xmm0, 112(%rsp)
movss %xmm0, 116(%rsp)
movss .LC3(%rip), %xmm3
movss %xmm3, 120(%rsp)
movss .LC4(%rip), %xmm2
movss %xmm2, 124(%rsp)
movss %xmm1, 128(%rsp)
movss %xmm0, 132(%rsp)
movss %xmm3, 136(%rsp)
movss %xmm2, 140(%rsp)
movss %xmm1, 144(%rsp)
movss %xmm0, 148(%rsp)
movss %xmm3, 152(%rsp)
movss %xmm2, 156(%rsp)
movss %xmm1, 160(%rsp)
movss %xmm0, 164(%rsp)
movss %xmm3, 168(%rsp)
movss %xmm2, 172(%rsp)
leaq 32(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 96(%rsp), %rdi
movl $2, %ecx
movl $16, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %ebx
leaq 96(%rsp), %r12
leaq .LC5(%rip), %rbp
leaq .LC6(%rip), %r13
jmp .L14
.L20:
movl $4, %r8d
movl $4, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z18vector_matrix_multPfS_S_iiPfS_S_ii
jmp .L12
.L21:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $4, %rbx
je .L15
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
jne .L21
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z18vector_matrix_multPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z18vector_matrix_multPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1073741824
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1077936128
.align 4
.LC4:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__vector_matrix_multPfS_S_ii # -- Begin function _Z33__device_stub__vector_matrix_multPfS_S_ii
.p2align 4, 0x90
.type _Z33__device_stub__vector_matrix_multPfS_S_ii,@function
_Z33__device_stub__vector_matrix_multPfS_S_ii: # @_Z33__device_stub__vector_matrix_multPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18vector_matrix_multPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__vector_matrix_multPfS_S_ii, .Lfunc_end0-_Z33__device_stub__vector_matrix_multPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x40000000 # float 2
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.long 0x3f800000 # float 1
.LCPI1_1:
.long 0x40000000 # float 2
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.LCPI1_2:
.long 0x3f800000 # float 1
.long 0x40000000 # float 2
.long 0x40400000 # float 3
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $0, 4(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2.0E+0,1.0E+0,1.0E+0,1.0E+0]
movaps %xmm0, 176(%rsp)
movaps .LCPI1_1(%rip), %xmm0 # xmm0 = [2.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 192(%rsp)
movaps .LCPI1_2(%rip), %xmm0 # xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
movaps %xmm0, 208(%rsp)
movaps %xmm0, 224(%rsp)
movaps %xmm0, 240(%rsp)
leaq 32(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $4, 52(%rsp)
movl $4, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z18vector_matrix_multPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $16, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movl $.L.str.2, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 128(%rsp,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpq $3, %r14
movl $.L.str.1, %edi
cmoveq %rbx, %rdi
xorl %eax, %eax
callq printf
incq %r14
cmpq $4, %r14
jne .LBB1_3
# %bb.4:
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18vector_matrix_multPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18vector_matrix_multPfS_S_ii,@object # @_Z18vector_matrix_multPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z18vector_matrix_multPfS_S_ii
.p2align 3, 0x0
_Z18vector_matrix_multPfS_S_ii:
.quad _Z33__device_stub__vector_matrix_multPfS_S_ii
.size _Z18vector_matrix_multPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\t"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The GPU time elapsed is %.6f ms \""
.size .L.str.3, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18vector_matrix_multPfS_S_ii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__vector_matrix_multPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18vector_matrix_multPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
cudaMalloc((void **) &d_x, M);
cudaMalloc((void **) &d_y, M);
cudaMalloc((void **) &d_z, M);
cudaMemcpy(d_x, h_x, M, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, M, cudaMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
cudaMemcpy(h_z, d_z, M, cudaMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} | code for sm_80
Function : _Z3addPKdS0_Pdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
cudaMalloc((void **) &d_x, M);
cudaMalloc((void **) &d_y, M);
cudaMalloc((void **) &d_z, M);
cudaMemcpy(d_x, h_x, M, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, M, cudaMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
cudaMemcpy(h_z, d_z, M, cudaMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} | .file "tmpxft_000120b8_00000000-6_add_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Has errors"
.LC1:
.string "No errors"
.LC5:
.string "%s\n"
.text
.globl _Z5checkPKdi
.type _Z5checkPKdi, @function
_Z5checkPKdi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rdx
testl %esi, %esi
jle .L4
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rsi
movl $0, %edx
movsd .LC2(%rip), %xmm3
movq .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
movl $1, %ecx
.L6:
movsd (%rax), %xmm0
subsd %xmm3, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
cmova %ecx, %edx
addq $8, %rax
cmpq %rsi, %rax
jne .L6
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
.L4:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5checkPKdi, .-_Z5checkPKdi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $6400000000, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC6(%rip), %xmm1
movsd .LC7(%rip), %xmm0
.L13:
movsd %xmm1, 0(%rbp,%rax)
movsd %xmm0, (%rbx,%rax)
addq $8, %rax
cmpq $800000000, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $800000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $781250, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movl $2, %ecx
movl $800000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100000000, %esi
movq %r12, %rdi
call _Z5checkPKdi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z3addPKdS0_Pd@PLT
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
.type _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi, @function
_Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKdS0_Pdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi, .-_Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
.globl _Z3addPKdS0_Pdi
.type _Z3addPKdS0_Pdi, @function
_Z3addPKdS0_Pdi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPKdS0_Pdi, .-_Z3addPKdS0_Pdi
.section .rodata.str1.1
.LC8:
.string "_Z3addPKdS0_Pdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKdS0_Pdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 687194767
.long 1074564956
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long -1629006314
.long 1020396463
.align 8
.LC6:
.long 2061584302
.long 1072934420
.align 8
.LC7:
.long -343597384
.long 1073920081
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
cudaMalloc((void **) &d_x, M);
cudaMalloc((void **) &d_y, M);
cudaMalloc((void **) &d_z, M);
cudaMemcpy(d_x, h_x, M, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, M, cudaMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
cudaMemcpy(h_z, d_z, M, cudaMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} | #include <hip/hip_runtime.h>
#include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
hipMalloc((void **) &d_x, M);
hipMalloc((void **) &d_y, M);
hipMalloc((void **) &d_z, M);
hipMemcpy(d_x, h_x, M, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, M, hipMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
hipMemcpy(h_z, d_z, M, hipMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
hipMalloc((void **) &d_x, M);
hipMalloc((void **) &d_y, M);
hipMalloc((void **) &d_z, M);
hipMemcpy(d_x, h_x, M, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, M, hipMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
hipMemcpy(h_z, d_z, M, hipMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKdS0_Pdi
.globl _Z3addPKdS0_Pdi
.p2align 8
.type _Z3addPKdS0_Pdi,@function
_Z3addPKdS0_Pdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKdS0_Pdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKdS0_Pdi, .Lfunc_end0-_Z3addPKdS0_Pdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKdS0_Pdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPKdS0_Pdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<math.h>
#include<stdio.h>
const double EPSILON = 1.0e-15;
const double a = 1.23;
const double b = 2.34;
const double c = 3.57;
void __global__ add(const double *x, const double *y, double *z);
void check(const double *z, const int N);
int main() {
const int N = 100000000;
const int M = sizeof(double) * N;
double *h_x = new double[M];
double *h_y = new double[M];
double *h_z = new double[M];
for (int n = 0; n < N; n++) {
h_x[n] = a;
h_y[n] = b;
}
double *d_x, *d_y, *d_z;
hipMalloc((void **) &d_x, M);
hipMalloc((void **) &d_y, M);
hipMalloc((void **) &d_z, M);
hipMemcpy(d_x, h_x, M, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, M, hipMemcpyHostToDevice);
const int block_size = 128;
// const int grid_size = N / block_size; // 整除
const int grid_size = (N-1) / block_size + 1; // 不整除
add<<<grid_size, block_size>>>(d_x, d_y, d_z);
hipMemcpy(h_z, d_z, M, hipMemcpyDeviceToHost);
check(h_z, N);
free(h_x);
free(h_y);
free(h_z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return 0;
}
void __global__ add(const double *x, const double *y, double *z, const int N){ // 单指令，多线程
const int n = blockDim.x * blockIdx.x + threadIdx.x;
if(n < N){ // 避免非法的内存操作
z[n] = x[n] + y[n];
}
}
void check(const double *z, const int N){
bool has_error = false;
for(int n=0;n<N;n++){
if(fabs(z[n]-c)>EPSILON){
has_error = true;
}
}
printf("%s\n", has_error ? "Has errors" : "No errors");
} | .text
.file "add_example.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0xc00c8f5c28f5c28f # double -3.5699999999999998
.LCPI0_2:
.quad 0x3cd203af9ee75616 # double 1.0000000000000001E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $6400000000, %r12 # imm = 0x17D784000
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %r15
xorl %eax, %eax
movabsq $4608218246714312622, %rcx # imm = 0x3FF3AE147AE147AE
movabsq $4612451630364040888, %rdx # imm = 0x4002B851EB851EB8
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movq %rsp, %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movq 16(%rsp), %rdi
movl $800000000, %edx # imm = 0x2FAF0800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $800000000, %edx # imm = 0x2FAF0800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -2105032576(%r12), %rdx
addq $-2104251454, %r12 # imm = 0x8293ABC2
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z18__device_stub__addPKdS0_Pd
.LBB0_4:
movq (%rsp), %rsi
movl $800000000, %edx # imm = 0x2FAF0800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %ecx, %ecx
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i
# in Loop: Header=BB0_5 Depth=1
movl %edx, %ecx
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
je .LBB0_8
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%r15,%rax,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $1, %edx
ja .LBB0_7
# %bb.6: # %.lr.ph.i
# in Loop: Header=BB0_5 Depth=1
movzbl %cl, %edx
jmp .LBB0_7
.LBB0_8: # %_Z5checkPKdi.exit
testb $1, %cl
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5checkPKdi
.LCPI1_0:
.quad 0xc00c8f5c28f5c28f # double -3.5699999999999998
.LCPI1_2:
.quad 0x3cd203af9ee75616 # double 1.0000000000000001E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z5checkPKdi
.p2align 4, 0x90
.type _Z5checkPKdi,@function
_Z5checkPKdi: # @_Z5checkPKdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %edx, %edx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movl %esi, %edx
incq %rcx
cmpq %rcx, %rax
je .LBB1_7
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $1, %esi
ja .LBB1_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movzbl %dl, %esi
jmp .LBB1_6
.LBB1_7: # %._crit_edge.loopexit
testb $1, %dl
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
jmp puts@PLT # TAILCALL
.LBB1_1:
movl $.L.str.2, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z5checkPKdi, .Lfunc_end1-_Z5checkPKdi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPKdS0_Pdi # -- Begin function _Z18__device_stub__addPKdS0_Pdi
.p2align 4, 0x90
.type _Z18__device_stub__addPKdS0_Pdi,@function
_Z18__device_stub__addPKdS0_Pdi: # @_Z18__device_stub__addPKdS0_Pdi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKdS0_Pdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__addPKdS0_Pdi, .Lfunc_end2-_Z18__device_stub__addPKdS0_Pdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKdS0_Pdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKdS0_Pdi,@object # @_Z3addPKdS0_Pdi
.section .rodata,"a",@progbits
.globl _Z3addPKdS0_Pdi
.p2align 3, 0x0
_Z3addPKdS0_Pdi:
.quad _Z18__device_stub__addPKdS0_Pdi
.size _Z3addPKdS0_Pdi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Has errors"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No errors"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKdS0_Pdi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKdS0_Pdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKdS0_Pdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPKdS0_Pdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x178], PT ; /* 0x00005e0008007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R8, R9, c[0x0][0x168] ; /* 0x00005a0008047625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R2, R8.reuse, R9.reuse, c[0x0][0x160] ; /* 0x0000580008027625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fe200078e0209 */
/*00d0*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*00e0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPKdS0_Pdi
.globl _Z3addPKdS0_Pdi
.p2align 8
.type _Z3addPKdS0_Pdi,@function
_Z3addPKdS0_Pdi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPKdS0_Pdi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPKdS0_Pdi, .Lfunc_end0-_Z3addPKdS0_Pdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPKdS0_Pdi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPKdS0_Pdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000120b8_00000000-6_add_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Has errors"
.LC1:
.string "No errors"
.LC5:
.string "%s\n"
.text
.globl _Z5checkPKdi
.type _Z5checkPKdi, @function
_Z5checkPKdi:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rdx
testl %esi, %esi
jle .L4
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,8), %rsi
movl $0, %edx
movsd .LC2(%rip), %xmm3
movq .LC3(%rip), %xmm2
movsd .LC4(%rip), %xmm1
movl $1, %ecx
.L6:
movsd (%rax), %xmm0
subsd %xmm3, %xmm0
andpd %xmm2, %xmm0
ucomisd %xmm1, %xmm0
cmova %ecx, %edx
addq $8, %rax
cmpq %rsi, %rax
jne .L6
testb %dl, %dl
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
.L4:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z5checkPKdi, .-_Z5checkPKdi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $6400000000, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
movsd .LC6(%rip), %xmm1
movsd .LC7(%rip), %xmm0
.L13:
movsd %xmm1, 0(%rbp,%rax)
movsd %xmm0, (%rbx,%rax)
addq $8, %rax
cmpq $800000000, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $800000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $800000000, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $800000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $781250, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movl $2, %ecx
movl $800000000, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $100000000, %esi
movq %r12, %rdi
call _Z5checkPKdi
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z3addPKdS0_Pd@PLT
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
.type _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi, @function
_Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPKdS0_Pdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi, .-_Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
.globl _Z3addPKdS0_Pdi
.type _Z3addPKdS0_Pdi, @function
_Z3addPKdS0_Pdi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z3addPKdS0_PdiPKdS0_Pdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3addPKdS0_Pdi, .-_Z3addPKdS0_Pdi
.section .rodata.str1.1
.LC8:
.string "_Z3addPKdS0_Pdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPKdS0_Pdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 687194767
.long 1074564956
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long -1629006314
.long 1020396463
.align 8
.LC6:
.long 2061584302
.long 1072934420
.align 8
.LC7:
.long -343597384
.long 1073920081
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_example.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0xc00c8f5c28f5c28f # double -3.5699999999999998
.LCPI0_2:
.quad 0x3cd203af9ee75616 # double 1.0000000000000001E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $6400000000, %r12 # imm = 0x17D784000
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %r15
xorl %eax, %eax
movabsq $4608218246714312622, %rcx # imm = 0x3FF3AE147AE147AE
movabsq $4612451630364040888, %rdx # imm = 0x4002B851EB851EB8
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq %rcx, (%rbx,%rax,8)
movq %rdx, (%r14,%rax,8)
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
jne .LBB0_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
leaq 8(%rsp), %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movq %rsp, %rdi
movl $800000000, %esi # imm = 0x2FAF0800
callq hipMalloc
movq 16(%rsp), %rdi
movl $800000000, %edx # imm = 0x2FAF0800
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $800000000, %edx # imm = 0x2FAF0800
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq -2105032576(%r12), %rdx
addq $-2104251454, %r12 # imm = 0x8293ABC2
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movq (%rsp), %rdx
callq _Z18__device_stub__addPKdS0_Pd
.LBB0_4:
movq (%rsp), %rsi
movl $800000000, %edx # imm = 0x2FAF0800
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI0_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %ecx, %ecx
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i
# in Loop: Header=BB0_5 Depth=1
movl %edx, %ecx
incq %rax
cmpq $100000000, %rax # imm = 0x5F5E100
je .LBB0_8
.LBB0_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsd (%r15,%rax,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $1, %edx
ja .LBB0_7
# %bb.6: # %.lr.ph.i
# in Loop: Header=BB0_5 Depth=1
movzbl %cl, %edx
jmp .LBB0_7
.LBB0_8: # %_Z5checkPKdi.exit
testb $1, %cl
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5checkPKdi
.LCPI1_0:
.quad 0xc00c8f5c28f5c28f # double -3.5699999999999998
.LCPI1_2:
.quad 0x3cd203af9ee75616 # double 1.0000000000000001E-15
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.text
.globl _Z5checkPKdi
.p2align 4, 0x90
.type _Z5checkPKdi,@function
_Z5checkPKdi: # @_Z5checkPKdi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
movapd .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
xorl %edx, %edx
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movl %esi, %edx
incq %rcx
cmpq %rcx, %rax
je .LBB1_7
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd (%rdi,%rcx,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm0, %xmm3
andpd %xmm1, %xmm3
ucomisd %xmm2, %xmm3
movl $1, %esi
ja .LBB1_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=1
movzbl %dl, %esi
jmp .LBB1_6
.LBB1_7: # %._crit_edge.loopexit
testb $1, %dl
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
jmp puts@PLT # TAILCALL
.LBB1_1:
movl $.L.str.2, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z5checkPKdi, .Lfunc_end1-_Z5checkPKdi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__addPKdS0_Pdi # -- Begin function _Z18__device_stub__addPKdS0_Pdi
.p2align 4, 0x90
.type _Z18__device_stub__addPKdS0_Pdi,@function
_Z18__device_stub__addPKdS0_Pdi: # @_Z18__device_stub__addPKdS0_Pdi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPKdS0_Pdi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__addPKdS0_Pdi, .Lfunc_end2-_Z18__device_stub__addPKdS0_Pdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPKdS0_Pdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPKdS0_Pdi,@object # @_Z3addPKdS0_Pdi
.section .rodata,"a",@progbits
.globl _Z3addPKdS0_Pdi
.p2align 3, 0x0
_Z3addPKdS0_Pdi:
.quad _Z18__device_stub__addPKdS0_Pdi
.size _Z3addPKdS0_Pdi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Has errors"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No errors"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPKdS0_Pdi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPKdS0_Pdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPKdS0_Pdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include <cuda_runtime.h>
#define seed 13
#define block_size 16
void printMatrix(float *matrix, int size){
int i;
for(i=0;i<size*size;i++){
if(i%size == 0 && i != 0)
printf("\n");
printf("%10.1f", matrix[i]);
}
printf("\n");
}
__global__ void version_1_matrixMul(float *dev_A, float *dev_B, float* dev_C,
int N){
// Each thread computes one elements of h_C
// by accumulating results into dev_C
float partial = 0.0;
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int k;
for(k =0; k < N;k++){
partial += dev_A[i * N + k] * dev_B[k * N + j];
}
dev_C[i * N + j] = partial;
}
__global__ void version_2_matrixMul(float *dev_A, float *dev_B, float *dev_C,
int matrix_size)
{
__shared__ float A_tile[block_size][block_size];
__shared__ float B_tile[block_size][block_size];
float partial = 0.0;
// block index
int bx = blockIdx.x;
int by = blockIdx.y;
// thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
// by the block
int m;
for( m=0 ; m < matrix_size/blockDim.x; m++){
A_tile[ty][tx] = dev_A[row * matrix_size + (m * block_size + tx)];
B_tile[ty][tx] = dev_B[col + (m * block_size + ty) * matrix_size];
__syncthreads();
int k;
for(k=0; k< blockDim.x; k++)
partial += A_tile[ty][k] * B_tile[k][tx];
__syncthreads();
dev_C[row * matrix_size + col] = partial;
}
}
int main(int argc, char **argv){
srand(seed);
if(argc != 2){
printf("Usage: \n");
printf("/lab4 <matrixSize>");
return 1;
}
int matrix_size = atoi(argv[1]);
float *h_A = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_B = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_C = (float*) malloc(matrix_size * matrix_size * sizeof(float));
int i,j;
for(i=0;i<matrix_size;i++){
for(j=0;j<matrix_size;j++){
h_A[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
h_B[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
}
}
//printf("This is matrix A: %d\n", matrix_size);
//printMatrix(h_A, matrix_size);
//printf("This is matrix B: \n");
//printMatrix(h_B, matrix_size);
float *d_A, *d_B, *d_C;
cudaMalloc((void**) &d_A, matrix_size * matrix_size * sizeof(float));
cudaMalloc((void**) &d_B, matrix_size * matrix_size * sizeof(float));
cudaMalloc((void**) &d_C, matrix_size * matrix_size * sizeof(float));
dim3 Block(block_size, block_size, 1);
dim3 Grid(matrix_size / Block.x, matrix_size / Block.y, 1);
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("=====This is naive version.======\n");
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
version_1_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
cudaMemcpy(h_C, d_C, matrix_size * matrix_size * sizeof(float),
cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("For naive version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
printf("=====This is tiled version.======\n");
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
version_2_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
cudaMemcpy(h_C, d_C, matrix_size* matrix_size * sizeof(float),
cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("For tiled version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .file "tmpxft_000d12ab_00000000-6_lab4_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "%10.1f"
.text
.globl _Z11printMatrixPfi
.type _Z11printMatrixPfi, @function
_Z11printMatrixPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r12d
imull %esi, %r12d
testl %r12d, %r12d
jle .L4
movq %rdi, %r13
movl %esi, %ebp
movslq %r12d, %r12
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L6
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
je .L4
.L6:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
testl %ebx, %ebx
je .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfi, .-_Z11printMatrixPfi
.globl _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19version_1_matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
.globl _Z19version_1_matrixMulPfS_S_i
.type _Z19version_1_matrixMulPfS_S_i, @function
_Z19version_1_matrixMulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19version_1_matrixMulPfS_S_i, .-_Z19version_1_matrixMulPfS_S_i
.globl _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19version_2_matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
.globl _Z19version_2_matrixMulPfS_S_i
.type _Z19version_2_matrixMulPfS_S_i, @function
_Z19version_2_matrixMulPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19version_2_matrixMulPfS_S_i, .-_Z19version_2_matrixMulPfS_S_i
.section .rodata.str1.1
.LC2:
.string "Usage: \n"
.LC3:
.string "/lab4 <matrixSize>"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "=====This is naive version.======\n"
.align 8
.LC6:
.string "For naive version, the elapsed time is %.4f(ms).\n"
.align 8
.LC7:
.string "=====This is tiled version.======\n"
.align 8
.LC8:
.string "For tiled version, the elapsed time is %.4f(ms).\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $13, %edi
call srand@PLT
cmpl $2, %ebx
je .L26
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L25:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 40(%rsp)
movl %eax, 20(%rsp)
imull %eax, %eax
cltq
leaq 0(,%rax,4), %r14
movq %r14, 24(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %ebx, %ebx
jle .L28
movslq %ebx, %r15
salq $2, %r15
leal -1(%rbx), %eax
leaq 4(%rbp,%rax,4), %r12
movl $0, %r13d
movl $0, %r14d
.L29:
movq (%rsp), %rax
leaq (%rax,%r13), %rbx
movq 8(%rsp), %rax
leaq (%rax,%r13), %rbp
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L30
addl $1, %r14d
addq %r15, %r12
addq %r15, %r13
movl 20(%rsp), %eax
cmpl %eax, %r14d
jne .L29
.L28:
leaq 56(%rsp), %rdi
movq 24(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl 40(%rsp), %eax
shrl $4, %eax
movl %eax, 108(%rsp)
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 96(%rsp)
movl $16, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movq 24(%rsp), %rbx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L32:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L25
.L37:
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
jmp .L31
.L38:
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z19version_2_matrixMulPfS_S_i"
.align 8
.LC10:
.string "_Z19version_1_matrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19version_2_matrixMulPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z19version_1_matrixMulPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1717986918
.long 1101633945
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include <cuda_runtime.h>
#define seed 13
#define block_size 16
void printMatrix(float *matrix, int size){
int i;
for(i=0;i<size*size;i++){
if(i%size == 0 && i != 0)
printf("\n");
printf("%10.1f", matrix[i]);
}
printf("\n");
}
__global__ void version_1_matrixMul(float *dev_A, float *dev_B, float* dev_C,
int N){
// Each thread computes one elements of h_C
// by accumulating results into dev_C
float partial = 0.0;
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int k;
for(k =0; k < N;k++){
partial += dev_A[i * N + k] * dev_B[k * N + j];
}
dev_C[i * N + j] = partial;
}
__global__ void version_2_matrixMul(float *dev_A, float *dev_B, float *dev_C,
int matrix_size)
{
__shared__ float A_tile[block_size][block_size];
__shared__ float B_tile[block_size][block_size];
float partial = 0.0;
// block index
int bx = blockIdx.x;
int by = blockIdx.y;
// thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
// by the block
int m;
for( m=0 ; m < matrix_size/blockDim.x; m++){
A_tile[ty][tx] = dev_A[row * matrix_size + (m * block_size + tx)];
B_tile[ty][tx] = dev_B[col + (m * block_size + ty) * matrix_size];
__syncthreads();
int k;
for(k=0; k< blockDim.x; k++)
partial += A_tile[ty][k] * B_tile[k][tx];
__syncthreads();
dev_C[row * matrix_size + col] = partial;
}
}
int main(int argc, char **argv){
srand(seed);
if(argc != 2){
printf("Usage: \n");
printf("/lab4 <matrixSize>");
return 1;
}
int matrix_size = atoi(argv[1]);
float *h_A = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_B = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_C = (float*) malloc(matrix_size * matrix_size * sizeof(float));
int i,j;
for(i=0;i<matrix_size;i++){
for(j=0;j<matrix_size;j++){
h_A[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
h_B[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
}
}
//printf("This is matrix A: %d\n", matrix_size);
//printMatrix(h_A, matrix_size);
//printf("This is matrix B: \n");
//printMatrix(h_B, matrix_size);
float *d_A, *d_B, *d_C;
cudaMalloc((void**) &d_A, matrix_size * matrix_size * sizeof(float));
cudaMalloc((void**) &d_B, matrix_size * matrix_size * sizeof(float));
cudaMalloc((void**) &d_C, matrix_size * matrix_size * sizeof(float));
dim3 Block(block_size, block_size, 1);
dim3 Grid(matrix_size / Block.x, matrix_size / Block.y, 1);
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("=====This is naive version.======\n");
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
version_1_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
cudaMemcpy(h_C, d_C, matrix_size * matrix_size * sizeof(float),
cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("For naive version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
printf("=====This is tiled version.======\n");
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
cudaMemcpyHostToDevice);
version_2_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
cudaMemcpy(h_C, d_C, matrix_size* matrix_size * sizeof(float),
cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("For tiled version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | #include<stdlib.h>
#include<stdio.h>
#include <hip/hip_runtime.h>
#define seed 13
#define block_size 16
void printMatrix(float *matrix, int size){
int i;
for(i=0;i<size*size;i++){
if(i%size == 0 && i != 0)
printf("\n");
printf("%10.1f", matrix[i]);
}
printf("\n");
}
__global__ void version_1_matrixMul(float *dev_A, float *dev_B, float* dev_C,
int N){
// Each thread computes one elements of h_C
// by accumulating results into dev_C
float partial = 0.0;
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int k;
for(k =0; k < N;k++){
partial += dev_A[i * N + k] * dev_B[k * N + j];
}
dev_C[i * N + j] = partial;
}
__global__ void version_2_matrixMul(float *dev_A, float *dev_B, float *dev_C,
int matrix_size)
{
__shared__ float A_tile[block_size][block_size];
__shared__ float B_tile[block_size][block_size];
float partial = 0.0;
// block index
int bx = blockIdx.x;
int by = blockIdx.y;
// thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
// by the block
int m;
for( m=0 ; m < matrix_size/blockDim.x; m++){
A_tile[ty][tx] = dev_A[row * matrix_size + (m * block_size + tx)];
B_tile[ty][tx] = dev_B[col + (m * block_size + ty) * matrix_size];
__syncthreads();
int k;
for(k=0; k< blockDim.x; k++)
partial += A_tile[ty][k] * B_tile[k][tx];
__syncthreads();
dev_C[row * matrix_size + col] = partial;
}
}
int main(int argc, char **argv){
srand(seed);
if(argc != 2){
printf("Usage: \n");
printf("/lab4 <matrixSize>");
return 1;
}
int matrix_size = atoi(argv[1]);
float *h_A = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_B = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_C = (float*) malloc(matrix_size * matrix_size * sizeof(float));
int i,j;
for(i=0;i<matrix_size;i++){
for(j=0;j<matrix_size;j++){
h_A[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
h_B[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
}
}
//printf("This is matrix A: %d\n", matrix_size);
//printMatrix(h_A, matrix_size);
//printf("This is matrix B: \n");
//printMatrix(h_B, matrix_size);
float *d_A, *d_B, *d_C;
hipMalloc((void**) &d_A, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_B, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_C, matrix_size * matrix_size * sizeof(float));
dim3 Block(block_size, block_size, 1);
dim3 Grid(matrix_size / Block.x, matrix_size / Block.y, 1);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("=====This is naive version.======\n");
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_1_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size * matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For naive version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
printf("=====This is tiled version.======\n");
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_2_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size* matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For tiled version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdlib.h>
#include<stdio.h>
#include <hip/hip_runtime.h>
#define seed 13
#define block_size 16
void printMatrix(float *matrix, int size){
int i;
for(i=0;i<size*size;i++){
if(i%size == 0 && i != 0)
printf("\n");
printf("%10.1f", matrix[i]);
}
printf("\n");
}
__global__ void version_1_matrixMul(float *dev_A, float *dev_B, float* dev_C,
int N){
// Each thread computes one elements of h_C
// by accumulating results into dev_C
float partial = 0.0;
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int k;
for(k =0; k < N;k++){
partial += dev_A[i * N + k] * dev_B[k * N + j];
}
dev_C[i * N + j] = partial;
}
__global__ void version_2_matrixMul(float *dev_A, float *dev_B, float *dev_C,
int matrix_size)
{
__shared__ float A_tile[block_size][block_size];
__shared__ float B_tile[block_size][block_size];
float partial = 0.0;
// block index
int bx = blockIdx.x;
int by = blockIdx.y;
// thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
// by the block
int m;
for( m=0 ; m < matrix_size/blockDim.x; m++){
A_tile[ty][tx] = dev_A[row * matrix_size + (m * block_size + tx)];
B_tile[ty][tx] = dev_B[col + (m * block_size + ty) * matrix_size];
__syncthreads();
int k;
for(k=0; k< blockDim.x; k++)
partial += A_tile[ty][k] * B_tile[k][tx];
__syncthreads();
dev_C[row * matrix_size + col] = partial;
}
}
int main(int argc, char **argv){
srand(seed);
if(argc != 2){
printf("Usage: \n");
printf("/lab4 <matrixSize>");
return 1;
}
int matrix_size = atoi(argv[1]);
float *h_A = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_B = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_C = (float*) malloc(matrix_size * matrix_size * sizeof(float));
int i,j;
for(i=0;i<matrix_size;i++){
for(j=0;j<matrix_size;j++){
h_A[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
h_B[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
}
}
//printf("This is matrix A: %d\n", matrix_size);
//printMatrix(h_A, matrix_size);
//printf("This is matrix B: \n");
//printMatrix(h_B, matrix_size);
float *d_A, *d_B, *d_C;
hipMalloc((void**) &d_A, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_B, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_C, matrix_size * matrix_size * sizeof(float));
dim3 Block(block_size, block_size, 1);
dim3 Grid(matrix_size / Block.x, matrix_size / Block.y, 1);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("=====This is naive version.======\n");
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_1_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size * matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For naive version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
printf("=====This is tiled version.======\n");
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_2_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size* matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For tiled version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19version_1_matrixMulPfS_S_i
.globl _Z19version_1_matrixMulPfS_S_i
.p2align 8
.type _Z19version_1_matrixMulPfS_S_i,@function
_Z19version_1_matrixMulPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19version_1_matrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19version_1_matrixMulPfS_S_i, .Lfunc_end0-_Z19version_1_matrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z19version_2_matrixMulPfS_S_i
.globl _Z19version_2_matrixMulPfS_S_i
.p2align 8
.type _Z19version_2_matrixMulPfS_S_i,@function
_Z19version_2_matrixMulPfS_S_i:
s_load_b32 s4, s[0:1], 0x2c
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_load_b32 s4, s[0:1], 0x18
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_waitcnt lgkmcnt(0)
s_cmp_gt_u32 s6, s4
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_readfirstlane_b32 s5, v1
s_cbranch_scc1 .LBB1_5
s_sub_i32 s7, 0, s6
s_load_b32 s2, s[2:3], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_mul_i32 s7, s7, s5
v_bfe_u32 v1, v0, 10, 10
s_mul_hi_u32 s3, s5, s7
v_and_b32_e32 v8, 0x3ff, v0
s_add_i32 s5, s5, s3
v_lshlrev_b32_e32 v0, 6, v1
s_mul_hi_u32 s3, s4, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b32_e32 v6, 2, v8
s_mul_i32 s5, s3, s6
s_add_i32 s7, s3, 1
s_sub_i32 s5, s4, s5
s_sub_i32 s8, s5, s6
s_cmp_ge_u32 s5, s6
s_cselect_b32 s3, s7, s3
s_cselect_b32 s5, s8, s5
s_add_i32 s7, s3, 1
s_cmp_ge_u32 s5, s6
s_load_b64 s[8:9], s[0:1], 0x10
s_cselect_b32 s5, s7, s3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_mov_b32 s7, 0
v_mad_u64_u32 v[4:5], null, s15, s2, v[1:2]
v_mad_u64_u32 v[2:3], null, s14, s6, v[8:9]
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v5, 0x400, v6
v_add_nc_u32_e32 v6, v0, v6
s_max_u32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v4, s4
v_add_nc_u32_e32 v7, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v9, v2
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, v9, v8
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_2:
s_lshl_b32 s8, s7, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, s8, v1
v_add_nc_u32_e32 v10, s8, v8
s_mov_b32 s8, s6
v_mad_u64_u32 v[12:13], null, v11, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v13, 31, v12
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[12:13], 2, v[12:13]
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, vcc_lo, s2, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
global_load_b32 v14, v[10:11], off
global_load_b32 v12, v[12:13], off
v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v10, v5
s_waitcnt vmcnt(1)
ds_store_b32 v6, v14
s_waitcnt vmcnt(0)
ds_store_b32 v7, v12
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_3:
ds_load_b32 v12, v11
ds_load_b32 v13, v10
v_add_nc_u32_e32 v11, 4, v11
v_add_nc_u32_e32 v10, 64, v10
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s8, 0
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v12, v13
s_cbranch_scc1 .LBB1_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_u32 s7, s5
s_barrier
buffer_gl0_inv
global_store_b32 v[3:4], v9, off
s_cbranch_scc1 .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19version_2_matrixMulPfS_S_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z19version_2_matrixMulPfS_S_i, .Lfunc_end1-_Z19version_2_matrixMulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19version_1_matrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19version_1_matrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19version_2_matrixMulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19version_2_matrixMulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdlib.h>
#include<stdio.h>
#include <hip/hip_runtime.h>
#define seed 13
#define block_size 16
void printMatrix(float *matrix, int size){
int i;
for(i=0;i<size*size;i++){
if(i%size == 0 && i != 0)
printf("\n");
printf("%10.1f", matrix[i]);
}
printf("\n");
}
__global__ void version_1_matrixMul(float *dev_A, float *dev_B, float* dev_C,
int N){
// Each thread computes one elements of h_C
// by accumulating results into dev_C
float partial = 0.0;
int i = blockIdx.y * blockDim.y + threadIdx.y;
int j = blockIdx.x * blockDim.x + threadIdx.x;
int k;
for(k =0; k < N;k++){
partial += dev_A[i * N + k] * dev_B[k * N + j];
}
dev_C[i * N + j] = partial;
}
__global__ void version_2_matrixMul(float *dev_A, float *dev_B, float *dev_C,
int matrix_size)
{
__shared__ float A_tile[block_size][block_size];
__shared__ float B_tile[block_size][block_size];
float partial = 0.0;
// block index
int bx = blockIdx.x;
int by = blockIdx.y;
// thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
// by the block
int m;
for( m=0 ; m < matrix_size/blockDim.x; m++){
A_tile[ty][tx] = dev_A[row * matrix_size + (m * block_size + tx)];
B_tile[ty][tx] = dev_B[col + (m * block_size + ty) * matrix_size];
__syncthreads();
int k;
for(k=0; k< blockDim.x; k++)
partial += A_tile[ty][k] * B_tile[k][tx];
__syncthreads();
dev_C[row * matrix_size + col] = partial;
}
}
int main(int argc, char **argv){
srand(seed);
if(argc != 2){
printf("Usage: \n");
printf("/lab4 <matrixSize>");
return 1;
}
int matrix_size = atoi(argv[1]);
float *h_A = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_B = (float*) malloc(matrix_size * matrix_size * sizeof(float));
float *h_C = (float*) malloc(matrix_size * matrix_size * sizeof(float));
int i,j;
for(i=0;i<matrix_size;i++){
for(j=0;j<matrix_size;j++){
h_A[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
h_B[i * matrix_size + j] = (float)rand()/((float)RAND_MAX/10.0);
}
}
//printf("This is matrix A: %d\n", matrix_size);
//printMatrix(h_A, matrix_size);
//printf("This is matrix B: \n");
//printMatrix(h_B, matrix_size);
float *d_A, *d_B, *d_C;
hipMalloc((void**) &d_A, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_B, matrix_size * matrix_size * sizeof(float));
hipMalloc((void**) &d_C, matrix_size * matrix_size * sizeof(float));
dim3 Block(block_size, block_size, 1);
dim3 Grid(matrix_size / Block.x, matrix_size / Block.y, 1);
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("=====This is naive version.======\n");
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_1_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size * matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For naive version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
printf("=====This is tiled version.======\n");
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipMemcpy(d_A, h_A, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B, matrix_size * matrix_size * sizeof(float),
hipMemcpyHostToDevice);
version_2_matrixMul<<< Grid, Block >>>(d_A, d_B, d_C, matrix_size);
hipMemcpy(h_C, d_C, matrix_size* matrix_size * sizeof(float),
hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("For tiled version, the elapsed time is %.4f(ms).\n", elapsedTime);
//printf("This is matrix C: \n");
//printMatrix(h_C, matrix_size);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
return 0;
} | .text
.file "lab4_2.hip"
.globl _Z11printMatrixPfi # -- Begin function _Z11printMatrixPfi
.p2align 4, 0x90
.type _Z11printMatrixPfi,@function
_Z11printMatrixPfi: # @_Z11printMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_7
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r12d
imull %r12d, %r12d
cmpl $1, %r12d
adcl $0, %r12d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r15d, %eax
cltd
idivl %ebx
testq %r15, %r15
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
testl %edx, %edx
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_5
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB0_7: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfi, .Lfunc_end0-_Z11printMatrixPfi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__version_1_matrixMulPfS_S_i # -- Begin function _Z34__device_stub__version_1_matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__version_1_matrixMulPfS_S_i,@function
_Z34__device_stub__version_1_matrixMulPfS_S_i: # @_Z34__device_stub__version_1_matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19version_1_matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__version_1_matrixMulPfS_S_i, .Lfunc_end1-_Z34__device_stub__version_1_matrixMulPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__version_2_matrixMulPfS_S_i # -- Begin function _Z34__device_stub__version_2_matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__version_2_matrixMulPfS_S_i,@function
_Z34__device_stub__version_2_matrixMulPfS_S_i: # @_Z34__device_stub__version_2_matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19version_2_matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__version_2_matrixMulPfS_S_i, .Lfunc_end2-_Z34__device_stub__version_2_matrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41a999999999999a # double 214748364.80000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $13, %edi
callq srand
cmpl $2, %ebp
jne .LBB3_1
# %bb.2:
movq 8(%rbx), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 136(%rsp) # 8-byte Spill
movl %eax, %r12d
movl %eax, %r15d
imull %r15d, %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 184(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
movl %r12d, 28(%rsp) # 4-byte Spill
testl %r12d, %r12d
jle .LBB3_7
# %bb.3: # %.preheader.lr.ph
movl 136(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
movq %r14, 208(%rsp) # 8-byte Spill
movq %rbx, 200(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl %ebp, %eax
leaq (%rbx,%rax,4), %rbx
leaq (%r14,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r15,4)
callq rand
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB3_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %r13
addl 28(%rsp), %ebp # 4-byte Folded Reload
cmpq %r12, %r13
movq 208(%rsp), %r14 # 8-byte Reload
movq 200(%rsp), %rbx # 8-byte Reload
jne .LBB3_4
.LBB3_7: # %._crit_edge88
movabsq $68719476752, %r15 # imm = 0x1000000010
leaq 56(%rsp), %rdi
movq 184(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 136(%rsp), %rax # 8-byte Reload
shrl $4, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z19version_1_matrixMulPfS_S_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 40(%rsp), %rsi
movq 192(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z19version_2_matrixMulPfS_S_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
jmp .LBB3_12
.LBB3_1:
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $1, %r13d
.LBB3_12:
movl %r13d, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19version_1_matrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19version_2_matrixMulPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%10.1f"
.size .L.str.1, 7
.type _Z19version_1_matrixMulPfS_S_i,@object # @_Z19version_1_matrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z19version_1_matrixMulPfS_S_i
.p2align 3, 0x0
_Z19version_1_matrixMulPfS_S_i:
.quad _Z34__device_stub__version_1_matrixMulPfS_S_i
.size _Z19version_1_matrixMulPfS_S_i, 8
.type _Z19version_2_matrixMulPfS_S_i,@object # @_Z19version_2_matrixMulPfS_S_i
.globl _Z19version_2_matrixMulPfS_S_i
.p2align 3, 0x0
_Z19version_2_matrixMulPfS_S_i:
.quad _Z34__device_stub__version_2_matrixMulPfS_S_i
.size _Z19version_2_matrixMulPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "/lab4 <matrixSize>"
.size .L.str.3, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "For naive version, the elapsed time is %.4f(ms).\n"
.size .L.str.5, 50
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "For tiled version, the elapsed time is %.4f(ms).\n"
.size .L.str.7, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19version_1_matrixMulPfS_S_i"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19version_2_matrixMulPfS_S_i"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "=====This is naive version.======"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "=====This is tiled version.======"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Usage: "
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__version_1_matrixMulPfS_S_i
.addrsig_sym _Z34__device_stub__version_2_matrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19version_1_matrixMulPfS_S_i
.addrsig_sym _Z19version_2_matrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d12ab_00000000-6_lab4_2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "%10.1f"
.text
.globl _Z11printMatrixPfi
.type _Z11printMatrixPfi, @function
_Z11printMatrixPfi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r12d
imull %esi, %r12d
testl %r12d, %r12d
jle .L4
movq %rdi, %r13
movl %esi, %ebp
movslq %r12d, %r12
movl $0, %ebx
leaq .LC0(%rip), %r15
leaq .LC1(%rip), %r14
jmp .L6
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
je .L4
.L6:
movl %ebx, %eax
cltd
idivl %ebp
testl %edx, %edx
jne .L5
testl %ebx, %ebx
je .L5
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11printMatrixPfi, .-_Z11printMatrixPfi
.globl _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19version_1_matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
.globl _Z19version_1_matrixMulPfS_S_i
.type _Z19version_1_matrixMulPfS_S_i, @function
_Z19version_1_matrixMulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19version_1_matrixMulPfS_S_i, .-_Z19version_1_matrixMulPfS_S_i
.globl _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
.type _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i, @function
_Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19version_2_matrixMulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i, .-_Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
.globl _Z19version_2_matrixMulPfS_S_i
.type _Z19version_2_matrixMulPfS_S_i, @function
_Z19version_2_matrixMulPfS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z19version_2_matrixMulPfS_S_i, .-_Z19version_2_matrixMulPfS_S_i
.section .rodata.str1.1
.LC2:
.string "Usage: \n"
.LC3:
.string "/lab4 <matrixSize>"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "=====This is naive version.======\n"
.align 8
.LC6:
.string "For naive version, the elapsed time is %.4f(ms).\n"
.align 8
.LC7:
.string "=====This is tiled version.======\n"
.align 8
.LC8:
.string "For tiled version, the elapsed time is %.4f(ms).\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $13, %edi
call srand@PLT
cmpl $2, %ebx
je .L26
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L25:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, 40(%rsp)
movl %eax, 20(%rsp)
imull %eax, %eax
cltq
leaq 0(,%rax,4), %r14
movq %r14, 24(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r14, %rdi
call malloc@PLT
movq %rax, 32(%rsp)
testl %ebx, %ebx
jle .L28
movslq %ebx, %r15
salq $2, %r15
leal -1(%rbx), %eax
leaq 4(%rbp,%rax,4), %r12
movl $0, %r13d
movl $0, %r14d
.L29:
movq (%rsp), %rax
leaq (%rax,%r13), %rbx
movq 8(%rsp), %rax
leaq (%rax,%r13), %rbp
.L30:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
addq $4, %rbp
cmpq %r12, %rbx
jne .L30
addl $1, %r14d
addq %r15, %r12
addq %r15, %r13
movl 20(%rsp), %eax
cmpl %eax, %r14d
jne .L29
.L28:
leaq 56(%rsp), %rdi
movq 24(%rsp), %rbx
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, 104(%rsp)
movl 40(%rsp), %eax
shrl $4, %eax
movl %eax, 108(%rsp)
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 96(%rsp)
movl $16, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L31:
movl $2, %ecx
movq 24(%rsp), %rbx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L32:
movl $2, %ecx
movq 24(%rsp), %rdx
movq 72(%rsp), %rsi
movq 32(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
jmp .L25
.L37:
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z19version_1_matrixMulPfS_S_iPfS_S_i
jmp .L31
.L38:
movl 20(%rsp), %ecx
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z44__device_stub__Z19version_2_matrixMulPfS_S_iPfS_S_i
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC9:
.string "_Z19version_2_matrixMulPfS_S_i"
.align 8
.LC10:
.string "_Z19version_1_matrixMulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z19version_2_matrixMulPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z19version_1_matrixMulPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long -1717986918
.long 1101633945
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab4_2.hip"
.globl _Z11printMatrixPfi # -- Begin function _Z11printMatrixPfi
.p2align 4, 0x90
.type _Z11printMatrixPfi,@function
_Z11printMatrixPfi: # @_Z11printMatrixPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB0_7
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
movl %esi, %r12d
imull %r12d, %r12d
cmpl $1, %r12d
adcl $0, %r12d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r15d, %eax
cltd
idivl %ebx
testq %r15, %r15
je .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
testl %edx, %edx
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_5
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB0_7: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z11printMatrixPfi, .Lfunc_end0-_Z11printMatrixPfi
.cfi_endproc
# -- End function
.globl _Z34__device_stub__version_1_matrixMulPfS_S_i # -- Begin function _Z34__device_stub__version_1_matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__version_1_matrixMulPfS_S_i,@function
_Z34__device_stub__version_1_matrixMulPfS_S_i: # @_Z34__device_stub__version_1_matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19version_1_matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z34__device_stub__version_1_matrixMulPfS_S_i, .Lfunc_end1-_Z34__device_stub__version_1_matrixMulPfS_S_i
.cfi_endproc
# -- End function
.globl _Z34__device_stub__version_2_matrixMulPfS_S_i # -- Begin function _Z34__device_stub__version_2_matrixMulPfS_S_i
.p2align 4, 0x90
.type _Z34__device_stub__version_2_matrixMulPfS_S_i,@function
_Z34__device_stub__version_2_matrixMulPfS_S_i: # @_Z34__device_stub__version_2_matrixMulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19version_2_matrixMulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z34__device_stub__version_2_matrixMulPfS_S_i, .Lfunc_end2-_Z34__device_stub__version_2_matrixMulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41a999999999999a # double 214748364.80000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $13, %edi
callq srand
cmpl $2, %ebp
jne .LBB3_1
# %bb.2:
movq 8(%rbx), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 136(%rsp) # 8-byte Spill
movl %eax, %r12d
movl %eax, %r15d
imull %r15d, %r15d
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %r15, 184(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, 192(%rsp) # 8-byte Spill
movl %r12d, 28(%rsp) # 4-byte Spill
testl %r12d, %r12d
jle .LBB3_7
# %bb.3: # %.preheader.lr.ph
movl 136(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
movq %r14, 208(%rsp) # 8-byte Spill
movq %rbx, 200(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_4: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl %ebp, %eax
leaq (%rbx,%rax,4), %rbx
leaq (%r14,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd .LCPI3_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r15,4)
callq rand
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cvtss2sd %xmm0, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB3_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB3_4 Depth=1
incq %r13
addl 28(%rsp), %ebp # 4-byte Folded Reload
cmpq %r12, %r13
movq 208(%rsp), %r14 # 8-byte Reload
movq 200(%rsp), %rbx # 8-byte Reload
jne .LBB3_4
.LBB3_7: # %._crit_edge88
movabsq $68719476752, %r15 # imm = 0x1000000010
leaq 56(%rsp), %rdi
movq 184(%rsp), %r12 # 8-byte Reload
movq %r12, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 136(%rsp), %rax # 8-byte Reload
shrl $4, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z19version_1_matrixMulPfS_S_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9:
movq 40(%rsp), %rsi
movq 192(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
leaq 128(%rsp), %rax
movq %rax, 144(%rsp)
leaq 120(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z19version_2_matrixMulPfS_S_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
jmp .LBB3_12
.LBB3_1:
movl $.Lstr.2, %edi
callq puts@PLT
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl $1, %r13d
.LBB3_12:
movl %r13d, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19version_1_matrixMulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19version_2_matrixMulPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%10.1f"
.size .L.str.1, 7
.type _Z19version_1_matrixMulPfS_S_i,@object # @_Z19version_1_matrixMulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z19version_1_matrixMulPfS_S_i
.p2align 3, 0x0
_Z19version_1_matrixMulPfS_S_i:
.quad _Z34__device_stub__version_1_matrixMulPfS_S_i
.size _Z19version_1_matrixMulPfS_S_i, 8
.type _Z19version_2_matrixMulPfS_S_i,@object # @_Z19version_2_matrixMulPfS_S_i
.globl _Z19version_2_matrixMulPfS_S_i
.p2align 3, 0x0
_Z19version_2_matrixMulPfS_S_i:
.quad _Z34__device_stub__version_2_matrixMulPfS_S_i
.size _Z19version_2_matrixMulPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "/lab4 <matrixSize>"
.size .L.str.3, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "For naive version, the elapsed time is %.4f(ms).\n"
.size .L.str.5, 50
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "For tiled version, the elapsed time is %.4f(ms).\n"
.size .L.str.7, 50
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19version_1_matrixMulPfS_S_i"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z19version_2_matrixMulPfS_S_i"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "=====This is naive version.======"
.size .Lstr, 34
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "=====This is tiled version.======"
.size .Lstr.1, 34
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Usage: "
.size .Lstr.2, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__version_1_matrixMulPfS_S_i
.addrsig_sym _Z34__device_stub__version_2_matrixMulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19version_1_matrixMulPfS_S_i
.addrsig_sym _Z19version_2_matrixMulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<time.h>
__global__ void gathertrajctoryKernel(int b,int n,int m,int t,const float * __restrict__ inp,const int * __restrict__ idx, float * __restrict__ out){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
out[tmp_idx1*3+0]=inp[tmp_idx2*3+0];
out[tmp_idx1*3+1]=inp[tmp_idx2*3+1];
out[tmp_idx1*3+2]=inp[tmp_idx2*3+2];
}
}
}
}
void gathertrajctoryLauncher(int b,int n,int m,int t,const float * inp,const int *idx, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajctoryKernel<<<32,512>>>(b,n,m,t,inp,idx,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajctoryKernel:%f b:%d n:%d m:%d t:%d \n",totaltime,b,n,m,t);
}
__global__ void gathertrajectorygradKernel(int b,int n,int m,int t,const float * __restrict__ out_g,const int * __restrict__ idx,float * __restrict__ inp_g){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
atomicAdd(&inp_g[tmp_idx2*3+0],out_g[tmp_idx1*3+0]);
atomicAdd(&inp_g[tmp_idx2*3+1],out_g[tmp_idx1*3+1]);
atomicAdd(&inp_g[tmp_idx2*3+2],out_g[tmp_idx1*3+2]);
}
}
}
}
void gathertrajectorygradLauncher(int b,int n,int m,int t,const float * out_g,const int * idx,float * inp_g){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajectorygradKernel<<<32,128>>>(b,n,m,t,out_g,idx,inp_g);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajectorygradKernel:%f \n",totaltime);
}
__global__ void farthestpointsamplingtrajectoryKernel(int b,int n,int m,int t,const float * __restrict__ trajectory,float * __restrict__ temp,int * __restrict__ sample_idx){
const int BlockSize = 512;
__shared__ float max_dists[BlockSize];
__shared__ int dists_idx[BlockSize];
const int BufferSize=2880;
__shared__ float buf[BufferSize*3];
const int framesize = 64;
__shared__ float framebufx[framesize];
__shared__ float framebufy[framesize];
__shared__ float framebufz[framesize];
for(int i=blockIdx.x;i<b;i+=gridDim.x){ //batch init
int last = 0;
if (threadIdx.x==0)
sample_idx[i*m+0]=last;
for(int j=threadIdx.x;j<n;j+=blockDim.x){
temp[blockIdx.x*n+j]=1e38;
}
for(int j=threadIdx.x;j<min(BufferSize,n*t)*3;j+=blockDim.x){
buf[j]=trajectory[i*n*t*3+j];
}
__syncthreads();
for(int j=0;j<m;j++){ //each sample step
float t_max_dists = -1;
int t_dist_idx = 0;
for(int k=0;k<min(t,framesize);k++){
int tmp_idx = i*n*t*3 + last*t*3 + k*3;
framebufx[k] = trajectory[tmp_idx + 0];
framebufy[k] = trajectory[tmp_idx + 1];
framebufz[k] = trajectory[tmp_idx + 2];
}
for(int k=threadIdx.x;k<n;k+=blockDim.x){ //compute dis
float td=temp[blockIdx.x*n+k];
float td_new = 0;
float tx1=0,ty1=0,tz1=0,tx2=0,ty2=0,tz2=0;
for(int u=0;u<t;u++){
if(u<framesize){
int tmp_idx = u;
tx1=framebufx[tmp_idx];
ty1=framebufy[tmp_idx];
tz1=framebufz[tmp_idx];
}else{
int tmp_idx = i*n*t*3 + last*t*3 + u*3;
tx1=trajectory[tmp_idx+0];
ty1=trajectory[tmp_idx+1];
tz1=trajectory[tmp_idx+2];
}
if(k*t+u<BufferSize){
int tmp_idx = (k*t+u)*3;
tx2=buf[tmp_idx+0];
ty2=buf[tmp_idx+1];
tz2=buf[tmp_idx+2];
}else{
int tmp_idx = i*n*t*3 + k*t*3 + u*3;
tx2=trajectory[tmp_idx+0];
ty2=trajectory[tmp_idx+1];
tz2=trajectory[tmp_idx+2];
}
td_new += max(((tx2-tx1)*(tx2-tx1)+(ty2-ty1)*(ty2-ty1)+(tz2-tz1)*(tz2-tz1)),1e-20f);
}
td_new/=t;
float d2=min(td,td_new);
if(d2!=td)
temp[blockIdx.x*n+k]=d2;
if(d2>t_max_dists){
t_max_dists=d2;
t_dist_idx=k;
}
}
max_dists[threadIdx.x]=t_max_dists;
dists_idx[threadIdx.x]=t_dist_idx;
for (int u=0;(1<<u)<blockDim.x;u++){ //reduce min
__syncthreads();
if (threadIdx.x<(blockDim.x>>(u+1))){
int i1=(threadIdx.x*2)<<u;
int i2=(threadIdx.x*2+1)<<u;
if (max_dists[i1]<max_dists[i2]){
max_dists[i1]=max_dists[i2];
dists_idx[i1]=dists_idx[i2];
}
}
}
__syncthreads();
last=dists_idx[0];
if (threadIdx.x==0)
sample_idx[i*m+j]=last;
}
}
}
//require 32*n working space
void farthestpointsamplingtrajectoryLauncher(int b,int n,int m,int t,const float * inp,float * temp,int *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
farthestpointsamplingtrajectoryKernel<<<32,512>>>(b,n,m,t,inp,temp,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("farthestpointsamplingtrajectoryKernel:%f \n",totaltime);
} | .file "tmpxft_001131c5_00000000-6_sampling_trajectory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
.type _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf, @function
_Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21gathertrajctoryKerneliiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf, .-_Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
.globl _Z21gathertrajctoryKerneliiiiPKfPKiPf
.type _Z21gathertrajctoryKerneliiiiPKfPKiPf, @function
_Z21gathertrajctoryKerneliiiiPKfPKiPf:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z21gathertrajctoryKerneliiiiPKfPKiPf, .-_Z21gathertrajctoryKerneliiiiPKfPKiPf
.globl _Z23gathertrajctoryLauncheriiiiPKfPKiPf
.type _Z23gathertrajctoryLauncheriiiiPKfPKiPf, @function
_Z23gathertrajctoryLauncheriiiiPKfPKiPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z23gathertrajctoryLauncheriiiiPKfPKiPf, .-_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.globl _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
.type _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf, @function
_Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26gathertrajectorygradKerneliiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf, .-_Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
.globl _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.type _Z26gathertrajectorygradKerneliiiiPKfPKiPf, @function
_Z26gathertrajectorygradKerneliiiiPKfPKiPf:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z26gathertrajectorygradKerneliiiiPKfPKiPf, .-_Z26gathertrajectorygradKerneliiiiPKfPKiPf
.globl _Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.type _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, @function
_Z28gathertrajectorygradLauncheriiiiPKfPKiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, .-_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.globl _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
.type _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi, @function
_Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi, .-_Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
.globl _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.type _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, @function
_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, .-_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.globl _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.type _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, @function
_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2059:
.size _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, .-_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi"
.align 8
.LC1:
.string "_Z26gathertrajectorygradKerneliiiiPKfPKiPf"
.align 8
.LC2:
.string "_Z21gathertrajctoryKerneliiiiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gathertrajectorygradKerneliiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21gathertrajctoryKerneliiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<time.h>
__global__ void gathertrajctoryKernel(int b,int n,int m,int t,const float * __restrict__ inp,const int * __restrict__ idx, float * __restrict__ out){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
out[tmp_idx1*3+0]=inp[tmp_idx2*3+0];
out[tmp_idx1*3+1]=inp[tmp_idx2*3+1];
out[tmp_idx1*3+2]=inp[tmp_idx2*3+2];
}
}
}
}
void gathertrajctoryLauncher(int b,int n,int m,int t,const float * inp,const int *idx, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajctoryKernel<<<32,512>>>(b,n,m,t,inp,idx,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajctoryKernel:%f b:%d n:%d m:%d t:%d \n",totaltime,b,n,m,t);
}
__global__ void gathertrajectorygradKernel(int b,int n,int m,int t,const float * __restrict__ out_g,const int * __restrict__ idx,float * __restrict__ inp_g){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
atomicAdd(&inp_g[tmp_idx2*3+0],out_g[tmp_idx1*3+0]);
atomicAdd(&inp_g[tmp_idx2*3+1],out_g[tmp_idx1*3+1]);
atomicAdd(&inp_g[tmp_idx2*3+2],out_g[tmp_idx1*3+2]);
}
}
}
}
void gathertrajectorygradLauncher(int b,int n,int m,int t,const float * out_g,const int * idx,float * inp_g){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajectorygradKernel<<<32,128>>>(b,n,m,t,out_g,idx,inp_g);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajectorygradKernel:%f \n",totaltime);
}
__global__ void farthestpointsamplingtrajectoryKernel(int b,int n,int m,int t,const float * __restrict__ trajectory,float * __restrict__ temp,int * __restrict__ sample_idx){
const int BlockSize = 512;
__shared__ float max_dists[BlockSize];
__shared__ int dists_idx[BlockSize];
const int BufferSize=2880;
__shared__ float buf[BufferSize*3];
const int framesize = 64;
__shared__ float framebufx[framesize];
__shared__ float framebufy[framesize];
__shared__ float framebufz[framesize];
for(int i=blockIdx.x;i<b;i+=gridDim.x){ //batch init
int last = 0;
if (threadIdx.x==0)
sample_idx[i*m+0]=last;
for(int j=threadIdx.x;j<n;j+=blockDim.x){
temp[blockIdx.x*n+j]=1e38;
}
for(int j=threadIdx.x;j<min(BufferSize,n*t)*3;j+=blockDim.x){
buf[j]=trajectory[i*n*t*3+j];
}
__syncthreads();
for(int j=0;j<m;j++){ //each sample step
float t_max_dists = -1;
int t_dist_idx = 0;
for(int k=0;k<min(t,framesize);k++){
int tmp_idx = i*n*t*3 + last*t*3 + k*3;
framebufx[k] = trajectory[tmp_idx + 0];
framebufy[k] = trajectory[tmp_idx + 1];
framebufz[k] = trajectory[tmp_idx + 2];
}
for(int k=threadIdx.x;k<n;k+=blockDim.x){ //compute dis
float td=temp[blockIdx.x*n+k];
float td_new = 0;
float tx1=0,ty1=0,tz1=0,tx2=0,ty2=0,tz2=0;
for(int u=0;u<t;u++){
if(u<framesize){
int tmp_idx = u;
tx1=framebufx[tmp_idx];
ty1=framebufy[tmp_idx];
tz1=framebufz[tmp_idx];
}else{
int tmp_idx = i*n*t*3 + last*t*3 + u*3;
tx1=trajectory[tmp_idx+0];
ty1=trajectory[tmp_idx+1];
tz1=trajectory[tmp_idx+2];
}
if(k*t+u<BufferSize){
int tmp_idx = (k*t+u)*3;
tx2=buf[tmp_idx+0];
ty2=buf[tmp_idx+1];
tz2=buf[tmp_idx+2];
}else{
int tmp_idx = i*n*t*3 + k*t*3 + u*3;
tx2=trajectory[tmp_idx+0];
ty2=trajectory[tmp_idx+1];
tz2=trajectory[tmp_idx+2];
}
td_new += max(((tx2-tx1)*(tx2-tx1)+(ty2-ty1)*(ty2-ty1)+(tz2-tz1)*(tz2-tz1)),1e-20f);
}
td_new/=t;
float d2=min(td,td_new);
if(d2!=td)
temp[blockIdx.x*n+k]=d2;
if(d2>t_max_dists){
t_max_dists=d2;
t_dist_idx=k;
}
}
max_dists[threadIdx.x]=t_max_dists;
dists_idx[threadIdx.x]=t_dist_idx;
for (int u=0;(1<<u)<blockDim.x;u++){ //reduce min
__syncthreads();
if (threadIdx.x<(blockDim.x>>(u+1))){
int i1=(threadIdx.x*2)<<u;
int i2=(threadIdx.x*2+1)<<u;
if (max_dists[i1]<max_dists[i2]){
max_dists[i1]=max_dists[i2];
dists_idx[i1]=dists_idx[i2];
}
}
}
__syncthreads();
last=dists_idx[0];
if (threadIdx.x==0)
sample_idx[i*m+j]=last;
}
}
}
//require 32*n working space
void farthestpointsamplingtrajectoryLauncher(int b,int n,int m,int t,const float * inp,float * temp,int *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
farthestpointsamplingtrajectoryKernel<<<32,512>>>(b,n,m,t,inp,temp,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("farthestpointsamplingtrajectoryKernel:%f \n",totaltime);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void gathertrajctoryKernel(int b,int n,int m,int t,const float * __restrict__ inp,const int * __restrict__ idx, float * __restrict__ out){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
out[tmp_idx1*3+0]=inp[tmp_idx2*3+0];
out[tmp_idx1*3+1]=inp[tmp_idx2*3+1];
out[tmp_idx1*3+2]=inp[tmp_idx2*3+2];
}
}
}
}
void gathertrajctoryLauncher(int b,int n,int m,int t,const float * inp,const int *idx, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajctoryKernel<<<32,512>>>(b,n,m,t,inp,idx,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajctoryKernel:%f b:%d n:%d m:%d t:%d \n",totaltime,b,n,m,t);
}
__global__ void gathertrajectorygradKernel(int b,int n,int m,int t,const float * __restrict__ out_g,const int * __restrict__ idx,float * __restrict__ inp_g){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
atomicAdd(&inp_g[tmp_idx2*3+0],out_g[tmp_idx1*3+0]);
atomicAdd(&inp_g[tmp_idx2*3+1],out_g[tmp_idx1*3+1]);
atomicAdd(&inp_g[tmp_idx2*3+2],out_g[tmp_idx1*3+2]);
}
}
}
}
void gathertrajectorygradLauncher(int b,int n,int m,int t,const float * out_g,const int * idx,float * inp_g){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajectorygradKernel<<<32,128>>>(b,n,m,t,out_g,idx,inp_g);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajectorygradKernel:%f \n",totaltime);
}
__global__ void farthestpointsamplingtrajectoryKernel(int b,int n,int m,int t,const float * __restrict__ trajectory,float * __restrict__ temp,int * __restrict__ sample_idx){
const int BlockSize = 512;
__shared__ float max_dists[BlockSize];
__shared__ int dists_idx[BlockSize];
const int BufferSize=2880;
__shared__ float buf[BufferSize*3];
const int framesize = 64;
__shared__ float framebufx[framesize];
__shared__ float framebufy[framesize];
__shared__ float framebufz[framesize];
for(int i=blockIdx.x;i<b;i+=gridDim.x){ //batch init
int last = 0;
if (threadIdx.x==0)
sample_idx[i*m+0]=last;
for(int j=threadIdx.x;j<n;j+=blockDim.x){
temp[blockIdx.x*n+j]=1e38;
}
for(int j=threadIdx.x;j<min(BufferSize,n*t)*3;j+=blockDim.x){
buf[j]=trajectory[i*n*t*3+j];
}
__syncthreads();
for(int j=0;j<m;j++){ //each sample step
float t_max_dists = -1;
int t_dist_idx = 0;
for(int k=0;k<min(t,framesize);k++){
int tmp_idx = i*n*t*3 + last*t*3 + k*3;
framebufx[k] = trajectory[tmp_idx + 0];
framebufy[k] = trajectory[tmp_idx + 1];
framebufz[k] = trajectory[tmp_idx + 2];
}
for(int k=threadIdx.x;k<n;k+=blockDim.x){ //compute dis
float td=temp[blockIdx.x*n+k];
float td_new = 0;
float tx1=0,ty1=0,tz1=0,tx2=0,ty2=0,tz2=0;
for(int u=0;u<t;u++){
if(u<framesize){
int tmp_idx = u;
tx1=framebufx[tmp_idx];
ty1=framebufy[tmp_idx];
tz1=framebufz[tmp_idx];
}else{
int tmp_idx = i*n*t*3 + last*t*3 + u*3;
tx1=trajectory[tmp_idx+0];
ty1=trajectory[tmp_idx+1];
tz1=trajectory[tmp_idx+2];
}
if(k*t+u<BufferSize){
int tmp_idx = (k*t+u)*3;
tx2=buf[tmp_idx+0];
ty2=buf[tmp_idx+1];
tz2=buf[tmp_idx+2];
}else{
int tmp_idx = i*n*t*3 + k*t*3 + u*3;
tx2=trajectory[tmp_idx+0];
ty2=trajectory[tmp_idx+1];
tz2=trajectory[tmp_idx+2];
}
td_new += max(((tx2-tx1)*(tx2-tx1)+(ty2-ty1)*(ty2-ty1)+(tz2-tz1)*(tz2-tz1)),1e-20f);
}
td_new/=t;
float d2=min(td,td_new);
if(d2!=td)
temp[blockIdx.x*n+k]=d2;
if(d2>t_max_dists){
t_max_dists=d2;
t_dist_idx=k;
}
}
max_dists[threadIdx.x]=t_max_dists;
dists_idx[threadIdx.x]=t_dist_idx;
for (int u=0;(1<<u)<blockDim.x;u++){ //reduce min
__syncthreads();
if (threadIdx.x<(blockDim.x>>(u+1))){
int i1=(threadIdx.x*2)<<u;
int i2=(threadIdx.x*2+1)<<u;
if (max_dists[i1]<max_dists[i2]){
max_dists[i1]=max_dists[i2];
dists_idx[i1]=dists_idx[i2];
}
}
}
__syncthreads();
last=dists_idx[0];
if (threadIdx.x==0)
sample_idx[i*m+j]=last;
}
}
}
//require 32*n working space
void farthestpointsamplingtrajectoryLauncher(int b,int n,int m,int t,const float * inp,float * temp,int *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
farthestpointsamplingtrajectoryKernel<<<32,512>>>(b,n,m,t,inp,temp,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("farthestpointsamplingtrajectoryKernel:%f \n",totaltime);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void gathertrajctoryKernel(int b,int n,int m,int t,const float * __restrict__ inp,const int * __restrict__ idx, float * __restrict__ out){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
out[tmp_idx1*3+0]=inp[tmp_idx2*3+0];
out[tmp_idx1*3+1]=inp[tmp_idx2*3+1];
out[tmp_idx1*3+2]=inp[tmp_idx2*3+2];
}
}
}
}
void gathertrajctoryLauncher(int b,int n,int m,int t,const float * inp,const int *idx, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajctoryKernel<<<32,512>>>(b,n,m,t,inp,idx,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajctoryKernel:%f b:%d n:%d m:%d t:%d \n",totaltime,b,n,m,t);
}
__global__ void gathertrajectorygradKernel(int b,int n,int m,int t,const float * __restrict__ out_g,const int * __restrict__ idx,float * __restrict__ inp_g){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
atomicAdd(&inp_g[tmp_idx2*3+0],out_g[tmp_idx1*3+0]);
atomicAdd(&inp_g[tmp_idx2*3+1],out_g[tmp_idx1*3+1]);
atomicAdd(&inp_g[tmp_idx2*3+2],out_g[tmp_idx1*3+2]);
}
}
}
}
void gathertrajectorygradLauncher(int b,int n,int m,int t,const float * out_g,const int * idx,float * inp_g){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajectorygradKernel<<<32,128>>>(b,n,m,t,out_g,idx,inp_g);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajectorygradKernel:%f \n",totaltime);
}
__global__ void farthestpointsamplingtrajectoryKernel(int b,int n,int m,int t,const float * __restrict__ trajectory,float * __restrict__ temp,int * __restrict__ sample_idx){
const int BlockSize = 512;
__shared__ float max_dists[BlockSize];
__shared__ int dists_idx[BlockSize];
const int BufferSize=2880;
__shared__ float buf[BufferSize*3];
const int framesize = 64;
__shared__ float framebufx[framesize];
__shared__ float framebufy[framesize];
__shared__ float framebufz[framesize];
for(int i=blockIdx.x;i<b;i+=gridDim.x){ //batch init
int last = 0;
if (threadIdx.x==0)
sample_idx[i*m+0]=last;
for(int j=threadIdx.x;j<n;j+=blockDim.x){
temp[blockIdx.x*n+j]=1e38;
}
for(int j=threadIdx.x;j<min(BufferSize,n*t)*3;j+=blockDim.x){
buf[j]=trajectory[i*n*t*3+j];
}
__syncthreads();
for(int j=0;j<m;j++){ //each sample step
float t_max_dists = -1;
int t_dist_idx = 0;
for(int k=0;k<min(t,framesize);k++){
int tmp_idx = i*n*t*3 + last*t*3 + k*3;
framebufx[k] = trajectory[tmp_idx + 0];
framebufy[k] = trajectory[tmp_idx + 1];
framebufz[k] = trajectory[tmp_idx + 2];
}
for(int k=threadIdx.x;k<n;k+=blockDim.x){ //compute dis
float td=temp[blockIdx.x*n+k];
float td_new = 0;
float tx1=0,ty1=0,tz1=0,tx2=0,ty2=0,tz2=0;
for(int u=0;u<t;u++){
if(u<framesize){
int tmp_idx = u;
tx1=framebufx[tmp_idx];
ty1=framebufy[tmp_idx];
tz1=framebufz[tmp_idx];
}else{
int tmp_idx = i*n*t*3 + last*t*3 + u*3;
tx1=trajectory[tmp_idx+0];
ty1=trajectory[tmp_idx+1];
tz1=trajectory[tmp_idx+2];
}
if(k*t+u<BufferSize){
int tmp_idx = (k*t+u)*3;
tx2=buf[tmp_idx+0];
ty2=buf[tmp_idx+1];
tz2=buf[tmp_idx+2];
}else{
int tmp_idx = i*n*t*3 + k*t*3 + u*3;
tx2=trajectory[tmp_idx+0];
ty2=trajectory[tmp_idx+1];
tz2=trajectory[tmp_idx+2];
}
td_new += max(((tx2-tx1)*(tx2-tx1)+(ty2-ty1)*(ty2-ty1)+(tz2-tz1)*(tz2-tz1)),1e-20f);
}
td_new/=t;
float d2=min(td,td_new);
if(d2!=td)
temp[blockIdx.x*n+k]=d2;
if(d2>t_max_dists){
t_max_dists=d2;
t_dist_idx=k;
}
}
max_dists[threadIdx.x]=t_max_dists;
dists_idx[threadIdx.x]=t_dist_idx;
for (int u=0;(1<<u)<blockDim.x;u++){ //reduce min
__syncthreads();
if (threadIdx.x<(blockDim.x>>(u+1))){
int i1=(threadIdx.x*2)<<u;
int i2=(threadIdx.x*2+1)<<u;
if (max_dists[i1]<max_dists[i2]){
max_dists[i1]=max_dists[i2];
dists_idx[i1]=dists_idx[i2];
}
}
}
__syncthreads();
last=dists_idx[0];
if (threadIdx.x==0)
sample_idx[i*m+j]=last;
}
}
}
//require 32*n working space
void farthestpointsamplingtrajectoryLauncher(int b,int n,int m,int t,const float * inp,float * temp,int *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
farthestpointsamplingtrajectoryKernel<<<32,512>>>(b,n,m,t,inp,temp,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("farthestpointsamplingtrajectoryKernel:%f \n",totaltime);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21gathertrajctoryKerneliiiiPKfPKiPf
.globl _Z21gathertrajctoryKerneliiiiPKfPKiPf
.p2align 8
.type _Z21gathertrajctoryKerneliiiiPKfPKiPf,@function
_Z21gathertrajctoryKerneliiiiPKfPKiPf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_9
s_clause 0x4
s_load_b64 s[8:9], s[0:1], 0x4
s_load_b32 s12, s[0:1], 0xc
s_load_b32 s13, s[0:1], 0x28
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mul_i32 s16, s12, 3
s_mul_i32 s18, s13, s12
s_cmp_gt_i32 s12, 0
v_cmp_gt_i32_e64 s2, s9, v0
s_mul_i32 s18, s18, s9
s_cselect_b32 s14, -1, 0
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v5, s16, v1
s_add_u32 s0, s0, 40
s_addc_u32 s1, s1, 0
s_mul_i32 s17, s15, s8
s_mul_i32 s8, s13, s8
s_mul_i32 s18, s18, 3
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s19
v_add_nc_u32_e32 v5, s18, v5
s_add_i32 s15, s13, s15
s_add_i32 s17, s17, s8
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_and_saveexec_b32 s19, s2
s_cbranch_execz .LBB0_2
s_load_b32 s20, s[0:1], 0xc
v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v7, v0
s_mul_i32 s21, s15, s9
s_mov_b32 s23, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s20, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s22, s16, s20
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v7, s20, v7
v_add_nc_u32_e32 v6, s22, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v7
s_or_b32 s23, vcc_lo, s23
s_and_not1_b32 exec_lo, exec_lo, s23
s_cbranch_execz .LBB0_2
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
v_add_nc_u32_e32 v1, s21, v7
v_mov_b32_e32 v3, v6
s_mov_b32 s24, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s17, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v1, s16, v1
.p2align 6
.LBB0_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s24, s24, -1
s_cmp_eq_u32 s24, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_lshlrev_b64 v[11:12], 2, v[3:4]
v_add_nc_u32_e32 v1, 3, v1
v_add_nc_u32_e32 v3, 3, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v11, vcc_lo, s10, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s11, v12, vcc_lo
global_load_b96 v[8:10], v[8:9], off
s_waitcnt vmcnt(0)
global_store_b96 v[11:12], v[8:10], off
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21gathertrajctoryKerneliiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 25
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21gathertrajctoryKerneliiiiPKfPKiPf, .Lfunc_end0-_Z21gathertrajctoryKerneliiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.globl _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.p2align 8
.type _Z26gathertrajectorygradKerneliiiiPKfPKiPf,@function
_Z26gathertrajectorygradKerneliiiiPKfPKiPf:
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_15
s_clause 0x4
s_load_b32 s12, s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x4
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s13, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s12, 0
v_cmp_gt_i32_e64 s2, s9, v0
s_cselect_b32 s14, -1, 0
s_add_u32 s0, s0, 40
s_addc_u32 s1, s1, 0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s15, s13, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB1_15
.LBB1_3:
s_and_saveexec_b32 s16, s2
s_cbranch_execz .LBB1_2
s_load_b32 s19, s[0:1], 0xc
v_mov_b32_e32 v7, v0
s_mul_i32 s17, s15, s9
s_mul_i32 s18, s15, s8
s_mov_b32 s20, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s19, 0xffff
s_branch .LBB1_6
.LBB1_5:
v_add_nc_u32_e32 v7, s19, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v7
s_or_b32 s20, vcc_lo, s20
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execz .LBB1_2
.LBB1_6:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB1_5
v_add_nc_u32_e32 v1, s17, v7
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v8, v1, s12
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, s18, v2
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v9, v2, s12
.LBB1_8:
v_add_nc_u32_e32 v1, s21, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s21, v9
s_mov_b32 s22, 0
v_lshl_add_u32 v1, v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v3, v2, 1, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s10, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v6, vcc_lo
global_load_b32 v10, v[3:4], off
global_load_b32 v6, v[1:2], off
.LBB1_9:
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v6, v10
global_atomic_cmpswap_b32 v5, v[1:2], v[5:6], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s22, vcc_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB1_9
s_or_b32 exec_lo, exec_lo, s22
global_load_b32 v10, v[3:4], off offset:4
global_load_b32 v6, v[1:2], off offset:4
s_mov_b32 s22, 0
.LBB1_11:
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v6, v10
global_atomic_cmpswap_b32 v5, v[1:2], v[5:6], off offset:4 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v5, v6
v_mov_b32_e32 v6, v5
s_or_b32 s22, vcc_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB1_11
s_or_b32 exec_lo, exec_lo, s22
global_load_b32 v5, v[3:4], off offset:8
global_load_b32 v4, v[1:2], off offset:8
s_mov_b32 s22, 0
.LBB1_13:
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v4, v5
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off offset:8 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s22, vcc_lo, s22
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB1_13
s_or_b32 exec_lo, exec_lo, s22
s_add_i32 s21, s21, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s21, s12
s_cbranch_scc0 .LBB1_8
s_branch .LBB1_5
.LBB1_15:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z26gathertrajectorygradKerneliiiiPKfPKiPf, .Lfunc_end1-_Z26gathertrajectorygradKerneliiiiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.globl _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.p2align 8
.type _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi,@function
_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi:
s_load_b32 s14, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB2_42
s_clause 0x4
s_load_b64 s[6:7], s[0:1], 0x4
s_load_b32 s28, s[0:1], 0xc
s_load_b128 s[8:11], s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x20
s_load_b32 s29, s[0:1], 0x28
s_add_u32 s16, s0, 40
s_addc_u32 s17, s1, 0
v_dual_mov_b32 v21, 0x7e967699 :: v_dual_lshlrev_b32 v12, 2, v0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v13, 1, v0
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v14, 0x8f00, v12
v_add_nc_u32_e32 v15, 0x8700, v12
v_or_b32_e32 v16, 1, v13
s_mov_b64 s[4:5], src_shared_base
s_waitcnt lgkmcnt(0)
s_mul_i32 s30, s15, s6
v_mul_lo_u32 v18, v0, s28
v_add_nc_u32_e32 v1, s30, v0
s_mul_i32 s1, s28, s6
s_mul_i32 s31, s28, 3
s_min_i32 s33, s1, 0xb40
s_cmp_gt_i32 s7, 0
v_mul_lo_u32 v20, s31, v1
s_mul_i32 s33, s33, 3
v_mul_lo_u32 v19, v18, 12
v_cmp_gt_i32_e64 s0, s6, v0
v_cvt_f32_i32_e32 v17, s28
s_cselect_b32 s34, -1, 0
s_min_i32 s35, s28, 64
v_cmp_gt_i32_e64 s1, s33, v0
s_cmp_gt_i32 s28, 0
s_mul_i32 s36, s29, s6
s_mul_i32 s37, s31, s30
s_mul_i32 s38, s31, s36
s_cselect_b32 s39, -1, 0
s_mul_i32 s40, s28, 12
s_mov_b32 s41, s30
s_branch .LBB2_3
.LBB2_2:
v_add_nc_u32_e32 v20, s38, v20
s_add_i32 s15, s29, s15
s_add_i32 s37, s37, s38
s_add_i32 s41, s41, s36
s_cmp_ge_i32 s15, s14
s_cbranch_scc1 .LBB2_42
.LBB2_3:
s_mul_i32 s18, s15, s7
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_5
s_ashr_i32 s19, s18, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[20:21], s[18:19], 2
s_add_u32 s20, s12, s20
s_addc_u32 s21, s13, s21
global_store_b32 v2, v2, s[20:21]
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB2_8
s_load_b32 s3, s[16:17], 0xc
v_mov_b32_e32 v3, v0
s_mov_b32 s20, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s3, 0xffff
.LBB2_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, s30, v3
v_add_nc_u32_e32 v3, s19, v3
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s6, v3
s_or_b32 s20, vcc_lo, s20
v_add_co_u32 v4, s3, s10, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s3, s11, v5, s3
global_store_b32 v[4:5], v21, off
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB2_7
.LBB2_8:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB2_11
s_load_b32 s4, s[16:17], 0xc
v_mov_b32_e32 v1, v12
v_mov_b32_e32 v3, v0
s_mov_b32 s20, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s19, s4, 2
.p2align 6
.LBB2_10:
v_add_nc_u32_e32 v4, s37, v3
v_add_nc_u32_e32 v3, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s33, v3
global_load_b32 v4, v[4:5], off
s_or_b32 s20, vcc_lo, s20
s_waitcnt vmcnt(0)
ds_store_b32 v1, v4
v_add_nc_u32_e32 v1, s19, v1
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB2_10
.LBB2_11:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s34
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB2_2
s_load_b32 s3, s[16:17], 0xc
s_mov_b32 s43, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s3, 0xffff
s_mov_b32 s3, 0
s_cmp_gt_u32 s19, 1
s_cselect_b32 s42, -1, 0
s_branch .LBB2_14
.LBB2_13:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s43, s43, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s43, s7
s_cbranch_scc1 .LBB2_2
.LBB2_14:
s_and_not1_b32 vcc_lo, exec_lo, s39
s_cbranch_vccnz .LBB2_17
s_add_i32 s20, s41, s3
s_mov_b32 s4, 0x9700
s_mul_i32 s20, s31, s20
s_mov_b32 s22, s35
.p2align 6
.LBB2_16:
s_ashr_i32 s21, s20, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[24:25], s[20:21], 2
s_add_u32 s24, s8, s24
s_addc_u32 s25, s9, s25
s_add_i32 s22, s22, -1
s_clause 0x1
s_load_b64 s[26:27], s[24:25], 0x0
s_load_b32 s21, s[24:25], 0x8
v_mov_b32_e32 v1, s4
s_add_i32 s20, s20, 3
s_add_i32 s4, s4, 4
s_cmp_eq_u32 s22, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v4, s27 :: v_dual_mov_b32 v3, s26
v_mov_b32_e32 v5, s21
ds_store_2addr_stride64_b32 v1, v3, v4 offset1:1
ds_store_b32 v1, v5 offset:512
s_cbranch_scc0 .LBB2_16
.LBB2_17:
v_dual_mov_b32 v22, -1.0 :: v_dual_mov_b32 v23, 0
s_and_saveexec_b32 s44, s0
s_cbranch_execz .LBB2_34
s_load_b32 s4, s[16:17], 0xc
v_dual_mov_b32 v22, -1.0 :: v_dual_mov_b32 v23, 0
v_dual_mov_b32 v24, v20 :: v_dual_mov_b32 v25, v18
v_dual_mov_b32 v26, v19 :: v_dual_mov_b32 v27, v0
s_add_i32 s3, s41, s3
s_mov_b32 s49, 0
s_mul_i32 s46, s31, s3
s_waitcnt lgkmcnt(0)
s_and_b32 s45, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s47, s40, s45
s_mul_i32 s48, s28, s45
s_mul_i32 s50, s31, s45
s_branch .LBB2_20
.LBB2_19:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_f32_e32 vcc_lo, v5, v22
v_add_nc_u32_e32 v26, s47, v26
v_add_nc_u32_e32 v25, s48, v25
v_dual_cndmask_b32 v23, v23, v27 :: v_dual_add_nc_u32 v24, s50, v24
v_dual_cndmask_b32 v22, v22, v5 :: v_dual_add_nc_u32 v27, s45, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s6, v27
s_or_b32 s49, vcc_lo, s49
s_and_not1_b32 exec_lo, exec_lo, s49
s_cbranch_execz .LBB2_33
.LBB2_20:
v_dual_mov_b32 v28, 0 :: v_dual_add_nc_u32 v1, s30, v27
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s39
global_load_b32 v1, v[3:4], off
s_cbranch_vccnz .LBB2_31
v_mov_b32_e32 v5, v24
v_mov_b32_e32 v29, v26
s_mov_b32 s51, 0
s_mov_b32 s20, s46
s_mov_b32 s52, 0
s_branch .LBB2_23
.LBB2_22:
s_or_b32 exec_lo, exec_lo, s21
flat_load_b32 v6, v[6:7]
flat_load_b32 v7, v[8:9]
flat_load_b32 v8, v[10:11]
s_add_i32 s52, s52, 1
s_add_i32 s20, s20, 3
s_add_i32 s51, s51, 4
s_cmp_eq_u32 s28, s52
v_add_nc_u32_e32 v5, 3, v5
s_waitcnt vmcnt(2) lgkmcnt(2)
v_dual_sub_f32 v6, v6, v32 :: v_dual_add_nc_u32 v29, 12, v29
s_waitcnt vmcnt(0) lgkmcnt(0)
v_dual_sub_f32 v7, v7, v31 :: v_dual_sub_f32 v8, v8, v30
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v6, v6
v_fmac_f32_e32 v6, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v8
v_max_f32_e32 v6, 0x1e3ce508, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v28, v28, v6
s_cbranch_scc1 .LBB2_31
.LBB2_23:
s_cmp_gt_u32 s52, 63
s_mov_b32 s3, -1
s_cbranch_scc0 .LBB2_25
s_ashr_i32 s21, s20, 31
s_mov_b32 s3, 0
s_lshl_b64 s[22:23], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s22, s8, s22
s_addc_u32 s23, s9, s23
s_add_u32 s24, s22, 4
s_addc_u32 s25, s23, 0
s_add_u32 s26, s22, 8
s_addc_u32 s27, s23, 0
.LBB2_25:
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB2_27
s_add_i32 s3, s51, 0x9700
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s3, -1
s_cselect_b32 s22, s3, 0
s_cselect_b32 s23, s5, 0
s_add_i32 s3, s51, 0x9800
s_cmp_lg_u32 s3, -1
s_cselect_b32 s24, s3, 0
s_cselect_b32 s25, s5, 0
s_add_i32 s3, s51, 0x9900
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, -1
s_cselect_b32 s26, s3, 0
s_cselect_b32 s27, s5, 0
.LBB2_27:
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v6, s26 :: v_dual_mov_b32 v7, s27
v_dual_mov_b32 v8, s24 :: v_dual_mov_b32 v9, s25
v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
flat_load_b32 v30, v[6:7]
flat_load_b32 v31, v[8:9]
flat_load_b32 v32, v[10:11]
v_add_nc_u32_e32 v6, s52, v25
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, 0xb3f, v6
s_and_saveexec_b32 s3, vcc_lo
s_xor_b32 s3, exec_lo, s3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, v6, 4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
v_add_co_u32 v10, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
s_and_not1_saveexec_b32 s21, s3
s_cbranch_execz .LBB2_22
v_add_nc_u32_e32 v8, 4, v29
v_add_nc_u32_e32 v9, 8, v29
v_cmp_ne_u32_e32 vcc_lo, -1, v29
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s3, -1, v8
v_cmp_ne_u32_e64 s4, -1, v9
v_cndmask_b32_e64 v7, 0, s5, vcc_lo
v_cndmask_b32_e32 v6, 0, v29, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, 0, v8, s3
v_cndmask_b32_e64 v10, 0, v9, s4
v_cndmask_b32_e64 v9, 0, s5, s3
v_cndmask_b32_e64 v11, 0, s5, s4
s_branch .LBB2_22
.LBB2_31:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v17, v17, v28
v_div_scale_f32 v8, vcc_lo, v28, v17, v28
s_mov_b32 s3, exec_lo
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v7, v8
v_div_fmas_f32 v5, v5, v6, v7
s_waitcnt vmcnt(0)
v_max_f32_e32 v6, v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v5, v17, v28
v_min_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_neq_f32_e32 v5, v1
s_cbranch_execz .LBB2_19
global_store_b32 v[3:4], v5, off
s_branch .LBB2_19
.LBB2_33:
s_or_b32 exec_lo, exec_lo, s49
.LBB2_34:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s44
s_and_not1_b32 vcc_lo, exec_lo, s42
ds_store_b32 v14, v22
ds_store_b32 v15, v23
s_cbranch_vccnz .LBB2_40
s_mov_b32 s3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_37
.p2align 6
.LBB2_36:
s_or_b32 exec_lo, exec_lo, s20
s_lshl_b32 s4, 2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s4, s19
s_cbranch_scc1 .LBB2_40
.LBB2_37:
s_mov_b32 s4, s3
s_add_i32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_lshr_b32 s20, s19, s3
s_barrier
v_cmp_gt_u32_e32 vcc_lo, s20, v0
buffer_gl0_inv
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB2_36
v_lshlrev_b32_e32 v1, s4, v13
v_lshlrev_b32_e32 v3, s4, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v1, 2, v1
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v5, v1 offset:36608
ds_load_b32 v3, v4 offset:36608
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v5, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_36
ds_load_b32 v4, v4 offset:34560
v_add_nc_u32_e32 v5, 0x8f00, v1
ds_store_b32 v5, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v1, v4 offset:34560
s_branch .LBB2_36
.LBB2_40:
s_set_inst_prefetch_distance 0x2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:34560
s_waitcnt lgkmcnt(0)
v_readfirstlane_b32 s3, v1
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_13
s_add_i32 s20, s43, s18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v1, s3
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s12, s20
s_addc_u32 s21, s13, s21
global_store_b32 v2, v1, s[20:21]
s_branch .LBB2_13
.LBB2_42:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.amdhsa_group_segment_fixed_size 39424
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 33
.amdhsa_next_free_sgpr 53
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, .Lfunc_end2-_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
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.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
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- 0
.max_flat_workgroup_size: 1024
.name: _Z21gathertrajctoryKerneliiiiPKfPKiPf
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.language: OpenCL C
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.name: _Z26gathertrajectorygradKerneliiiiPKfPKiPf
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.language: OpenCL C
.language_version:
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- 0
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.name: _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.private_segment_fixed_size: 0
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.symbol: _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi.kd
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<time.h>
__global__ void gathertrajctoryKernel(int b,int n,int m,int t,const float * __restrict__ inp,const int * __restrict__ idx, float * __restrict__ out){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
out[tmp_idx1*3+0]=inp[tmp_idx2*3+0];
out[tmp_idx1*3+1]=inp[tmp_idx2*3+1];
out[tmp_idx1*3+2]=inp[tmp_idx2*3+2];
}
}
}
}
void gathertrajctoryLauncher(int b,int n,int m,int t,const float * inp,const int *idx, float *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajctoryKernel<<<32,512>>>(b,n,m,t,inp,idx,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajctoryKernel:%f b:%d n:%d m:%d t:%d \n",totaltime,b,n,m,t);
}
__global__ void gathertrajectorygradKernel(int b,int n,int m,int t,const float * __restrict__ out_g,const int * __restrict__ idx,float * __restrict__ inp_g){
for(int i = blockIdx.x;i<b;i+=gridDim.x){
for(int j = threadIdx.x;j<m; j+=blockDim.x){
int tmp = idx[i*m+j];
for(int k = 0;k<t;k++){
int tmp_idx1 = ((i*m+j)*t+k);
int tmp_idx2 = ((i*n+tmp)*t+k);
atomicAdd(&inp_g[tmp_idx2*3+0],out_g[tmp_idx1*3+0]);
atomicAdd(&inp_g[tmp_idx2*3+1],out_g[tmp_idx1*3+1]);
atomicAdd(&inp_g[tmp_idx2*3+2],out_g[tmp_idx1*3+2]);
}
}
}
}
void gathertrajectorygradLauncher(int b,int n,int m,int t,const float * out_g,const int * idx,float * inp_g){
//clock_t start,finish;
//double totaltime;
//start=clock();
gathertrajectorygradKernel<<<32,128>>>(b,n,m,t,out_g,idx,inp_g);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("gathertrajectorygradKernel:%f \n",totaltime);
}
__global__ void farthestpointsamplingtrajectoryKernel(int b,int n,int m,int t,const float * __restrict__ trajectory,float * __restrict__ temp,int * __restrict__ sample_idx){
const int BlockSize = 512;
__shared__ float max_dists[BlockSize];
__shared__ int dists_idx[BlockSize];
const int BufferSize=2880;
__shared__ float buf[BufferSize*3];
const int framesize = 64;
__shared__ float framebufx[framesize];
__shared__ float framebufy[framesize];
__shared__ float framebufz[framesize];
for(int i=blockIdx.x;i<b;i+=gridDim.x){ //batch init
int last = 0;
if (threadIdx.x==0)
sample_idx[i*m+0]=last;
for(int j=threadIdx.x;j<n;j+=blockDim.x){
temp[blockIdx.x*n+j]=1e38;
}
for(int j=threadIdx.x;j<min(BufferSize,n*t)*3;j+=blockDim.x){
buf[j]=trajectory[i*n*t*3+j];
}
__syncthreads();
for(int j=0;j<m;j++){ //each sample step
float t_max_dists = -1;
int t_dist_idx = 0;
for(int k=0;k<min(t,framesize);k++){
int tmp_idx = i*n*t*3 + last*t*3 + k*3;
framebufx[k] = trajectory[tmp_idx + 0];
framebufy[k] = trajectory[tmp_idx + 1];
framebufz[k] = trajectory[tmp_idx + 2];
}
for(int k=threadIdx.x;k<n;k+=blockDim.x){ //compute dis
float td=temp[blockIdx.x*n+k];
float td_new = 0;
float tx1=0,ty1=0,tz1=0,tx2=0,ty2=0,tz2=0;
for(int u=0;u<t;u++){
if(u<framesize){
int tmp_idx = u;
tx1=framebufx[tmp_idx];
ty1=framebufy[tmp_idx];
tz1=framebufz[tmp_idx];
}else{
int tmp_idx = i*n*t*3 + last*t*3 + u*3;
tx1=trajectory[tmp_idx+0];
ty1=trajectory[tmp_idx+1];
tz1=trajectory[tmp_idx+2];
}
if(k*t+u<BufferSize){
int tmp_idx = (k*t+u)*3;
tx2=buf[tmp_idx+0];
ty2=buf[tmp_idx+1];
tz2=buf[tmp_idx+2];
}else{
int tmp_idx = i*n*t*3 + k*t*3 + u*3;
tx2=trajectory[tmp_idx+0];
ty2=trajectory[tmp_idx+1];
tz2=trajectory[tmp_idx+2];
}
td_new += max(((tx2-tx1)*(tx2-tx1)+(ty2-ty1)*(ty2-ty1)+(tz2-tz1)*(tz2-tz1)),1e-20f);
}
td_new/=t;
float d2=min(td,td_new);
if(d2!=td)
temp[blockIdx.x*n+k]=d2;
if(d2>t_max_dists){
t_max_dists=d2;
t_dist_idx=k;
}
}
max_dists[threadIdx.x]=t_max_dists;
dists_idx[threadIdx.x]=t_dist_idx;
for (int u=0;(1<<u)<blockDim.x;u++){ //reduce min
__syncthreads();
if (threadIdx.x<(blockDim.x>>(u+1))){
int i1=(threadIdx.x*2)<<u;
int i2=(threadIdx.x*2+1)<<u;
if (max_dists[i1]<max_dists[i2]){
max_dists[i1]=max_dists[i2];
dists_idx[i1]=dists_idx[i2];
}
}
}
__syncthreads();
last=dists_idx[0];
if (threadIdx.x==0)
sample_idx[i*m+j]=last;
}
}
}
//require 32*n working space
void farthestpointsamplingtrajectoryLauncher(int b,int n,int m,int t,const float * inp,float * temp,int *out){
//clock_t start,finish;
//double totaltime;
//start=clock();
farthestpointsamplingtrajectoryKernel<<<32,512>>>(b,n,m,t,inp,temp,out);
//finish=clock();
//totaltime=(double)(finish-start)/CLOCKS_PER_SEC;
//printf("farthestpointsamplingtrajectoryKernel:%f \n",totaltime);
} | .text
.file "sampling_trajectory.hip"
.globl _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf # -- Begin function _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.p2align 4, 0x90
.type _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf,@function
_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf: # @_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf, .Lfunc_end0-_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z23gathertrajctoryLauncheriiiiPKfPKiPf # -- Begin function _Z23gathertrajctoryLauncheriiiiPKfPKiPf
.p2align 4, 0x90
.type _Z23gathertrajctoryLauncheriiiiPKfPKiPf,@function
_Z23gathertrajctoryLauncheriiiiPKfPKiPf: # @_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23gathertrajctoryLauncheriiiiPKfPKiPf, .Lfunc_end1-_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf # -- Begin function _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.p2align 4, 0x90
.type _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf,@function
_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf: # @_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf, .Lfunc_end2-_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z28gathertrajectorygradLauncheriiiiPKfPKiPf # -- Begin function _Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.p2align 4, 0x90
.type _Z28gathertrajectorygradLauncheriiiiPKfPKiPf,@function
_Z28gathertrajectorygradLauncheriiiiPKfPKiPf: # @_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 96(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, .Lfunc_end3-_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi # -- Begin function _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.p2align 4, 0x90
.type _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi,@function
_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi: # @_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end4:
.size _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, .Lfunc_end4-_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi # -- Begin function _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.p2align 4, 0x90
.type _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi,@function
_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi: # @_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, .Lfunc_end5-_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21gathertrajctoryKerneliiiiPKfPKiPf,@object # @_Z21gathertrajctoryKerneliiiiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z21gathertrajctoryKerneliiiiPKfPKiPf
.p2align 3, 0x0
_Z21gathertrajctoryKerneliiiiPKfPKiPf:
.quad _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.size _Z21gathertrajctoryKerneliiiiPKfPKiPf, 8
.type _Z26gathertrajectorygradKerneliiiiPKfPKiPf,@object # @_Z26gathertrajectorygradKerneliiiiPKfPKiPf
.globl _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.p2align 3, 0x0
_Z26gathertrajectorygradKerneliiiiPKfPKiPf:
.quad _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.size _Z26gathertrajectorygradKerneliiiiPKfPKiPf, 8
.type _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi,@object # @_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.globl _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.p2align 3, 0x0
_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi:
.quad _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.size _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21gathertrajctoryKerneliiiiPKfPKiPf"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gathertrajectorygradKerneliiiiPKfPKiPf"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi"
.size .L__unnamed_3, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.addrsig_sym _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.addrsig_sym _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21gathertrajctoryKerneliiiiPKfPKiPf
.addrsig_sym _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.addrsig_sym _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001131c5_00000000-6_sampling_trajectory.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
.type _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf, @function
_Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21gathertrajctoryKerneliiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf, .-_Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
.globl _Z21gathertrajctoryKerneliiiiPKfPKiPf
.type _Z21gathertrajctoryKerneliiiiPKfPKiPf, @function
_Z21gathertrajctoryKerneliiiiPKfPKiPf:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z21gathertrajctoryKerneliiiiPKfPKiPf, .-_Z21gathertrajctoryKerneliiiiPKfPKiPf
.globl _Z23gathertrajctoryLauncheriiiiPKfPKiPf
.type _Z23gathertrajctoryLauncheriiiiPKfPKiPf, @function
_Z23gathertrajctoryLauncheriiiiPKfPKiPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z51__device_stub__Z21gathertrajctoryKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z23gathertrajctoryLauncheriiiiPKfPKiPf, .-_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.globl _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
.type _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf, @function
_Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26gathertrajectorygradKerneliiiiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf, .-_Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
.globl _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.type _Z26gathertrajectorygradKerneliiiiPKfPKiPf, @function
_Z26gathertrajectorygradKerneliiiiPKfPKiPf:
.LFB2087:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z26gathertrajectorygradKerneliiiiPKfPKiPf, .-_Z26gathertrajectorygradKerneliiiiPKfPKiPf
.globl _Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.type _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, @function
_Z28gathertrajectorygradLauncheriiiiPKfPKiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z56__device_stub__Z26gathertrajectorygradKerneliiiiPKfPKiPfiiiiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2058:
.size _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, .-_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.globl _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
.type _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi, @function
_Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi:
.LFB2088:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi, .-_Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
.globl _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.type _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, @function
_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi:
.LFB2089:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, .-_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.globl _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.type _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, @function
_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, %r13d
movq %r8, %r14
movq %r9, %r15
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $32, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movl %r13d, %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z66__device_stub__Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPiiiiiPKfPfPi
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L35
.cfi_endproc
.LFE2059:
.size _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, .-_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi"
.align 8
.LC1:
.string "_Z26gathertrajectorygradKerneliiiiPKfPKiPf"
.align 8
.LC2:
.string "_Z21gathertrajctoryKerneliiiiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26gathertrajectorygradKerneliiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z21gathertrajctoryKerneliiiiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sampling_trajectory.hip"
.globl _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf # -- Begin function _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.p2align 4, 0x90
.type _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf,@function
_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf: # @_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf, .Lfunc_end0-_Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z23gathertrajctoryLauncheriiiiPKfPKiPf # -- Begin function _Z23gathertrajctoryLauncheriiiiPKfPKiPf
.p2align 4, 0x90
.type _Z23gathertrajctoryLauncheriiiiPKfPKiPf,@function
_Z23gathertrajctoryLauncheriiiiPKfPKiPf: # @_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z23gathertrajctoryLauncheriiiiPKfPKiPf, .Lfunc_end1-_Z23gathertrajctoryLauncheriiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf # -- Begin function _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.p2align 4, 0x90
.type _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf,@function
_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf: # @_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf, .Lfunc_end2-_Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z28gathertrajectorygradLauncheriiiiPKfPKiPf # -- Begin function _Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.p2align 4, 0x90
.type _Z28gathertrajectorygradLauncheriiiiPKfPKiPf,@function
_Z28gathertrajectorygradLauncheriiiiPKfPKiPf: # @_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 96(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z28gathertrajectorygradLauncheriiiiPKfPKiPf, .Lfunc_end3-_Z28gathertrajectorygradLauncheriiiiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi # -- Begin function _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.p2align 4, 0x90
.type _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi,@function
_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi: # @_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end4:
.size _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, .Lfunc_end4-_Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.cfi_endproc
# -- End function
.globl _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi # -- Begin function _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.p2align 4, 0x90
.type _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi,@function
_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi: # @_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r15d
movl %esi, %r12d
movl %edi, %r13d
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 480(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 208(%rsp), %rax
movl %r13d, 20(%rsp)
movl %r12d, 16(%rsp)
movl %r15d, 12(%rsp)
movl %ebp, 8(%rsp)
movq %r14, 88(%rsp)
movq %rbx, 80(%rsp)
movq %rax, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi, .Lfunc_end5-_Z39farthestpointsamplingtrajectoryLauncheriiiiPKfPfPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21gathertrajctoryKerneliiiiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26gathertrajectorygradKerneliiiiPKfPKiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21gathertrajctoryKerneliiiiPKfPKiPf,@object # @_Z21gathertrajctoryKerneliiiiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z21gathertrajctoryKerneliiiiPKfPKiPf
.p2align 3, 0x0
_Z21gathertrajctoryKerneliiiiPKfPKiPf:
.quad _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.size _Z21gathertrajctoryKerneliiiiPKfPKiPf, 8
.type _Z26gathertrajectorygradKerneliiiiPKfPKiPf,@object # @_Z26gathertrajectorygradKerneliiiiPKfPKiPf
.globl _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.p2align 3, 0x0
_Z26gathertrajectorygradKerneliiiiPKfPKiPf:
.quad _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.size _Z26gathertrajectorygradKerneliiiiPKfPKiPf, 8
.type _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi,@object # @_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.globl _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.p2align 3, 0x0
_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi:
.quad _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.size _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21gathertrajctoryKerneliiiiPKfPKiPf"
.size .L__unnamed_1, 38
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26gathertrajectorygradKerneliiiiPKfPKiPf"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi"
.size .L__unnamed_3, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__gathertrajctoryKerneliiiiPKfPKiPf
.addrsig_sym _Z41__device_stub__gathertrajectorygradKerneliiiiPKfPKiPf
.addrsig_sym _Z52__device_stub__farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21gathertrajctoryKerneliiiiPKfPKiPf
.addrsig_sym _Z26gathertrajectorygradKerneliiiiPKfPKiPf
.addrsig_sym _Z37farthestpointsamplingtrajectoryKerneliiiiPKfPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void gpu_sort(int *d_a, int *d_b){
__shared__ int tmp[512];
int tid = threadIdx.x;
int ttid = threadIdx.x + blockIdx.x * blockDim.x;
int val = d_a[ttid];
int count =0;
for(int i=tid;i<N;i+=512){
tmp[tid] = d_a[i];
__syncthreads();
for(int j=0;j<512;j++){
if(val>tmp[j]){
count++;
}
}
__syncthreads();
}
d_b[count] = val;
}
int main(){
int sizeByte = sizeof(int)*N;
int *h_a = (int*) malloc(sizeByte);
int *h_b = (int*) malloc(sizeByte);
int *h_a_cpu = (int*) malloc(sizeByte);
int *h_b_cpu = (int*) malloc(sizeByte);
int *d_a, *d_b;
cudaMalloc(&d_a, sizeByte);
cudaMalloc(&d_b, sizeByte);
for(int i=0;i<N;i++){
h_a[i] = rand();
h_a_cpu[i] = h_a[i];
}
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
cudaMemcpy(d_a, h_a, sizeByte, cudaMemcpyHostToDevice);
gpu_sort<<<2, 512>>>(d_a,d_b);
cudaMemcpy(h_b, d_b, sizeByte, cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float time = 0;
cudaEventElapsedTime(&time, start, stop);
printf("Time consumption on GPU: %lf\n", time);
for(int i=0;i<N-1;i++){
if(h_b[i]>h_b[i+1]){
printf("Error at index %d\n GPU[%d] = %d\n", i,i,h_b[i]);
break;
}
}
cudaEvent_t start_cpu,stop_cpu;
cudaEventCreate(&start_cpu);
cudaEventCreate(&stop_cpu);
cudaEventRecord(start_cpu,0);
//sort on cpu
for(int i=N;i>0;i--){
for(int j=0;j<i-1;j++){
if(h_a_cpu[j]>h_a_cpu[j+1]){
int tmp = h_a_cpu[j];
h_a_cpu[j] = h_a_cpu[j + 1];
h_a_cpu[j+1] = tmp;
}
}
}
cudaEventRecord(stop_cpu,0);
cudaEventSynchronize(stop_cpu);
float time_cpu = 0;
cudaEventElapsedTime(&time_cpu, start_cpu, stop_cpu);
printf("Time consumption on CPU: %lf\n", time_cpu);
return 0;
} | .file "tmpxft_000de9f4_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8gpu_sortPiS_PiS_
.type _Z29__device_stub__Z8gpu_sortPiS_PiS_, @function
_Z29__device_stub__Z8gpu_sortPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_sortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8gpu_sortPiS_PiS_, .-_Z29__device_stub__Z8gpu_sortPiS_PiS_
.globl _Z8gpu_sortPiS_
.type _Z8gpu_sortPiS_, @function
_Z8gpu_sortPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_sortPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8gpu_sortPiS_, .-_Z8gpu_sortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time consumption on GPU: %lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Error at index %d\n GPU[%d] = %d\n"
.section .rodata.str1.1
.LC3:
.string "Time consumption on CPU: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %ebp
.L12:
call rand@PLT
movl %eax, (%r12,%rbp)
movl %eax, (%rbx,%rbp)
addq $4, %rbp
cmpq $4096, %rbp
jne .L12
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L13:
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, (%rsp)
movq %rsp, %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L16:
movl 0(%r13,%rax,4), %r8d
cmpl 4(%r13,%rax,4), %r8d
jg .L27
addq $1, %rax
cmpq $1023, %rax
jne .L16
jmp .L15
.L26:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z8gpu_sortPiS_PiS_
jmp .L13
.L27:
movl %eax, %edx
movl %eax, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, %esi
.L17:
subl $1, %esi
je .L28
movl $0, %eax
jmp .L19
.L18:
addq $1, %rax
cmpl %eax, %esi
jle .L17
.L19:
movl (%rbx,%rax,4), %edx
movl 4(%rbx,%rax,4), %ecx
cmpl %ecx, %edx
jle .L18
movl %ecx, (%rbx,%rax,4)
movl %edx, 4(%rbx,%rax,4)
jmp .L18
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8gpu_sortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_sortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void gpu_sort(int *d_a, int *d_b){
__shared__ int tmp[512];
int tid = threadIdx.x;
int ttid = threadIdx.x + blockIdx.x * blockDim.x;
int val = d_a[ttid];
int count =0;
for(int i=tid;i<N;i+=512){
tmp[tid] = d_a[i];
__syncthreads();
for(int j=0;j<512;j++){
if(val>tmp[j]){
count++;
}
}
__syncthreads();
}
d_b[count] = val;
}
int main(){
int sizeByte = sizeof(int)*N;
int *h_a = (int*) malloc(sizeByte);
int *h_b = (int*) malloc(sizeByte);
int *h_a_cpu = (int*) malloc(sizeByte);
int *h_b_cpu = (int*) malloc(sizeByte);
int *d_a, *d_b;
cudaMalloc(&d_a, sizeByte);
cudaMalloc(&d_b, sizeByte);
for(int i=0;i<N;i++){
h_a[i] = rand();
h_a_cpu[i] = h_a[i];
}
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
cudaMemcpy(d_a, h_a, sizeByte, cudaMemcpyHostToDevice);
gpu_sort<<<2, 512>>>(d_a,d_b);
cudaMemcpy(h_b, d_b, sizeByte, cudaMemcpyDeviceToHost);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float time = 0;
cudaEventElapsedTime(&time, start, stop);
printf("Time consumption on GPU: %lf\n", time);
for(int i=0;i<N-1;i++){
if(h_b[i]>h_b[i+1]){
printf("Error at index %d\n GPU[%d] = %d\n", i,i,h_b[i]);
break;
}
}
cudaEvent_t start_cpu,stop_cpu;
cudaEventCreate(&start_cpu);
cudaEventCreate(&stop_cpu);
cudaEventRecord(start_cpu,0);
//sort on cpu
for(int i=N;i>0;i--){
for(int j=0;j<i-1;j++){
if(h_a_cpu[j]>h_a_cpu[j+1]){
int tmp = h_a_cpu[j];
h_a_cpu[j] = h_a_cpu[j + 1];
h_a_cpu[j+1] = tmp;
}
}
}
cudaEventRecord(stop_cpu,0);
cudaEventSynchronize(stop_cpu);
float time_cpu = 0;
cudaEventElapsedTime(&time_cpu, start_cpu, stop_cpu);
printf("Time consumption on CPU: %lf\n", time_cpu);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void gpu_sort(int *d_a, int *d_b){
__shared__ int tmp[512];
int tid = threadIdx.x;
int ttid = threadIdx.x + blockIdx.x * blockDim.x;
int val = d_a[ttid];
int count =0;
for(int i=tid;i<N;i+=512){
tmp[tid] = d_a[i];
__syncthreads();
for(int j=0;j<512;j++){
if(val>tmp[j]){
count++;
}
}
__syncthreads();
}
d_b[count] = val;
}
int main(){
int sizeByte = sizeof(int)*N;
int *h_a = (int*) malloc(sizeByte);
int *h_b = (int*) malloc(sizeByte);
int *h_a_cpu = (int*) malloc(sizeByte);
int *h_b_cpu = (int*) malloc(sizeByte);
int *d_a, *d_b;
hipMalloc(&d_a, sizeByte);
hipMalloc(&d_b, sizeByte);
for(int i=0;i<N;i++){
h_a[i] = rand();
h_a_cpu[i] = h_a[i];
}
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipMemcpy(d_a, h_a, sizeByte, hipMemcpyHostToDevice);
gpu_sort<<<2, 512>>>(d_a,d_b);
hipMemcpy(h_b, d_b, sizeByte, hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float time = 0;
hipEventElapsedTime(&time, start, stop);
printf("Time consumption on GPU: %lf\n", time);
for(int i=0;i<N-1;i++){
if(h_b[i]>h_b[i+1]){
printf("Error at index %d\n GPU[%d] = %d\n", i,i,h_b[i]);
break;
}
}
hipEvent_t start_cpu,stop_cpu;
hipEventCreate(&start_cpu);
hipEventCreate(&stop_cpu);
hipEventRecord(start_cpu,0);
//sort on cpu
for(int i=N;i>0;i--){
for(int j=0;j<i-1;j++){
if(h_a_cpu[j]>h_a_cpu[j+1]){
int tmp = h_a_cpu[j];
h_a_cpu[j] = h_a_cpu[j + 1];
h_a_cpu[j+1] = tmp;
}
}
}
hipEventRecord(stop_cpu,0);
hipEventSynchronize(stop_cpu);
float time_cpu = 0;
hipEventElapsedTime(&time_cpu, start_cpu, stop_cpu);
printf("Time consumption on CPU: %lf\n", time_cpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void gpu_sort(int *d_a, int *d_b){
__shared__ int tmp[512];
int tid = threadIdx.x;
int ttid = threadIdx.x + blockIdx.x * blockDim.x;
int val = d_a[ttid];
int count =0;
for(int i=tid;i<N;i+=512){
tmp[tid] = d_a[i];
__syncthreads();
for(int j=0;j<512;j++){
if(val>tmp[j]){
count++;
}
}
__syncthreads();
}
d_b[count] = val;
}
int main(){
int sizeByte = sizeof(int)*N;
int *h_a = (int*) malloc(sizeByte);
int *h_b = (int*) malloc(sizeByte);
int *h_a_cpu = (int*) malloc(sizeByte);
int *h_b_cpu = (int*) malloc(sizeByte);
int *d_a, *d_b;
hipMalloc(&d_a, sizeByte);
hipMalloc(&d_b, sizeByte);
for(int i=0;i<N;i++){
h_a[i] = rand();
h_a_cpu[i] = h_a[i];
}
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipMemcpy(d_a, h_a, sizeByte, hipMemcpyHostToDevice);
gpu_sort<<<2, 512>>>(d_a,d_b);
hipMemcpy(h_b, d_b, sizeByte, hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float time = 0;
hipEventElapsedTime(&time, start, stop);
printf("Time consumption on GPU: %lf\n", time);
for(int i=0;i<N-1;i++){
if(h_b[i]>h_b[i+1]){
printf("Error at index %d\n GPU[%d] = %d\n", i,i,h_b[i]);
break;
}
}
hipEvent_t start_cpu,stop_cpu;
hipEventCreate(&start_cpu);
hipEventCreate(&stop_cpu);
hipEventRecord(start_cpu,0);
//sort on cpu
for(int i=N;i>0;i--){
for(int j=0;j<i-1;j++){
if(h_a_cpu[j]>h_a_cpu[j+1]){
int tmp = h_a_cpu[j];
h_a_cpu[j] = h_a_cpu[j + 1];
h_a_cpu[j+1] = tmp;
}
}
}
hipEventRecord(stop_cpu,0);
hipEventSynchronize(stop_cpu);
float time_cpu = 0;
hipEventElapsedTime(&time_cpu, start_cpu, stop_cpu);
printf("Time consumption on CPU: %lf\n", time_cpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8gpu_sortPiS_
.globl _Z8gpu_sortPiS_
.p2align 8
.type _Z8gpu_sortPiS_,@function
_Z8gpu_sortPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v4, v[1:2], off
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_mov_b32 s5, 0
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_mov_b32_e32 v5, s5
s_add_i32 s5, s5, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_eq_i32 s5, 0x800
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_cbranch_scc0 .LBB0_2
v_add_nc_u32_e32 v5, 0x200, v0
v_cmp_lt_u32_e32 vcc_lo, 0x1ff, v0
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v0, v5
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8gpu_sortPiS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8gpu_sortPiS_, .Lfunc_end0-_Z8gpu_sortPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8gpu_sortPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8gpu_sortPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 1024
__global__ void gpu_sort(int *d_a, int *d_b){
__shared__ int tmp[512];
int tid = threadIdx.x;
int ttid = threadIdx.x + blockIdx.x * blockDim.x;
int val = d_a[ttid];
int count =0;
for(int i=tid;i<N;i+=512){
tmp[tid] = d_a[i];
__syncthreads();
for(int j=0;j<512;j++){
if(val>tmp[j]){
count++;
}
}
__syncthreads();
}
d_b[count] = val;
}
int main(){
int sizeByte = sizeof(int)*N;
int *h_a = (int*) malloc(sizeByte);
int *h_b = (int*) malloc(sizeByte);
int *h_a_cpu = (int*) malloc(sizeByte);
int *h_b_cpu = (int*) malloc(sizeByte);
int *d_a, *d_b;
hipMalloc(&d_a, sizeByte);
hipMalloc(&d_b, sizeByte);
for(int i=0;i<N;i++){
h_a[i] = rand();
h_a_cpu[i] = h_a[i];
}
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
hipMemcpy(d_a, h_a, sizeByte, hipMemcpyHostToDevice);
gpu_sort<<<2, 512>>>(d_a,d_b);
hipMemcpy(h_b, d_b, sizeByte, hipMemcpyDeviceToHost);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float time = 0;
hipEventElapsedTime(&time, start, stop);
printf("Time consumption on GPU: %lf\n", time);
for(int i=0;i<N-1;i++){
if(h_b[i]>h_b[i+1]){
printf("Error at index %d\n GPU[%d] = %d\n", i,i,h_b[i]);
break;
}
}
hipEvent_t start_cpu,stop_cpu;
hipEventCreate(&start_cpu);
hipEventCreate(&stop_cpu);
hipEventRecord(start_cpu,0);
//sort on cpu
for(int i=N;i>0;i--){
for(int j=0;j<i-1;j++){
if(h_a_cpu[j]>h_a_cpu[j+1]){
int tmp = h_a_cpu[j];
h_a_cpu[j] = h_a_cpu[j + 1];
h_a_cpu[j+1] = tmp;
}
}
}
hipEventRecord(stop_cpu,0);
hipEventSynchronize(stop_cpu);
float time_cpu = 0;
hipEventElapsedTime(&time_cpu, start_cpu, stop_cpu);
printf("Time consumption on CPU: %lf\n", time_cpu);
return 0;
} | .text
.file "sort.hip"
.globl _Z23__device_stub__gpu_sortPiS_ # -- Begin function _Z23__device_stub__gpu_sortPiS_
.p2align 4, 0x90
.type _Z23__device_stub__gpu_sortPiS_,@function
_Z23__device_stub__gpu_sortPiS_: # @_Z23__device_stub__gpu_sortPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_sortPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_sortPiS_, .Lfunc_end0-_Z23__device_stub__gpu_sortPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 80(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r15,%r12,4)
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, (%rsp)
movq %rcx, 112(%rsp)
movq %rsp, %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8gpu_sortPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 80(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
cmpq $1023, %r15 # imm = 0x3FF
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl (%r14,%r15,4), %ecx
leaq 1(%r15), %rdx
cmpl 4(%r14,%r15,4), %ecx
movq %rdx, %r15
jle .LBB1_5
# %bb.7:
decl %edx
movl $.L.str.1, %edi
movl %edx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_8: # %.loopexit57
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1024, %ecx # imm = 0x400
movl $1023, %eax # imm = 0x3FF
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # %.loopexit
# in Loop: Header=BB1_10 Depth=1
leal -1(%rcx), %edx
decq %rax
cmpl $2, %ecx
movl %edx, %ecx
jb .LBB1_15
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
cmpl $2, %ecx
jb .LBB1_9
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %edx, %edx
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=2
incq %rdx
cmpq %rdx, %rax
je .LBB1_9
.LBB1_12: # %.lr.ph
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rdx,4), %esi
movl 4(%rbx,%rdx,4), %edi
cmpl %edi, %esi
jle .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=2
movl %edi, (%rbx,%rdx,4)
movl %esi, 4(%rbx,%rdx,4)
jmp .LBB1_14
.LBB1_15:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_sortPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_sortPiS_,@object # @_Z8gpu_sortPiS_
.section .rodata,"a",@progbits
.globl _Z8gpu_sortPiS_
.p2align 3, 0x0
_Z8gpu_sortPiS_:
.quad _Z23__device_stub__gpu_sortPiS_
.size _Z8gpu_sortPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time consumption on GPU: %lf\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at index %d\n GPU[%d] = %d\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time consumption on CPU: %lf\n"
.size .L.str.2, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_sortPiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_sortPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_sortPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de9f4_00000000-6_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8gpu_sortPiS_PiS_
.type _Z29__device_stub__Z8gpu_sortPiS_PiS_, @function
_Z29__device_stub__Z8gpu_sortPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8gpu_sortPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8gpu_sortPiS_PiS_, .-_Z29__device_stub__Z8gpu_sortPiS_PiS_
.globl _Z8gpu_sortPiS_
.type _Z8gpu_sortPiS_, @function
_Z8gpu_sortPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8gpu_sortPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8gpu_sortPiS_, .-_Z8gpu_sortPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Time consumption on GPU: %lf\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Error at index %d\n GPU[%d] = %d\n"
.section .rodata.str1.1
.LC3:
.string "Time consumption on CPU: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
movq %rax, %r13
movl $4096, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $0, %ebp
.L12:
call rand@PLT
movl %eax, (%r12,%rbp)
movl %eax, (%rbx,%rbp)
addq $4, %rbp
cmpq $4096, %rbp
jne .L12
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L13:
movl $2, %ecx
movl $4096, %edx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, (%rsp)
movq %rsp, %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L16:
movl 0(%r13,%rax,4), %r8d
cmpl 4(%r13,%rax,4), %r8d
jg .L27
addq $1, %rax
cmpq $1023, %rax
jne .L16
jmp .L15
.L26:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z8gpu_sortPiS_PiS_
jmp .L13
.L27:
movl %eax, %edx
movl %eax, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, %esi
.L17:
subl $1, %esi
je .L28
movl $0, %eax
jmp .L19
.L18:
addq $1, %rax
cmpl %eax, %esi
jle .L17
.L19:
movl (%rbx,%rax,4), %edx
movl 4(%rbx,%rax,4), %ecx
cmpl %ecx, %edx
jle .L18
movl %ecx, (%rbx,%rax,4)
movl %edx, 4(%rbx,%rax,4)
jmp .L18
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 4(%rsp)
leaq 4(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z8gpu_sortPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_sortPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sort.hip"
.globl _Z23__device_stub__gpu_sortPiS_ # -- Begin function _Z23__device_stub__gpu_sortPiS_
.p2align 4, 0x90
.type _Z23__device_stub__gpu_sortPiS_,@function
_Z23__device_stub__gpu_sortPiS_: # @_Z23__device_stub__gpu_sortPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8gpu_sortPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_sortPiS_, .Lfunc_end0-_Z23__device_stub__gpu_sortPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r15
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 80(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r15,%r12,4)
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1024, %r12 # imm = 0x400
jne .LBB1_1
# %bb.2:
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 88(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq %rax, (%rsp)
movq %rcx, 112(%rsp)
movq %rsp, %rax
movq %rax, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8gpu_sortPiS_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 80(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 72(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
cmpq $1023, %r15 # imm = 0x3FF
je .LBB1_8
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl (%r14,%r15,4), %ecx
leaq 1(%r15), %rdx
cmpl 4(%r14,%r15,4), %ecx
movq %rdx, %r15
jle .LBB1_5
# %bb.7:
decl %edx
movl $.L.str.1, %edi
movl %edx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
.LBB1_8: # %.loopexit57
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $1024, %ecx # imm = 0x400
movl $1023, %eax # imm = 0x3FF
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # %.loopexit
# in Loop: Header=BB1_10 Depth=1
leal -1(%rcx), %edx
decq %rax
cmpl $2, %ecx
movl %edx, %ecx
jb .LBB1_15
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
cmpl $2, %ecx
jb .LBB1_9
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %edx, %edx
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_14: # in Loop: Header=BB1_12 Depth=2
incq %rdx
cmpq %rdx, %rax
je .LBB1_9
.LBB1_12: # %.lr.ph
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%rdx,4), %esi
movl 4(%rbx,%rdx,4), %edi
cmpl %edi, %esi
jle .LBB1_14
# %bb.13: # in Loop: Header=BB1_12 Depth=2
movl %edi, (%rbx,%rdx,4)
movl %esi, 4(%rbx,%rdx,4)
jmp .LBB1_14
.LBB1_15:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, (%rsp)
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_sortPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_sortPiS_,@object # @_Z8gpu_sortPiS_
.section .rodata,"a",@progbits
.globl _Z8gpu_sortPiS_
.p2align 3, 0x0
_Z8gpu_sortPiS_:
.quad _Z23__device_stub__gpu_sortPiS_
.size _Z8gpu_sortPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time consumption on GPU: %lf\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error at index %d\n GPU[%d] = %d\n"
.size .L.str.1, 33
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Time consumption on CPU: %lf\n"
.size .L.str.2, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_sortPiS_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_sortPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_sortPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} | code for sm_80
Function : _Z18kernelSumHistogramPyS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ BSSY B0, 0xee0 ; /* 0x00000eb000007945 */
/* 0x000fe60003800000 */
/*0030*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*0040*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0050*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0060*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0070*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0080*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0090*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00a0*/ IABS R4, c[0x0][0x170] ; /* 0x00005c0000047a13 */
/* 0x000fc60000000000 */
/*00b0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00c0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*00d0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*00f0*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fe400078e0204 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a05 */
/*0130*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R0, R4, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0004007a12 */
/* 0x000fe200078e3cff */
/*0170*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e260000002100 */
/*0180*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0190*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01a0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*01b0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff039a12 */
/* 0x000fca00078e33ff */
/*01c0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R0, R7, c[0x0][0x178], R4 ; /* 0x00005e0007007a24 */
/* 0x000fca00078e0204 */
/*01e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*01f0*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fce0003f26270 */
/*0220*/ @!P0 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fcc00078e0203 */
/*0230*/ @P1 BRA 0xed0 ; /* 0x00000c9000001947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0250*/ @!P0 BRA 0xe50 ; /* 0x00000bf000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f04070 */
/*0270*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fc80000011402 */
/*0280*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80003f04100 */
/*0290*/ SEL R3, R2, 0x1, P0 ; /* 0x0000000102037807 */
/* 0x000fe40000000000 */
/*02a0*/ SEL R4, R4, RZ, P0 ; /* 0x000000ff04047207 */
/* 0x000fe40000000000 */
/*02b0*/ IADD3 R5, P2, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe40007f5e0ff */
/*02c0*/ LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303027812 */
/* 0x000fe400078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f26070 */
/*02e0*/ IADD3 R3, P0, R2, -R3, RZ ; /* 0x8000000302037210 */
/* 0x000fc40007f1e0ff */
/*02f0*/ IADD3.X R5, R4, -0x1, RZ, P2, !PT ; /* 0xffffffff04057810 */
/* 0x000fc600017fe4ff */
/*0300*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0e04 */
/*0310*/ ISETP.GE.U32.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fce0003f26110 */
/*0320*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0330*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P1 BRA 0xb90 ; /* 0x0000082000009947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f06270 */
/*0380*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0390*/ LEA R28, P2, R0, c[0x0][0x160], 0x3 ; /* 0x00005800001c7a11 */
/* 0x000fe200078418ff */
/*03a0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fc400078e00ff */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*03c0*/ LEA.HI.X R29, R0, c[0x0][0x164], R5, 0x3, P2 ; /* 0x00005900001d7a11 */
/* 0x000fe200010f1c05 */
/*03d0*/ IMAD.MOV.U32 R22, RZ, RZ, R3 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0003 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0004 */
/*03f0*/ @P0 BRA 0xa50 ; /* 0x0000065000000947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R8, P0, RZ, -R22, RZ ; /* 0x80000016ff087210 */
/* 0x000fc80007f1e0ff */
/*0410*/ ISETP.GT.U32.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f44070 */
/*0420*/ IMAD.X R8, RZ, RZ, ~R7, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e07 */
/*0430*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0440*/ ISETP.GT.AND.EX P2, PT, R8, RZ, PT, P2 ; /* 0x000000ff0800720c */
/* 0x000fda0003f44320 */
/*0450*/ @!P2 BRA 0x7f0 ; /* 0x000003900000a947 */
/* 0x000fea0003800000 */
/*0460*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0470*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff177624 */
/* 0x000fe200078e00ff */
/*0480*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0490*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IMAD.WIDE R10, R23, 0x8, R28 ; /* 0x00000008170a7825 */
/* 0x000fca00078e021c */
/*04b0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x0000a2000c1e1b00 */
/*04c0*/ IMAD.WIDE R16, R23, 0x8, R10 ; /* 0x0000000817107825 */
/* 0x000fcc00078e020a */
/*04d0*/ IMAD.WIDE R14, R23.reuse, 0x8, R16 ; /* 0x00000008170e7825 */
/* 0x040fe400078e0210 */
/*04e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0010e2000c1e1b00 */
/*0500*/ IMAD.WIDE R18, R23, 0x8, R14 ; /* 0x0000000817127825 */
/* 0x000fcc00078e020e */
/*0510*/ IMAD.WIDE R8, R23.reuse, 0x8, R18 ; /* 0x0000000817087825 */
/* 0x040fe400078e0212 */
/*0520*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1b00 */
/*0530*/ IMAD.WIDE R14, R23, 0x8, R8 ; /* 0x00000008170e7825 */
/* 0x001fe400078e0208 */
/*0540*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f22000c1e1b00 */
/*0550*/ IADD3 R25, P2, P3, R12, R20, R25 ; /* 0x000000140c197210 */
/* 0x004fc80007b5e019 */
/*0560*/ IADD3.X R21, R13, R21, R27, P2, P3 ; /* 0x000000150d157210 */
/* 0x000fe200017e641b */
/*0570*/ IMAD.WIDE R12, R23.reuse, 0x8, R14 ; /* 0x00000008170c7825 */
/* 0x040fe400078e020e */
/*0580*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ IMAD.WIDE R26, R23, 0x8, R12 ; /* 0x00000008171a7825 */
/* 0x000fe400078e020c */
/*05a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ IADD3 R25, P2, P3, R10, R16, R25 ; /* 0x000000100a197210 */
/* 0x008fc60007b5e019 */
/*05c0*/ IMAD.WIDE R28, R23, 0x8, R26 ; /* 0x00000008171c7825 */
/* 0x000fe200078e021a */
/*05d0*/ IADD3.X R24, R11, R17, R21, P2, P3 ; /* 0x000000110b187210 */
/* 0x000fe400017e6415 */
/*05e0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0600*/ IMAD.WIDE R20, R23, 0x8, R28 ; /* 0x0000000817147825 */
/* 0x000fe200078e021c */
/*0610*/ IADD3 R25, P2, P3, R8, R18, R25 ; /* 0x0000001208197210 */
/* 0x010fc80007b5e019 */
/*0620*/ IADD3.X R24, R9, R19, R24, P2, P3 ; /* 0x0000001309187210 */
/* 0x000fe200017e6418 */
/*0630*/ IMAD.WIDE R18, R23.reuse, 0x8, R20 ; /* 0x0000000817127825 */
/* 0x040fe400078e0214 */
/*0640*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1b00 */
/*0650*/ IMAD.WIDE R8, R23, 0x8, R18 ; /* 0x0000000817087825 */
/* 0x000fe400078e0212 */
/*0660*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1b00 */
/*0670*/ IADD3 R25, P2, P3, R12, R14, R25 ; /* 0x0000000e0c197210 */
/* 0x004fc80007b5e019 */
/*0680*/ IADD3.X R24, R13, R15, R24, P2, P3 ; /* 0x0000000f0d187210 */
/* 0x000fe200017e6418 */
/*0690*/ IMAD.WIDE R12, R23.reuse, 0x8, R8 ; /* 0x00000008170c7825 */
/* 0x040fe400078e0208 */
/*06a0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*06b0*/ IMAD.WIDE R14, R23, 0x8, R12 ; /* 0x00000008170e7825 */
/* 0x000fe200078e020c */
/*06c0*/ IADD3 R25, P2, P3, R10, R16, R25 ; /* 0x000000100a197210 */
/* 0x008fe20007b5e019 */
/*06d0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea6000c1e1b00 */
/*06e0*/ IADD3.X R27, R11, R17, R24, P2, P3 ; /* 0x000000110b1b7210 */
/* 0x000fe200017e6418 */
/*06f0*/ IMAD.WIDE R10, R23, 0x8, R14 ; /* 0x00000008170a7825 */
/* 0x000fc400078e020e */
/*0700*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0710*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee2000c1e1b00 */
/*0720*/ IADD3 R22, P4, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x000fe40007f9e0ff */
/*0730*/ IADD3 R25, P2, P3, R18, R20, R25 ; /* 0x0000001412197210 */
/* 0x010fc60007b5e019 */
/*0740*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0750*/ IADD3.X R27, R19, R21, R27, P2, P3 ; /* 0x00000015131b7210 */
/* 0x000fe400017e641b */
/*0760*/ ISETP.GE.U32.AND P2, PT, R22, -0xc, PT ; /* 0xfffffff41600780c */
/* 0x000fc80003f46070 */
/*0770*/ ISETP.GE.AND.EX P2, PT, R7, -0x1, PT, P2 ; /* 0xffffffff0700780c */
/* 0x000fe20003f46320 */
/*0780*/ IMAD.WIDE R28, R23, 0x8, R10 ; /* 0x00000008171c7825 */
/* 0x000fe200078e020a */
/*0790*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*07a0*/ IADD3 R25, P4, P3, R12, R8, R25 ; /* 0x000000080c197210 */
/* 0x004fc80007b9e019 */
/*07b0*/ IADD3.X R9, R13, R9, R27, P4, P3 ; /* 0x000000090d097210 */
/* 0x000fe400027e641b */
/*07c0*/ IADD3 R25, P5, P6, R16, R14, R25 ; /* 0x0000000e10197210 */
/* 0x008fc80007ebe019 */
/*07d0*/ IADD3.X R27, R17, R15, R9, P5, P6 ; /* 0x0000000f111b7210 */
/* 0x000fe20002fec409 */
/*07e0*/ @!P2 BRA 0x470 ; /* 0xfffffc800000a947 */
/* 0x000fea000383ffff */
/*07f0*/ IADD3 R8, P3, RZ, -R22, RZ ; /* 0x80000016ff087210 */
/* 0x000fc80007f7e0ff */
/*0800*/ ISETP.GT.U32.AND P2, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f44070 */
/*0810*/ IMAD.X R8, RZ, RZ, ~R7, P3 ; /* 0x000000ffff087224 */
/* 0x000fca00018e0e07 */
/*0820*/ ISETP.GT.AND.EX P2, PT, R8, RZ, PT, P2 ; /* 0x000000ff0800720c */
/* 0x000fda0003f44320 */
/*0830*/ @!P2 BRA 0xa20 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff177624 */
/* 0x000fe200078e00ff */
/*0850*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0860*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea2000c1e1b00 */
/*0870*/ IMAD.WIDE R14, R23, 0x8, R28 ; /* 0x00000008170e7825 */
/* 0x000fca00078e021c */
/*0880*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x0000a2000c1e1b00 */
/*0890*/ IMAD.WIDE R8, R23, 0x8, R14 ; /* 0x0000000817087825 */
/* 0x000fcc00078e020e */
/*08a0*/ IMAD.WIDE R10, R23.reuse, 0x8, R8 ; /* 0x00000008170a7825 */
/* 0x040fe400078e0208 */
/*08b0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1b00 */
/*08c0*/ IMAD.WIDE R12, R23.reuse, 0x8, R10 ; /* 0x00000008170c7825 */
/* 0x040fe400078e020a */
/*08d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ IMAD.WIDE R14, R23, 0x8, R12 ; /* 0x00000008170e7825 */
/* 0x001fc400078e020c */
/*08f0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*0900*/ IMAD.WIDE R18, R23, 0x8, R14 ; /* 0x0000000817127825 */
/* 0x000fe400078e020e */
/*0910*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*0920*/ IADD3 R25, P0, P2, R16, R20, R25 ; /* 0x0000001410197210 */
/* 0x004fc80007a1e019 */
/*0930*/ IADD3.X R27, R17, R21, R27, P0, P2 ; /* 0x00000015111b7210 */
/* 0x000fe200007e441b */
/*0940*/ IMAD.WIDE R16, R23, 0x8, R18 ; /* 0x0000000817107825 */
/* 0x000fe400078e0212 */
/*0950*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1b00 */
/*0960*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1b00 */
/*0970*/ IADD3 R25, P0, P2, R10, R8, R25 ; /* 0x000000080a197210 */
/* 0x008fc80007a1e019 */
/*0980*/ IADD3.X R27, R11, R9, R27, P0, P2 ; /* 0x000000090b1b7210 */
/* 0x000fe400007e441b */
/*0990*/ IADD3 R22, P4, R22, 0x8, RZ ; /* 0x0000000816167810 */
/* 0x000fe40007f9e0ff */
/*09a0*/ IADD3 R25, P0, P2, R14, R12, R25 ; /* 0x0000000c0e197210 */
/* 0x010fc80007a1e019 */
/*09b0*/ IADD3.X R27, R15, R13, R27, P0, P2 ; /* 0x0000000d0f1b7210 */
/* 0x000fe200007e441b */
/*09c0*/ IMAD.WIDE R28, R23, 0x8, R16 ; /* 0x00000008171c7825 */
/* 0x000fe200078e0210 */
/*09d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09e0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0a00*/ IADD3 R25, P2, P3, R20, R18, R25 ; /* 0x0000001214197210 */
/* 0x004fc80007b5e019 */
/*0a10*/ IADD3.X R27, R21, R19, R27, P2, P3 ; /* 0x00000013151b7210 */
/* 0x000fe400017e641b */
/*0a20*/ ISETP.NE.U32.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003f45070 */
/*0a30*/ ISETP.NE.OR.EX P0, PT, R7, RZ, P0, P2 ; /* 0x000000ff0700720c */
/* 0x000fda0000705720 */
/*0a40*/ @!P0 BRA 0xb90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0a50*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff117624 */
/* 0x000fe200078e00ff */
/*0a60*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0a70*/ IMAD.WIDE R14, R17.reuse, 0x8, R28 ; /* 0x00000008110e7825 */
/* 0x040fe400078e021c */
/*0a80*/ LDG.E.64 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1b00 */
/*0a90*/ IMAD.WIDE R8, R17.reuse, 0x8, R14 ; /* 0x0000000811087825 */
/* 0x040fe400078e020e */
/*0aa0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ IMAD.WIDE R12, R17, 0x8, R8 ; /* 0x00000008110c7825 */
/* 0x000fc400078e0208 */
/*0ac0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1b00 */
/*0ad0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0ae0*/ IADD3 R22, P0, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fca0007f1e0ff */
/*0af0*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0b00*/ ISETP.NE.U32.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003f05070 */
/*0b10*/ ISETP.NE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe40003f05300 */
/*0b20*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0b30*/ IADD3 R25, P2, P3, R14, R28, R25 ; /* 0x0000001c0e197210 */
/* 0x004fc80007b5e019 */
/*0b40*/ IADD3.X R27, R15, R29, R27, P2, P3 ; /* 0x0000001d0f1b7210 */
/* 0x000fe200017e641b */
/*0b50*/ IMAD.WIDE R28, R17, 0x8, R12 ; /* 0x00000008111c7825 */
/* 0x000fe200078e020c */
/*0b60*/ IADD3 R25, P4, P5, R10, R8, R25 ; /* 0x000000080a197210 */
/* 0x008fc80007d9e019 */
/*0b70*/ IADD3.X R27, R11, R9, R27, P4, P5 ; /* 0x000000090b1b7210 */
/* 0x000fe200027ea41b */
/*0b80*/ @P0 BRA 0xa50 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f05070 */
/*0ba0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0bb0*/ @!P0 BRA 0xdb0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ IMAD R9, R6, c[0x0][0x174], RZ ; /* 0x00005d0006097a24 */
/* 0x000fe200078e02ff */
/*0bd0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0be0*/ IADD3 R7, P0, R9, R0, RZ ; /* 0x0000000009077210 */
/* 0x000fc80007f1e0ff */
/*0bf0*/ LEA.HI.X.SX32 R8, R9, R5, 0x1, P0 ; /* 0x0000000509087211 */
/* 0x000fe400000f0eff */
/*0c00*/ LEA R6, P0, R7, c[0x0][0x160], 0x3 ; /* 0x0000580007067a11 */
/* 0x000fc800078018ff */
/*0c10*/ LEA.HI.X R7, R7, c[0x0][0x164], R8, 0x3, P0 ; /* 0x0000590007077a11 */
/* 0x000fcc00000f1c08 */
/*0c20*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0c30*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05070 */
/*0c40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*0c50*/ IADD3 R25, P2, R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x004fca0007f5e0ff */
/*0c60*/ IMAD.X R27, R7, 0x1, R27, P2 ; /* 0x00000001071b7824 */
/* 0x000fcc00010e061b */
/*0c70*/ @!P0 BRA 0xdb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05070 */
/*0c90*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0ca0*/ IADD3 R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a10 */
/* 0x000fe40007ffe0ff */
/*0cb0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*0cc0*/ IADD3 R7, P2, R9, R0, RZ ; /* 0x0000000009077210 */
/* 0x000fc80007f5e0ff */
/*0cd0*/ LEA.HI.X.SX32 R10, R9, R5, 0x1, P2 ; /* 0x00000005090a7211 */
/* 0x000fe400010f0eff */
/*0ce0*/ LEA R6, P2, R7, c[0x0][0x160], 0x3 ; /* 0x0000580007067a11 */
/* 0x000fc800078418ff */
/*0cf0*/ LEA.HI.X R7, R7, c[0x0][0x164], R10, 0x3, P2 ; /* 0x0000590007077a11 */
/* 0x000fe400010f1c0a */
/*0d00*/ @P0 IADD3 R8, R9, c[0x0][0x174], RZ ; /* 0x00005d0009080a10 */
/* 0x000fc80007ffe0ff */
/*0d10*/ @P0 IADD3 R9, P3, R8.reuse, R0, RZ ; /* 0x0000000008090210 */
/* 0x040fe20007f7e0ff */
/*0d20*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1b00 */
/*0d30*/ @P0 LEA.HI.X.SX32 R10, R8, R5, 0x1, P3 ; /* 0x00000005080a0211 */
/* 0x000fe400018f0eff */
/*0d40*/ @P0 LEA R8, P2, R9, c[0x0][0x160], 0x3 ; /* 0x0000580009080a11 */
/* 0x000fc800078418ff */
/*0d50*/ @P0 LEA.HI.X R9, R9, c[0x0][0x164], R10, 0x3, P2 ; /* 0x0000590009090a11 */
/* 0x000fcc00010f1c0a */
/*0d60*/ @P0 LDG.E.64 R8, [R8.64] ; /* 0x0000000408080981 */
/* 0x000ee2000c1e1b00 */
/*0d70*/ IADD3 R25, P2, R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x004fca0007f5e0ff */
/*0d80*/ IMAD.X R27, R7, 0x1, R27, P2 ; /* 0x00000001071b7824 */
/* 0x000fe200010e061b */
/*0d90*/ @P0 IADD3 R25, P3, R8, R25, RZ ; /* 0x0000001908190210 */
/* 0x008fca0007f7e0ff */
/*0da0*/ @P0 IMAD.X R27, R9, 0x1, R27, P3 ; /* 0x00000001091b0824 */
/* 0x000fe400018e061b */
/*0db0*/ LEA R6, P0, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x040fe200078018ff */
/*0dc0*/ IMAD.MOV.U32 R26, RZ, RZ, R25 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0019 */
/*0dd0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0de0*/ LEA.HI.X R7, R0, c[0x0][0x16c], R5, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fe200000f1c05 */
/*0df0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc800078e00ff */
/*0e00*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*0e10*/ STG.E.64 [R6.64], R26 ; /* 0x0000001a06007986 */
/* 0x0001e8000c101b04 */
/*0e20*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0e30*/ @!P0 BRA 0x320 ; /* 0xfffff4e000008947 */
/* 0x001fea000383ffff */
/*0e40*/ BRA 0xed0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e50*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0e60*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*0e70*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fe200078e0200 */
/*0e80*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0e90*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*0ea0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101b04 */
/*0eb0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0ec0*/ @!P0 BRA 0xe70 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0ed0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ef0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} | .file "tmpxft_001a870c_00000000-6_kernelSumHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
.type _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii, @function
_Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernelSumHistogramPyS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii, .-_Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
.globl _Z18kernelSumHistogramPyS_iii
.type _Z18kernelSumHistogramPyS_iii, @function
_Z18kernelSumHistogramPyS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernelSumHistogramPyS_iii, .-_Z18kernelSumHistogramPyS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernelSumHistogramPyS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernelSumHistogramPyS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl atom_list_GPU
.bss
.align 8
.type atom_list_GPU, @object
.size atom_list_GPU, 8
atom_list_GPU:
.zero 8
.globl temp_histogram_GPU
.align 8
.type temp_histogram_GPU, @object
.size temp_histogram_GPU, 8
temp_histogram_GPU:
.zero 8
.globl histogram_GPU
.align 8
.type histogram_GPU, @object
.size histogram_GPU, 8
histogram_GPU:
.zero 8
.globl atom_list
.align 8
.type atom_list, @object
.size atom_list, 8
atom_list:
.zero 8
.globl PDH_res
.align 4
.type PDH_res, @object
.size PDH_res, 4
PDH_res:
.zero 4
.globl num_buckets
.align 4
.type num_buckets, @object
.size num_buckets, 4
num_buckets:
.zero 4
.globl block_size
.align 4
.type block_size, @object
.size block_size, 4
block_size:
.zero 4
.globl PDH_acnt
.align 8
.type PDH_acnt, @object
.size PDH_acnt, 8
PDH_acnt:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernelSumHistogramPyS_iii
.globl _Z18kernelSumHistogramPyS_iii
.p2align 8
.type _Z18kernelSumHistogramPyS_iii,@function
_Z18kernelSumHistogramPyS_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x2c
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_ashr_i32 s12, s3, 31
s_and_b32 s13, s4, 0xffff
s_add_i32 s5, s3, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s11, s5, s12
v_cvt_f32_u32_e32 v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
v_cvt_u32_f32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s14, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s15, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_sub_i32 s16, 0, s11
s_load_b32 s8, s[8:9], 0x0
s_mul_i32 s16, s16, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s14, s16
s_add_i32 s14, s14, s1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s16, s15, s0
s_mul_i32 s13, s8, s13
s_xor_b32 s1, s16, s0
s_xor_b32 s0, s0, s12
s_mul_hi_u32 s14, s1, s14
s_mul_i32 s16, s14, s11
s_add_i32 s12, s14, 1
s_sub_i32 s1, s1, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s16, s1, s11
s_cmp_ge_u32 s1, s11
s_cselect_b32 s12, s12, s14
s_cselect_b32 s1, s16, s1
s_add_i32 s14, s12, 1
s_cmp_ge_u32 s1, s11
s_mov_b32 s11, 0
s_cselect_b32 s1, s14, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s1, s0
s_sub_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s1, s0, s3
s_sub_i32 s1, s15, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cselect_b32 s1, -1, 0
s_cmp_lg_u32 s1, 0
s_addc_u32 s1, s0, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cselect_b32 s12, -1, 0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[8:9], s[2:3], 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_3:
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s2, v1
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_or_b32 s11, vcc_lo, s11
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, s1
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_6:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v7, v3
v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernelSumHistogramPyS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernelSumHistogramPyS_iii, .Lfunc_end0-_Z18kernelSumHistogramPyS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernelSumHistogramPyS_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z18kernelSumHistogramPyS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* ==================================================================
Programmers:
Kevin Wagner
Elijah Malaby
John Casey
Omptimizing SDH histograms for input larger then global memory
==================================================================
*/
#define BOX_SIZE 23000 /* size of the data box on one dimension */
/* descriptors for single atom in the tree */
typedef struct atomdesc {
float x_pos;
float y_pos;
float z_pos;
} atom;
unsigned long long * histogram; /* list of all buckets in the histogram */
unsigned long long PDH_acnt; /* total number of data points */
int block_size; /* Number of threads per block */
int num_buckets; /* total number of buckets in the histogram */
float PDH_res; /* value of w */
atom * atom_list; /* list of all data points */
unsigned long long * histogram_GPU;
unsigned long long * temp_histogram_GPU;
atom * atom_list_GPU;
__global__ void kernelSumHistogram( unsigned long long int *InputHists, unsigned long long int *hist, int num_atoms, int num_buckets, int block_size) {
unsigned long long int tid = threadIdx.x + blockIdx.x * blockDim.x;
int h_pos = tid;
unsigned long long int NumberOfSumLoop = 0;
NumberOfSumLoop = (num_atoms)/block_size + ((num_atoms%block_size) ? 1:0);
while(h_pos < num_buckets) {
unsigned long long int tmpAns = 0;
for(int i=0;i<NumberOfSumLoop;i++){
tmpAns = tmpAns + *(InputHists+(i*num_buckets)+h_pos);
}
hist[h_pos] = tmpAns;
h_pos += blockDim.x * gridDim.x;
}
__syncthreads();
} | .text
.file "kernelSumHistogram.hip"
.globl _Z33__device_stub__kernelSumHistogramPyS_iii # -- Begin function _Z33__device_stub__kernelSumHistogramPyS_iii
.p2align 4, 0x90
.type _Z33__device_stub__kernelSumHistogramPyS_iii,@function
_Z33__device_stub__kernelSumHistogramPyS_iii: # @_Z33__device_stub__kernelSumHistogramPyS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernelSumHistogramPyS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernelSumHistogramPyS_iii, .Lfunc_end0-_Z33__device_stub__kernelSumHistogramPyS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernelSumHistogramPyS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type histogram,@object # @histogram
.bss
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type PDH_acnt,@object # @PDH_acnt
.globl PDH_acnt
.p2align 3, 0x0
PDH_acnt:
.quad 0 # 0x0
.size PDH_acnt, 8
.type block_size,@object # @block_size
.globl block_size
.p2align 2, 0x0
block_size:
.long 0 # 0x0
.size block_size, 4
.type num_buckets,@object # @num_buckets
.globl num_buckets
.p2align 2, 0x0
num_buckets:
.long 0 # 0x0
.size num_buckets, 4
.type PDH_res,@object # @PDH_res
.globl PDH_res
.p2align 2, 0x0
PDH_res:
.long 0x00000000 # float 0
.size PDH_res, 4
.type atom_list,@object # @atom_list
.globl atom_list
.p2align 3, 0x0
atom_list:
.quad 0
.size atom_list, 8
.type histogram_GPU,@object # @histogram_GPU
.globl histogram_GPU
.p2align 3, 0x0
histogram_GPU:
.quad 0
.size histogram_GPU, 8
.type temp_histogram_GPU,@object # @temp_histogram_GPU
.globl temp_histogram_GPU
.p2align 3, 0x0
temp_histogram_GPU:
.quad 0
.size temp_histogram_GPU, 8
.type atom_list_GPU,@object # @atom_list_GPU
.globl atom_list_GPU
.p2align 3, 0x0
atom_list_GPU:
.quad 0
.size atom_list_GPU, 8
.type _Z18kernelSumHistogramPyS_iii,@object # @_Z18kernelSumHistogramPyS_iii
.section .rodata,"a",@progbits
.globl _Z18kernelSumHistogramPyS_iii
.p2align 3, 0x0
_Z18kernelSumHistogramPyS_iii:
.quad _Z33__device_stub__kernelSumHistogramPyS_iii
.size _Z18kernelSumHistogramPyS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernelSumHistogramPyS_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernelSumHistogramPyS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernelSumHistogramPyS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernelSumHistogramPyS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x178] ; /* 0x00005e0000057a13 */
/* 0x000fe20000000000 */
/*0020*/ BSSY B0, 0xee0 ; /* 0x00000eb000007945 */
/* 0x000fe60003800000 */
/*0030*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e300000209400 */
/*0040*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0050*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0060*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0070*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0080*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0090*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*00a0*/ IABS R4, c[0x0][0x170] ; /* 0x00005c0000047a13 */
/* 0x000fc60000000000 */
/*00b0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe400078e0002 */
/*00c0*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*00d0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00e0*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*00f0*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fe400078e0204 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GT.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x0000000100009824 */
/* 0x000fe200078e0a05 */
/*0130*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R0, R4, c[0x0][0x178], RZ, 0x3c, !PT ; /* 0x00005e0004007a12 */
/* 0x000fe200078e3cff */
/*0170*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e260000002100 */
/*0180*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f46270 */
/*0190*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fcc0007ffe0ff */
/*01a0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fe200078e0a03 */
/*01b0*/ @!P1 LOP3.LUT R3, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff039a12 */
/* 0x000fca00078e33ff */
/*01c0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*01d0*/ IMAD R0, R7, c[0x0][0x178], R4 ; /* 0x00005e0007007a24 */
/* 0x000fca00078e0204 */
/*01e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*01f0*/ IMAD R0, R2, c[0x0][0x0], R5 ; /* 0x0000000002007a24 */
/* 0x001fe200078e0205 */
/*0200*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fce0003f26270 */
/*0220*/ @!P0 IMAD.MOV R2, RZ, RZ, R3 ; /* 0x000000ffff028224 */
/* 0x000fcc00078e0203 */
/*0230*/ @P1 BRA 0xed0 ; /* 0x00000c9000001947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0250*/ @!P0 BRA 0xe50 ; /* 0x00000bf000008947 */
/* 0x000fea0003800000 */
/*0260*/ ISETP.GT.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f04070 */
/*0270*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fc80000011402 */
/*0280*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80003f04100 */
/*0290*/ SEL R3, R2, 0x1, P0 ; /* 0x0000000102037807 */
/* 0x000fe40000000000 */
/*02a0*/ SEL R4, R4, RZ, P0 ; /* 0x000000ff04047207 */
/* 0x000fe40000000000 */
/*02b0*/ IADD3 R5, P2, R3.reuse, -0x1, RZ ; /* 0xffffffff03057810 */
/* 0x040fe40007f5e0ff */
/*02c0*/ LOP3.LUT R2, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303027812 */
/* 0x000fe400078ec0ff */
/*02d0*/ ISETP.GE.U32.AND P1, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f26070 */
/*02e0*/ IADD3 R3, P0, R2, -R3, RZ ; /* 0x8000000302037210 */
/* 0x000fc40007f1e0ff */
/*02f0*/ IADD3.X R5, R4, -0x1, RZ, P2, !PT ; /* 0xffffffff04057810 */
/* 0x000fc600017fe4ff */
/*0300*/ IMAD.X R4, RZ, RZ, ~R4, P0 ; /* 0x000000ffff047224 */
/* 0x000fe200000e0e04 */
/*0310*/ ISETP.GE.U32.AND.EX P1, PT, R5, RZ, PT, P1 ; /* 0x000000ff0500720c */
/* 0x000fce0003f26110 */
/*0320*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*0330*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe400078e00ff */
/*0340*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0360*/ @!P1 BRA 0xb90 ; /* 0x0000082000009947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f06270 */
/*0380*/ IMAD.MOV.U32 R25, RZ, RZ, RZ ; /* 0x000000ffff197224 */
/* 0x000fe200078e00ff */
/*0390*/ LEA R28, P2, R0, c[0x0][0x160], 0x3 ; /* 0x00005800001c7a11 */
/* 0x000fe200078418ff */
/*03a0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fc400078e00ff */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*03c0*/ LEA.HI.X R29, R0, c[0x0][0x164], R5, 0x3, P2 ; /* 0x00005900001d7a11 */
/* 0x000fe200010f1c05 */
/*03d0*/ IMAD.MOV.U32 R22, RZ, RZ, R3 ; /* 0x000000ffff167224 */
/* 0x000fe400078e0003 */
/*03e0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0004 */
/*03f0*/ @P0 BRA 0xa50 ; /* 0x0000065000000947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R8, P0, RZ, -R22, RZ ; /* 0x80000016ff087210 */
/* 0x000fc80007f1e0ff */
/*0410*/ ISETP.GT.U32.AND P2, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f44070 */
/*0420*/ IMAD.X R8, RZ, RZ, ~R7, P0 ; /* 0x000000ffff087224 */
/* 0x000fe200000e0e07 */
/*0430*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0f070 */
/*0440*/ ISETP.GT.AND.EX P2, PT, R8, RZ, PT, P2 ; /* 0x000000ff0800720c */
/* 0x000fda0003f44320 */
/*0450*/ @!P2 BRA 0x7f0 ; /* 0x000003900000a947 */
/* 0x000fea0003800000 */
/*0460*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0470*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff177624 */
/* 0x000fe200078e00ff */
/*0480*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0490*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea2000c1e1b00 */
/*04a0*/ IMAD.WIDE R10, R23, 0x8, R28 ; /* 0x00000008170a7825 */
/* 0x000fca00078e021c */
/*04b0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x0000a2000c1e1b00 */
/*04c0*/ IMAD.WIDE R16, R23, 0x8, R10 ; /* 0x0000000817107825 */
/* 0x000fcc00078e020a */
/*04d0*/ IMAD.WIDE R14, R23.reuse, 0x8, R16 ; /* 0x00000008170e7825 */
/* 0x040fe400078e0210 */
/*04e0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee8000c1e1b00 */
/*04f0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x0010e2000c1e1b00 */
/*0500*/ IMAD.WIDE R18, R23, 0x8, R14 ; /* 0x0000000817127825 */
/* 0x000fcc00078e020e */
/*0510*/ IMAD.WIDE R8, R23.reuse, 0x8, R18 ; /* 0x0000000817087825 */
/* 0x040fe400078e0212 */
/*0520*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f28000c1e1b00 */
/*0530*/ IMAD.WIDE R14, R23, 0x8, R8 ; /* 0x00000008170e7825 */
/* 0x001fe400078e0208 */
/*0540*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f22000c1e1b00 */
/*0550*/ IADD3 R25, P2, P3, R12, R20, R25 ; /* 0x000000140c197210 */
/* 0x004fc80007b5e019 */
/*0560*/ IADD3.X R21, R13, R21, R27, P2, P3 ; /* 0x000000150d157210 */
/* 0x000fe200017e641b */
/*0570*/ IMAD.WIDE R12, R23.reuse, 0x8, R14 ; /* 0x00000008170c7825 */
/* 0x040fe400078e020e */
/*0580*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0590*/ IMAD.WIDE R26, R23, 0x8, R12 ; /* 0x00000008171a7825 */
/* 0x000fe400078e020c */
/*05a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*05b0*/ IADD3 R25, P2, P3, R10, R16, R25 ; /* 0x000000100a197210 */
/* 0x008fc60007b5e019 */
/*05c0*/ IMAD.WIDE R28, R23, 0x8, R26 ; /* 0x00000008171c7825 */
/* 0x000fe200078e021a */
/*05d0*/ IADD3.X R24, R11, R17, R21, P2, P3 ; /* 0x000000110b187210 */
/* 0x000fe400017e6415 */
/*05e0*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000ee8000c1e1b00 */
/*05f0*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0600*/ IMAD.WIDE R20, R23, 0x8, R28 ; /* 0x0000000817147825 */
/* 0x000fe200078e021c */
/*0610*/ IADD3 R25, P2, P3, R8, R18, R25 ; /* 0x0000001208197210 */
/* 0x010fc80007b5e019 */
/*0620*/ IADD3.X R24, R9, R19, R24, P2, P3 ; /* 0x0000001309187210 */
/* 0x000fe200017e6418 */
/*0630*/ IMAD.WIDE R18, R23.reuse, 0x8, R20 ; /* 0x0000000817127825 */
/* 0x040fe400078e0214 */
/*0640*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1b00 */
/*0650*/ IMAD.WIDE R8, R23, 0x8, R18 ; /* 0x0000000817087825 */
/* 0x000fe400078e0212 */
/*0660*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1b00 */
/*0670*/ IADD3 R25, P2, P3, R12, R14, R25 ; /* 0x0000000e0c197210 */
/* 0x004fc80007b5e019 */
/*0680*/ IADD3.X R24, R13, R15, R24, P2, P3 ; /* 0x0000000f0d187210 */
/* 0x000fe200017e6418 */
/*0690*/ IMAD.WIDE R12, R23.reuse, 0x8, R8 ; /* 0x00000008170c7825 */
/* 0x040fe400078e0208 */
/*06a0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*06b0*/ IMAD.WIDE R14, R23, 0x8, R12 ; /* 0x00000008170e7825 */
/* 0x000fe200078e020c */
/*06c0*/ IADD3 R25, P2, P3, R10, R16, R25 ; /* 0x000000100a197210 */
/* 0x008fe20007b5e019 */
/*06d0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea6000c1e1b00 */
/*06e0*/ IADD3.X R27, R11, R17, R24, P2, P3 ; /* 0x000000110b1b7210 */
/* 0x000fe200017e6418 */
/*06f0*/ IMAD.WIDE R10, R23, 0x8, R14 ; /* 0x00000008170a7825 */
/* 0x000fc400078e020e */
/*0700*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee8000c1e1b00 */
/*0710*/ LDG.E.64 R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee2000c1e1b00 */
/*0720*/ IADD3 R22, P4, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x000fe40007f9e0ff */
/*0730*/ IADD3 R25, P2, P3, R18, R20, R25 ; /* 0x0000001412197210 */
/* 0x010fc60007b5e019 */
/*0740*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0750*/ IADD3.X R27, R19, R21, R27, P2, P3 ; /* 0x00000015131b7210 */
/* 0x000fe400017e641b */
/*0760*/ ISETP.GE.U32.AND P2, PT, R22, -0xc, PT ; /* 0xfffffff41600780c */
/* 0x000fc80003f46070 */
/*0770*/ ISETP.GE.AND.EX P2, PT, R7, -0x1, PT, P2 ; /* 0xffffffff0700780c */
/* 0x000fe20003f46320 */
/*0780*/ IMAD.WIDE R28, R23, 0x8, R10 ; /* 0x00000008171c7825 */
/* 0x000fe200078e020a */
/*0790*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*07a0*/ IADD3 R25, P4, P3, R12, R8, R25 ; /* 0x000000080c197210 */
/* 0x004fc80007b9e019 */
/*07b0*/ IADD3.X R9, R13, R9, R27, P4, P3 ; /* 0x000000090d097210 */
/* 0x000fe400027e641b */
/*07c0*/ IADD3 R25, P5, P6, R16, R14, R25 ; /* 0x0000000e10197210 */
/* 0x008fc80007ebe019 */
/*07d0*/ IADD3.X R27, R17, R15, R9, P5, P6 ; /* 0x0000000f111b7210 */
/* 0x000fe20002fec409 */
/*07e0*/ @!P2 BRA 0x470 ; /* 0xfffffc800000a947 */
/* 0x000fea000383ffff */
/*07f0*/ IADD3 R8, P3, RZ, -R22, RZ ; /* 0x80000016ff087210 */
/* 0x000fc80007f7e0ff */
/*0800*/ ISETP.GT.U32.AND P2, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fe20003f44070 */
/*0810*/ IMAD.X R8, RZ, RZ, ~R7, P3 ; /* 0x000000ffff087224 */
/* 0x000fca00018e0e07 */
/*0820*/ ISETP.GT.AND.EX P2, PT, R8, RZ, PT, P2 ; /* 0x000000ff0800720c */
/* 0x000fda0003f44320 */
/*0830*/ @!P2 BRA 0xa20 ; /* 0x000001e00000a947 */
/* 0x000fea0003800000 */
/*0840*/ IMAD.MOV.U32 R23, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff177624 */
/* 0x000fe200078e00ff */
/*0850*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0860*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000ea2000c1e1b00 */
/*0870*/ IMAD.WIDE R14, R23, 0x8, R28 ; /* 0x00000008170e7825 */
/* 0x000fca00078e021c */
/*0880*/ LDG.E.64 R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x0000a2000c1e1b00 */
/*0890*/ IMAD.WIDE R8, R23, 0x8, R14 ; /* 0x0000000817087825 */
/* 0x000fcc00078e020e */
/*08a0*/ IMAD.WIDE R10, R23.reuse, 0x8, R8 ; /* 0x00000008170a7825 */
/* 0x040fe400078e0208 */
/*08b0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1b00 */
/*08c0*/ IMAD.WIDE R12, R23.reuse, 0x8, R10 ; /* 0x00000008170c7825 */
/* 0x040fe400078e020a */
/*08d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ IMAD.WIDE R14, R23, 0x8, R12 ; /* 0x00000008170e7825 */
/* 0x001fc400078e020c */
/*08f0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f28000c1e1b00 */
/*0900*/ IMAD.WIDE R18, R23, 0x8, R14 ; /* 0x0000000817127825 */
/* 0x000fe400078e020e */
/*0910*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1b00 */
/*0920*/ IADD3 R25, P0, P2, R16, R20, R25 ; /* 0x0000001410197210 */
/* 0x004fc80007a1e019 */
/*0930*/ IADD3.X R27, R17, R21, R27, P0, P2 ; /* 0x00000015111b7210 */
/* 0x000fe200007e441b */
/*0940*/ IMAD.WIDE R16, R23, 0x8, R18 ; /* 0x0000000817107825 */
/* 0x000fe400078e0212 */
/*0950*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1b00 */
/*0960*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1b00 */
/*0970*/ IADD3 R25, P0, P2, R10, R8, R25 ; /* 0x000000080a197210 */
/* 0x008fc80007a1e019 */
/*0980*/ IADD3.X R27, R11, R9, R27, P0, P2 ; /* 0x000000090b1b7210 */
/* 0x000fe400007e441b */
/*0990*/ IADD3 R22, P4, R22, 0x8, RZ ; /* 0x0000000816167810 */
/* 0x000fe40007f9e0ff */
/*09a0*/ IADD3 R25, P0, P2, R14, R12, R25 ; /* 0x0000000c0e197210 */
/* 0x010fc80007a1e019 */
/*09b0*/ IADD3.X R27, R15, R13, R27, P0, P2 ; /* 0x0000000d0f1b7210 */
/* 0x000fe200007e441b */
/*09c0*/ IMAD.WIDE R28, R23, 0x8, R16 ; /* 0x00000008171c7825 */
/* 0x000fe200078e0210 */
/*09d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09e0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.X R7, RZ, RZ, R7, P4 ; /* 0x000000ffff077224 */
/* 0x000fe200020e0607 */
/*0a00*/ IADD3 R25, P2, P3, R20, R18, R25 ; /* 0x0000001214197210 */
/* 0x004fc80007b5e019 */
/*0a10*/ IADD3.X R27, R21, R19, R27, P2, P3 ; /* 0x00000013151b7210 */
/* 0x000fe400017e641b */
/*0a20*/ ISETP.NE.U32.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003f45070 */
/*0a30*/ ISETP.NE.OR.EX P0, PT, R7, RZ, P0, P2 ; /* 0x000000ff0700720c */
/* 0x000fda0000705720 */
/*0a40*/ @!P0 BRA 0xb90 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0a50*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff117624 */
/* 0x000fe200078e00ff */
/*0a60*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0a70*/ IMAD.WIDE R14, R17.reuse, 0x8, R28 ; /* 0x00000008110e7825 */
/* 0x040fe400078e021c */
/*0a80*/ LDG.E.64 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea8000c1e1b00 */
/*0a90*/ IMAD.WIDE R8, R17.reuse, 0x8, R14 ; /* 0x0000000811087825 */
/* 0x040fe400078e020e */
/*0aa0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ IMAD.WIDE R12, R17, 0x8, R8 ; /* 0x00000008110c7825 */
/* 0x000fc400078e0208 */
/*0ac0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee8000c1e1b00 */
/*0ad0*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ee2000c1e1b00 */
/*0ae0*/ IADD3 R22, P0, R22, 0x4, RZ ; /* 0x0000000416167810 */
/* 0x000fca0007f1e0ff */
/*0af0*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0b00*/ ISETP.NE.U32.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fc80003f05070 */
/*0b10*/ ISETP.NE.AND.EX P0, PT, R7, RZ, PT, P0 ; /* 0x000000ff0700720c */
/* 0x000fe40003f05300 */
/*0b20*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007ffe0ff */
/*0b30*/ IADD3 R25, P2, P3, R14, R28, R25 ; /* 0x0000001c0e197210 */
/* 0x004fc80007b5e019 */
/*0b40*/ IADD3.X R27, R15, R29, R27, P2, P3 ; /* 0x0000001d0f1b7210 */
/* 0x000fe200017e641b */
/*0b50*/ IMAD.WIDE R28, R17, 0x8, R12 ; /* 0x00000008111c7825 */
/* 0x000fe200078e020c */
/*0b60*/ IADD3 R25, P4, P5, R10, R8, R25 ; /* 0x000000080a197210 */
/* 0x008fc80007d9e019 */
/*0b70*/ IADD3.X R27, R11, R9, R27, P4, P5 ; /* 0x000000090b1b7210 */
/* 0x000fe200027ea41b */
/*0b80*/ @P0 BRA 0xa50 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*0b90*/ ISETP.NE.U32.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc80003f05070 */
/*0ba0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05300 */
/*0bb0*/ @!P0 BRA 0xdb0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ IMAD R9, R6, c[0x0][0x174], RZ ; /* 0x00005d0006097a24 */
/* 0x000fe200078e02ff */
/*0bd0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0be0*/ IADD3 R7, P0, R9, R0, RZ ; /* 0x0000000009077210 */
/* 0x000fc80007f1e0ff */
/*0bf0*/ LEA.HI.X.SX32 R8, R9, R5, 0x1, P0 ; /* 0x0000000509087211 */
/* 0x000fe400000f0eff */
/*0c00*/ LEA R6, P0, R7, c[0x0][0x160], 0x3 ; /* 0x0000580007067a11 */
/* 0x000fc800078018ff */
/*0c10*/ LEA.HI.X R7, R7, c[0x0][0x164], R8, 0x3, P0 ; /* 0x0000590007077a11 */
/* 0x000fcc00000f1c08 */
/*0c20*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1b00 */
/*0c30*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05070 */
/*0c40*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*0c50*/ IADD3 R25, P2, R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x004fca0007f5e0ff */
/*0c60*/ IMAD.X R27, R7, 0x1, R27, P2 ; /* 0x00000001071b7824 */
/* 0x000fcc00010e061b */
/*0c70*/ @!P0 BRA 0xdb0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0c80*/ ISETP.NE.U32.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fe20003f05070 */
/*0c90*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0ca0*/ IADD3 R9, R9, c[0x0][0x174], RZ ; /* 0x00005d0009097a10 */
/* 0x000fe40007ffe0ff */
/*0cb0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*0cc0*/ IADD3 R7, P2, R9, R0, RZ ; /* 0x0000000009077210 */
/* 0x000fc80007f5e0ff */
/*0cd0*/ LEA.HI.X.SX32 R10, R9, R5, 0x1, P2 ; /* 0x00000005090a7211 */
/* 0x000fe400010f0eff */
/*0ce0*/ LEA R6, P2, R7, c[0x0][0x160], 0x3 ; /* 0x0000580007067a11 */
/* 0x000fc800078418ff */
/*0cf0*/ LEA.HI.X R7, R7, c[0x0][0x164], R10, 0x3, P2 ; /* 0x0000590007077a11 */
/* 0x000fe400010f1c0a */
/*0d00*/ @P0 IADD3 R8, R9, c[0x0][0x174], RZ ; /* 0x00005d0009080a10 */
/* 0x000fc80007ffe0ff */
/*0d10*/ @P0 IADD3 R9, P3, R8.reuse, R0, RZ ; /* 0x0000000008090210 */
/* 0x040fe20007f7e0ff */
/*0d20*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea6000c1e1b00 */
/*0d30*/ @P0 LEA.HI.X.SX32 R10, R8, R5, 0x1, P3 ; /* 0x00000005080a0211 */
/* 0x000fe400018f0eff */
/*0d40*/ @P0 LEA R8, P2, R9, c[0x0][0x160], 0x3 ; /* 0x0000580009080a11 */
/* 0x000fc800078418ff */
/*0d50*/ @P0 LEA.HI.X R9, R9, c[0x0][0x164], R10, 0x3, P2 ; /* 0x0000590009090a11 */
/* 0x000fcc00010f1c0a */
/*0d60*/ @P0 LDG.E.64 R8, [R8.64] ; /* 0x0000000408080981 */
/* 0x000ee2000c1e1b00 */
/*0d70*/ IADD3 R25, P2, R6, R25, RZ ; /* 0x0000001906197210 */
/* 0x004fca0007f5e0ff */
/*0d80*/ IMAD.X R27, R7, 0x1, R27, P2 ; /* 0x00000001071b7824 */
/* 0x000fe200010e061b */
/*0d90*/ @P0 IADD3 R25, P3, R8, R25, RZ ; /* 0x0000001908190210 */
/* 0x008fca0007f7e0ff */
/*0da0*/ @P0 IMAD.X R27, R9, 0x1, R27, P3 ; /* 0x00000001091b0824 */
/* 0x000fe400018e061b */
/*0db0*/ LEA R6, P0, R0.reuse, c[0x0][0x168], 0x3 ; /* 0x00005a0000067a11 */
/* 0x040fe200078018ff */
/*0dc0*/ IMAD.MOV.U32 R26, RZ, RZ, R25 ; /* 0x000000ffff1a7224 */
/* 0x000fe200078e0019 */
/*0dd0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0de0*/ LEA.HI.X R7, R0, c[0x0][0x16c], R5, 0x3, P0 ; /* 0x00005b0000077a11 */
/* 0x000fe200000f1c05 */
/*0df0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc800078e00ff */
/*0e00*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*0e10*/ STG.E.64 [R6.64], R26 ; /* 0x0000001a06007986 */
/* 0x0001e8000c101b04 */
/*0e20*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0e30*/ @!P0 BRA 0x320 ; /* 0xfffff4e000008947 */
/* 0x001fea000383ffff */
/*0e40*/ BRA 0xed0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e50*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0e60*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe400078e00ff */
/*0e70*/ IMAD.WIDE R2, R5, R0, c[0x0][0x168] ; /* 0x00005a0005027625 */
/* 0x000fe200078e0200 */
/*0e80*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0e90*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*0ea0*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101b04 */
/*0eb0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fda0003f06270 */
/*0ec0*/ @!P0 BRA 0xe70 ; /* 0xffffffa000008947 */
/* 0x001fea000383ffff */
/*0ed0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ef0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f00*/ BRA 0xf00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernelSumHistogramPyS_iii
.globl _Z18kernelSumHistogramPyS_iii
.p2align 8
.type _Z18kernelSumHistogramPyS_iii,@function
_Z18kernelSumHistogramPyS_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x14
s_load_b32 s4, s[0:1], 0x2c
s_add_u32 s8, s0, 32
s_addc_u32 s9, s1, 0
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_ashr_i32 s12, s3, 31
s_and_b32 s13, s4, 0xffff
s_add_i32 s5, s3, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s11, s5, s12
v_cvt_f32_u32_e32 v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v1
v_mad_u64_u32 v[1:2], null, s15, s13, v[0:1]
v_cvt_u32_f32_e32 v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s14, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s15, s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_sub_i32 s16, 0, s11
s_load_b32 s8, s[8:9], 0x0
s_mul_i32 s16, s16, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s1, s14, s16
s_add_i32 s14, s14, s1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s0, s15, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s16, s15, s0
s_mul_i32 s13, s8, s13
s_xor_b32 s1, s16, s0
s_xor_b32 s0, s0, s12
s_mul_hi_u32 s14, s1, s14
s_mul_i32 s16, s14, s11
s_add_i32 s12, s14, 1
s_sub_i32 s1, s1, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s16, s1, s11
s_cmp_ge_u32 s1, s11
s_cselect_b32 s12, s12, s14
s_cselect_b32 s1, s16, s1
s_add_i32 s14, s12, 1
s_cmp_ge_u32 s1, s11
s_mov_b32 s11, 0
s_cselect_b32 s1, s14, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s1, s0
s_sub_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s1, s0, s3
s_sub_i32 s1, s15, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cselect_b32 s1, -1, 0
s_cmp_lg_u32 s1, 0
s_addc_u32 s1, s0, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cselect_b32 s12, -1, 0
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[8:9], s[2:3], 3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_2:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_3:
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s13, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s2, v1
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
s_or_b32 s11, vcc_lo, s11
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_7
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_and_not1_b32 vcc_lo, exec_lo, s12
s_cbranch_vccnz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, s1
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
.LBB0_6:
global_load_b64 v[7:8], v[5:6], off
v_add_co_u32 v5, vcc_lo, v5, s8
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s0, 0
s_waitcnt vmcnt(0)
v_add_co_u32 v3, vcc_lo, v7, v3
v_add_co_ci_u32_e32 v4, vcc_lo, v8, v4, vcc_lo
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s10
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernelSumHistogramPyS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernelSumHistogramPyS_iii, .Lfunc_end0-_Z18kernelSumHistogramPyS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernelSumHistogramPyS_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z18kernelSumHistogramPyS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a870c_00000000-6_kernelSumHistogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
.type _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii, @function
_Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernelSumHistogramPyS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii, .-_Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
.globl _Z18kernelSumHistogramPyS_iii
.type _Z18kernelSumHistogramPyS_iii, @function
_Z18kernelSumHistogramPyS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18kernelSumHistogramPyS_iiiPyS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernelSumHistogramPyS_iii, .-_Z18kernelSumHistogramPyS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernelSumHistogramPyS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernelSumHistogramPyS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl atom_list_GPU
.bss
.align 8
.type atom_list_GPU, @object
.size atom_list_GPU, 8
atom_list_GPU:
.zero 8
.globl temp_histogram_GPU
.align 8
.type temp_histogram_GPU, @object
.size temp_histogram_GPU, 8
temp_histogram_GPU:
.zero 8
.globl histogram_GPU
.align 8
.type histogram_GPU, @object
.size histogram_GPU, 8
histogram_GPU:
.zero 8
.globl atom_list
.align 8
.type atom_list, @object
.size atom_list, 8
atom_list:
.zero 8
.globl PDH_res
.align 4
.type PDH_res, @object
.size PDH_res, 4
PDH_res:
.zero 4
.globl num_buckets
.align 4
.type num_buckets, @object
.size num_buckets, 4
num_buckets:
.zero 4
.globl block_size
.align 4
.type block_size, @object
.size block_size, 4
block_size:
.zero 4
.globl PDH_acnt
.align 8
.type PDH_acnt, @object
.size PDH_acnt, 8
PDH_acnt:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelSumHistogram.hip"
.globl _Z33__device_stub__kernelSumHistogramPyS_iii # -- Begin function _Z33__device_stub__kernelSumHistogramPyS_iii
.p2align 4, 0x90
.type _Z33__device_stub__kernelSumHistogramPyS_iii,@function
_Z33__device_stub__kernelSumHistogramPyS_iii: # @_Z33__device_stub__kernelSumHistogramPyS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernelSumHistogramPyS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__kernelSumHistogramPyS_iii, .Lfunc_end0-_Z33__device_stub__kernelSumHistogramPyS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernelSumHistogramPyS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type histogram,@object # @histogram
.bss
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type PDH_acnt,@object # @PDH_acnt
.globl PDH_acnt
.p2align 3, 0x0
PDH_acnt:
.quad 0 # 0x0
.size PDH_acnt, 8
.type block_size,@object # @block_size
.globl block_size
.p2align 2, 0x0
block_size:
.long 0 # 0x0
.size block_size, 4
.type num_buckets,@object # @num_buckets
.globl num_buckets
.p2align 2, 0x0
num_buckets:
.long 0 # 0x0
.size num_buckets, 4
.type PDH_res,@object # @PDH_res
.globl PDH_res
.p2align 2, 0x0
PDH_res:
.long 0x00000000 # float 0
.size PDH_res, 4
.type atom_list,@object # @atom_list
.globl atom_list
.p2align 3, 0x0
atom_list:
.quad 0
.size atom_list, 8
.type histogram_GPU,@object # @histogram_GPU
.globl histogram_GPU
.p2align 3, 0x0
histogram_GPU:
.quad 0
.size histogram_GPU, 8
.type temp_histogram_GPU,@object # @temp_histogram_GPU
.globl temp_histogram_GPU
.p2align 3, 0x0
temp_histogram_GPU:
.quad 0
.size temp_histogram_GPU, 8
.type atom_list_GPU,@object # @atom_list_GPU
.globl atom_list_GPU
.p2align 3, 0x0
atom_list_GPU:
.quad 0
.size atom_list_GPU, 8
.type _Z18kernelSumHistogramPyS_iii,@object # @_Z18kernelSumHistogramPyS_iii
.section .rodata,"a",@progbits
.globl _Z18kernelSumHistogramPyS_iii
.p2align 3, 0x0
_Z18kernelSumHistogramPyS_iii:
.quad _Z33__device_stub__kernelSumHistogramPyS_iii
.size _Z18kernelSumHistogramPyS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernelSumHistogramPyS_iii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernelSumHistogramPyS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernelSumHistogramPyS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .file "tmpxft_0000c49b_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | #include <hip/hip_runtime.h>
#include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// Helper function for using CUDA to add vectors in parallel.
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
} | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000c49b_00000000-6_addKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addKernel.hip"
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // file esempio tantiprint
#include "stdio.h"
__global__ void miokernel(void){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
printf("Sono il thread %d!\n", tid);
}
int main() {
//miokernel<<<2,32>>>();
miokernel<<<1,8>>>();
printf("Hello World!\n");
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z9miokernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // file esempio tantiprint
#include "stdio.h"
__global__ void miokernel(void){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
printf("Sono il thread %d!\n", tid);
}
int main() {
//miokernel<<<2,32>>>();
miokernel<<<1,8>>>();
printf("Hello World!\n");
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000bec23_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9miokernelvv
.type _Z27__device_stub__Z9miokernelvv, @function
_Z27__device_stub__Z9miokernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9miokernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9miokernelvv, .-_Z27__device_stub__Z9miokernelvv
.globl _Z9miokernelv
.type _Z9miokernelv, @function
_Z9miokernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9miokernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9miokernelv, .-_Z9miokernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9miokernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9miokernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9miokernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // file esempio tantiprint
#include "stdio.h"
__global__ void miokernel(void){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
printf("Sono il thread %d!\n", tid);
}
int main() {
//miokernel<<<2,32>>>();
miokernel<<<1,8>>>();
printf("Hello World!\n");
cudaDeviceSynchronize();
return 0;
} | // file esempio tantiprint
#include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void miokernel(void){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
printf("Sono il thread %d!\n", tid);
}
int main() {
//miokernel<<<2,32>>>();
miokernel<<<1,8>>>();
printf("Hello World!\n");
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // file esempio tantiprint
#include <hip/hip_runtime.h>
#include "stdio.h"
__global__ void miokernel(void){
int tid = blockIdx.x * blockDim.x + threadIdx.x;
printf("Sono il thread %d!\n", tid);
}
int main() {
//miokernel<<<2,32>>>();
miokernel<<<1,8>>>();
printf("Hello World!\n");
hipDeviceSynchronize();
return 0;
} | .text
.file "main.hip"
.globl _Z24__device_stub__miokernelv # -- Begin function _Z24__device_stub__miokernelv
.p2align 4, 0x90
.type _Z24__device_stub__miokernelv,@function
_Z24__device_stub__miokernelv: # @_Z24__device_stub__miokernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9miokernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__miokernelv, .Lfunc_end0-_Z24__device_stub__miokernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9miokernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9miokernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9miokernelv,@object # @_Z9miokernelv
.section .rodata,"a",@progbits
.globl _Z9miokernelv
.p2align 3, 0x0
_Z9miokernelv:
.quad _Z24__device_stub__miokernelv
.size _Z9miokernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9miokernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__miokernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9miokernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bec23_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9miokernelvv
.type _Z27__device_stub__Z9miokernelvv, @function
_Z27__device_stub__Z9miokernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z9miokernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9miokernelvv, .-_Z27__device_stub__Z9miokernelvv
.globl _Z9miokernelv
.type _Z9miokernelv, @function
_Z9miokernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9miokernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9miokernelv, .-_Z9miokernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z27__device_stub__Z9miokernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9miokernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9miokernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z24__device_stub__miokernelv # -- Begin function _Z24__device_stub__miokernelv
.p2align 4, 0x90
.type _Z24__device_stub__miokernelv,@function
_Z24__device_stub__miokernelv: # @_Z24__device_stub__miokernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9miokernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z24__device_stub__miokernelv, .Lfunc_end0-_Z24__device_stub__miokernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z9miokernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9miokernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9miokernelv,@object # @_Z9miokernelv
.section .rodata,"a",@progbits
.globl _Z9miokernelv
.p2align 3, 0x0
_Z9miokernelv:
.quad _Z24__device_stub__miokernelv
.size _Z9miokernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9miokernelv"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__miokernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9miokernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} | code for sm_80
Function : _Z6DTWSSMPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff087624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0030*/ SHF.R.S32.HI R8, RZ, 0x9, R8 ; /* 0x00000009ff087819 */
/* 0x000fe20000011408 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e660000002600 */
/*0050*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc80003f05270 */
/*0060*/ SEL R8, R8, 0x1, P0 ; /* 0x0000000108087807 */
/* 0x000fc80000000000 */
/*0070*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0080*/ @!P0 BRA 0x420 ; /* 0x0000039000008947 */
/* 0x000fea0003800000 */
/*0090*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x003e220000002100 */
/*00a0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ LOP3.LUT R3, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308037812 */
/* 0x000fe400078ec0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fd60003f05270 */
/*00f0*/ @!P1 BRA 0x320 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.IADD R4, R8, 0x1, -R3 ; /* 0x0000000108047824 */
/* 0x000fe400078e0a03 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD R7, R2, 0x200, R5 ; /* 0x0000020002077824 */
/* 0x001fe200078e0205 */
/*0130*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe40007ffe0ff */
/*0140*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fe20007ffe0ff */
/*0150*/ IMAD.SHL.U32 R10, R7.reuse, 0x4, RZ ; /* 0x00000004070a7824 */
/* 0x040fe200078e00ff */
/*0160*/ IADD3 R6, R7.reuse, 0x200, RZ ; /* 0x0000020007067810 */
/* 0x040fe40007ffe0ff */
/*0170*/ ISETP.GE.U32.AND P1, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x040fe40003f26070 */
/*0180*/ IADD3 R11, R7, 0x400, RZ ; /* 0x00000400070b7810 */
/* 0x000fc40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fe20003f46070 */
/*01a0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3 R12, R7, 0x600, RZ ; /* 0x00000600070c7810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P3, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fe20003f66070 */
/*01d0*/ IMAD R11, R6, 0x4, R10 ; /* 0x00000004060b7824 */
/* 0x000fe200078e020a */
/*01e0*/ ISETP.GE.U32.AND P4, PT, R12, c[0x0][0x180], PT ; /* 0x000060000c007a0c */
/* 0x000fc60003f86070 */
/*01f0*/ @!P1 IMAD.MOV.U32 R7, RZ, RZ, -0x40800000 ; /* 0xbf800000ff079424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD R6, R6, 0x4, R11 ; /* 0x0000000406067824 */
/* 0x000fe400078e020b */
/*0210*/ @!P2 IMAD.MOV.U32 R13, RZ, RZ, -0x40800000 ; /* 0xbf800000ff0da424 */
/* 0x000fe200078e00ff */
/*0220*/ @!P1 STS [R10], R7 ; /* 0x000000070a009388 */
/* 0x0001e60000000800 */
/*0230*/ @!P3 IMAD.MOV.U32 R15, RZ, RZ, -0x40800000 ; /* 0xbf800000ff0fb424 */
/* 0x000fe200078e00ff */
/*0240*/ @!P1 STS [R11], R7 ; /* 0x000000070b009388 */
/* 0x0001e20000000800 */
/*0250*/ @!P4 IMAD.MOV.U32 R17, RZ, RZ, -0x40800000 ; /* 0xbf800000ff11c424 */
/* 0x000fc600078e00ff */
/*0260*/ @!P1 STS [R6], R7 ; /* 0x0000000706009388 */
/* 0x0001e20000000800 */
/*0270*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f25270 */
/*0280*/ @!P2 STS [R10+0x800], R13 ; /* 0x0008000d0a00a388 */
/* 0x0001e80000000800 */
/*0290*/ @!P2 STS [R11+0x800], R13 ; /* 0x0008000d0b00a388 */
/* 0x0001e80000000800 */
/*02a0*/ @!P2 STS [R6+0x800], R13 ; /* 0x0008000d0600a388 */
/* 0x0001e80000000800 */
/*02b0*/ @!P3 STS [R10+0x1000], R15 ; /* 0x0010000f0a00b388 */
/* 0x0001e80000000800 */
/*02c0*/ @!P3 STS [R11+0x1000], R15 ; /* 0x0010000f0b00b388 */
/* 0x0001e80000000800 */
/*02d0*/ @!P3 STS [R6+0x1000], R15 ; /* 0x0010000f0600b388 */
/* 0x0001e80000000800 */
/*02e0*/ @!P4 STS [R10+0x1800], R17 ; /* 0x001800110a00c388 */
/* 0x0001e80000000800 */
/*02f0*/ @!P4 STS [R11+0x1800], R17 ; /* 0x001800110b00c388 */
/* 0x0001e80000000800 */
/*0300*/ @!P4 STS [R6+0x1800], R17 ; /* 0x001800110600c388 */
/* 0x0001e20000000800 */
/*0310*/ @P1 BRA 0x120 ; /* 0xfffffe0000001947 */
/* 0x000fea000383ffff */
/*0320*/ @!P0 BRA 0x420 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0330*/ IMAD R2, R2, 0x200, R5 ; /* 0x0000020002027824 */
/* 0x001fc800078e0205 */
/*0340*/ IMAD.SHL.U32 R4, R2, 0x4, RZ ; /* 0x0000000402047824 */
/* 0x000fe400078e00ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x040fe40003f06070 */
/*0360*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fd20007ffe0ff */
/*0380*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff068624 */
/* 0x000fe400078e00ff */
/*0390*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40800000 ; /* 0xbf800000ff078424 */
/* 0x000fe400078e00ff */
/*03a0*/ @!P0 IMAD R5, R6, 0x4, R4 ; /* 0x0000000406058824 */
/* 0x000fc600078e0204 */
/*03b0*/ @!P0 STS [R4], R7 ; /* 0x0000000704008388 */
/* 0x0001e20000000800 */
/*03c0*/ @!P0 IMAD R6, R6, 0x4, R5 ; /* 0x0000000406068824 */
/* 0x000fc600078e0205 */
/*03d0*/ @!P0 STS [R5], R7 ; /* 0x0000000705008388 */
/* 0x0003e80000000800 */
/*03e0*/ @!P0 STS [R6], R7 ; /* 0x0000000706008388 */
/* 0x0003e20000000800 */
/*03f0*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f05270 */
/*0400*/ IADD3 R4, R4, 0x800, RZ ; /* 0x0000080004047810 */
/* 0x001fd60007ffe0ff */
/*0410*/ @P0 BRA 0x350 ; /* 0xffffff3000000947 */
/* 0x002fea000383ffff */
/*0420*/ ULDC.64 UR6, c[0x0][0x178] ; /* 0x00005e0000067ab9 */
/* 0x003fe40000000a00 */
/*0430*/ UIADD3 UR5, UR7, UR6, URZ ; /* 0x0000000607057290 */
/* 0x000fc8000fffe03f */
/*0440*/ UISETP.GE.AND UP0, UPT, UR5, 0x2, UPT ; /* 0x000000020500788c */
/* 0x000fcc000bf06270 */
/*0450*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0003f0f008 */
/*0460*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0470*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002100 */
/*0480*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0490*/ UIADD3 UR6, UR7, -0x1, URZ ; /* 0xffffffff07067890 */
/* 0x000fe2000fffe03f */
/*04a0*/ IMAD R2, R9.reuse, c[0x0][0x17c], R0 ; /* 0x00005f0009027a24 */
/* 0x040fe200078e0200 */
/*04b0*/ IADD3 R12, R0, 0x1, RZ ; /* 0x00000001000c7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*04d0*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe20007ffe0ff */
/*04e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe200078e0203 */
/*04f0*/ UMOV UR7, 0x1 ; /* 0x0000000100077882 */
/* 0x000fe40000000000 */
/*0500*/ ULDC UR8, c[0x0][0x178] ; /* 0x00005e0000087ab9 */
/* 0x000fc40000000800 */
/*0510*/ UIADD3 UR10, UR5, -0x2, URZ ; /* 0xfffffffe050a7890 */
/* 0x000fe4000fffe03f */
/*0520*/ UIADD3 UR9, UR5, -0x1, URZ ; /* 0xffffffff05097890 */
/* 0x000fe4000fffe03f */
/*0530*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0540*/ UIADD3 UR5, -UR7, UR8, URZ ; /* 0x0000000807057290 */
/* 0x000fe4000fffe13f */
/*0550*/ ULDC.64 UR12, c[0x0][0x118] ; /* 0x00004600000c7ab9 */
/* 0x000fe40000000a00 */
/*0560*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0570*/ ULDC.64 UR14, c[0x0][0x178] ; /* 0x00005e00000e7ab9 */
/* 0x000fe40000000a00 */
/*0580*/ UIADD3 UR7, -UR5, UR4, URZ ; /* 0x0000000405077290 */
/* 0x000fc4000fffe13f */
/*0590*/ UISETP.GE.AND UP1, UPT, UR4, UR14, UPT ; /* 0x0000000e0400728c */
/* 0x000fe4000bf26270 */
/*05a0*/ UISETP.GE.AND UP0, UPT, UR4, UR15, UPT ; /* 0x0000000f0400728c */
/* 0x000fe4000bf06270 */
/*05b0*/ UIADD3 UR8, -UR6, UR4, URZ ; /* 0x0000000406087290 */
/* 0x000fe4000fffe13f */
/*05c0*/ USEL UR7, UR7, URZ, UP1 ; /* 0x0000003f07077287 */
/* 0x000fe40008800000 */
/*05d0*/ USEL UR8, UR8, URZ, UP0 ; /* 0x0000003f08087287 */
/* 0x000fe20008000000 */
/*05e0*/ @!P0 BRA 0x1200 ; /* 0x00000c1000008947 */
/* 0x001fea0003800000 */
/*05f0*/ USEL UR14, UR5, UR4, UP1 ; /* 0x00000004050e7287 */
/* 0x000fe20008800000 */
/*0600*/ IADD3 R14, R10.reuse, 0x1, RZ ; /* 0x000000010a0e7810 */
/* 0x040fe20007ffe0ff */
/*0610*/ UISETP.GT.AND UP1, UPT, UR7, 0x1, UPT ; /* 0x000000010700788c */
/* 0x000fe2000bf24270 */
/*0620*/ IADD3 R15, R10, 0x2, RZ ; /* 0x000000020a0f7810 */
/* 0x000fe20007ffe0ff */
/*0630*/ ULDC UR11, c[0x0][0x178] ; /* 0x00005e00000b7ab9 */
/* 0x000fe20000000800 */
/*0640*/ BSSY B0, 0x1200 ; /* 0x00000bb000007945 */
/* 0x000fe20003800000 */
/*0650*/ IMAD.U32 R5, RZ, RZ, UR14 ; /* 0x0000000eff057e24 */
/* 0x000fe2000f8e00ff */
/*0660*/ UISETP.GE.AND UP2, UPT, UR4, UR11, UPT ; /* 0x0000000b0400728c */
/* 0x000fe2000bf46270 */
/*0670*/ PLOP3.LUT P0, PT, PT, PT, UP1, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0f018 */
/*0680*/ IMAD.HI R4, R14, 0x55555556, RZ ; /* 0x555555560e047827 */
/* 0x000fe200078e02ff */
/*0690*/ USEL UR15, UR6, UR4, UP0 ; /* 0x00000004060f7287 */
/* 0x000fe20008000000 */
/*06a0*/ ISETP.EQ.AND P1, PT, R5, UR5, PT ; /* 0x0000000505007c0c */
/* 0x000fe2000bf22270 */
/*06b0*/ USEL UR11, URZ, 0xffffffff, UP2 ; /* 0xffffffff3f0b7887 */
/* 0x000fe20009000000 */
/*06c0*/ IMAD.HI R6, R15, 0x55555556, RZ ; /* 0x555555560f067827 */
/* 0x000fe200078e02ff */
/*06d0*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fc800078f08ff */
/*06e0*/ LEA.HI R6, R6, R6, RZ, 0x1 ; /* 0x0000000606067211 */
/* 0x000fe200078f08ff */
/*06f0*/ IMAD.U32 R16, RZ, RZ, UR11 ; /* 0x0000000bff107e24 */
/* 0x000fe4000f8e00ff */
/*0700*/ IMAD R14, R5, -0x3, R14 ; /* 0xfffffffd050e7824 */
/* 0x000fe400078e020e */
/*0710*/ IMAD R15, R6, -0x3, R15 ; /* 0xfffffffd060f7824 */
/* 0x000fe200078e020f */
/*0720*/ @P0 BRA P1, 0xc90 ; /* 0x0000056000000947 */
/* 0x000fea0000800000 */
/*0730*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD R21, R17, 0x200, R13 ; /* 0x0000020011157824 */
/* 0x001fca00078e020d */
/*0750*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x180], PT ; /* 0x0000600015007a0c */
/* 0x000fda0003f06270 */
/*0760*/ @P0 BRA 0x11f0 ; /* 0x00000a8000000947 */
/* 0x000fea0003800000 */
/*0770*/ IADD3 R19, R21.reuse, UR7, RZ ; /* 0x0000000715137c10 */
/* 0x040fe2000fffe0ff */
/*0780*/ IMAD R18, R10, c[0x0][0x180], R21 ; /* 0x000060000a127a24 */
/* 0x000fe200078e0215 */
/*0790*/ IADD3 R20, -R21, UR14, RZ ; /* 0x0000000e15147c10 */
/* 0x000fe2000fffe1ff */
/*07a0*/ BSSY B1, 0xc50 ; /* 0x000004a000017945 */
/* 0x000fe20003800000 */
/*07b0*/ ISETP.GT.AND P0, PT, R19, UR15, PT ; /* 0x0000000f13007c0c */
/* 0x000fe2000bf04270 */
/*07c0*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fc600078e00ff */
/*07d0*/ ISETP.LT.OR P0, PT, R20, UR8, P0 ; /* 0x0000000814007c0c */
/* 0x000fda0008701670 */
/*07e0*/ @P0 BRA 0xc20 ; /* 0x0000043000000947 */
/* 0x000fea0003800000 */
/*07f0*/ ISETP.GT.AND P0, PT, R20.reuse, R9.reuse, PT ; /* 0x000000091400720c */
/* 0x0c0fe20003f04270 */
/*0800*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fe200078e00ff */
/*0810*/ ISETP.GE.AND P1, PT, R20, R9, PT ; /* 0x000000091400720c */
/* 0x000fe40003f26270 */
/*0820*/ ISETP.LE.AND P0, PT, R19.reuse, R0.reuse, !P0 ; /* 0x000000001300720c */
/* 0x0c0fe40004703270 */
/*0830*/ ISETP.GE.AND P1, PT, R19, R0, P1 ; /* 0x000000001300720c */
/* 0x000fc80000f26270 */
/*0840*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0850*/ @!P0 STS [R18], R5 ; /* 0x0000000512008388 */
/* 0x0001e20000000800 */
/*0860*/ @!P0 BRA 0xc40 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0880*/ IMAD R4, R9, c[0x0][0x178], R20 ; /* 0x00005e0009047a24 */
/* 0x000fe400078e0214 */
/*0890*/ IMAD R6, R0, c[0x0][0x17c], R19 ; /* 0x00005f0000067a24 */
/* 0x000fe400078e0213 */
/*08a0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fc800078e0207 */
/*08b0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*08c0*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x0000a8000c1e1900 */
/*08d0*/ LDG.E R6, [R6.64] ; /* 0x0000000c06067981 */
/* 0x000ea2000c1e1900 */
/*08e0*/ IMAD.IADD R22, R16, 0x1, R21 ; /* 0x0000000110167824 */
/* 0x000fe200078e0215 */
/*08f0*/ ISETP.NE.AND P2, PT, R19.reuse, R12, PT ; /* 0x0000000c1300720c */
/* 0x040fe20003f45270 */
/*0900*/ BSSY B2, 0xa70 ; /* 0x0000016000027945 */
/* 0x000fe20003800000 */
/*0910*/ ISETP.NE.AND P0, PT, R19, R0, PT ; /* 0x000000001300720c */
/* 0x000fc40003f05270 */
/*0920*/ IADD3 R21, R22, 0x1, RZ ; /* 0x0000000116157810 */
/* 0x000fe20007ffe0ff */
/*0930*/ IMAD.MOV.U32 R4, RZ, RZ, -0x40800000 ; /* 0xbf800000ff047424 */
/* 0x001fe200078e00ff */
/*0940*/ ISETP.GT.AND P1, PT, R20.reuse, RZ, PT ; /* 0x000000ff1400720c */
/* 0x040fe40003f24270 */
/*0950*/ ISETP.GE.AND P4, PT, R21, UR9, PT ; /* 0x0000000915007c0c */
/* 0x000fe4000bf86270 */
/*0960*/ ISETP.EQ.AND P2, PT, R20.reuse, R9, !P2 ; /* 0x000000091400720c */
/* 0x040fe40005742270 */
/*0970*/ ISETP.LT.OR P4, PT, R20.reuse, 0x1, P4 ; /* 0x000000011400780c */
/* 0x040fe40002781670 */
/*0980*/ ISETP.EQ.AND P0, PT, R20, R11, !P0 ; /* 0x0000000b1400720c */
/* 0x000fc40004702270 */
/*0990*/ ISETP.GT.AND P1, PT, R22, -0x1, P1 ; /* 0xffffffff1600780c */
/* 0x000fe40000f24270 */
/*09a0*/ ISETP.GE.AND P3, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x000fe20003f66270 */
/*09b0*/ IMAD R19, R14, c[0x0][0x180], R22 ; /* 0x000060000e137a24 */
/* 0x000fe200078e0216 */
/*09c0*/ PLOP3.LUT P0, PT, P1, P2, P0, 0x10, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000f04200 */
/*09d0*/ ISETP.LT.OR P3, PT, R22, RZ, !P3 ; /* 0x000000ff1600720c */
/* 0x000fe20005f61670 */
/*09e0*/ FADD R7, -R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000100 */
/*09f0*/ FSETP.GEU.AND P1, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fe20003f2e000 */
/*0a00*/ IMAD.SHL.U32 R6, R19, 0x4, RZ ; /* 0x0000000413067824 */
/* 0x000fc600078e00ff */
/*0a10*/ FSEL R19, -R7, R7, !P1 ; /* 0x0000000707137208 */
/* 0x000fe20004800100 */
/*0a20*/ @P4 BRA 0xa60 ; /* 0x0000003000004947 */
/* 0x000fea0003800000 */
/*0a30*/ LDS R20, [R6+0x4] ; /* 0x0000040006147984 */
/* 0x000e240000000800 */
/*0a40*/ FSETP.GT.AND P1, PT, R20, -1, PT ; /* 0xbf8000001400780b */
/* 0x001fda0003f24000 */
/*0a50*/ @P1 FADD R4, R19, R20 ; /* 0x0000001413041221 */
/* 0x000fe40000000000 */
/*0a60*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a70*/ BSSY B2, 0xb00 ; /* 0x0000008000027945 */
/* 0x000fe20003800000 */
/*0a80*/ @P3 BRA 0xaf0 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0a90*/ LDS R6, [R6] ; /* 0x0000000006067984 */
/* 0x000e240000000800 */
/*0aa0*/ FSETP.GT.AND P2, PT, R6, -1, PT ; /* 0xbf8000000600780b */
/* 0x001fda0003f44000 */
/*0ab0*/ @P2 FADD R5, R19, R6 ; /* 0x0000000613052221 */
/* 0x000fca0000000000 */
/*0ac0*/ @P2 FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500220b */
/* 0x000fc80003f2e000 */
/*0ad0*/ @P2 FSETP.EQ.OR P1, PT, R4, -1, !P1 ; /* 0xbf8000000400280b */
/* 0x000fc80004f22400 */
/*0ae0*/ @P2 FSEL R4, R5, R4, P1 ; /* 0x0000000405042208 */
/* 0x000fc80000800000 */
/*0af0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b00*/ BSSY B2, 0xba0 ; /* 0x0000009000027945 */
/* 0x000fe20003800000 */
/*0b10*/ @!P0 BRA 0xb90 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IMAD R5, R15, c[0x0][0x180], R22 ; /* 0x000060000f057a24 */
/* 0x000fca00078e0216 */
/*0b30*/ LDS R6, [R5.X4] ; /* 0x0000000005067984 */
/* 0x000e240000004800 */
/*0b40*/ FSETP.GT.AND P1, PT, R6, -1, PT ; /* 0xbf8000000600780b */
/* 0x001fda0003f24000 */
/*0b50*/ @P1 FADD R7, R19, R6 ; /* 0x0000000613071221 */
/* 0x000fca0000000000 */
/*0b60*/ @P1 FSETP.GEU.AND P0, PT, R7, R4, PT ; /* 0x000000040700120b */
/* 0x000fc80003f0e000 */
/*0b70*/ @P1 FSETP.EQ.OR P0, PT, R4, -1, !P0 ; /* 0xbf8000000400180b */
/* 0x000fc80004702400 */
/*0b80*/ @P1 FSEL R4, R7, R4, P0 ; /* 0x0000000407041208 */
/* 0x000fc80000000000 */
/*0b90*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ba0*/ FSETP.NEU.AND P0, PT, R4, -1, PT ; /* 0xbf8000000400780b */
/* 0x000fe20003f0d000 */
/*0bb0*/ UISETP.NE.AND UP0, UPT, UR4, UR10, UPT ; /* 0x0000000a0400728c */
/* 0x000fc6000bf05270 */
/*0bc0*/ FSEL R19, R19, R4, !P0 ; /* 0x0000000413137208 */
/* 0x000fc60004000000 */
/*0bd0*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f008 */
/*0be0*/ STS [R18], R19 ; /* 0x0000001312007388 */
/* 0x0001f60000000800 */
/*0bf0*/ @P0 BRA 0xc40 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0c00*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0011e2000c10190c */
/*0c10*/ BRA 0xc40 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c20*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fca00078e00ff */
/*0c30*/ STS [R18], R5 ; /* 0x0000000512007388 */
/* 0x0001e40000000800 */
/*0c40*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0c50*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fc80007ffe0ff */
/*0c60*/ ISETP.GE.AND P0, PT, R17, R8, PT ; /* 0x000000081100720c */
/* 0x000fda0003f06270 */
/*0c70*/ @!P0 BRA 0x740 ; /* 0xfffffac000008947 */
/* 0x000fea000383ffff */
/*0c80*/ BRA 0x11f0 ; /* 0x0000056000007947 */
/* 0x000fea0003800000 */
/*0c90*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fc800078e00ff */
/*0ca0*/ IMAD R19, R17, 0x200, R13 ; /* 0x0000020011137824 */
/* 0x001fca00078e020d */
/*0cb0*/ ISETP.GE.AND P0, PT, R19, c[0x0][0x180], PT ; /* 0x0000600013007a0c */
/* 0x000fda0003f06270 */
/*0cc0*/ @P0 BRA 0x11f0 ; /* 0x0000052000000947 */
/* 0x000fea0003800000 */
/*0cd0*/ IADD3 R21, R19.reuse, UR7, RZ ; /* 0x0000000713157c10 */
/* 0x040fe2000fffe0ff */
/*0ce0*/ IMAD R18, R10, c[0x0][0x180], R19 ; /* 0x000060000a127a24 */
/* 0x000fe200078e0213 */
/*0cf0*/ IADD3 R20, -R19, UR5, RZ ; /* 0x0000000513147c10 */
/* 0x000fe2000fffe1ff */
/*0d00*/ BSSY B1, 0x11c0 ; /* 0x000004b000017945 */
/* 0x000fe20003800000 */
/*0d10*/ ISETP.GT.AND P0, PT, R21, UR15, PT ; /* 0x0000000f15007c0c */
/* 0x000fe2000bf04270 */
/*0d20*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fc600078e00ff */
/*0d30*/ ISETP.LT.OR P0, PT, R20, UR8, P0 ; /* 0x0000000814007c0c */
/* 0x000fda0008701670 */
/*0d40*/ @P0 BRA 0x1190 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*0d50*/ ISETP.GT.AND P0, PT, R20.reuse, R9.reuse, PT ; /* 0x000000091400720c */
/* 0x0c0fe20003f04270 */
/*0d60*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fe200078e00ff */
/*0d70*/ ISETP.GE.AND P1, PT, R20, R9, PT ; /* 0x000000091400720c */
/* 0x000fe40003f26270 */
/*0d80*/ ISETP.LE.AND P0, PT, R21.reuse, R0.reuse, !P0 ; /* 0x000000001500720c */
/* 0x0c0fe40004703270 */
/*0d90*/ ISETP.GE.AND P1, PT, R21, R0, P1 ; /* 0x000000001500720c */
/* 0x000fc80000f26270 */
/*0da0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0db0*/ @!P0 STS [R18], R5 ; /* 0x0000000512008388 */
/* 0x0001e20000000800 */
/*0dc0*/ @!P0 BRA 0x11b0 ; /* 0x000003e000008947 */
/* 0x000fea0003800000 */
/*0dd0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0de0*/ IMAD R4, R9, c[0x0][0x178], R20 ; /* 0x00005e0009047a24 */
/* 0x000fe400078e0214 */
/*0df0*/ IMAD R6, R0, c[0x0][0x17c], R21 ; /* 0x00005f0000067a24 */
/* 0x000fe400078e0215 */
/*0e00*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x001fc800078e0207 */
/*0e10*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*0e20*/ LDG.E R5, [R4.64] ; /* 0x0000000c04057981 */
/* 0x0000a8000c1e1900 */
/*0e30*/ LDG.E R6, [R6.64] ; /* 0x0000000c06067981 */
/* 0x000ea2000c1e1900 */
/*0e40*/ IMAD.IADD R23, R16, 0x1, R19 ; /* 0x0000000110177824 */
/* 0x000fe200078e0213 */
/*0e50*/ ISETP.NE.AND P2, PT, R21.reuse, R12, PT ; /* 0x0000000c1500720c */
/* 0x040fe20003f45270 */
/*0e60*/ BSSY B2, 0xfd0 ; /* 0x0000016000027945 */
/* 0x000fe20003800000 */
/*0e70*/ ISETP.NE.AND P0, PT, R21, R0, PT ; /* 0x000000001500720c */
/* 0x000fc40003f05270 */
/*0e80*/ IADD3 R16, R23, 0x1, RZ ; /* 0x0000000117107810 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD.MOV.U32 R4, RZ, RZ, -0x40800000 ; /* 0xbf800000ff047424 */
/* 0x001fe200078e00ff */
/*0ea0*/ ISETP.GT.AND P1, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f24270 */
/*0eb0*/ ISETP.GE.AND P4, PT, R16, UR9, PT ; /* 0x0000000910007c0c */
/* 0x000fe2000bf86270 */
/*0ec0*/ IMAD R16, R14, c[0x0][0x180], R23 ; /* 0x000060000e107a24 */
/* 0x000fe200078e0217 */
/*0ed0*/ ISETP.EQ.AND P2, PT, R20.reuse, R9, !P2 ; /* 0x000000091400720c */
/* 0x040fe40005742270 */
/*0ee0*/ ISETP.LT.OR P4, PT, R20, 0x1, P4 ; /* 0x000000011400780c */
/* 0x000fe20002781670 */
/*0ef0*/ IMAD.SHL.U32 R16, R16, 0x4, RZ ; /* 0x0000000410107824 */
/* 0x000fe200078e00ff */
/*0f00*/ ISETP.EQ.AND P0, PT, R20, R11, !P0 ; /* 0x0000000b1400720c */
/* 0x000fc40004702270 */
/*0f10*/ ISETP.GT.AND P1, PT, R19, -0x2, P1 ; /* 0xfffffffe1300780c */
/* 0x000fe40000f24270 */
/*0f20*/ ISETP.GE.AND P3, PT, R21, 0x1, PT ; /* 0x000000011500780c */
/* 0x000fe40003f66270 */
/*0f30*/ PLOP3.LUT P0, PT, P1, P2, P0, 0x10, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000f04200 */
/*0f40*/ ISETP.LT.OR P3, PT, R23, RZ, !P3 ; /* 0x000000ff1700720c */
/* 0x000fe20005f61670 */
/*0f50*/ FADD R7, -R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000100 */
/*0f60*/ FSETP.GEU.AND P1, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc80003f2e000 */
/*0f70*/ FSEL R7, -R7, R7, !P1 ; /* 0x0000000707077208 */
/* 0x000fe20004800100 */
/*0f80*/ @P4 BRA 0xfc0 ; /* 0x0000003000004947 */
/* 0x000fea0003800000 */
/*0f90*/ LDS R6, [R16+0x4] ; /* 0x0000040010067984 */
/* 0x000e240000000800 */
/*0fa0*/ FSETP.GT.AND P1, PT, R6, -1, PT ; /* 0xbf8000000600780b */
/* 0x001fda0003f24000 */
/*0fb0*/ @P1 FADD R4, R7, R6 ; /* 0x0000000607041221 */
/* 0x000fe40000000000 */
/*0fc0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0fd0*/ BSSY B2, 0x1060 ; /* 0x0000008000027945 */
/* 0x000fe20003800000 */
/*0fe0*/ @P3 BRA 0x1050 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0ff0*/ LDS R16, [R16] ; /* 0x0000000010107984 */
/* 0x000e240000000800 */
/*1000*/ FSETP.GT.AND P2, PT, R16, -1, PT ; /* 0xbf8000001000780b */
/* 0x001fda0003f44000 */
/*1010*/ @P2 FADD R5, R7, R16 ; /* 0x0000001007052221 */
/* 0x000fca0000000000 */
/*1020*/ @P2 FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500220b */
/* 0x000fc80003f2e000 */
/*1030*/ @P2 FSETP.EQ.OR P1, PT, R4, -1, !P1 ; /* 0xbf8000000400280b */
/* 0x000fc80004f22400 */
/*1040*/ @P2 FSEL R4, R5, R4, P1 ; /* 0x0000000405042208 */
/* 0x000fc80000800000 */
/*1050*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1060*/ BSSY B2, 0x1100 ; /* 0x0000009000027945 */
/* 0x000fe20003800000 */
/*1070*/ @!P0 BRA 0x10f0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*1080*/ IMAD R19, R15, c[0x0][0x180], R19 ; /* 0x000060000f137a24 */
/* 0x000fca00078e0213 */
/*1090*/ LDS R6, [R19.X4+0x4] ; /* 0x0000040013067984 */
/* 0x000e240000004800 */
/*10a0*/ FSETP.GT.AND P1, PT, R6, -1, PT ; /* 0xbf8000000600780b */
/* 0x001fda0003f24000 */
/*10b0*/ @P1 FADD R5, R7, R6 ; /* 0x0000000607051221 */
/* 0x000fca0000000000 */
/*10c0*/ @P1 FSETP.GEU.AND P0, PT, R5, R4, PT ; /* 0x000000040500120b */
/* 0x000fc80003f0e000 */
/*10d0*/ @P1 FSETP.EQ.OR P0, PT, R4, -1, !P0 ; /* 0xbf8000000400180b */
/* 0x000fc80004702400 */
/*10e0*/ @P1 FSEL R4, R5, R4, P0 ; /* 0x0000000405041208 */
/* 0x000fc80000000000 */
/*10f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1100*/ FSETP.NEU.AND P0, PT, R4, -1, PT ; /* 0xbf8000000400780b */
/* 0x000fe20003f0d000 */
/*1110*/ UISETP.NE.AND UP0, UPT, UR4, UR10, UPT ; /* 0x0000000a0400728c */
/* 0x000fe2000bf05270 */
/*1120*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe400078e00ff */
/*1130*/ FSEL R7, R7, R4, !P0 ; /* 0x0000000407077208 */
/* 0x000fc60004000000 */
/*1140*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f008 */
/*1150*/ STS [R18], R7 ; /* 0x0000000712007388 */
/* 0x0001f60000000800 */
/*1160*/ @P0 BRA 0x11b0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*1170*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0011e2000c10190c */
/*1180*/ BRA 0x11b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1190*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fca00078e00ff */
/*11a0*/ STS [R18], R5 ; /* 0x0000000512007388 */
/* 0x0001e40000000800 */
/*11b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*11c0*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fc80007ffe0ff */
/*11d0*/ ISETP.GE.AND P0, PT, R17, R8, PT ; /* 0x000000081100720c */
/* 0x000fda0003f06270 */
/*11e0*/ @!P0 BRA 0xca0 ; /* 0xfffffab000008947 */
/* 0x000fea000383ffff */
/*11f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1200*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*1210*/ IADD3 R10, R10, 0x2, RZ ; /* 0x000000020a0a7810 */
/* 0x000fe20007ffe0ff */
/*1220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*1230*/ UISETP.GE.AND UP0, UPT, UR4, UR9, UPT ; /* 0x000000090400728c */
/* 0x000fe4000bf06270 */
/*1240*/ IMAD.HI R4, R10, 0x55555556, RZ ; /* 0x555555560a047827 */
/* 0x000fc800078e02ff */
/*1250*/ PLOP3.LUT P0, PT, PT, PT, UP0, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f008 */
/*1260*/ LEA.HI R5, R4, R4, RZ, 0x1 ; /* 0x0000000404057211 */
/* 0x000fca00078f08ff */
/*1270*/ IMAD R10, R5, -0x3, R10 ; /* 0xfffffffd050a7824 */
/* 0x000fcc00078e020a */
/*1280*/ @P0 CALL.REL.NOINC 0x12a0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*1290*/ BRA 0x560 ; /* 0xfffff2c000007947 */
/* 0x000fea000383ffff */
/*12a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12b0*/ BRA 0x12b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} | .file "tmpxft_00141098_00000000-6_DTWSSMGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
.type _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, @function
_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6DTWSSMPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, .-_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
.globl _Z6DTWSSMPfS_S_iiii
.type _Z6DTWSSMPfS_S_iiii, @function
_Z6DTWSSMPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6DTWSSMPfS_S_iiii, .-_Z6DTWSSMPfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6DTWSSMPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6DTWSSMPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} | #include <hip/hip_runtime.h>
__global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6DTWSSMPfS_S_iiii
.globl _Z6DTWSSMPfS_S_iiii
.p2align 8
.type _Z6DTWSSMPfS_S_iiii,@function
_Z6DTWSSMPfS_S_iiii:
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s3, 9
s_cmpk_gt_u32 s3, 0x1ff
s_cselect_b32 s3, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_7
v_lshl_add_u32 v1, v0, 2, 0
v_mov_b32_e32 v2, -1.0
s_mov_b32 s4, 0
s_lshl_b32 s5, s2, 2
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v1, 0x800, v1
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, s3
s_cbranch_scc1 .LBB0_7
.LBB0_3:
v_lshl_add_u32 v3, s4, 9, v0
s_mov_b32 s6, 3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v3
v_mov_b32_e32 v3, v1
s_branch .LBB0_5
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v3, s5, v3
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 0
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_4
ds_store_b32 v3, v2
s_branch .LBB0_4
.LBB0_7:
s_load_b64 s[8:9], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_add_i32 s21, s9, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s21, 2
s_cbranch_scc1 .LBB0_44
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
s_add_i32 s12, s21, -1
s_add_i32 s13, s8, -1
s_add_i32 s16, s9, -1
s_mul_i32 s0, s14, s9
s_cmp_gt_i32 s3, 0
v_sub_nc_u32_e32 v1, 0, v0
s_cselect_b32 s20, -1, 0
s_add_i32 s0, s0, s15
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, -1.0
s_ashr_i32 s1, s0, 31
s_add_i32 s21, s21, -2
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s19, 0
s_mul_i32 s17, s14, s8
s_mul_i32 s18, s15, s9
s_mov_b32 s24, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s10, s10, s0
s_addc_u32 s11, s11, s1
s_max_i32 s22, s12, 1
s_sub_i32 s23, 0, s14
s_branch .LBB0_11
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s28
.LBB0_10:
s_add_i32 s0, s19, 2
s_add_i32 s24, s24, 1
s_mul_hi_u32 s1, s0, 0xaaaaaaab
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_lshr_b32 s1, s1, 1
s_barrier
s_mul_i32 s1, s1, 3
buffer_gl0_inv
s_sub_i32 s19, s0, s1
s_cmp_lg_u32 s24, s22
s_cbranch_scc0 .LBB0_44
.LBB0_11:
s_and_not1_b32 vcc_lo, exec_lo, s20
s_cbranch_vccnz .LBB0_10
s_sub_i32 s0, s24, s13
s_cmp_lt_i32 s24, s8
v_mad_u64_u32 v[6:7], null, s19, s2, v[0:1]
s_cselect_b32 s1, -1, 0
v_mov_b32_e32 v7, v0
v_cndmask_b32_e64 v4, 0, -1, s1
s_and_b32 s1, s1, exec_lo
s_cselect_b32 s25, 0, s0
s_cselect_b32 s0, s24, s13
s_sub_i32 s1, s24, s16
s_cmp_lt_i32 s24, s9
v_add_nc_u32_e32 v5, s0, v1
s_cselect_b32 s26, 0, s1
s_cselect_b32 s27, s24, s16
s_add_i32 s1, s19, 1
v_lshl_add_u32 v6, v6, 2, 0
s_cmp_lg_u32 s1, 3
s_mov_b32 s28, 0
s_cselect_b32 s29, s1, 0
s_cmp_eq_u32 s0, s13
s_mul_i32 s29, s29, s2
s_cselect_b32 s1, -1, 0
s_cmp_gt_i32 s25, 1
s_mov_b32 s40, s3
s_cselect_b32 s30, -1, 0
s_add_i32 s31, s19, 2
s_and_b32 s30, s1, s30
s_mul_hi_u32 s33, s31, 0xaaaaaaab
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s33, s33, 1
s_mul_i32 s33, s33, 3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s31, s31, s33
s_cmp_eq_u32 s24, s21
s_mul_i32 s31, s31, s2
s_cselect_b32 s33, -1, 0
s_add_i32 s35, s23, s0
s_sub_i32 s37, s15, s25
s_add_i32 s34, s29, 1
s_add_i32 s36, s35, -1
s_add_i32 s38, s37, 1
s_add_i32 s39, s18, s25
s_branch .LBB0_15
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s40, s40, -1
v_dual_mov_b32 v4, v8 :: v_dual_add_nc_u32 v7, 0x200, v7
s_cmp_eq_u32 s40, 0
v_add_nc_u32_e32 v5, 0xfffffe00, v5
s_cselect_b32 s0, -1, 0
v_add_nc_u32_e32 v6, 0x800, v6
s_and_not1_b32 s1, s41, exec_lo
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s41, s1, s0
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s42
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s41
s_or_b32 s28, s0, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execz .LBB0_9
.LBB0_15:
s_or_b32 s41, s41, exec_lo
s_mov_b32 s42, exec_lo
v_cmpx_gt_i32_e64 s2, v7
s_cbranch_execz .LBB0_14
v_add_nc_u32_e32 v11, s25, v7
v_cmp_le_i32_e32 vcc_lo, s26, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, s27, v11
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_xor_b32 s43, exec_lo, s1
s_cbranch_execz .LBB0_42
v_cmp_lt_i32_e32 vcc_lo, s14, v5
v_cmp_lt_i32_e64 s0, s15, v11
s_mov_b32 s44, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_xor_b32 s1, s0, -1
s_and_saveexec_b32 s45, s0
v_cmp_le_i32_e32 vcc_lo, s14, v5
v_cmp_le_i32_e64 s0, s15, v11
s_and_not1_b32 s1, s1, exec_lo
s_mov_b32 s44, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s1, s0
s_or_b32 exec_lo, exec_lo, s45
s_and_saveexec_b32 s45, s1
s_cbranch_execz .LBB0_39
v_add_nc_u32_e32 v8, s17, v5
v_add_nc_u32_e32 v12, s39, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0, v5
global_load_b32 v9, v[8:9], off
global_load_b32 v10, v[12:13], off
v_add_nc_u32_e32 v8, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v12, 1, v8
v_cmp_gt_i32_e64 s0, s12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_and_b32 s0, vcc_lo, s0
s_waitcnt vmcnt(0)
v_dual_sub_f32 v9, v9, v10 :: v_dual_mov_b32 v10, -1.0
v_cmp_gt_f32_e64 s1, 0, v9
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v9, v9, -v9, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_24
v_add3_u32 v10, s34, v7, v4
s_mov_b32 s46, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v10, v10, 2, 0
ds_load_b32 v12, v10
v_mov_b32_e32 v10, -1.0
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 -1.0, v12
v_add_f32_e32 v10, v9, v12
s_or_b32 exec_lo, exec_lo, s46
.LBB0_24:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s1
v_cmp_lt_i32_e64 s0, -1, v8
v_cmp_lt_i32_e64 s1, 0, v11
s_and_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s46, s0
s_cbranch_execz .LBB0_28
v_add3_u32 v8, s29, v7, v4
s_mov_b32 s47, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 2, 0
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 -1.0, v8
v_add_f32_e32 v8, v9, v8
v_cmp_eq_f32_e64 s0, -1.0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s1, v8, v10
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
v_cndmask_b32_e64 v10, v10, v8, s0
s_or_b32 exec_lo, exec_lo, s47
.LBB0_28:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s46
v_cmp_ne_u32_e64 s0, s35, v7
v_cmp_ne_u32_e64 s1, s38, v7
v_cndmask_b32_e64 v8, v4, 1, s30
s_or_b32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s46, s0
s_cbranch_execz .LBB0_36
v_cmp_ne_u32_e64 s0, s36, v7
v_cmp_ne_u32_e64 s1, s37, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, s0, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_35
v_add_nc_u32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e64 s0, -1, v11
s_and_b32 s0, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s47, s0
s_cbranch_execz .LBB0_34
v_add3_u32 v11, s31, v8, v7
s_mov_b32 s48, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v11, v11, 2, 0
ds_load_b32 v11, v11
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 -1.0, v11
v_add_f32_e32 v11, v9, v11
v_cmp_eq_f32_e32 vcc_lo, -1.0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, v11, v10
s_or_b32 vcc_lo, vcc_lo, s0
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
s_or_b32 exec_lo, exec_lo, s48
.LBB0_34:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s47
.LBB0_35:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
.LBB0_36:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s46
v_cmp_eq_f32_e32 vcc_lo, -1.0, v10
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s33
ds_store_b32 v6, v9
s_cbranch_vccnz .LBB0_38
global_store_b32 v2, v9, s[10:11]
.LBB0_38:
s_and_not1_b32 s44, s44, exec_lo
.LBB0_39:
s_or_b32 exec_lo, exec_lo, s45
s_and_saveexec_b32 s0, s44
s_cbranch_execz .LBB0_41
v_mov_b32_e32 v8, v4
ds_store_b32 v6, v3
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_42:
s_and_not1_saveexec_b32 s0, s43
s_cbranch_execz .LBB0_13
v_mov_b32_e32 v8, v4
ds_store_b32 v6, v3
s_branch .LBB0_13
.LBB0_44:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6DTWSSMPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 49
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6DTWSSMPfS_S_iiii, .Lfunc_end0-_Z6DTWSSMPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6DTWSSMPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 51
.sgpr_spill_count: 0
.symbol: _Z6DTWSSMPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void DTWSSM(float* SSMA, float* SSMB, float* CSM, int M, int N, int diagLen, int diagLenPow2) {
//Have circularly rotating system of 3 buffers
extern __shared__ float x[]; //Circular buffer
int off = 0;
int upoff = 0;
//Other local variables
int i, k;
int i1, i2, j1, j2;
int thisi, thisj;
int idx;
float val, score;
int ci = blockIdx.x;
int cj = blockIdx.y;
//Figure out K (number of batches)
int K = diagLenPow2 >> 9;
if (K == 0) {
K = 1;
}
//Initialize all buffer elements to -1
for (k = 0; k < K; k++) {
for (off = 0; off < 3; off++) {
if (512*k + threadIdx.x < diagLen) {
x[512*k + threadIdx.x + off*diagLen] = -1;
}
}
}
off = 0;
//Process each diagonal
for (i = 0; i < N + M - 1; i++) {
//Figure out the bounds of this diagonal
i1 = i;
j1 = 0;
upoff = -1;
if (i1 >= M) {
i1 = M-1;
j1 = i - (M-1);
upoff = 0;
}
j2 = i;
i2 = 0;
if (j2 >= N) {
j2 = N-1;
i2 = i - (N-1);
}
//Update each batch
for (k = 0; k < K; k++) {
idx = k*512 + threadIdx.x;
if (idx >= diagLen) {
break;
}
thisi = i1 - idx;
thisj = j1 + idx;
if (thisi < i2 || thisj > j2) {
x[off*diagLen + idx] = -1;
continue;
}
if (!((thisi <= ci && thisj <= cj) || (thisi >= ci && thisj >= cj))) {
x[off*diagLen + idx] = -1;
continue;
}
val = SSMA[ci*M + thisi] - SSMB[cj*N + thisj];
if (val < 0) {
val *= -1;
}
score = -1;
//Above
if (idx + upoff + 1 < N + M - 1 && thisi > 0) {
if (x[((off+1)%3)*diagLen + idx + upoff + 1] > -1) {
score = val + x[((off+1)%3)*diagLen + idx + upoff + 1];
}
}
if (idx + upoff >= 0 && thisj > 0) {
//Left
if (x[((off+1)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+1)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+1)%3)*diagLen + idx + upoff] + val;
}
}
}
if (i1 == M-1 && j1 > 1) {
upoff = 1;
}
if (!((thisi == ci && thisj == cj + 1) || (thisi == ci + 1 && thisj == cj))) {
if (idx + upoff >= 0 && thisi > 0) {
//Diagonal
if (x[((off+2)%3)*diagLen + idx + upoff] > -1) {
if (score == -1 || x[((off+2)%3)*diagLen + idx + upoff] + val < score) {
score = x[((off+2)%3)*diagLen + idx + upoff] + val;
}
}
}
}
if (score == -1) {
score = val;
}
x[off*diagLen + idx] = score;
if (i == N + M - 2) {
CSM[ci*N + cj] = score;
}
}
off = (off + 2) % 3; //Cycle buffers
__syncthreads();
}
} | .text
.file "DTWSSMGPU.hip"
.globl _Z21__device_stub__DTWSSMPfS_S_iiii # -- Begin function _Z21__device_stub__DTWSSMPfS_S_iiii
.p2align 4, 0x90
.type _Z21__device_stub__DTWSSMPfS_S_iiii,@function
_Z21__device_stub__DTWSSMPfS_S_iiii: # @_Z21__device_stub__DTWSSMPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6DTWSSMPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__DTWSSMPfS_S_iiii, .Lfunc_end0-_Z21__device_stub__DTWSSMPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6DTWSSMPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6DTWSSMPfS_S_iiii,@object # @_Z6DTWSSMPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z6DTWSSMPfS_S_iiii
.p2align 3, 0x0
_Z6DTWSSMPfS_S_iiii:
.quad _Z21__device_stub__DTWSSMPfS_S_iiii
.size _Z6DTWSSMPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6DTWSSMPfS_S_iiii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__DTWSSMPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6DTWSSMPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00141098_00000000-6_DTWSSMGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
.type _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, @function
_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6DTWSSMPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii, .-_Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
.globl _Z6DTWSSMPfS_S_iiii
.type _Z6DTWSSMPfS_S_iiii, @function
_Z6DTWSSMPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z6DTWSSMPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6DTWSSMPfS_S_iiii, .-_Z6DTWSSMPfS_S_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6DTWSSMPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6DTWSSMPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DTWSSMGPU.hip"
.globl _Z21__device_stub__DTWSSMPfS_S_iiii # -- Begin function _Z21__device_stub__DTWSSMPfS_S_iiii
.p2align 4, 0x90
.type _Z21__device_stub__DTWSSMPfS_S_iiii,@function
_Z21__device_stub__DTWSSMPfS_S_iiii: # @_Z21__device_stub__DTWSSMPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6DTWSSMPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z21__device_stub__DTWSSMPfS_S_iiii, .Lfunc_end0-_Z21__device_stub__DTWSSMPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6DTWSSMPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6DTWSSMPfS_S_iiii,@object # @_Z6DTWSSMPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z6DTWSSMPfS_S_iiii
.p2align 3, 0x0
_Z6DTWSSMPfS_S_iiii:
.quad _Z21__device_stub__DTWSSMPfS_S_iiii
.size _Z6DTWSSMPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6DTWSSMPfS_S_iiii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__DTWSSMPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6DTWSSMPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
cudaMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
cudaMemcpy(&hA, dA, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
cudaFree(dA);
} | code for sm_80
Function : _Z11calc_kerneliPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fc600078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
cudaMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
cudaMemcpy(&hA, dA, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
cudaFree(dA);
} | .file "tmpxft_000425e0_00000000-6_task2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4244:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4244:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11calc_kerneliPiiiPii
.type _Z33__device_stub__Z11calc_kerneliPiiiPii, @function
_Z33__device_stub__Z11calc_kerneliPiiiPii:
.LFB4266:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calc_kerneliPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4266:
.size _Z33__device_stub__Z11calc_kerneliPiiiPii, .-_Z33__device_stub__Z11calc_kerneliPiiiPii
.globl _Z11calc_kerneliPii
.type _Z11calc_kerneliPii, @function
_Z11calc_kerneliPii:
.LFB4267:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11calc_kerneliPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4267:
.size _Z11calc_kerneliPii, .-_Z11calc_kerneliPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11calc_kerneliPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4269:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_kerneliPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4269:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB4947:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L17:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE4947:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB4883:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L24
.L22:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4883:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB4779:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L36
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L30
movq %rsp, %r15
.L34:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L34
cmpq %r13, %rax
jb .L34
jmp .L29
.L36:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L27
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L27
.L28:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L28
.L27:
movq %rcx, %rax
shrq $32, %rax
.L29:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4779:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z10random_intv
.type _Z10random_intv, @function
_Z10random_intv:
.LFB4240:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $936, %rsp
.cfi_def_cfa_offset 5040
movq %fs:40, %rax
movq %rax, 5016(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %eax
movq %rax, 16(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L39:
movq 8(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 16(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L39
movq $624, 5008(%rsp)
movl $1, 8(%rsp)
movl $100, 12(%rsp)
leaq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rdi, %rdx
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq 5016(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $5032, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4240:
.size _Z10random_intv, .-_Z10random_intv
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB4241:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _Z10random_intv
movl %eax, %ebx
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L45:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %r12
leaq .LC1(%rip), %rbp
.L46:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L46
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl $8, %edx
movq (%rsp), %rsi
movl %ebx, %edi
call _Z33__device_stub__Z11calc_kerneliPiiiPii
jmp .L45
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4241:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
cudaMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
cudaMemcpy(&hA, dA, sizeof(int) * n, cudaMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
cudaFree(dA);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
hipMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
hipMemcpy(&hA, dA, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
hipFree(dA);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
hipMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
hipMemcpy(&hA, dA, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
hipFree(dA);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11calc_kerneliPii
.globl _Z11calc_kerneliPii
.p2align 8
.type _Z11calc_kerneliPii,@function
_Z11calc_kerneliPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mad_u64_u32 v[3:4], null, v0, s4, s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calc_kerneliPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11calc_kerneliPii, .Lfunc_end0-_Z11calc_kerneliPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calc_kerneliPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11calc_kerneliPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <chrono>
#include <random>
__global__ void calc_kernel(int a, int *dA, int dim)
{
int t_x = threadIdx.x;
int b_x = blockIdx.x;
dA[(dim * b_x) + t_x] = a * t_x + b_x;
}
int random_int()
{
// randomize the seed, create distribution
auto seed = std::chrono::system_clock::now().time_since_epoch().count();
std::mt19937 gen(seed);
std::uniform_int_distribution<int> int_dist(1, 100);
// return random int between 1 and 100
return int_dist(gen);
}
int main() {
const int a = random_int();
const int n = 16;
const int blocks = 2;
const int threads_per_block = 8;
int hA[n], *dA;
hipMalloc((void **)&dA, sizeof(int) * n);
calc_kernel<<<blocks, threads_per_block>>>(a, dA, n / 2);
hipMemcpy(&hA, dA, sizeof(int) * n, hipMemcpyDeviceToHost);
for (int i : hA)
{
printf("%d ", i);
}
printf("\n");
hipFree(dA);
} | .text
.file "task2.hip"
.globl _Z26__device_stub__calc_kerneliPii # -- Begin function _Z26__device_stub__calc_kerneliPii
.p2align 4, 0x90
.type _Z26__device_stub__calc_kerneliPii,@function
_Z26__device_stub__calc_kerneliPii: # @_Z26__device_stub__calc_kerneliPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calc_kerneliPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calc_kerneliPii, .Lfunc_end0-_Z26__device_stub__calc_kerneliPii
.cfi_endproc
# -- End function
.globl _Z10random_intv # -- Begin function _Z10random_intv
.p2align 4, 0x90
.type _Z10random_intv,@function
_Z10random_intv: # @_Z10random_intv
.cfi_startproc
# %bb.0:
subq $5016, %rsp # imm = 0x1398
.cfi_def_cfa_offset 5024
callq _ZNSt6chrono3_V212system_clock3nowEv
movl %eax, %eax
movq %rax, 16(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 16(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB1_1
# %bb.2: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5008(%rsp) # imm = 0x270
movabsq $429496729601, %rax # imm = 0x6400000001
movq %rax, 8(%rsp)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
addq $5016, %rsp # imm = 0x1398
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10random_intv, .Lfunc_end1-_Z10random_intv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $5088, %rsp # imm = 0x13E0
.cfi_def_cfa_offset 5104
.cfi_offset %rbx, -16
callq _ZNSt6chrono3_V212system_clock3nowEv
movl %eax, %eax
movq %rax, 80(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 80(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB2_1
# %bb.2: # %_Z10random_intv.exit
movq $624, 5072(%rsp) # imm = 0x270
movabsq $429496729601, %rax # imm = 0x6400000001
movq %rax, 24(%rsp)
leaq 80(%rsp), %rsi
leaq 24(%rsp), %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movl %ebx, 20(%rsp)
movq %rax, 72(%rsp)
movl $8, 16(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calc_kerneliPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $4, %rbx
cmpq $64, %rbx
jne .LBB2_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $5088, %rsp # imm = 0x13E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB3_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB3_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB3_4
.LBB3_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB3_11
.LBB3_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB3_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB3_11
.LBB3_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB3_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB3_8
# %bb.9: # in Loop: Header=BB3_8 Depth=1
testb %cl, %cl
jne .LBB3_8
.LBB3_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_kerneliPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calc_kerneliPii,@object # @_Z11calc_kerneliPii
.section .rodata,"a",@progbits
.globl _Z11calc_kerneliPii
.p2align 3, 0x0
_Z11calc_kerneliPii:
.quad _Z26__device_stub__calc_kerneliPii
.size _Z11calc_kerneliPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11calc_kerneliPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calc_kerneliPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calc_kerneliPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11calc_kerneliPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R0, c[0x0][0x170], R5 ; /* 0x00005c0000027a24 */
/* 0x001fe400078e0205 */
/*0060*/ IMAD R5, R5, c[0x0][0x160], R0 ; /* 0x0000580005057a24 */
/* 0x000fc600078e0200 */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11calc_kerneliPii
.globl _Z11calc_kerneliPii
.p2align 8
.type _Z11calc_kerneliPii,@function
_Z11calc_kerneliPii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mad_u64_u32 v[3:4], null, v0, s4, s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calc_kerneliPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11calc_kerneliPii, .Lfunc_end0-_Z11calc_kerneliPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calc_kerneliPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11calc_kerneliPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000425e0_00000000-6_task2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4244:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4244:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11calc_kerneliPiiiPii
.type _Z33__device_stub__Z11calc_kerneliPiiiPii, @function
_Z33__device_stub__Z11calc_kerneliPiiiPii:
.LFB4266:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11calc_kerneliPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4266:
.size _Z33__device_stub__Z11calc_kerneliPiiiPii, .-_Z33__device_stub__Z11calc_kerneliPiiiPii
.globl _Z11calc_kerneliPii
.type _Z11calc_kerneliPii, @function
_Z11calc_kerneliPii:
.LFB4267:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11calc_kerneliPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4267:
.size _Z11calc_kerneliPii, .-_Z11calc_kerneliPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11calc_kerneliPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4269:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_kerneliPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4269:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB4947:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L15:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L15
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L17:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L17
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE4947:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB4883:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L24
.L22:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L22
.cfi_endproc
.LFE4883:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB4779:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L36
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L30
movq %rsp, %r15
.L34:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L34
cmpq %r13, %rax
jb .L34
jmp .L29
.L36:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L27
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L27
.L28:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L28
.L27:
movq %rcx, %rax
shrq $32, %rax
.L29:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L37
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L29
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4779:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z10random_intv
.type _Z10random_intv, @function
_Z10random_intv:
.LFB4240:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $936, %rsp
.cfi_def_cfa_offset 5040
movq %fs:40, %rax
movq %rax, 5016(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movl %eax, %eax
movq %rax, 16(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L39:
movq 8(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 16(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L39
movq $624, 5008(%rsp)
movl $1, 8(%rsp)
movl $100, 12(%rsp)
leaq 8(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %rdi, %rdx
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq 5016(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $5032, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4240:
.size _Z10random_intv, .-_Z10random_intv
.section .rodata.str1.1
.LC1:
.string "%d "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB4241:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _Z10random_intv
movl %eax, %ebx
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L45:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $64, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %r12
leaq .LC1(%rip), %rbp
.L46:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L46
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl $8, %edx
movq (%rsp), %rsi
movl %ebx, %edi
call _Z33__device_stub__Z11calc_kerneliPiiiPii
jmp .L45
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4241:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task2.hip"
.globl _Z26__device_stub__calc_kerneliPii # -- Begin function _Z26__device_stub__calc_kerneliPii
.p2align 4, 0x90
.type _Z26__device_stub__calc_kerneliPii,@function
_Z26__device_stub__calc_kerneliPii: # @_Z26__device_stub__calc_kerneliPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
movl %edx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11calc_kerneliPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__calc_kerneliPii, .Lfunc_end0-_Z26__device_stub__calc_kerneliPii
.cfi_endproc
# -- End function
.globl _Z10random_intv # -- Begin function _Z10random_intv
.p2align 4, 0x90
.type _Z10random_intv,@function
_Z10random_intv: # @_Z10random_intv
.cfi_startproc
# %bb.0:
subq $5016, %rsp # imm = 0x1398
.cfi_def_cfa_offset 5024
callq _ZNSt6chrono3_V212system_clock3nowEv
movl %eax, %eax
movq %rax, 16(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 16(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB1_1
# %bb.2: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5008(%rsp) # imm = 0x270
movabsq $429496729601, %rax # imm = 0x6400000001
movq %rax, 8(%rsp)
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
addq $5016, %rsp # imm = 0x1398
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10random_intv, .Lfunc_end1-_Z10random_intv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $5088, %rsp # imm = 0x13E0
.cfi_def_cfa_offset 5104
.cfi_offset %rbx, -16
callq _ZNSt6chrono3_V212system_clock3nowEv
movl %eax, %eax
movq %rax, 80(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 80(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB2_1
# %bb.2: # %_Z10random_intv.exit
movq $624, 5072(%rsp) # imm = 0x270
movabsq $429496729601, %rax # imm = 0x6400000001
movq %rax, 24(%rsp)
leaq 80(%rsp), %rsi
leaq 24(%rsp), %rdi
movq %rdi, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebx
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 6(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 8(%rsp), %rax
movl %ebx, 20(%rsp)
movq %rax, 72(%rsp)
movl $8, 16(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calc_kerneliPii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $4, %rbx
cmpq $64, %rbx
jne .LBB2_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $5088, %rsp # imm = 0x13E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB3_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB3_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB3_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB3_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB3_4
.LBB3_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB3_11
.LBB3_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB3_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB3_11
.LBB3_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB3_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB3_8
# %bb.9: # in Loop: Header=BB3_8 Depth=1
testb %cl, %cl
jne .LBB3_8
.LBB3_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end3-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB4_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB4_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB4_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB4_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB4_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end4:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end4-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_kerneliPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11calc_kerneliPii,@object # @_Z11calc_kerneliPii
.section .rodata,"a",@progbits
.globl _Z11calc_kerneliPii
.p2align 3, 0x0
_Z11calc_kerneliPii:
.quad _Z26__device_stub__calc_kerneliPii
.size _Z11calc_kerneliPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11calc_kerneliPii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__calc_kerneliPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11calc_kerneliPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
We consider 1024 map, which are initially constructed with (at most)size = 4096 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations, which only include 'g': search/getting values (If did not find, return -1.), 'e': check empty, 'z': check size.
*/
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 1024;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MAX_MAP_SIZE = 4096;
const int MOD = 10000;
__device__ float cuMapGetValue(int size, int *keys, float *values, int key){
for(int i=0;i<size;++i) if(keys[i] == key) return values[i];
return -1.;
}
/*
here we assume that the operation is only 'g', which is getting values.
Currently we are only testing the case that do not need synchronization
*/
__global__ void cudaProcKernel(int n_ins, int *sizes, int *keys, float *values, int n_ops, int *input, float *ans){
int b_sz = blockDim.x, b_idx = blockIdx.x, t_idx = threadIdx.x;
__shared__ int local_keys[MAX_MAP_SIZE];
__shared__ float local_values[MAX_MAP_SIZE];
int map_size = sizes[b_idx], map_start = MAX_MAP_SIZE * b_idx, ops_start = n_ops * b_idx;
assert(map_size <= MAX_MAP_SIZE);
for(int i=t_idx ; i<map_size ; i+=b_sz){
local_keys[i] = keys[map_start + i];
local_values[i] = values[map_start + i];
}
__syncthreads();
for(int i=t_idx;i<n_ops;i+=b_sz){
ans[ops_start + i] = cuMapGetValue(map_size, local_keys, local_values, input[ops_start + i]);
}
return ;
}
// CPU version
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinput, dsizes;
def_dvec(float) dvalues;
public:
GPUMapTest(const vector<vector<int>> &keys, const vector<vector<float>> &values): N_ins((int)keys.size()){
assert((int)values.size() == N_ins);
dkeys.resize(N_ins * MAX_MAP_SIZE);
dvalues.resize(N_ins * MAX_MAP_SIZE);
dsizes.resize(N_ins);
for(int i=0;i<N_ins;++i){
gpu_copy_to(keys[i], dkeys, i*MAX_MAP_SIZE);
gpu_copy_to(values[i], dvalues, i*MAX_MAP_SIZE);
dsizes[i] = (int)keys[i].size();
}
}
void loadOps(const vector<int> &input, int n_ops){
N_ops = n_ops;
assert((int)input.size() == N_ops * N_ins);
dinput.resize(N_ops * N_ins);
gpu_copy(input, dinput);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
cudaProcKernel<<<N_ins, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops, to_ptr(dinput), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
int size = MAX_MAP_SIZE, num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
cudaEvent_t start, stop;
float cuda_time;
cudaEventCreate(&start); // creating the event 1
cudaEventCreate(&stop); // creating the event 2
/* Generating data*/
cudaEventRecord(start, 0);
vector<vector<int>> keys(num_ins);
vector<vector<float>> values(num_ins);
vector<int> input(num_ins * num_ops);
for(int i=0;i<num_ins;++i){
unordered_set<int> exist;
for(int j=0;j<size;++j){
int tmp_key = rand()%MOD;
if(!exist.count(tmp_key)){
keys[i].push_back(tmp_key);
values[i].push_back(float(rand())/RAND_MAX);
exist.insert(tmp_key);
}
}
}
generate(input.begin(), input.end(), [](){return rand()%MOD;});
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
GPUMapTest gpu_test(keys, values);
gpu_test.loadOps(input, num_ops);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14cudaProcKerneliPiS_PfiS_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0209 */
/*0050*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0060*/ BSSY B0, 0x630 ; /* 0x000005c000007945 */
/* 0x000fe60003800000 */
/*0070*/ S2R R13, SR_TID.X ; /* 0x00000000000d7919 */
/* 0x000ea40000002100 */
/*0080*/ ISETP.GE.AND P0, PT, R13, R8, PT ; /* 0x000000080d00720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 BRA 0x620 ; /* 0x0000058000000947 */
/* 0x000fea0003800000 */
/*00a0*/ I2F.U32.RP R4, c[0x0][0x0] ; /* 0x0000000000047b06 */
/* 0x000e220000209000 */
/*00b0*/ LOP3.LUT R5, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff057212 */
/* 0x000fe200078e33ff */
/*00c0*/ BSSY B1, 0x380 ; /* 0x000002b000017945 */
/* 0x000fe20003800000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003f45070 */
/*00e0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e000d */
/*00f0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fe400078e0205 */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*0140*/ IADD3 R7, RZ, -R3, RZ ; /* 0x80000003ff077210 */
/* 0x002fca0007ffe0ff */
/*0150*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R6, R3, R7, R2 ; /* 0x0000000703067227 */
/* 0x000fcc00078e0002 */
/*0170*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0180*/ IADD3 R4, -R6, RZ, RZ ; /* 0x000000ff06047210 */
/* 0x000fca0007ffe1ff */
/*0190*/ IMAD R5, R4, c[0x0][0x0], R5 ; /* 0x0000000004057a24 */
/* 0x000fca00078e0205 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R5, R5, -c[0x0][0x0], RZ ; /* 0x8000000005050a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x0], PT ; /* 0x0000000005007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff06aa12 */
/* 0x000fc800078e33ff */
/*0200*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*0220*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0230*/ @!P0 BRA 0x370 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0240*/ LEA R4, R0, R13.reuse, 0xc ; /* 0x0000000d00047211 */
/* 0x080fe200078e60ff */
/*0250*/ IMAD.SHL.U32 R12, R13, 0x4, RZ ; /* 0x000000040d0c7824 */
/* 0x000fe200078e00ff */
/*0260*/ MOV R15, R13 ; /* 0x0000000d000f7202 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*0280*/ IMAD.WIDE R2, R4, R9, c[0x0][0x178] ; /* 0x00005e0004027625 */
/* 0x000fe200078e0209 */
/*0290*/ IADD3 R10, R12, 0x4000, RZ ; /* 0x000040000c0a7810 */
/* 0x000fc60007ffe0ff */
/*02a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0209 */
/*02b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x0000a8000c1e1900 */
/*02c0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x0002e2000c1e1900 */
/*02d0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R15, R15, c[0x0][0x0], RZ ; /* 0x000000000f0f7a10 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0300*/ IMAD.WIDE R4, R9, c[0x0][0x0], R4 ; /* 0x0000000009047a25 */
/* 0x001fc800078e0204 */
/*0310*/ IMAD.WIDE R2, R9.reuse, c[0x0][0x0], R2 ; /* 0x0000000009027a25 */
/* 0x042fe200078e0202 */
/*0320*/ STS [R12], R7 ; /* 0x000000070c007388 */
/* 0x0041e80000000800 */
/*0330*/ STS [R10], R11 ; /* 0x0000000b0a007388 */
/* 0x0083e20000000800 */
/*0340*/ IMAD R12, R9.reuse, c[0x0][0x0], R12 ; /* 0x00000000090c7a24 */
/* 0x041fe400078e020c */
/*0350*/ IMAD R10, R9, c[0x0][0x0], R10 ; /* 0x00000000090a7a24 */
/* 0x002fe200078e020a */
/*0360*/ @P0 BRA 0x2b0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0380*/ @!P1 BRA 0x620 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.SHL.U32 R14, R15, 0x4, RZ ; /* 0x000000040f0e7824 */
/* 0x000fca00078e00ff */
/*03a0*/ IADD3 R12, R14, 0x4000, RZ ; /* 0x000040000e0c7810 */
/* 0x000fe40007ffe0ff */
/*03b0*/ LEA R22, R0, R15, 0xc ; /* 0x0000000f00167211 */
/* 0x000fca00078e60ff */
/*03c0*/ IMAD.WIDE R20, R22, R9, c[0x0][0x170] ; /* 0x00005c0016147625 */
/* 0x000fc800078e0209 */
/*03d0*/ IMAD.WIDE R22, R22, R9, c[0x0][0x178] ; /* 0x00005e0016167625 */
/* 0x000fc800078e0209 */
/*03e0*/ IMAD.WIDE R10, R9.reuse, c[0x0][0x0], R20 ; /* 0x00000000090a7a25 */
/* 0x040fe400078e0214 */
/*03f0*/ LDG.E R21, [R20.64] ; /* 0x0000000414157981 */
/* 0x0000a4000c1e1900 */
/*0400*/ IMAD.WIDE R6, R9.reuse, c[0x0][0x0], R22 ; /* 0x0000000009067a25 */
/* 0x040fe400078e0216 */
/*0410*/ LDG.E R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000ee4000c1e1900 */
/*0420*/ IMAD.WIDE R2, R9.reuse, c[0x0][0x0], R10 ; /* 0x0000000009027a25 */
/* 0x040fe400078e020a */
/*0430*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000324000c1e1900 */
/*0440*/ IMAD.WIDE R4, R9, c[0x0][0x0], R6 ; /* 0x0000000009047a25 */
/* 0x000fc400078e0206 */
/*0450*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000b24000c1e1900 */
/*0460*/ IMAD.WIDE R16, R9.reuse, c[0x0][0x0], R2 ; /* 0x0000000009107a25 */
/* 0x040fe400078e0202 */
/*0470*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000124000c1e1900 */
/*0480*/ IMAD.WIDE R18, R9.reuse, c[0x0][0x0], R4 ; /* 0x0000000009127a25 */
/* 0x040fe400078e0204 */
/*0490*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000328000c1e1900 */
/*04a0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f22000c1e1900 */
/*04c0*/ IMAD R20, R9, c[0x0][0x0], R14 ; /* 0x0000000009147a24 */
/* 0x001fc400078e020e */
/*04d0*/ IMAD R24, R9.reuse, c[0x0][0x0], R12 ; /* 0x0000000009187a24 */
/* 0x040fe400078e020c */
/*04e0*/ IMAD R11, R9.reuse, c[0x0][0x0], R20 ; /* 0x00000000090b7a24 */
/* 0x042fe400078e0214 */
/*04f0*/ IMAD R7, R9.reuse, c[0x0][0x0], R24 ; /* 0x0000000009077a24 */
/* 0x060fe400078e0218 */
/*0500*/ IMAD R3, R9.reuse, c[0x0][0x0], R11 ; /* 0x0000000009037a24 */
/* 0x040fe400078e020b */
/*0510*/ IMAD R5, R9, c[0x0][0x0], R7 ; /* 0x0000000009057a24 */
/* 0x000fe200078e0207 */
/*0520*/ STS [R14], R21 ; /* 0x000000150e007388 */
/* 0x0041e80000000800 */
/*0530*/ STS [R12], R23 ; /* 0x000000170c007388 */
/* 0x0083e20000000800 */
/*0540*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff0e7624 */
/* 0x001fc600078e00ff */
/*0550*/ STS [R20], R10 ; /* 0x0000000a14007388 */
/* 0x0101e20000000800 */
/*0560*/ IMAD R15, R14, 0x2, R15 ; /* 0x000000020e0f7824 */
/* 0x000fc600078e020f */
/*0570*/ STS [R24], R6 ; /* 0x0000000618007388 */
/* 0x0001e20000000800 */
/*0580*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x002fc60000000f00 */
/*0590*/ STS [R11], R2 ; /* 0x000000020b007388 */
/* 0x0001e20000000800 */
/*05a0*/ LEA R15, R12, R15, 0x1 ; /* 0x0000000f0c0f7211 */
/* 0x000fc600078e08ff */
/*05b0*/ STS [R7], R4 ; /* 0x0000000407007388 */
/* 0x0001e80000000800 */
/*05c0*/ STS [R3], R16 ; /* 0x0000001003007388 */
/* 0x0001e80000000800 */
/*05d0*/ STS [R5], R18 ; /* 0x0000001205007388 */
/* 0x0001e20000000800 */
/*05e0*/ ISETP.GE.AND P0, PT, R15, R8, PT ; /* 0x000000080f00720c */
/* 0x000fe20003f06270 */
/*05f0*/ IMAD R14, R9, c[0x0][0x0], R3 ; /* 0x00000000090e7a24 */
/* 0x000fc400078e0203 */
/*0600*/ IMAD R12, R9, c[0x0][0x0], R5 ; /* 0x00000000090c7a24 */
/* 0x000fd400078e0205 */
/*0610*/ @!P0 BRA 0x3b0 ; /* 0xfffffd9000008947 */
/* 0x001fea000383ffff */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0640*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fda0003f06270 */
/*0650*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*0670*/ @P0 BRA 0x9e0 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*0680*/ I2F.U32.RP R5, c[0x0][0x0] ; /* 0x0000000000057b06 */
/* 0x000e220000209000 */
/*0690*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*06a0*/ LOP3.LUT R4, RZ, R13, RZ, 0x33, !PT ; /* 0x0000000dff047212 */
/* 0x000fe200078e33ff */
/*06b0*/ BSSY B0, 0x8c0 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*06c0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fc80003f45070 */
/*06d0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*06e0*/ IADD3 R6, R5, 0xffffffe, RZ ; /* 0x0ffffffe05067810 */
/* 0x001fcc0007ffe0ff */
/*06f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R6 ; /* 0x0000000600037305 */
/* 0x000e24000021f000 */
/*0700*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x001fc800078e0a03 */
/*0710*/ IMAD R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a24 */
/* 0x000fc800078e02ff */
/*0720*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0730*/ IADD3 R2, R4, c[0x0][0x180], RZ ; /* 0x0000600004027a10 */
/* 0x000fca0007ffe0ff */
/*0740*/ IMAD.HI.U32 R3, R3, R2, RZ ; /* 0x0000000203037227 */
/* 0x000fc800078e00ff */
/*0750*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0760*/ IMAD R2, R5, c[0x0][0x0], R2 ; /* 0x0000000005027a24 */
/* 0x000fca00078e0202 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f06070 */
/*0780*/ @P0 IADD3 R2, R2, -c[0x0][0x0], RZ ; /* 0x8000000002020a10 */
/* 0x000fe40007ffe0ff */
/*0790*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*07a0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x0], PT ; /* 0x0000000002007a0c */
/* 0x000fda0003f26070 */
/*07b0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*07c0*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff03aa12 */
/* 0x000fc800078e33ff */
/*07d0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*07e0*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*07f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0800*/ @!P0 BRA 0x8b0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD R6, R0, c[0x0][0x180], R13 ; /* 0x0000600000067a24 */
/* 0x000fe200078e020d */
/*0820*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fe400078e00ff */
/*0840*/ IMAD.WIDE R2, R6, R9, c[0x0][0x190] ; /* 0x0000640006027625 */
/* 0x000fc800078e0209 */
/*0850*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0860*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0870*/ IADD3 R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0880*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0890*/ IMAD.WIDE R2, R9, c[0x0][0x0], R2 ; /* 0x0000000009027a25 */
/* 0x001fd800078e0202 */
/*08a0*/ @P0 BRA 0x850 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*08d0*/ MOV R15, 0xbf800000 ; /* 0xbf800000000f7802 */
/* 0x000fe40000000f00 */
/*08e0*/ IMAD R2, R0, c[0x0][0x180], R13 ; /* 0x0000600000027a24 */
/* 0x001fe200078e020d */
/*08f0*/ MOV R12, c[0x0][0x0] ; /* 0x00000000000c7a02 */
/* 0x000fe20000000f00 */
/*0900*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff087624 */
/* 0x000fe400078e00ff */
/*0910*/ IMAD.WIDE R2, R2, R9, c[0x0][0x190] ; /* 0x0000640002027625 */
/* 0x000fc800078e0209 */
/*0920*/ IMAD R13, R8, 0x2, R13 ; /* 0x00000002080d7824 */
/* 0x000fe200078e020d */
/*0930*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0940*/ IMAD.WIDE R4, R9, c[0x0][0x0], R2 ; /* 0x0000000009047a25 */
/* 0x000fc600078e0202 */
/*0950*/ LEA R13, R12, R13, 0x1 ; /* 0x0000000d0c0d7211 */
/* 0x000fe400078e08ff */
/*0960*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e2000c101904 */
/*0970*/ IMAD.WIDE R6, R9, c[0x0][0x0], R4 ; /* 0x0000000009067a25 */
/* 0x000fe200078e0204 */
/*0980*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fc80003f06270 */
/*0990*/ STG.E [R6.64], R15 ; /* 0x0000000f06007986 */
/* 0x0001e2000c101904 */
/*09a0*/ IMAD.WIDE R10, R9, c[0x0][0x0], R6 ; /* 0x00000000090a7a25 */
/* 0x000fca00078e0206 */
/*09b0*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001e6000c101904 */
/*09c0*/ @!P0 BRA 0x8e0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x002fe400078e00ff */
/*09f0*/ IMAD R4, R0, c[0x0][0x180], R13 ; /* 0x0000600000047a24 */
/* 0x000fc800078e020d */
/*0a00*/ IMAD.WIDE R2, R4, R3, c[0x0][0x188] ; /* 0x0000620004027625 */
/* 0x000fcc00078e0203 */
/*0a10*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001162000c1e1900 */
/*0a20*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0a30*/ BSSY B0, 0xb00 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0a40*/ SHF.R.S32.HI R7, RZ, 0x1f, R4 ; /* 0x0000001fff077819 */
/* 0x000fd00000011404 */
/*0a50*/ IMAD.SHL.U32 R6, R5, 0x4, RZ ; /* 0x0000000405067824 */
/* 0x000fca00078e00ff */
/*0a60*/ LDS R2, [R6] ; /* 0x0000000006027984 */
/* 0x001e240000000800 */
/*0a70*/ ISETP.NE.AND P0, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x021fda0003f05270 */
/*0a80*/ @!P0 BRA 0xae0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0a90*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0aa0*/ ISETP.GE.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f06270 */
/*0ab0*/ @!P0 BRA 0xa50 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0ac0*/ MOV R5, 0xbf800000 ; /* 0xbf80000000057802 */
/* 0x000fe20000000f00 */
/*0ad0*/ BRA 0xaf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LDS R5, [R6+0x4000] ; /* 0x0040000006057984 */
/* 0x0000640000000800 */
/*0af0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b00*/ LEA R2, P0, R4.reuse, c[0x0][0x190], 0x2 ; /* 0x0000640004027a11 */
/* 0x040fe400078010ff */
/*0b10*/ IADD3 R13, R13, c[0x0][0x0], RZ ; /* 0x000000000d0d7a10 */
/* 0x000fe40007ffe0ff */
/*0b20*/ LEA.HI.X R3, R4, c[0x0][0x194], R7, 0x2, P0 ; /* 0x0000650004037a11 */
/* 0x000fe400000f1407 */
/*0b30*/ ISETP.GE.AND P0, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fc60003f06270 */
/*0b40*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0023f4000c101904 */
/*0b50*/ @!P0 BRA 0x9e0 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0b60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b70*/ BRA 0xb70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
We consider 1024 map, which are initially constructed with (at most)size = 4096 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations, which only include 'g': search/getting values (If did not find, return -1.), 'e': check empty, 'z': check size.
*/
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 1024;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MAX_MAP_SIZE = 4096;
const int MOD = 10000;
__device__ float cuMapGetValue(int size, int *keys, float *values, int key){
for(int i=0;i<size;++i) if(keys[i] == key) return values[i];
return -1.;
}
/*
here we assume that the operation is only 'g', which is getting values.
Currently we are only testing the case that do not need synchronization
*/
__global__ void cudaProcKernel(int n_ins, int *sizes, int *keys, float *values, int n_ops, int *input, float *ans){
int b_sz = blockDim.x, b_idx = blockIdx.x, t_idx = threadIdx.x;
__shared__ int local_keys[MAX_MAP_SIZE];
__shared__ float local_values[MAX_MAP_SIZE];
int map_size = sizes[b_idx], map_start = MAX_MAP_SIZE * b_idx, ops_start = n_ops * b_idx;
assert(map_size <= MAX_MAP_SIZE);
for(int i=t_idx ; i<map_size ; i+=b_sz){
local_keys[i] = keys[map_start + i];
local_values[i] = values[map_start + i];
}
__syncthreads();
for(int i=t_idx;i<n_ops;i+=b_sz){
ans[ops_start + i] = cuMapGetValue(map_size, local_keys, local_values, input[ops_start + i]);
}
return ;
}
// CPU version
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinput, dsizes;
def_dvec(float) dvalues;
public:
GPUMapTest(const vector<vector<int>> &keys, const vector<vector<float>> &values): N_ins((int)keys.size()){
assert((int)values.size() == N_ins);
dkeys.resize(N_ins * MAX_MAP_SIZE);
dvalues.resize(N_ins * MAX_MAP_SIZE);
dsizes.resize(N_ins);
for(int i=0;i<N_ins;++i){
gpu_copy_to(keys[i], dkeys, i*MAX_MAP_SIZE);
gpu_copy_to(values[i], dvalues, i*MAX_MAP_SIZE);
dsizes[i] = (int)keys[i].size();
}
}
void loadOps(const vector<int> &input, int n_ops){
N_ops = n_ops;
assert((int)input.size() == N_ops * N_ins);
dinput.resize(N_ops * N_ins);
gpu_copy(input, dinput);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
cudaProcKernel<<<N_ins, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops, to_ptr(dinput), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
int size = MAX_MAP_SIZE, num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
cudaEvent_t start, stop;
float cuda_time;
cudaEventCreate(&start); // creating the event 1
cudaEventCreate(&stop); // creating the event 2
/* Generating data*/
cudaEventRecord(start, 0);
vector<vector<int>> keys(num_ins);
vector<vector<float>> values(num_ins);
vector<int> input(num_ins * num_ops);
for(int i=0;i<num_ins;++i){
unordered_set<int> exist;
for(int j=0;j<size;++j){
int tmp_key = rand()%MOD;
if(!exist.count(tmp_key)){
keys[i].push_back(tmp_key);
values[i].push_back(float(rand())/RAND_MAX);
exist.insert(tmp_key);
}
}
}
generate(input.begin(), input.end(), [](){return rand()%MOD;});
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
GPUMapTest gpu_test(keys, values);
gpu_test.loadOps(input, num_ops);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
cudaEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
cudaEventRecord(stop, 0); // Stop time measuring
cudaEventSynchronize(stop);
cudaEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} | /*
We consider 1024 map, which are initially constructed with (at most)size = 4096 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations, which only include 'g': search/getting values (If did not find, return -1.), 'e': check empty, 'z': check size.
*/
#include <hip/hip_runtime.h>
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 1024;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MAX_MAP_SIZE = 4096;
const int MOD = 10000;
__device__ float cuMapGetValue(int size, int *keys, float *values, int key){
for(int i=0;i<size;++i) if(keys[i] == key) return values[i];
return -1.;
}
/*
here we assume that the operation is only 'g', which is getting values.
Currently we are only testing the case that do not need synchronization
*/
__global__ void cudaProcKernel(int n_ins, int *sizes, int *keys, float *values, int n_ops, int *input, float *ans){
int b_sz = blockDim.x, b_idx = blockIdx.x, t_idx = threadIdx.x;
__shared__ int local_keys[MAX_MAP_SIZE];
__shared__ float local_values[MAX_MAP_SIZE];
int map_size = sizes[b_idx], map_start = MAX_MAP_SIZE * b_idx, ops_start = n_ops * b_idx;
assert(map_size <= MAX_MAP_SIZE);
for(int i=t_idx ; i<map_size ; i+=b_sz){
local_keys[i] = keys[map_start + i];
local_values[i] = values[map_start + i];
}
__syncthreads();
for(int i=t_idx;i<n_ops;i+=b_sz){
ans[ops_start + i] = cuMapGetValue(map_size, local_keys, local_values, input[ops_start + i]);
}
return ;
}
// CPU version
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinput, dsizes;
def_dvec(float) dvalues;
public:
GPUMapTest(const vector<vector<int>> &keys, const vector<vector<float>> &values): N_ins((int)keys.size()){
assert((int)values.size() == N_ins);
dkeys.resize(N_ins * MAX_MAP_SIZE);
dvalues.resize(N_ins * MAX_MAP_SIZE);
dsizes.resize(N_ins);
for(int i=0;i<N_ins;++i){
gpu_copy_to(keys[i], dkeys, i*MAX_MAP_SIZE);
gpu_copy_to(values[i], dvalues, i*MAX_MAP_SIZE);
dsizes[i] = (int)keys[i].size();
}
}
void loadOps(const vector<int> &input, int n_ops){
N_ops = n_ops;
assert((int)input.size() == N_ops * N_ins);
dinput.resize(N_ops * N_ins);
gpu_copy(input, dinput);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
cudaProcKernel<<<N_ins, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops, to_ptr(dinput), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
int size = MAX_MAP_SIZE, num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
hipEvent_t start, stop;
float cuda_time;
hipEventCreate(&start); // creating the event 1
hipEventCreate(&stop); // creating the event 2
/* Generating data*/
hipEventRecord(start, 0);
vector<vector<int>> keys(num_ins);
vector<vector<float>> values(num_ins);
vector<int> input(num_ins * num_ops);
for(int i=0;i<num_ins;++i){
unordered_set<int> exist;
for(int j=0;j<size;++j){
int tmp_key = rand()%MOD;
if(!exist.count(tmp_key)){
keys[i].push_back(tmp_key);
values[i].push_back(float(rand())/RAND_MAX);
exist.insert(tmp_key);
}
}
}
generate(input.begin(), input.end(), [](){return rand()%MOD;});
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
GPUMapTest gpu_test(keys, values);
gpu_test.loadOps(input, num_ops);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
We consider 1024 map, which are initially constructed with (at most)size = 4096 key, value pairs, for which keys are integers and values are float point numbers.
Then each of them processes 262,144 operations, which only include 'g': search/getting values (If did not find, return -1.), 'e': check empty, 'z': check size.
*/
#include <hip/hip_runtime.h>
#include <bits/stdc++.h>
#include <cassert>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#define to_ptr(x) thrust::raw_pointer_cast(&x[0])
#define gpu_copy(x, y) thrust::copy((x).begin(), (x).end(), (y).begin())
#define gpu_copy_to(x, y, pos) thrust::copy((x).begin(), (x).end(), (y).begin() + (pos))
#define def_dvec(t) thrust::device_vector<t>
using namespace std;
const int BLOCK_SIZE = 1024;
const int NUM_INSTANCE = 1024;
const int NUM_OPERATION = 262144;
const int MAX_MAP_SIZE = 4096;
const int MOD = 10000;
__device__ float cuMapGetValue(int size, int *keys, float *values, int key){
for(int i=0;i<size;++i) if(keys[i] == key) return values[i];
return -1.;
}
/*
here we assume that the operation is only 'g', which is getting values.
Currently we are only testing the case that do not need synchronization
*/
__global__ void cudaProcKernel(int n_ins, int *sizes, int *keys, float *values, int n_ops, int *input, float *ans){
int b_sz = blockDim.x, b_idx = blockIdx.x, t_idx = threadIdx.x;
__shared__ int local_keys[MAX_MAP_SIZE];
__shared__ float local_values[MAX_MAP_SIZE];
int map_size = sizes[b_idx], map_start = MAX_MAP_SIZE * b_idx, ops_start = n_ops * b_idx;
assert(map_size <= MAX_MAP_SIZE);
for(int i=t_idx ; i<map_size ; i+=b_sz){
local_keys[i] = keys[map_start + i];
local_values[i] = values[map_start + i];
}
__syncthreads();
for(int i=t_idx;i<n_ops;i+=b_sz){
ans[ops_start + i] = cuMapGetValue(map_size, local_keys, local_values, input[ops_start + i]);
}
return ;
}
// CPU version
class GPUMapTest{
int N_ins, N_ops;
def_dvec(int) dkeys, dinput, dsizes;
def_dvec(float) dvalues;
public:
GPUMapTest(const vector<vector<int>> &keys, const vector<vector<float>> &values): N_ins((int)keys.size()){
assert((int)values.size() == N_ins);
dkeys.resize(N_ins * MAX_MAP_SIZE);
dvalues.resize(N_ins * MAX_MAP_SIZE);
dsizes.resize(N_ins);
for(int i=0;i<N_ins;++i){
gpu_copy_to(keys[i], dkeys, i*MAX_MAP_SIZE);
gpu_copy_to(values[i], dvalues, i*MAX_MAP_SIZE);
dsizes[i] = (int)keys[i].size();
}
}
void loadOps(const vector<int> &input, int n_ops){
N_ops = n_ops;
assert((int)input.size() == N_ops * N_ins);
dinput.resize(N_ops * N_ins);
gpu_copy(input, dinput);
}
void procOps(vector<float> &ans){
ans.resize(N_ins * N_ops);
def_dvec(float) dans(N_ins * N_ops);
cudaProcKernel<<<N_ins, BLOCK_SIZE>>>(N_ins, to_ptr(dsizes), to_ptr(dkeys), to_ptr(dvalues), N_ops, to_ptr(dinput), to_ptr(dans));
gpu_copy(dans, ans);
return ;
}
};
int main(int argc, char *argv[]){
int size = MAX_MAP_SIZE, num_ins = NUM_INSTANCE, num_ops = NUM_OPERATION;
if(argc > 1) num_ins = stoi(argv[1]);
if(argc > 2) num_ops = stoi(argv[2]);
/* using cudaEvent to evaluate time */
hipEvent_t start, stop;
float cuda_time;
hipEventCreate(&start); // creating the event 1
hipEventCreate(&stop); // creating the event 2
/* Generating data*/
hipEventRecord(start, 0);
vector<vector<int>> keys(num_ins);
vector<vector<float>> values(num_ins);
vector<int> input(num_ins * num_ops);
for(int i=0;i<num_ins;++i){
unordered_set<int> exist;
for(int j=0;j<size;++j){
int tmp_key = rand()%MOD;
if(!exist.count(tmp_key)){
keys[i].push_back(tmp_key);
values[i].push_back(float(rand())/RAND_MAX);
exist.insert(tmp_key);
}
}
}
generate(input.begin(), input.end(), [](){return rand()%MOD;});
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for generating random data is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
GPUMapTest gpu_test(keys, values);
gpu_test.loadOps(input, num_ops);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for preparing maps is: "<<cuda_time/1000<<"s"<<endl;
hipEventRecord(start, 0);
vector<float> ans;
gpu_test.procOps(ans);
hipEventRecord(stop, 0); // Stop time measuring
hipEventSynchronize(stop);
hipEventElapsedTime(&cuda_time, start, stop); // Saving the time measured
cout<<"Time Usage for processing operations is: "<<cuda_time/1000<<"s"<<endl;
cout<<"Showing GPU code answers:"<<endl;
for(int i=0;i<num_ins*num_ops ; i+=num_ins*num_ops/25 + 1) cout<<ans[i]<<' ';
cout << endl;
cout<<"DONE!"<<endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14cudaProcKerneliPiS_PfiS_S0_
.globl _Z14cudaProcKerneliPiS_PfiS_S0_
.p2align 8
.type _Z14cudaProcKerneliPiS_PfiS_S0_,@function
_Z14cudaProcKerneliPiS_PfiS_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s8, s15
s_ashr_i32 s9, s15, 31
s_mov_b32 s10, exec_lo
s_lshl_b64 s[6:7], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_load_b32 s9, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x10
v_lshl_or_b32 v1, s8, 12, v0
v_dual_mov_b32 v4, v0 :: v_dual_lshlrev_b32 v3, 2, v0
s_mov_b32 s11, 0
s_lshl_b32 s12, s3, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s13, s11
v_lshlrev_b64 v[1:2], 2, v[1:2]
.p2align 6
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
v_add_nc_u32_e32 v4, s3, v4
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
v_add_co_u32 v1, vcc_lo, v1, s12
v_cmp_le_i32_e64 s2, s9, v4
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s13, s2, s13
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v3, v5, v6 offset1:64
v_add_nc_u32_e32 v3, s12, v3
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s10
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s2, v0
s_cbranch_execz .LBB0_15
s_load_b128 s[4:7], s[0:1], 0x28
s_cmp_gt_i32 s9, 0
s_mul_i32 s8, s8, s2
s_cselect_b32 s1, -1, 0
s_mov_b32 s10, 0
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_6:
v_add_nc_u32_e32 v0, s3, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s7, v2, s0
v_cmp_le_i32_e32 vcc_lo, s2, v0
global_store_b32 v[1:2], v4, off
s_or_b32 s10, vcc_lo, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_15
.LBB0_7:
v_add_nc_u32_e32 v1, s8, v0
s_and_not1_b32 vcc_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_cbranch_vccnz .LBB0_14
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s13, 0
s_mov_b32 s0, 0
s_mov_b32 s12, s9
global_load_b32 v3, v[3:4], off
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s18, exec_lo, s15
v_dual_mov_b32 v4, s17 :: v_dual_mov_b32 v5, s13
s_or_b32 s0, s18, s0
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s13, s14, exec_lo
s_or_b32 s11, s11, s13
s_mov_b32 s13, s16
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_12
.LBB0_10:
v_mov_b32_e32 v4, s13
s_or_b32 s14, s14, exec_lo
s_or_b32 s15, s15, exec_lo
s_mov_b32 s18, exec_lo
ds_load_b32 v4, v4
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_ne_u32_e64 v4, v3
s_cbranch_execz .LBB0_9
s_add_i32 s12, s12, -1
s_add_i32 s16, s13, 4
s_cmp_eq_u32 s12, 0
s_mov_b32 s17, -1.0
s_cselect_b32 s19, -1, 0
s_and_not1_b32 s15, s15, exec_lo
s_and_b32 s19, s19, exec_lo
s_and_not1_b32 s14, s14, exec_lo
s_or_b32 s15, s15, s19
s_branch .LBB0_9
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
ds_load_b32 v4, v5 offset:16384
s_branch .LBB0_5
.LBB0_14:
v_mov_b32_e32 v4, -1.0
s_branch .LBB0_6
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14cudaProcKerneliPiS_PfiS_S0_
.amdhsa_group_segment_fixed_size 32768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14cudaProcKerneliPiS_PfiS_S0_, .Lfunc_end0-_Z14cudaProcKerneliPiS_PfiS_S0_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
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.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
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amdhsa.version:
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...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <cuda_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o linear_regression_ques_a linear_regression_ques_a.cu -lm
*
* To run:
* ./linear_regression_ques_a
*
*****************************************************************************/
typedef struct point_t {
double a;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000;
//actual data
point_t data[] = {
{77.98,130.36},{79.09,148.43},{72.34,123.95},{65.93,116.99},
{77.57,132.91},{79.38,148.35},{85.45,141.04},{68.12,112.26},
{83.96,140.95},{65.32,107.96},{73.70,144.54},{68.51,110.97},
{23.70,43.30},{32.60,75.51},{97.45,167.12},{24.44,62.51},
{35.26,73.73},{42.05,87.45},{80.60,154.01},{42.19,78.14},
{11.57,36.87},{89.39,138.89},{79.04,151.16},{75.37,140.63},
{16.37,48.59},{85.73,138.70},{19.40,60.34},{ 1.87,30.33},
{64.62,100.67},{82.50,149.78},{69.86,126.38},{76.07,111.45},
{75.30,138.59},{ 8.55,34.53},{76.84,150.23},{88.69,149.26},
{69.72,143.26},{37.04,75.54},{84.39,168.66},{42.23,83.86},
{ 9.89,36.55},{74.04,123.28},{75.72,123.75},{19.76,61.01},
{ 7.21,24.85},{47.72,87.46},{46.74,99.94},{87.50,141.68},
{29.77,84.23},{58.59,112.53},{56.40,110.57},{72.64,133.51},
{18.77,73.65},{50.47,92.54},{17.67,50.48},{22.96,50.27},
{93.80,157.23},{28.78,62.97},{70.77,137.07},{18.46,48.76},
{78.73,147.81},{28.64,64.04},{15.87,71.24},{20.60,58.87},
{24.04,71.30},{29.82,64.70},{74.92,119.91},{57.65,128.03},
{ 8.60,17.53},{64.15,114.03},{54.12,111.55},{46.26,86.85},
{69.34,128.76},{62.32,123.58},{35.54,91.65},{63.94,108.18},
{ 8.79,26.44},{94.79,158.97},{69.39,127.07},{54.95,85.68},
{80.80,123.50},{ 5.04,28.59},{60.70,122.70},{64.93,116.81},
{75.21,140.82},{94.73,158.77},{70.97,119.67},{18.60,49.57},
{35.65,90.07},{51.29,106.23},{99.39,164.53},{68.69,128.54},
{43.27,97.46},{54.00,103.11},{98.43,155.75},{85.94,149.47},
{77.76,130.00},{ 9.66,21.48},{65.38,113.14},{86.03,135.26},
{52.91,109.09},{40.51,88.36},{96.33,178.71},{65.01,112.30},
{22.21,63.56},{92.23,155.97},{ 5.44,50.68},{47.24,91.65},
{70.34,134.08},{91.42,134.44},{ 6.25,45.93},{30.84,78.59},
{59.59,93.17},{59.66,116.00},{56.91,124.37},{26.40,80.75},
{41.75,104.14},{92.10,151.34},{24.18,73.47},{71.32,139.54},
{94.73,165.99},{54.05,102.18},{58.35,108.14},{54.49,84.38},
{60.06,111.97},{72.99,135.35},{74.88,134.12},{55.44,112.28},
{99.26,172.77},{15.34,42.67},{53.88,93.18},{35.90,73.13},
{79.41,137.27},{52.71,100.10},{14.90,64.25},{77.27,143.40},
{94.85,161.63},{27.95,67.70},{22.65,69.15},{19.92,75.99},
{21.63,58.86},{63.89,125.04},{31.18,68.30},{85.21,142.92},
{ 6.99,41.71},{65.13,123.67},{43.22,91.87},{14.54,51.08},
{71.03,120.54},{85.32,139.23},{ 1.65,15.42},{68.44,114.18},
{24.89,43.34},{44.09,71.91},{52.78,100.42},{39.00,104.71},
{30.45,68.40},{93.79,152.03},{43.67,82.38},{60.03,110.47},
{72.81,133.44},{ 3.36,39.56},{23.63,51.23},{ 2.24,35.53},
{69.37,120.48},{21.85,53.01},{99.40,148.97},{48.26,95.05},
{19.43,47.20},{18.54,58.80},{59.71,130.46},{83.76,146.14},
{61.24,108.80},{59.79,118.94},{32.18,74.26},{69.93,107.25},
{18.80,65.71},{77.62,135.24},{36.38,80.62},{22.11,61.87},
{87.67,159.19},{18.27,42.13},{59.46,113.12},{27.86,76.32},
{44.58,81.58},{51.48,91.53},{34.66,68.59},{24.31,60.65},
{77.44,155.88},{89.86,165.12},{14.31,40.08},{ 8.99,63.09},
{62.05,109.52},{99.16,166.58},{16.23,62.72},{21.00,57.58},
{64.70,110.52},{36.50,70.82},{13.60,32.41},{72.48,132.93},
{16.55,48.30},{72.33,146.17},{74.80,144.98},{86.52,145.51},
{18.74,53.20},{42.46,84.17},{34.14,83.02},{48.40,105.26},
{94.58,164.10},{54.73,97.10},{15.98,54.69},{41.41,82.26},
{54.70,107.38},{78.82,140.70},{18.53,70.95},{ 7.02,48.19},
{36.99,81.18},{11.80,22.97},{89.96,163.81},{18.02,55.52},
{70.09,123.95},{84.84,138.33},{70.15,139.19},{17.89,44.33},
{91.76,146.52},{35.98,77.33},{71.59,112.49},{44.29,103.12},
{ 6.47,33.93},{ 2.33,39.95},{64.72,113.89},{48.82,88.91},
{71.34,127.29},{99.75,165.06},{51.38,91.86},{76.72,118.85},
{ 9.09,53.80},{44.40,95.91},{55.88,112.71},{27.00,65.93},
{43.09,89.10},{15.77,58.36},{ 6.66,52.56},{ 0.72,15.70},
{ 9.10,32.67},{73.31,146.06},{80.63,145.39},{89.34,151.93},
{70.99,109.10},{18.48,40.16},{13.53,60.15},{ 3.62,35.30},
{ 0.67,22.84},{10.18,34.71},{62.39,115.13},{16.83,50.51},
{ 4.95,34.83},{17.56,65.63},{20.46,71.24},{ 3.24,22.13},
{62.62,108.31},{83.41,159.53},{13.94,62.74},{39.53,75.26},
{70.08,127.75},{96.18,154.40},{ 4.70,51.92},{ 4.83,34.24},
{86.68,155.95},{39.14,95.10},{54.83,101.35},{45.90,113.05},
{83.84,164.08},{91.32,141.46},{99.38,151.63},{57.80,88.41},
{15.70,64.96},{50.13,86.85},{ 5.49,49.01},{46.72,94.05},
{89.37,154.06},{30.59,63.82},{71.14,121.90},{17.65,61.37},
{17.22,71.53},{63.80,131.31},{48.19,93.75},{46.52,99.40},
{93.86,171.03},{23.64,68.51},{89.26,157.22},{49.78,104.78},
{85.35,137.00},{72.36,124.10},{82.00,138.39},{13.84,48.03},
{89.78,154.55},{90.40,143.48},{ 3.06,22.06},{51.56,99.83},
{61.82,112.08},{38.70,87.78},{31.97,74.39},{99.69,176.25},
{78.62,152.64},{52.43,102.53},{92.86,145.69},{81.64,144.55},
{76.06,122.34},{ 4.95,32.38},{87.52,171.59},{95.04,149.43},
{60.28,110.39},{82.25,169.12},{22.81,57.02},{ 6.91,40.13},
{53.36,106.12},{96.26,156.75},{15.49,45.17},{36.79,83.03},
{82.18,147.65},{31.99,74.58},{44.35,86.62},{35.53,75.38},
{41.16,96.88},{98.23,160.31},{48.38,84.37},{86.01,161.33},
{ 7.43,31.88},{24.37,44.83},{11.01,41.83},{16.86,44.57},
{13.72,32.74},{61.53,119.79},{48.45,82.98},{34.80,74.74},
{73.82,131.76},{45.49,87.37},{44.29,99.77},{85.94,167.42},
{38.49,75.27},{30.29,70.78},{68.66,114.49},{27.31,67.54},
{67.58,121.97},{66.72,123.44},{61.54,95.46},{43.92,85.74},
{43.87,109.10},{56.28,107.24},{86.68,137.08},{ 0.81,20.16},
{18.28,49.52},{51.27,112.06},{43.31,65.28},{29.32,52.29},
{98.77,169.88},{17.18,52.57},{76.85,145.82},{82.70,135.08},
{83.64,131.25},{12.33,38.01},{76.06,153.75},{83.89,135.10},
{29.57,65.30},{47.52,108.75},{ 8.76,39.70},{20.95,67.72},
{ 5.41,42.36},{61.13,90.13},{ 3.08,14.51},{38.82,95.19},
{17.75,66.51},{ 1.83,29.54},{60.84,110.57},{44.30,95.26},
{58.12,115.47},{43.36,84.41},{74.23,122.77},{46.90,93.52},
{95.44,148.73},{ 7.39,45.61},{52.81,104.35},{37.16,60.15},
{ 9.81,46.92},{15.75,52.64},{ 7.55,55.70},{80.65,123.61},
{70.31,144.36},{56.05,118.04},{41.85,90.23},{48.33,100.55},
{61.36,129.79},{30.99,63.92},{97.88,165.01},{88.06,163.98},
{ 3.94,42.78},{51.10,94.74},{25.92,56.47},{32.24,56.10},
{56.42,105.70},{35.94,65.57},{88.44,140.75},{18.42,50.02},
{92.97,165.67},{93.14,152.64},{84.46,142.58},{59.79,101.62},
{47.70,93.97},{85.61,150.83},{75.95,125.79},{68.98,124.25},
{12.19,46.92},{64.71,111.41},{65.35,117.94},{56.03,117.75},
{33.65,80.22},{99.83,154.54},{42.11,91.90},{29.26,71.92},
{12.45,42.87},{31.86,58.42},{67.32,131.56},{62.65,119.19},
{21.02,60.23},{36.42,63.61},{21.46,68.57},{87.10,154.60},
{54.01,111.59},{79.76,131.26},{20.26,40.04},{92.15,144.67},
{18.69,56.39},{77.38,133.16},{34.32,90.42},{66.53,107.16},
{32.44,72.36},{57.18,99.61},{17.61,67.09},{19.97,67.47},
{60.67,108.28},{46.88,87.00},{97.25,170.60},{80.52,149.02},
{37.36,79.89},{94.27,169.69},{80.94,147.55},{30.75,71.59},
{66.58,128.72},{63.16,95.21},{ 4.90,18.07},{50.47,91.47},
{73.25,120.81},{57.26,113.72},{98.04,168.70},{ 6.88,43.58},
{52.69,84.44},{86.30,154.21},{63.61,125.07},{44.90,77.52},
{13.76,44.88},{88.55,157.17},{39.41,85.60},{56.27,99.27},
{93.04,146.91},{ 1.71,16.08},{84.43,171.48},{90.37,147.40},
{32.91,74.15},{96.28,183.66},{48.10,93.15},{86.94,140.01},
{20.19,46.78},{54.74,118.64},{93.47,156.25},{83.56,159.37},
{58.91,104.24},{17.17,55.02},{61.22,119.69},{45.82,94.79},
{17.17,74.27},{21.22,47.78},{17.64,50.62},{16.56,56.21},
{32.37,76.59},{66.74,114.96},{26.23,60.03},{27.07,75.08},
{16.26,45.80},{46.20,97.82},{ 9.14,45.88},{13.38,43.76},
{27.19,59.57},{34.86,88.57},{85.63,144.87},{55.71,110.49},
{55.62,101.77},{76.12,137.16},{53.24,109.80},{61.48,121.39},
{ 6.40,25.24},{46.74,92.45},{71.59,132.39},{28.43,77.52},
{68.73,131.25},{44.27,107.42},{65.88,128.88},{32.63,73.60},
{ 5.98,46.75},{ 8.52,36.36},{80.13,150.13},{99.95,172.25},
{49.04,82.13},{74.27,131.66},{ 2.55,21.35},{37.91,72.65},
{58.32,98.33},{78.65,138.32},{64.44,142.24},{39.76,102.27},
{34.24,88.03},{34.36,86.23},{58.79,107.80},{27.45,68.17},
{85.03,134.11},{43.05,102.99},{73.68,124.75},{59.46,111.47},
{25.43,70.54},{78.96,141.05},{52.15,117.19},{83.16,143.72},
{82.92,147.05},{24.77,54.57},{ 4.47,13.97},{20.28,47.25},
{59.33,116.38},{42.32,88.75},{29.10,72.39},{ 3.09,34.29},
{89.79,156.34},{16.88,42.49},{29.57,57.84},{20.46,70.34},
{ 3.32,30.40},{50.04,115.30},{ 8.70,34.66},{56.89,127.48},
{44.98,110.33},{78.79,142.46},{75.98,125.64},{67.87,132.39},
{12.65,55.67},{29.76,68.30},{23.04,68.87},{ 1.39,46.55},
{11.93,47.74},{76.81,130.63},{36.23,60.87},{82.17,148.30},
{57.96,98.37},{55.25,110.04},{90.64,157.35},{ 6.46,53.56},
{37.06,76.23},{ 0.78,20.01},{18.00,57.24},{39.01,86.87},
{81.30,137.64},{93.07,160.70},{46.12,107.39},{28.41,54.49},
{ 3.98,12.01},{ 1.40,26.15},{17.50,42.51},{63.86,122.40},
{34.02,58.71},{26.39,74.74},{84.32,133.79},{43.45,94.44},
{65.57,109.22},{87.73,148.77},{ 6.60,22.61},{25.00,57.85},
{78.06,141.20},{59.36,120.65},{40.58,82.33},{60.34,94.44},
{28.54,59.24},{28.87,62.43},{16.30,58.16},{15.93,46.27},
{81.31,145.87},{ 4.11,32.68},{ 4.59,26.34},{46.27,77.29},
{76.18,141.01},{54.57,106.15},{50.88,91.60},{29.43,70.00},
{40.28,71.90},{ 7.40,54.73},{47.47,96.96},{37.73,81.98},
{50.41,98.64},{51.27,75.77},{18.77,57.85},{89.78,149.43},
{52.15,97.04},{96.49,149.33},{10.02,31.91},{66.31,117.85},
{23.53,46.57},{13.75,58.44},{79.11,126.53},{88.69,156.62},
{48.84,95.55},{16.67,59.50},{38.77,78.61},{ 1.34,17.60},
{42.10,92.77},{16.13,59.32},{39.91,52.59},{29.80,73.67},
{32.05,78.76},{79.15,138.73},{ 4.87,38.81},{39.19,78.12},
{91.91,151.01},{ 6.42,30.39},{75.87,144.60},{31.41,70.40},
{53.11,97.77},{95.82,150.10},{81.34,142.82},{43.06,82.20},
{48.51,119.24},{33.72,96.27},{39.97,84.44},{73.14,151.85},
{88.82,160.36},{20.75,47.84},{27.20,78.42},{90.60,146.84},
{29.83,59.96},{89.87,146.86},{13.72,51.99},{99.15,167.18},
{52.08,100.57},{82.43,144.09},{11.42,35.59},{ 5.44,17.65},
{80.93,125.60},{33.03,80.04},{85.31,146.26},{ 3.22,44.89},
{23.00,52.64},{ 7.39,47.54},{48.59,98.05},{10.55,51.61},
{69.16,123.97},{87.24,155.52},{92.00,168.71},{ 6.61,45.05},
{32.89,66.39},{55.80,119.58},{43.54,111.85},{68.67,135.21},
{ 0.24,30.71},{57.59,114.41},{16.17,58.04},{ 6.25,41.72},
{ 9.16,46.64},{91.22,162.13},{46.47,104.68},{18.86,49.65},
{52.75,108.61},{85.46,133.74},{73.60,138.14},{50.55,118.86},
{30.54,66.35},{50.85,111.86},{70.25,126.00},{49.48,102.17},
{24.93,66.08},{ 2.63,34.63},{62.07,118.69},{62.25,108.45},
{20.28,61.81},{32.06,67.70},{54.64,97.24},{48.12,90.16},
{19.27,44.36},{80.24,141.84},{65.21,113.97},{53.61,115.71},
{84.83,148.51},{34.33,75.45},{93.22,152.04},{91.56,151.73},
{10.38,49.46},{39.41,92.74},{26.89,56.87},{95.22,146.87},
{41.17,86.91},{81.89,147.34},{14.58,45.46},{18.39,54.05},
{71.89,104.40},{ 0.30,30.11},{63.96,110.11},{44.40,92.86},
{83.48,154.12},{14.82,50.29},{36.78,76.46},{51.66,100.51},
{88.52,152.67},{93.61,159.05},{16.01,50.41},{16.07,48.57},
{68.77,130.06},{32.32,67.18},{33.34,89.63},{37.47,77.02},
{44.11,89.78},{40.36,80.08},{50.29,99.98},{65.33,109.83},
{24.20,58.45},{13.68,51.23},{54.82,103.81},{98.53,163.98},
{72.10,125.16},{ 5.72,29.97},{ 4.33,37.36},{13.79,49.50},
{72.88,133.72},{35.89,57.79},{24.93,66.44},{65.67,123.16},
{10.63,52.88},{82.36,150.47},{ 0.62,27.36},{16.79,58.06},
{ 3.84,26.35},{85.22,153.42},{74.02,107.95},{32.04,83.35},
{71.72,122.28},{54.89,104.07},{74.45,141.35},{ 1.42,26.12},
{36.63,61.69},{42.20,92.21},{26.41,71.01},{99.70,173.70},
{81.19,154.01},{ 5.16,18.63},{54.40,94.12},{15.33,59.58},
{70.31,127.16},{11.42,44.79},{35.26,99.03},{18.03,48.41},
{22.02,70.90},{73.79,131.75},{71.15,135.36},{23.14,33.04},
{86.06,160.02},{70.34,123.21},{45.58,78.57},{87.12,151.37},
{67.94,115.34},{69.98,133.49},{15.68,59.43},{71.70,151.09},
{51.82,102.37},{ 0.58,15.36},{ 2.90,47.52},{44.80,92.48},
{82.32,132.50},{ 4.63,14.38},{31.96,48.86},{46.05,84.79},
{13.51,51.36},{51.24,107.59},{44.03,90.54},{51.97,108.04},
{68.32,116.35},{62.22,102.36},{61.33,123.14},{69.45,108.62},
{34.29,68.38},{94.12,159.76},{88.61,164.29},{21.54,61.18},
{80.70,148.58},{32.74,70.20},{91.67,148.53},{67.20,129.49},
{47.66,89.84},{20.00,42.76},{ 4.79,28.06},{40.06,81.69},
{ 9.27,20.83},{73.38,145.35},{86.29,149.36},{68.78,139.89},
{ 9.72,52.80},{34.60,73.98},{84.87,152.58},{23.98,60.25},
{20.35,57.12},{53.22,101.34},{78.28,147.59},{74.65,135.40},
{69.74,121.56},{86.11,141.16},{52.67,93.22},{36.21,73.36},
{62.41,119.51},{96.71,171.05},{48.40,115.07},{77.92,128.50},
{38.72,94.44},{19.42,60.45},{27.74,67.47},{65.43,136.98},
{48.30,100.65},{22.79,41.37},{50.96,87.94},{69.21,128.50},
{58.99,119.90},{ 6.56,37.55},{58.15,93.18},{75.73,133.38},
{63.81,138.63},{19.75,58.04},{63.51,112.74},{92.64,158.71},
{73.19,119.83},{74.40,120.50},{80.13,153.79},{98.06,176.77},
{26.53,71.35},{39.94,89.47},{10.63,46.96},{22.47,70.86},
{23.26,50.74},{76.09,143.68},{79.01,149.60},{75.69,115.59},
{60.72,114.92},{ 8.69,34.04},{66.46,127.71},{85.83,144.31},
{91.27,152.15},{ 2.99,30.02},{37.62,71.00},{60.92,102.47},
{44.12,101.36},{37.63,62.04},{68.97,120.90},{53.24,112.70},
{ 4.07,47.04},{60.77,110.59},{87.05,154.03},{92.55,155.02},
{73.87,130.02},{22.58,59.37},{ 3.30,26.74},{48.73,102.89},
{ 5.67,29.37},{83.16,143.34},{65.46,115.06},{37.49,78.43},
{11.22,42.48},{32.22,88.20},{68.33,125.75},{86.67,144.24},
{34.74,74.45},{95.02,159.49},{73.56,125.83},{72.81,144.78},
{29.15,50.65},{ 8.90,31.43},{85.79,142.73},{56.29,115.86},
{50.87,101.85},{74.48,131.71},{ 9.10,50.93},{65.98,128.12},
{53.17,96.22},{95.92,160.00},{51.40,105.43},{49.84,99.95},
{12.84,43.78},{26.81,78.07},{35.84,67.05},{51.20,106.73},
{52.67,99.15},{ 2.97,22.17},{87.10,158.04},{97.92,150.43},
{19.36,66.09},{26.94,81.91},{74.10,139.62},{48.95,95.97},
{73.76,131.04},{43.02,100.53},{52.41,98.19},{ 0.03,32.02},
{94.16,161.53},{42.19,92.10},{ 0.09,37.47},{33.99,72.70},
{99.79,162.51},{33.87,64.33},{80.79,143.75},{32.37,84.16},
{92.68,162.80},{48.63,95.91},{79.88,160.76},{55.73,103.59},
{97.68,174.76},{91.55,150.78},{61.67,96.86},{62.10,104.76},
{10.15,30.28},{99.29,174.74},{77.47,128.21},{79.09,137.80},
{97.86,168.94},{87.41,152.14},{47.77,100.51},{ 7.12,31.81},
{74.21,128.46},{98.33,161.20},{31.56,65.88},{ 8.51,60.46},
{29.91,78.70},{25.98,54.92},{89.41,143.94},{87.04,143.13},
{40.64,67.19},{58.30,119.17},{47.49,98.34},{13.46,52.97},
{15.42,38.65},{99.33,171.47},{ 1.32,41.87},{ 0.76,29.01},
{94.15,167.71},{42.90,104.51},{51.04,112.91},{43.17,76.83},
{75.58,141.83},{76.09,127.74},{78.98,147.69},{40.88,76.51},
{ 3.39,34.13},{47.86,98.78},{60.23,116.36},{27.28,85.94},
{67.71,118.19},{29.86,61.94},{72.12,131.79},{97.82,178.48},
{38.60,70.05},{75.57,116.03},{38.59,89.37},{59.33,119.02},
{26.31,58.70},{80.91,149.89},{ 9.16,29.56},{ 3.76,25.74},
{41.59,89.75},{86.21,158.11},{84.75,154.34},{21.36,56.39},
{56.08,99.09},{42.90,79.09},{56.57,95.10},{61.51,129.85},
{34.02,79.24},{ 0.78,17.70},{98.72,175.73},{30.08,77.88},
{50.75,100.00},{92.19,157.85},{49.00,84.27},{79.00,142.36},
{75.20,137.48},{57.53,105.12},{84.52,151.03},{34.09,88.44},
{49.31,109.97},{59.81,105.11},{ 8.99,26.04},{15.12,46.94}
};
double residual_error(double a, double y, double m, double c) {
double e = (m * a) + c - y;
return e * e;
}
__device__ double d_residual_error(double a, double y, double m, double c) {
double e = (m * a) + c - y;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].a, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Calculate the current index by using:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//Work out the error sum 1000 times and store them in an array.
error_sum_arr[i] = d_residual_error(d_data[i].a, d_data[i].y, *m, *c);
}
int time_difference(struct timespec *start, struct timespec *finish,
long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
//Get the system time before we begin the linear regression.
clock_gettime(CLOCK_MONOTONIC, &start);
cudaError_t error;
//Device variables
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
//Allocate memory for d_dm
error = cudaMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Allocate memory for d_dc
error = cudaMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "cudaMalloc on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Allocate memory for d_error_sum_arr
error = cudaMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "cudaMalloc on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Allocate memory for d_data
error = cudaMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "cudaMalloc on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
//Copy memory for dm to d_dm
error = cudaMemcpy(d_dm, dm, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dm returned %d %s\n", error,
cudaGetErrorString(error));
}
//Copy memory for dc to d_dc
error = cudaMemcpy(d_dc, dc, (sizeof(double) * 8), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_dc returned %d %s\n", error,
cudaGetErrorString(error));
}
//Copy memory for data to d_data
error = cudaMemcpy(d_data, data, sizeof(data), cudaMemcpyHostToDevice);
if(error){
fprintf(stderr, "cudaMemcpy to d_data returned %d %s\n", error,
cudaGetErrorString(error));
}
for(i=0;i<8;i++) {
//Host variable storing the array returned from the kernel function.
double h_error_sum_arr[1000];
//Stores the total sum of the values from the error sum array.
double error_sum_total;
//Stores the mean of the total sum of the error sums.
double error_sum_mean;
//Call the rms_error function using 100 blocks and 10 threads.
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
cudaThreadSynchronize();
//Copy memory for d_error_sum_arr
error = cudaMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000), cudaMemcpyDeviceToHost);
if(error){
fprintf(stderr, "cudaMemcpy to error_sum returned %d %s\n", error,
cudaGetErrorString(error));
}
//Loop through the error sum array returned from the kernel function
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
//Calculate the mean for the error sum.
error_sum_mean = error_sum_total / n_data;
//Calculate the square root for the error sum mean.
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
//printf("best m,c is %lf,%lf with error %lf in direction %d\n",
//dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//Free memory for d_dm
error = cudaFree(d_dm);
if(error){
fprintf(stderr, "cudaFree on d_dm returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Free memory for d_dc
error = cudaFree(d_dc);
if(error){
fprintf(stderr, "cudaFree on d_dc returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Free memory for d_data
error = cudaFree(d_data);
if(error){
fprintf(stderr, "cudaFree on d_data returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
//Free memory for d_error_sum_arr
error = cudaFree(d_error_sum_arr);
if(error){
fprintf(stderr, "cudaFree on d_error_sum_arr returned %d %s\n", error,
cudaGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
//Get the system time after we have run the linear regression function.
clock_gettime(CLOCK_MONOTONIC, &finish);
//Calculate the time spent between the start time and end time.
time_difference(&start, &finish, &time_elapsed);
//Output the time spent running the program.
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <time.h>
#include <unistd.h>
#include <hip/hip_runtime_api.h>
#include <errno.h>
#include <unistd.h>
/******************************************************************************
* This program takes an initial estimate of m and c and finds the associated
* rms error. It is then as a base to generate and evaluate 8 new estimates,
* which are steps in different directions in m-c space. The best estimate is
* then used as the base for another iteration of "generate and evaluate". This
* continues until none of the new estimates are better than the base. This is
* a gradient search for a minimum in mc-space.
*
* To compile:
* nvcc -o linear_regression_ques_a linear_regression_ques_a.cu -lm
*
* To run:
* ./linear_regression_ques_a
*
*****************************************************************************/
typedef struct point_t {
double a;
double y;
} point_t;
int n_data = 1000;
__device__ int d_n_data = 1000;
//actual data
point_t data[] = {
{77.98,130.36},{79.09,148.43},{72.34,123.95},{65.93,116.99},
{77.57,132.91},{79.38,148.35},{85.45,141.04},{68.12,112.26},
{83.96,140.95},{65.32,107.96},{73.70,144.54},{68.51,110.97},
{23.70,43.30},{32.60,75.51},{97.45,167.12},{24.44,62.51},
{35.26,73.73},{42.05,87.45},{80.60,154.01},{42.19,78.14},
{11.57,36.87},{89.39,138.89},{79.04,151.16},{75.37,140.63},
{16.37,48.59},{85.73,138.70},{19.40,60.34},{ 1.87,30.33},
{64.62,100.67},{82.50,149.78},{69.86,126.38},{76.07,111.45},
{75.30,138.59},{ 8.55,34.53},{76.84,150.23},{88.69,149.26},
{69.72,143.26},{37.04,75.54},{84.39,168.66},{42.23,83.86},
{ 9.89,36.55},{74.04,123.28},{75.72,123.75},{19.76,61.01},
{ 7.21,24.85},{47.72,87.46},{46.74,99.94},{87.50,141.68},
{29.77,84.23},{58.59,112.53},{56.40,110.57},{72.64,133.51},
{18.77,73.65},{50.47,92.54},{17.67,50.48},{22.96,50.27},
{93.80,157.23},{28.78,62.97},{70.77,137.07},{18.46,48.76},
{78.73,147.81},{28.64,64.04},{15.87,71.24},{20.60,58.87},
{24.04,71.30},{29.82,64.70},{74.92,119.91},{57.65,128.03},
{ 8.60,17.53},{64.15,114.03},{54.12,111.55},{46.26,86.85},
{69.34,128.76},{62.32,123.58},{35.54,91.65},{63.94,108.18},
{ 8.79,26.44},{94.79,158.97},{69.39,127.07},{54.95,85.68},
{80.80,123.50},{ 5.04,28.59},{60.70,122.70},{64.93,116.81},
{75.21,140.82},{94.73,158.77},{70.97,119.67},{18.60,49.57},
{35.65,90.07},{51.29,106.23},{99.39,164.53},{68.69,128.54},
{43.27,97.46},{54.00,103.11},{98.43,155.75},{85.94,149.47},
{77.76,130.00},{ 9.66,21.48},{65.38,113.14},{86.03,135.26},
{52.91,109.09},{40.51,88.36},{96.33,178.71},{65.01,112.30},
{22.21,63.56},{92.23,155.97},{ 5.44,50.68},{47.24,91.65},
{70.34,134.08},{91.42,134.44},{ 6.25,45.93},{30.84,78.59},
{59.59,93.17},{59.66,116.00},{56.91,124.37},{26.40,80.75},
{41.75,104.14},{92.10,151.34},{24.18,73.47},{71.32,139.54},
{94.73,165.99},{54.05,102.18},{58.35,108.14},{54.49,84.38},
{60.06,111.97},{72.99,135.35},{74.88,134.12},{55.44,112.28},
{99.26,172.77},{15.34,42.67},{53.88,93.18},{35.90,73.13},
{79.41,137.27},{52.71,100.10},{14.90,64.25},{77.27,143.40},
{94.85,161.63},{27.95,67.70},{22.65,69.15},{19.92,75.99},
{21.63,58.86},{63.89,125.04},{31.18,68.30},{85.21,142.92},
{ 6.99,41.71},{65.13,123.67},{43.22,91.87},{14.54,51.08},
{71.03,120.54},{85.32,139.23},{ 1.65,15.42},{68.44,114.18},
{24.89,43.34},{44.09,71.91},{52.78,100.42},{39.00,104.71},
{30.45,68.40},{93.79,152.03},{43.67,82.38},{60.03,110.47},
{72.81,133.44},{ 3.36,39.56},{23.63,51.23},{ 2.24,35.53},
{69.37,120.48},{21.85,53.01},{99.40,148.97},{48.26,95.05},
{19.43,47.20},{18.54,58.80},{59.71,130.46},{83.76,146.14},
{61.24,108.80},{59.79,118.94},{32.18,74.26},{69.93,107.25},
{18.80,65.71},{77.62,135.24},{36.38,80.62},{22.11,61.87},
{87.67,159.19},{18.27,42.13},{59.46,113.12},{27.86,76.32},
{44.58,81.58},{51.48,91.53},{34.66,68.59},{24.31,60.65},
{77.44,155.88},{89.86,165.12},{14.31,40.08},{ 8.99,63.09},
{62.05,109.52},{99.16,166.58},{16.23,62.72},{21.00,57.58},
{64.70,110.52},{36.50,70.82},{13.60,32.41},{72.48,132.93},
{16.55,48.30},{72.33,146.17},{74.80,144.98},{86.52,145.51},
{18.74,53.20},{42.46,84.17},{34.14,83.02},{48.40,105.26},
{94.58,164.10},{54.73,97.10},{15.98,54.69},{41.41,82.26},
{54.70,107.38},{78.82,140.70},{18.53,70.95},{ 7.02,48.19},
{36.99,81.18},{11.80,22.97},{89.96,163.81},{18.02,55.52},
{70.09,123.95},{84.84,138.33},{70.15,139.19},{17.89,44.33},
{91.76,146.52},{35.98,77.33},{71.59,112.49},{44.29,103.12},
{ 6.47,33.93},{ 2.33,39.95},{64.72,113.89},{48.82,88.91},
{71.34,127.29},{99.75,165.06},{51.38,91.86},{76.72,118.85},
{ 9.09,53.80},{44.40,95.91},{55.88,112.71},{27.00,65.93},
{43.09,89.10},{15.77,58.36},{ 6.66,52.56},{ 0.72,15.70},
{ 9.10,32.67},{73.31,146.06},{80.63,145.39},{89.34,151.93},
{70.99,109.10},{18.48,40.16},{13.53,60.15},{ 3.62,35.30},
{ 0.67,22.84},{10.18,34.71},{62.39,115.13},{16.83,50.51},
{ 4.95,34.83},{17.56,65.63},{20.46,71.24},{ 3.24,22.13},
{62.62,108.31},{83.41,159.53},{13.94,62.74},{39.53,75.26},
{70.08,127.75},{96.18,154.40},{ 4.70,51.92},{ 4.83,34.24},
{86.68,155.95},{39.14,95.10},{54.83,101.35},{45.90,113.05},
{83.84,164.08},{91.32,141.46},{99.38,151.63},{57.80,88.41},
{15.70,64.96},{50.13,86.85},{ 5.49,49.01},{46.72,94.05},
{89.37,154.06},{30.59,63.82},{71.14,121.90},{17.65,61.37},
{17.22,71.53},{63.80,131.31},{48.19,93.75},{46.52,99.40},
{93.86,171.03},{23.64,68.51},{89.26,157.22},{49.78,104.78},
{85.35,137.00},{72.36,124.10},{82.00,138.39},{13.84,48.03},
{89.78,154.55},{90.40,143.48},{ 3.06,22.06},{51.56,99.83},
{61.82,112.08},{38.70,87.78},{31.97,74.39},{99.69,176.25},
{78.62,152.64},{52.43,102.53},{92.86,145.69},{81.64,144.55},
{76.06,122.34},{ 4.95,32.38},{87.52,171.59},{95.04,149.43},
{60.28,110.39},{82.25,169.12},{22.81,57.02},{ 6.91,40.13},
{53.36,106.12},{96.26,156.75},{15.49,45.17},{36.79,83.03},
{82.18,147.65},{31.99,74.58},{44.35,86.62},{35.53,75.38},
{41.16,96.88},{98.23,160.31},{48.38,84.37},{86.01,161.33},
{ 7.43,31.88},{24.37,44.83},{11.01,41.83},{16.86,44.57},
{13.72,32.74},{61.53,119.79},{48.45,82.98},{34.80,74.74},
{73.82,131.76},{45.49,87.37},{44.29,99.77},{85.94,167.42},
{38.49,75.27},{30.29,70.78},{68.66,114.49},{27.31,67.54},
{67.58,121.97},{66.72,123.44},{61.54,95.46},{43.92,85.74},
{43.87,109.10},{56.28,107.24},{86.68,137.08},{ 0.81,20.16},
{18.28,49.52},{51.27,112.06},{43.31,65.28},{29.32,52.29},
{98.77,169.88},{17.18,52.57},{76.85,145.82},{82.70,135.08},
{83.64,131.25},{12.33,38.01},{76.06,153.75},{83.89,135.10},
{29.57,65.30},{47.52,108.75},{ 8.76,39.70},{20.95,67.72},
{ 5.41,42.36},{61.13,90.13},{ 3.08,14.51},{38.82,95.19},
{17.75,66.51},{ 1.83,29.54},{60.84,110.57},{44.30,95.26},
{58.12,115.47},{43.36,84.41},{74.23,122.77},{46.90,93.52},
{95.44,148.73},{ 7.39,45.61},{52.81,104.35},{37.16,60.15},
{ 9.81,46.92},{15.75,52.64},{ 7.55,55.70},{80.65,123.61},
{70.31,144.36},{56.05,118.04},{41.85,90.23},{48.33,100.55},
{61.36,129.79},{30.99,63.92},{97.88,165.01},{88.06,163.98},
{ 3.94,42.78},{51.10,94.74},{25.92,56.47},{32.24,56.10},
{56.42,105.70},{35.94,65.57},{88.44,140.75},{18.42,50.02},
{92.97,165.67},{93.14,152.64},{84.46,142.58},{59.79,101.62},
{47.70,93.97},{85.61,150.83},{75.95,125.79},{68.98,124.25},
{12.19,46.92},{64.71,111.41},{65.35,117.94},{56.03,117.75},
{33.65,80.22},{99.83,154.54},{42.11,91.90},{29.26,71.92},
{12.45,42.87},{31.86,58.42},{67.32,131.56},{62.65,119.19},
{21.02,60.23},{36.42,63.61},{21.46,68.57},{87.10,154.60},
{54.01,111.59},{79.76,131.26},{20.26,40.04},{92.15,144.67},
{18.69,56.39},{77.38,133.16},{34.32,90.42},{66.53,107.16},
{32.44,72.36},{57.18,99.61},{17.61,67.09},{19.97,67.47},
{60.67,108.28},{46.88,87.00},{97.25,170.60},{80.52,149.02},
{37.36,79.89},{94.27,169.69},{80.94,147.55},{30.75,71.59},
{66.58,128.72},{63.16,95.21},{ 4.90,18.07},{50.47,91.47},
{73.25,120.81},{57.26,113.72},{98.04,168.70},{ 6.88,43.58},
{52.69,84.44},{86.30,154.21},{63.61,125.07},{44.90,77.52},
{13.76,44.88},{88.55,157.17},{39.41,85.60},{56.27,99.27},
{93.04,146.91},{ 1.71,16.08},{84.43,171.48},{90.37,147.40},
{32.91,74.15},{96.28,183.66},{48.10,93.15},{86.94,140.01},
{20.19,46.78},{54.74,118.64},{93.47,156.25},{83.56,159.37},
{58.91,104.24},{17.17,55.02},{61.22,119.69},{45.82,94.79},
{17.17,74.27},{21.22,47.78},{17.64,50.62},{16.56,56.21},
{32.37,76.59},{66.74,114.96},{26.23,60.03},{27.07,75.08},
{16.26,45.80},{46.20,97.82},{ 9.14,45.88},{13.38,43.76},
{27.19,59.57},{34.86,88.57},{85.63,144.87},{55.71,110.49},
{55.62,101.77},{76.12,137.16},{53.24,109.80},{61.48,121.39},
{ 6.40,25.24},{46.74,92.45},{71.59,132.39},{28.43,77.52},
{68.73,131.25},{44.27,107.42},{65.88,128.88},{32.63,73.60},
{ 5.98,46.75},{ 8.52,36.36},{80.13,150.13},{99.95,172.25},
{49.04,82.13},{74.27,131.66},{ 2.55,21.35},{37.91,72.65},
{58.32,98.33},{78.65,138.32},{64.44,142.24},{39.76,102.27},
{34.24,88.03},{34.36,86.23},{58.79,107.80},{27.45,68.17},
{85.03,134.11},{43.05,102.99},{73.68,124.75},{59.46,111.47},
{25.43,70.54},{78.96,141.05},{52.15,117.19},{83.16,143.72},
{82.92,147.05},{24.77,54.57},{ 4.47,13.97},{20.28,47.25},
{59.33,116.38},{42.32,88.75},{29.10,72.39},{ 3.09,34.29},
{89.79,156.34},{16.88,42.49},{29.57,57.84},{20.46,70.34},
{ 3.32,30.40},{50.04,115.30},{ 8.70,34.66},{56.89,127.48},
{44.98,110.33},{78.79,142.46},{75.98,125.64},{67.87,132.39},
{12.65,55.67},{29.76,68.30},{23.04,68.87},{ 1.39,46.55},
{11.93,47.74},{76.81,130.63},{36.23,60.87},{82.17,148.30},
{57.96,98.37},{55.25,110.04},{90.64,157.35},{ 6.46,53.56},
{37.06,76.23},{ 0.78,20.01},{18.00,57.24},{39.01,86.87},
{81.30,137.64},{93.07,160.70},{46.12,107.39},{28.41,54.49},
{ 3.98,12.01},{ 1.40,26.15},{17.50,42.51},{63.86,122.40},
{34.02,58.71},{26.39,74.74},{84.32,133.79},{43.45,94.44},
{65.57,109.22},{87.73,148.77},{ 6.60,22.61},{25.00,57.85},
{78.06,141.20},{59.36,120.65},{40.58,82.33},{60.34,94.44},
{28.54,59.24},{28.87,62.43},{16.30,58.16},{15.93,46.27},
{81.31,145.87},{ 4.11,32.68},{ 4.59,26.34},{46.27,77.29},
{76.18,141.01},{54.57,106.15},{50.88,91.60},{29.43,70.00},
{40.28,71.90},{ 7.40,54.73},{47.47,96.96},{37.73,81.98},
{50.41,98.64},{51.27,75.77},{18.77,57.85},{89.78,149.43},
{52.15,97.04},{96.49,149.33},{10.02,31.91},{66.31,117.85},
{23.53,46.57},{13.75,58.44},{79.11,126.53},{88.69,156.62},
{48.84,95.55},{16.67,59.50},{38.77,78.61},{ 1.34,17.60},
{42.10,92.77},{16.13,59.32},{39.91,52.59},{29.80,73.67},
{32.05,78.76},{79.15,138.73},{ 4.87,38.81},{39.19,78.12},
{91.91,151.01},{ 6.42,30.39},{75.87,144.60},{31.41,70.40},
{53.11,97.77},{95.82,150.10},{81.34,142.82},{43.06,82.20},
{48.51,119.24},{33.72,96.27},{39.97,84.44},{73.14,151.85},
{88.82,160.36},{20.75,47.84},{27.20,78.42},{90.60,146.84},
{29.83,59.96},{89.87,146.86},{13.72,51.99},{99.15,167.18},
{52.08,100.57},{82.43,144.09},{11.42,35.59},{ 5.44,17.65},
{80.93,125.60},{33.03,80.04},{85.31,146.26},{ 3.22,44.89},
{23.00,52.64},{ 7.39,47.54},{48.59,98.05},{10.55,51.61},
{69.16,123.97},{87.24,155.52},{92.00,168.71},{ 6.61,45.05},
{32.89,66.39},{55.80,119.58},{43.54,111.85},{68.67,135.21},
{ 0.24,30.71},{57.59,114.41},{16.17,58.04},{ 6.25,41.72},
{ 9.16,46.64},{91.22,162.13},{46.47,104.68},{18.86,49.65},
{52.75,108.61},{85.46,133.74},{73.60,138.14},{50.55,118.86},
{30.54,66.35},{50.85,111.86},{70.25,126.00},{49.48,102.17},
{24.93,66.08},{ 2.63,34.63},{62.07,118.69},{62.25,108.45},
{20.28,61.81},{32.06,67.70},{54.64,97.24},{48.12,90.16},
{19.27,44.36},{80.24,141.84},{65.21,113.97},{53.61,115.71},
{84.83,148.51},{34.33,75.45},{93.22,152.04},{91.56,151.73},
{10.38,49.46},{39.41,92.74},{26.89,56.87},{95.22,146.87},
{41.17,86.91},{81.89,147.34},{14.58,45.46},{18.39,54.05},
{71.89,104.40},{ 0.30,30.11},{63.96,110.11},{44.40,92.86},
{83.48,154.12},{14.82,50.29},{36.78,76.46},{51.66,100.51},
{88.52,152.67},{93.61,159.05},{16.01,50.41},{16.07,48.57},
{68.77,130.06},{32.32,67.18},{33.34,89.63},{37.47,77.02},
{44.11,89.78},{40.36,80.08},{50.29,99.98},{65.33,109.83},
{24.20,58.45},{13.68,51.23},{54.82,103.81},{98.53,163.98},
{72.10,125.16},{ 5.72,29.97},{ 4.33,37.36},{13.79,49.50},
{72.88,133.72},{35.89,57.79},{24.93,66.44},{65.67,123.16},
{10.63,52.88},{82.36,150.47},{ 0.62,27.36},{16.79,58.06},
{ 3.84,26.35},{85.22,153.42},{74.02,107.95},{32.04,83.35},
{71.72,122.28},{54.89,104.07},{74.45,141.35},{ 1.42,26.12},
{36.63,61.69},{42.20,92.21},{26.41,71.01},{99.70,173.70},
{81.19,154.01},{ 5.16,18.63},{54.40,94.12},{15.33,59.58},
{70.31,127.16},{11.42,44.79},{35.26,99.03},{18.03,48.41},
{22.02,70.90},{73.79,131.75},{71.15,135.36},{23.14,33.04},
{86.06,160.02},{70.34,123.21},{45.58,78.57},{87.12,151.37},
{67.94,115.34},{69.98,133.49},{15.68,59.43},{71.70,151.09},
{51.82,102.37},{ 0.58,15.36},{ 2.90,47.52},{44.80,92.48},
{82.32,132.50},{ 4.63,14.38},{31.96,48.86},{46.05,84.79},
{13.51,51.36},{51.24,107.59},{44.03,90.54},{51.97,108.04},
{68.32,116.35},{62.22,102.36},{61.33,123.14},{69.45,108.62},
{34.29,68.38},{94.12,159.76},{88.61,164.29},{21.54,61.18},
{80.70,148.58},{32.74,70.20},{91.67,148.53},{67.20,129.49},
{47.66,89.84},{20.00,42.76},{ 4.79,28.06},{40.06,81.69},
{ 9.27,20.83},{73.38,145.35},{86.29,149.36},{68.78,139.89},
{ 9.72,52.80},{34.60,73.98},{84.87,152.58},{23.98,60.25},
{20.35,57.12},{53.22,101.34},{78.28,147.59},{74.65,135.40},
{69.74,121.56},{86.11,141.16},{52.67,93.22},{36.21,73.36},
{62.41,119.51},{96.71,171.05},{48.40,115.07},{77.92,128.50},
{38.72,94.44},{19.42,60.45},{27.74,67.47},{65.43,136.98},
{48.30,100.65},{22.79,41.37},{50.96,87.94},{69.21,128.50},
{58.99,119.90},{ 6.56,37.55},{58.15,93.18},{75.73,133.38},
{63.81,138.63},{19.75,58.04},{63.51,112.74},{92.64,158.71},
{73.19,119.83},{74.40,120.50},{80.13,153.79},{98.06,176.77},
{26.53,71.35},{39.94,89.47},{10.63,46.96},{22.47,70.86},
{23.26,50.74},{76.09,143.68},{79.01,149.60},{75.69,115.59},
{60.72,114.92},{ 8.69,34.04},{66.46,127.71},{85.83,144.31},
{91.27,152.15},{ 2.99,30.02},{37.62,71.00},{60.92,102.47},
{44.12,101.36},{37.63,62.04},{68.97,120.90},{53.24,112.70},
{ 4.07,47.04},{60.77,110.59},{87.05,154.03},{92.55,155.02},
{73.87,130.02},{22.58,59.37},{ 3.30,26.74},{48.73,102.89},
{ 5.67,29.37},{83.16,143.34},{65.46,115.06},{37.49,78.43},
{11.22,42.48},{32.22,88.20},{68.33,125.75},{86.67,144.24},
{34.74,74.45},{95.02,159.49},{73.56,125.83},{72.81,144.78},
{29.15,50.65},{ 8.90,31.43},{85.79,142.73},{56.29,115.86},
{50.87,101.85},{74.48,131.71},{ 9.10,50.93},{65.98,128.12},
{53.17,96.22},{95.92,160.00},{51.40,105.43},{49.84,99.95},
{12.84,43.78},{26.81,78.07},{35.84,67.05},{51.20,106.73},
{52.67,99.15},{ 2.97,22.17},{87.10,158.04},{97.92,150.43},
{19.36,66.09},{26.94,81.91},{74.10,139.62},{48.95,95.97},
{73.76,131.04},{43.02,100.53},{52.41,98.19},{ 0.03,32.02},
{94.16,161.53},{42.19,92.10},{ 0.09,37.47},{33.99,72.70},
{99.79,162.51},{33.87,64.33},{80.79,143.75},{32.37,84.16},
{92.68,162.80},{48.63,95.91},{79.88,160.76},{55.73,103.59},
{97.68,174.76},{91.55,150.78},{61.67,96.86},{62.10,104.76},
{10.15,30.28},{99.29,174.74},{77.47,128.21},{79.09,137.80},
{97.86,168.94},{87.41,152.14},{47.77,100.51},{ 7.12,31.81},
{74.21,128.46},{98.33,161.20},{31.56,65.88},{ 8.51,60.46},
{29.91,78.70},{25.98,54.92},{89.41,143.94},{87.04,143.13},
{40.64,67.19},{58.30,119.17},{47.49,98.34},{13.46,52.97},
{15.42,38.65},{99.33,171.47},{ 1.32,41.87},{ 0.76,29.01},
{94.15,167.71},{42.90,104.51},{51.04,112.91},{43.17,76.83},
{75.58,141.83},{76.09,127.74},{78.98,147.69},{40.88,76.51},
{ 3.39,34.13},{47.86,98.78},{60.23,116.36},{27.28,85.94},
{67.71,118.19},{29.86,61.94},{72.12,131.79},{97.82,178.48},
{38.60,70.05},{75.57,116.03},{38.59,89.37},{59.33,119.02},
{26.31,58.70},{80.91,149.89},{ 9.16,29.56},{ 3.76,25.74},
{41.59,89.75},{86.21,158.11},{84.75,154.34},{21.36,56.39},
{56.08,99.09},{42.90,79.09},{56.57,95.10},{61.51,129.85},
{34.02,79.24},{ 0.78,17.70},{98.72,175.73},{30.08,77.88},
{50.75,100.00},{92.19,157.85},{49.00,84.27},{79.00,142.36},
{75.20,137.48},{57.53,105.12},{84.52,151.03},{34.09,88.44},
{49.31,109.97},{59.81,105.11},{ 8.99,26.04},{15.12,46.94}
};
double residual_error(double a, double y, double m, double c) {
double e = (m * a) + c - y;
return e * e;
}
__device__ double d_residual_error(double a, double y, double m, double c) {
double e = (m * a) + c - y;
return e * e;
}
double rms_error(double m, double c) {
int i;
double mean;
double error_sum = 0;
for(i=0; i<n_data; i++) {
error_sum += residual_error(data[i].a, data[i].y, m, c);
}
mean = error_sum / n_data;
return sqrt(mean);
}
__global__ void d_rms_error(double *m, double *c, double *error_sum_arr, point_t *d_data) {
/*
Calculate the current index by using:
- The thread id
- The block id
- The number of threads per block
*/
int i = threadIdx.x + blockIdx.x * blockDim.x;
//Work out the error sum 1000 times and store them in an array.
error_sum_arr[i] = d_residual_error(d_data[i].a, d_data[i].y, *m, *c);
}
int time_difference(struct timespec *start, struct timespec *finish,
long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if(dn < 0 ) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return !(*difference > 0);
}
int main() {
int i;
double bm = 1.3;
double bc = 10;
double be;
double dm[8];
double dc[8];
double e[8];
double step = 0.01;
double best_error = 999999999;
int best_error_i;
int minimum_found = 0;
double om[] = {0,1,1, 1, 0,-1,-1,-1};
double oc[] = {1,1,0,-1,-1,-1, 0, 1};
struct timespec start, finish;
long long int time_elapsed;
//Get the system time before we begin the linear regression.
clock_gettime(CLOCK_MONOTONIC, &start);
hipError_t error;
//Device variables
double *d_dm;
double *d_dc;
double *d_error_sum_arr;
point_t *d_data;
be = rms_error(bm, bc);
//Allocate memory for d_dm
error = hipMalloc(&d_dm, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Allocate memory for d_dc
error = hipMalloc(&d_dc, (sizeof(double) * 8));
if(error){
fprintf(stderr, "hipMalloc on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Allocate memory for d_error_sum_arr
error = hipMalloc(&d_error_sum_arr, (sizeof(double) * 1000));
if(error){
fprintf(stderr, "hipMalloc on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Allocate memory for d_data
error = hipMalloc(&d_data, sizeof(data));
if(error){
fprintf(stderr, "hipMalloc on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
while(!minimum_found) {
for(i=0;i<8;i++) {
dm[i] = bm + (om[i] * step);
dc[i] = bc + (oc[i] * step);
}
//Copy memory for dm to d_dm
error = hipMemcpy(d_dm, dm, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dm returned %d %s\n", error,
hipGetErrorString(error));
}
//Copy memory for dc to d_dc
error = hipMemcpy(d_dc, dc, (sizeof(double) * 8), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_dc returned %d %s\n", error,
hipGetErrorString(error));
}
//Copy memory for data to d_data
error = hipMemcpy(d_data, data, sizeof(data), hipMemcpyHostToDevice);
if(error){
fprintf(stderr, "hipMemcpy to d_data returned %d %s\n", error,
hipGetErrorString(error));
}
for(i=0;i<8;i++) {
//Host variable storing the array returned from the kernel function.
double h_error_sum_arr[1000];
//Stores the total sum of the values from the error sum array.
double error_sum_total;
//Stores the mean of the total sum of the error sums.
double error_sum_mean;
//Call the rms_error function using 100 blocks and 10 threads.
d_rms_error <<<100,10>>>(&d_dm[i], &d_dc[i], d_error_sum_arr, d_data);
hipDeviceSynchronize();
//Copy memory for d_error_sum_arr
error = hipMemcpy(&h_error_sum_arr, d_error_sum_arr, (sizeof(double) * 1000), hipMemcpyDeviceToHost);
if(error){
fprintf(stderr, "hipMemcpy to error_sum returned %d %s\n", error,
hipGetErrorString(error));
}
//Loop through the error sum array returned from the kernel function
for(int j=0; j<n_data; j++) {
//Add each error sum to the error sum total.
error_sum_total += h_error_sum_arr[j];
}
//Calculate the mean for the error sum.
error_sum_mean = error_sum_total / n_data;
//Calculate the square root for the error sum mean.
e[i] = sqrt(error_sum_mean);
if(e[i] < best_error) {
best_error = e[i];
best_error_i = i;
}
//Reset the error sum total.
error_sum_total = 0;
}
//printf("best m,c is %lf,%lf with error %lf in direction %d\n",
//dm[best_error_i], dc[best_error_i], best_error, best_error_i);
if(best_error < be) {
be = best_error;
bm = dm[best_error_i];
bc = dc[best_error_i];
} else {
minimum_found = 1;
}
}
//Free memory for d_dm
error = hipFree(d_dm);
if(error){
fprintf(stderr, "hipFree on d_dm returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Free memory for d_dc
error = hipFree(d_dc);
if(error){
fprintf(stderr, "hipFree on d_dc returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Free memory for d_data
error = hipFree(d_data);
if(error){
fprintf(stderr, "hipFree on d_data returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
//Free memory for d_error_sum_arr
error = hipFree(d_error_sum_arr);
if(error){
fprintf(stderr, "hipFree on d_error_sum_arr returned %d %s\n", error,
hipGetErrorString(error));
exit(1);
}
printf("minimum m,c is %lf,%lf with error %lf\n", bm, bc, be);
//Get the system time after we have run the linear regression function.
clock_gettime(CLOCK_MONOTONIC, &finish);
//Calculate the time spent between the start time and end time.
time_difference(&start, &finish, &time_elapsed);
//Output the time spent running the program.
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed,
(time_elapsed/1.0e9));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11d_rms_errorPdS_S_P7point_t
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R9, c[0x0][0x164] ; /* 0x0000590000097a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R11, c[0x0][0x16c] ; /* 0x00005b00000b7a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*00b0*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*00e0*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ee2000c1e1b00 */
/*00f0*/ DFMA R4, R4, R8, R10 ; /* 0x000000080404722b */
/* 0x004ecc000000000a */
/*0100*/ DADD R4, -R6, R4 ; /* 0x0000000006047229 */
/* 0x0080640000000104 */
/*0110*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x001fc80000000f00 */
/*0120*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x002e220000000000 */
/*0130*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fcc00078e0207 */
/*0140*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x001fe2000c101b04 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11d_rms_errorPdS_S_P7point_t
.globl _Z11d_rms_errorPdS_S_P7point_t
.p2align 8
.type _Z11d_rms_errorPdS_S_P7point_t,@function
_Z11d_rms_errorPdS_S_P7point_t:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, s8, v[0:1]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[0:1], v[0:1], s[0:1], s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_lshlrev_b64 v[2:3], 3, v[4:5]
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_mul_f64 v[0:1], v[0:1], v[0:1]
global_store_b64 v[2:3], v[0:1], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11d_rms_errorPdS_S_P7point_t
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11d_rms_errorPdS_S_P7point_t, .Lfunc_end0-_Z11d_rms_errorPdS_S_P7point_t
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_n_data
.type d_n_data,@object
.data
.globl d_n_data
.p2align 2, 0x0
d_n_data:
.long 1000
.size d_n_data, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11d_rms_errorPdS_S_P7point_t
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11d_rms_errorPdS_S_P7point_t.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Find BLANK and replace your own code.
* And submit report why do you replace the blank that way.
*/
#include<stdlib.h>
#include<iostream>
#include<fstream>
#include<vector>
#include<string>
#define TILE_WIDTH 16 /* set TILE_WIDTH 16 for the evaluation! */
#define MAXPOOL_INPUT_FILENAME "input.txt"
#define A_FILENAME "a.txt"
#define B_FILENAME "b.txt"
#define C_FILENAME "c.txt"
using namespace std;
__global__ void maxpool(float *input, float *output, const int input_size, const int filter_size) {
// input : input_matrix address
// output : output buffer address
// input_size : width, height of input matrix
// filter_size : filter_size of maxpolling
// all input, output matrices are vectorized
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
int large = 0;
__shared__ float s_large[TILE_WIDTH];
if(threadIdx.x == 0){
large = input[input_size*row];
for(int i = 1; i < TILE_WIDTH; i++){
if (large < input[input_size*row+i]){
large = input[input_size*row+i];
}
}
s_large[threadIdx.y] = large;
}else{
return;
}
__syncthreads();
if(threadIdx.x == 0 && threadIdx.y == 0){
for(int i = 1; i < TILE_WIDTH; i++){
if(large < s_large[i]){
large = s_large[i];
}
}
output[blockIdx.y*TILE_WIDTH + blockIdx.x] = large;
}else{
return;
}
}
// a, b, c : input matrix address
// alpha, beta : input constant
// output : output buffer address
// input_size : width, height of input matrix
// all input, output matrices are vectorized
__global__ void gemm(float *a, float *b, float *c, const float alpha, const float beta, float *output, const int input_s){
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int row = by*blockDim.y + ty;
int col = bx*blockDim.x + tx;
int input_size = input_s;
int a_default = input_size*row +tx;
int b_default = input_size*ty + col;
//if(row>=input_size ||col>=input_size) { return; }
// allocate 2D tiles in __shared__ memory
__shared__ float s_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float s_b[TILE_WIDTH][TILE_WIDTH];
float result = 0;
for(int p = 0; p < input_size / TILE_WIDTH + 1; ++p){
s_a[ty][tx] = a[a_default + p*TILE_WIDTH];
s_b[ty][tx] = b[b_default + p*input_size*TILE_WIDTH];
if(col >= input_size || p*TILE_WIDTH + ty >= input_size){
s_b[ty][tx] = 0;
}
if(row >= input_size || p*TILE_WIDTH + tx >= input_size){
s_a[ty][tx] = 0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH;i++){
result += (s_a[ty][i]*s_b[i][tx]);
}
__syncthreads();
}
if(col < input_size && row < input_size){
output[row*input_size + col] = alpha * result + beta * c[row*input_size + col];
}
}
int main(int argc, char **argv) {
if(argc < 4) {
cout << "usage : " << argv[0] << " input_size filter_size alpha beta\n" << "example : " << argv[0] << " 100 2 0.5 0.8\n";
return 1;
}
const int input_size = stoi(argv[1]);
const int filter_size = stoi(argv[2]); // used for maxpooling
const float alpha = stof(argv[3]);
const float beta = stof(argv[4]);
const int maxpool_output_size = input_size/filter_size;
// check input_size is power of 2
if(input_size == 0 && (input_size & (input_size-1))){
cout << "input_size must be power of 2\n";
return 1;
}
if(filter_size == 0){
cout << "filter_size cannot be 0\n";
return 1;
}
float maxpool_input[input_size*input_size];
float a[input_size*input_size];
float b[input_size*input_size];
float c[input_size*input_size];
// read input matrices
ifstream input_in(MAXPOOL_INPUT_FILENAME);
ifstream a_in(A_FILENAME);
ifstream b_in(B_FILENAME);
ifstream c_in(C_FILENAME);
for (int i = 0; i < input_size*input_size; ++i) {
input_in >> maxpool_input[i];
a_in >> a[i];
b_in >> b[i];
c_in >> c[i];
}
// prints inputs for debugging.
cout<<"filter size : "<<filter_size;
cout<<"\n========== MAXPOOL_INPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<maxpool_input[i]<<" ";
}
cout<<"\nalpha : "<<alpha<<'\n';
cout<<"========== A ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<a[i]<<" ";
}
cout<<"\n========== B ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<b[i]<<" ";
}
cout<<"\nbeta : "<<beta<<'\n';
cout<<"========== C ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<c[i]<<" ";
}
cout<<'\n';
// set thread, block dimensions
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
cout<<block_size.x;
const dim3 num_of_maxpool_blocks(input_size / block_size.x, input_size/ block_size.y);
const dim3 num_of_blocks(input_size/block_size.x+1, input_size/block_size.y+1);
// memory allocation for the device
float *dev_mem_a, *dev_mem_b, *dev_mem_c, *dev_mem_input, *gemm_output, *maxpool_output;
cudaMalloc(&dev_mem_a, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_b, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_c, sizeof(float) * input_size * input_size);
cudaMalloc(&gemm_output, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_input, sizeof(float) * input_size * input_size);
cudaMalloc(&maxpool_output, sizeof(float) * maxpool_output_size * maxpool_output_size);
// copy variable to device memory
cudaMemcpy(dev_mem_a, &a, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_b, &b, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_c, &c, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_input, &maxpool_input, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaEvent_t gemm_start, gemm_stop, maxpool_start, maxpool_stop;
cudaEventCreate(&gemm_start);
cudaEventCreate(&gemm_stop);
cudaEventCreate(&maxpool_start);
cudaEventCreate(&maxpool_stop);
// launch CUDA kernels
// First launch gemm kernel
cudaEventRecord(gemm_start);
gemm<<<num_of_blocks, block_size>>>(dev_mem_a, dev_mem_b, dev_mem_c, alpha, beta, gemm_output, input_size);
cudaEventRecord(gemm_stop);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(gemm_stop);
float gemm_t = 0;
cudaEventElapsedTime(&gemm_t,gemm_start,gemm_stop);
// Then run maxpooling
cudaEventRecord(maxpool_start);
maxpool<<<num_of_maxpool_blocks, block_size>>>(dev_mem_input, maxpool_output, input_size, filter_size);
cudaEventRecord(maxpool_stop);
cudaDeviceSynchronize();
//cudaError_t error = cudaGetLastError();
error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(maxpool_stop);
float maxpool_t = 0;
cudaEventElapsedTime(&maxpool_t, maxpool_start, maxpool_stop);
// allocate output buf in main memory
float *gemm_output_buf = (float*) malloc (sizeof(float)*input_size*input_size);
float *maxpool_output_buf = (float*) malloc (sizeof(float)*maxpool_output_size*maxpool_output_size);
// copy results from device to host
cudaMemcpy(gemm_output_buf, gemm_output, sizeof(float)*input_size*input_size, cudaMemcpyDeviceToHost);
cudaMemcpy(maxpool_output_buf, maxpool_output, sizeof(float)*maxpool_output_size*maxpool_output_size, cudaMemcpyDeviceToHost);
// prints the results
cout<<"\n========== GEMM OUTPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<gemm_output_buf[i]<<" ";
}
cout<<'\n';
cout<<"gemm time: " << gemm_t;
cout<<"\n========== MAXPOOL OUTPUT ==========\n";
for (int i = 0; i < maxpool_output_size * maxpool_output_size; ++i) {
if(i%maxpool_output_size==0) cout<<"\n";
cout<<maxpool_output_buf[i]<<" ";
}
cout<<'\n';
cout <<"maxpool time: " <<maxpool_t;
cudaFree(dev_mem_a);
cudaFree(dev_mem_b);
cudaFree(dev_mem_c);
cudaFree(gemm_output);
cudaFree(dev_mem_input);
cudaFree(maxpool_output);
free(gemm_output_buf);
free(maxpool_output_buf);
return 0;
} | code for sm_80
Function : _Z4gemmPfS_S_ffS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ MOV R4, c[0x0][0x188] ; /* 0x0000620000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R12, SR_TID.Y ; /* 0x00000000000c7919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P1, PT, R4, -0xf, PT ; /* 0xfffffff10400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0080*/ S2R R15, SR_TID.X ; /* 0x00000000000f7919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R2, R0, c[0x0][0x4], R12 ; /* 0x0000010000027a24 */
/* 0x001fca00078e020c */
/*00a0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x0], R15 ; /* 0x0000000003037a24 */
/* 0x002fca00078e020f */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x188], P0 ; /* 0x0000620003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x580 ; /* 0x000004a000009947 */
/* 0x000fd80003800000 */
/*00e0*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD R20, R2, c[0x0][0x188], R15 ; /* 0x0000620002147a24 */
/* 0x000fe200078e020f */
/*0100*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*0110*/ IMAD R14, R12.reuse, c[0x0][0x188], R3 ; /* 0x000062000c0e7a24 */
/* 0x040fe200078e0203 */
/*0120*/ SHF.L.U32 R18, R12, 0x6, RZ ; /* 0x000000060c127819 */
/* 0x000fe200000006ff */
/*0130*/ IMAD.WIDE R20, R20, R21, c[0x0][0x160] ; /* 0x0000580014147625 */
/* 0x000fe200078e0215 */
/*0140*/ LEA.HI R4, R4, c[0x0][0x188], RZ, 0x4 ; /* 0x0000620004047a11 */
/* 0x000fe200078f20ff */
/*0150*/ UMOV UR4, 0xffffffff ; /* 0xffffffff00047882 */
/* 0x000fe20000000000 */
/*0160*/ LEA R17, R15, 0x400, 0x2 ; /* 0x000004000f117811 */
/* 0x000fe400078e10ff */
/*0170*/ MOV R13, R21 ; /* 0x00000015000d7202 */
/* 0x000fc40000000f00 */
/*0180*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0190*/ SHF.R.S32.HI R19, RZ, 0x4, R4 ; /* 0x00000004ff137819 */
/* 0x000fe40000011404 */
/*01a0*/ LEA R16, R15, R18, 0x2 ; /* 0x000000120f107211 */
/* 0x000fe400078e10ff */
/*01b0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R4, R14, R5, c[0x0][0x168] ; /* 0x00005a000e047625 */
/* 0x000fca00078e0205 */
/*01d0*/ LDG.E R6, [R4.64] ; /* 0x0000000604067981 */
/* 0x0000a4000c1e1900 */
/*01e0*/ MOV R4, R20 ; /* 0x0000001400047202 */
/* 0x001fe40000000f00 */
/*01f0*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fca0000000f00 */
/*0200*/ LDG.E R25, [R4.64] ; /* 0x0000000604197981 */
/* 0x000ee2000c1e1900 */
/*0210*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x188], PT ; /* 0x000062000f007a0c */
/* 0x000fe20003f26270 */
/*0220*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0230*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x188], PT ; /* 0x000062000c007a0c */
/* 0x000fe40003f46270 */
/*0240*/ ISETP.LT.AND P1, PT, R2, c[0x0][0x188], !P1 ; /* 0x0000620002007a0c */
/* 0x000fe40004f21270 */
/*0250*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x188], P2 ; /* 0x0000620003007a0c */
/* 0x000fe40001746670 */
/*0260*/ IADD3 R12, R12, 0x10, RZ ; /* 0x000000100c0c7810 */
/* 0x000fe40007ffe0ff */
/*0270*/ IADD3 R15, R15, 0x10, RZ ; /* 0x000000100f0f7810 */
/* 0x000fc40007ffe0ff */
/*0280*/ FSEL R29, R6, RZ, !P2 ; /* 0x000000ff061d7208 */
/* 0x004fe40005000000 */
/*0290*/ IADD3 R20, P2, R20, 0x40, RZ ; /* 0x0000004014147810 */
/* 0x000fc60007f5e0ff */
/*02a0*/ STS [R16+0x400], R29 ; /* 0x0004001d10007388 */
/* 0x000fe20000000800 */
/*02b0*/ IADD3.X R13, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff0d7210 */
/* 0x000fc600017fe4ff */
/*02c0*/ STS [R16], R25 ; /* 0x0000001910007388 */
/* 0x008fe80000000800 */
/*02d0*/ @!P1 STS [R16], RZ ; /* 0x000000ff10009388 */
/* 0x000fe80000000800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02f0*/ ISETP.LE.AND P1, PT, R19, UR4, PT ; /* 0x0000000413007c0c */
/* 0x000fca000bf23270 */
/*0300*/ LDS R24, [R17] ; /* 0x0000000011187984 */
/* 0x000fe80000000800 */
/*0310*/ LDS.128 R8, [R18] ; /* 0x0000000012087984 */
/* 0x000e280000000c00 */
/*0320*/ LDS R26, [R17+0x40] ; /* 0x00004000111a7984 */
/* 0x000e680000000800 */
/*0330*/ LDS R27, [R17+0x80] ; /* 0x00008000111b7984 */
/* 0x000ea80000000800 */
/*0340*/ LDS R22, [R17+0xc0] ; /* 0x0000c00011167984 */
/* 0x000ee80000000800 */
/*0350*/ LDS R23, [R17+0x100] ; /* 0x0001000011177984 */
/* 0x000fe80000000800 */
/*0360*/ LDS.128 R4, [R18+0x10] ; /* 0x0000100012047984 */
/* 0x000f280000000c00 */
/*0370*/ LDS R25, [R17+0x180] ; /* 0x0001800011197984 */
/* 0x000fe20000000800 */
/*0380*/ FFMA R8, R24, R8, R21 ; /* 0x0000000818087223 */
/* 0x001fc60000000015 */
/*0390*/ LDS R24, [R17+0x140] ; /* 0x0001400011187984 */
/* 0x000e220000000800 */
/*03a0*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc60000000008 */
/*03b0*/ LDS R26, [R17+0x1c0] ; /* 0x0001c000111a7984 */
/* 0x000e620000000800 */
/*03c0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc60000000008 */
/*03d0*/ LDS R21, [R17+0x200] ; /* 0x0002000011157984 */
/* 0x000fe20000000800 */
/*03e0*/ FFMA R22, R22, R11, R8 ; /* 0x0000000b16167223 */
/* 0x008fc60000000008 */
/*03f0*/ LDS.128 R8, [R18+0x20] ; /* 0x0000200012087984 */
/* 0x000ea20000000c00 */
/*0400*/ FFMA R4, R23, R4, R22 ; /* 0x0000000417047223 */
/* 0x010fc60000000016 */
/*0410*/ LDS R22, [R17+0x240] ; /* 0x0002400011167984 */
/* 0x000ee80000000800 */
/*0420*/ LDS R23, [R17+0x280] ; /* 0x0002800011177984 */
/* 0x000f220000000800 */
/*0430*/ FFMA R4, R24, R5, R4 ; /* 0x0000000518047223 */
/* 0x001fc60000000004 */
/*0440*/ LDS R24, [R17+0x2c0] ; /* 0x0002c00011187984 */
/* 0x000e220000000800 */
/*0450*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc60000000004 */
/*0460*/ LDS R25, [R17+0x300] ; /* 0x0003000011197984 */
/* 0x000fe20000000800 */
/*0470*/ FFMA R26, R26, R7, R4 ; /* 0x000000071a1a7223 */
/* 0x002fc60000000004 */
/*0480*/ LDS.128 R4, [R18+0x30] ; /* 0x0000300012047984 */
/* 0x000e620000000c00 */
/*0490*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x004fc6000000001a */
/*04a0*/ LDS R8, [R17+0x340] ; /* 0x0003400011087984 */
/* 0x000ea80000000800 */
/*04b0*/ LDS R21, [R17+0x380] ; /* 0x0003800011157984 */
/* 0x000f620000000800 */
/*04c0*/ FFMA R9, R22, R9, R26 ; /* 0x0000000916097223 */
/* 0x008fc6000000001a */
/*04d0*/ LDS R22, [R17+0x3c0] ; /* 0x0003c00011167984 */
/* 0x000ee20000000800 */
/*04e0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x010fc80000000009 */
/*04f0*/ FFMA R9, R24, R11, R9 ; /* 0x0000000b18097223 */
/* 0x001fc80000000009 */
/*0500*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x002fc80000000009 */
/*0510*/ FFMA R4, R8, R5, R4 ; /* 0x0000000508047223 */
/* 0x004fe20000000004 */
/*0520*/ MOV R5, c[0x0][0x188] ; /* 0x0000620000057a02 */
/* 0x000fc60000000f00 */
/*0530*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x020fe20000000004 */
/*0540*/ LEA R14, R5, R14, 0x4 ; /* 0x0000000e050e7211 */
/* 0x000fc600078e20ff */
/*0550*/ FFMA R21, R22, R7, R21 ; /* 0x0000000716157223 */
/* 0x008fe20000000015 */
/*0560*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0570*/ @!P1 BRA 0x1b0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0580*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0590*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*05a0*/ IMAD R4, R0, c[0x0][0x4], R5 ; /* 0x0000010000047a24 */
/* 0x001fe200078e0205 */
/*05b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*05c0*/ IMAD R4, R4, c[0x0][0x188], R3 ; /* 0x0000620004047a24 */
/* 0x000fce00078e0203 */
/*05d0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fcc00078e0205 */
/*05e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x180] ; /* 0x0000600004047625 */
/* 0x000fc800078e0205 */
/*0600*/ FMUL R0, R2, c[0x0][0x17c] ; /* 0x00005f0002007a20 */
/* 0x004fc80000400000 */
/*0610*/ FFMA R21, R21, c[0x0][0x178], R0 ; /* 0x00005e0015157a23 */
/* 0x000fca0000000000 */
/*0620*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x000fe2000c101906 */
/*0630*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0640*/ BRA 0x640; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7maxpoolPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0050*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ S2R R6, SR_TID.Y ; /* 0x0000000000067919 */
/* 0x000e240000002200 */
/*0080*/ IMAD R3, R0, c[0x0][0x4], R6 ; /* 0x0000010000037a24 */
/* 0x001fc800078e0206 */
/*0090*/ IMAD R3, R3, c[0x0][0x170], RZ ; /* 0x00005c0003037a24 */
/* 0x000fc800078e02ff */
/*00a0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000f28000c1e1900 */
/*00e0*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000f68000c1e1900 */
/*00f0*/ LDG.E R14, [R4.64+0x10] ; /* 0x00001004040e7981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R16, [R4.64+0x14] ; /* 0x0000140404107981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000ee8000c1e1900 */
/*0120*/ LDG.E R20, [R4.64+0x1c] ; /* 0x00001c0404147981 */
/* 0x000ee8000c1e1900 */
/*0130*/ LDG.E R22, [R4.64+0x20] ; /* 0x0000200404167981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R24, [R4.64+0x24] ; /* 0x0000240404187981 */
/* 0x000f28000c1e1900 */
/*0150*/ LDG.E R26, [R4.64+0x28] ; /* 0x00002804041a7981 */
/* 0x000f22000c1e1900 */
/*0160*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x004e30000020f100 */
/*0170*/ I2F R3, R7 ; /* 0x0000000700037306 */
/* 0x001ee40000201400 */
/*0180*/ FSETP.GT.AND P0, PT, R8, R3, PT ; /* 0x000000030800720b */
/* 0x008fda0003f04000 */
/*0190*/ @P0 F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800080305 */
/* 0x000e30000020f100 */
/*01a0*/ @P0 I2F R3, R8 ; /* 0x0000000800030306 */
/* 0x0011240000201400 */
/*01b0*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0404087981 */
/* 0x001ea2000c1e1900 */
/*01c0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x010fda0003f04000 */
/*01d0*/ @P0 F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a0305 */
/* 0x000e30000020f100 */
/*01e0*/ @P0 I2F R3, R10 ; /* 0x0000000a00030306 */
/* 0x0011640000201400 */
/*01f0*/ LDG.E R10, [R4.64+0x30] ; /* 0x00003004040a7981 */
/* 0x001ee2000c1e1900 */
/*0200*/ FSETP.GT.AND P0, PT, R12, R3, PT ; /* 0x000000030c00720b */
/* 0x020fda0003f04000 */
/*0210*/ @P0 F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c0305 */
/* 0x000e30000020f100 */
/*0220*/ @P0 I2F R3, R12 ; /* 0x0000000c00030306 */
/* 0x0010640000201400 */
/*0230*/ LDG.E R12, [R4.64+0x34] ; /* 0x00003404040c7981 */
/* 0x001f22000c1e1900 */
/*0240*/ FSETP.GT.AND P0, PT, R14, R3, PT ; /* 0x000000030e00720b */
/* 0x002fda0003f04000 */
/*0250*/ @P0 F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e0305 */
/* 0x000e30000020f100 */
/*0260*/ @P0 I2F R3, R14 ; /* 0x0000000e00030306 */
/* 0x0010640000201400 */
/*0270*/ LDG.E R14, [R4.64+0x38] ; /* 0x00003804040e7981 */
/* 0x001f62000c1e1900 */
/*0280*/ FSETP.GT.AND P0, PT, R16, R3, PT ; /* 0x000000031000720b */
/* 0x002fda0003f04000 */
/*0290*/ @P0 F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000100305 */
/* 0x000e30000020f100 */
/*02a0*/ @P0 I2F R3, R16 ; /* 0x0000001000030306 */
/* 0x0010640000201400 */
/*02b0*/ LDG.E R16, [R4.64+0x3c] ; /* 0x00003c0404107981 */
/* 0x001f22000c1e1900 */
/*02c0*/ FSETP.GT.AND P0, PT, R18, R3, PT ; /* 0x000000031200720b */
/* 0x002fda0003f04000 */
/*02d0*/ @P0 F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200120305 */
/* 0x000e30000020f100 */
/*02e0*/ @P0 I2F R3, R18 ; /* 0x0000001200030306 */
/* 0x001e240000201400 */
/*02f0*/ FSETP.GT.AND P0, PT, R20, R3, PT ; /* 0x000000031400720b */
/* 0x001fda0003f04000 */
/*0300*/ @P0 F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400140305 */
/* 0x000e30000020f100 */
/*0310*/ @P0 I2F R3, R20 ; /* 0x0000001400030306 */
/* 0x001e240000201400 */
/*0320*/ FSETP.GT.AND P0, PT, R22, R3, PT ; /* 0x000000031600720b */
/* 0x001fda0003f04000 */
/*0330*/ @P0 F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600160305 */
/* 0x000e30000020f100 */
/*0340*/ @P0 I2F R3, R22 ; /* 0x0000001600030306 */
/* 0x001e240000201400 */
/*0350*/ FSETP.GT.AND P0, PT, R24, R3, PT ; /* 0x000000031800720b */
/* 0x001fda0003f04000 */
/*0360*/ @P0 F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800180305 */
/* 0x000e30000020f100 */
/*0370*/ @P0 I2F R3, R24 ; /* 0x0000001800030306 */
/* 0x001e240000201400 */
/*0380*/ FSETP.GT.AND P0, PT, R26, R3, PT ; /* 0x000000031a00720b */
/* 0x001fda0003f04000 */
/*0390*/ @P0 F2I.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a0305 */
/* 0x000e30000020f100 */
/*03a0*/ @P0 I2F R3, R26 ; /* 0x0000001a00030306 */
/* 0x001ea40000201400 */
/*03b0*/ FSETP.GT.AND P0, PT, R8, R3, PT ; /* 0x000000030800720b */
/* 0x004fda0003f04000 */
/*03c0*/ @P0 F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800080305 */
/* 0x000e30000020f100 */
/*03d0*/ @P0 I2F R3, R8 ; /* 0x0000000800030306 */
/* 0x001ee40000201400 */
/*03e0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x008fda0003f04000 */
/*03f0*/ @P0 F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a0305 */
/* 0x000e30000020f100 */
/*0400*/ @P0 I2F R3, R10 ; /* 0x0000000a00030306 */
/* 0x001f240000201400 */
/*0410*/ FSETP.GT.AND P0, PT, R12, R3, PT ; /* 0x000000030c00720b */
/* 0x010fda0003f04000 */
/*0420*/ @P0 F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c0305 */
/* 0x000e30000020f100 */
/*0430*/ @P0 I2F R3, R12 ; /* 0x0000000c00030306 */
/* 0x001f640000201400 */
/*0440*/ FSETP.GT.AND P0, PT, R14, R3, PT ; /* 0x000000030e00720b */
/* 0x020fda0003f04000 */
/*0450*/ @P0 F2I.TRUNC.NTZ R14, R14 ; /* 0x0000000e000e0305 */
/* 0x000e30000020f100 */
/*0460*/ @P0 I2F R3, R14 ; /* 0x0000000e00030306 */
/* 0x001e240000201400 */
/*0470*/ FSETP.GT.AND P0, PT, R16, R3, PT ; /* 0x000000031000720b */
/* 0x001fda0003f04000 */
/*0480*/ @P0 F2I.TRUNC.NTZ R16, R16 ; /* 0x0000001000100305 */
/* 0x000e30000020f100 */
/*0490*/ @P0 I2F R3, R16 ; /* 0x0000001000030306 */
/* 0x001e220000201400 */
/*04a0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*04b0*/ STS [R6.X4], R3 ; /* 0x0000000306007388 */
/* 0x0011e80000004800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*04d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04e0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x001e280000000c00 */
/*04f0*/ LDS.128 R4, [0x10] ; /* 0x00001000ff047984 */
/* 0x000e620000000c00 */
/*0500*/ FSETP.GT.AND P0, PT, R9, R3, PT ; /* 0x000000030900720b */
/* 0x001fda0003f04000 */
/*0510*/ @P0 F2I.TRUNC.NTZ R8, R9 ; /* 0x0000000900080305 */
/* 0x000e30000020f100 */
/*0520*/ @P0 I2F R3, R8 ; /* 0x0000000800030306 */
/* 0x001e240000201400 */
/*0530*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x001fda0003f04000 */
/*0540*/ @P0 F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a0305 */
/* 0x000e30000020f100 */
/*0550*/ @P0 I2F R3, R10 ; /* 0x0000000a00030306 */
/* 0x001e240000201400 */
/*0560*/ FSETP.GT.AND P0, PT, R11, R3, PT ; /* 0x000000030b00720b */
/* 0x001fda0003f04000 */
/*0570*/ @P0 F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b0305 */
/* 0x000e30000020f100 */
/*0580*/ @P0 I2F R3, R11 ; /* 0x0000000b00030306 */
/* 0x0010640000201400 */
/*0590*/ LDS.128 R8, [0x20] ; /* 0x00002000ff087984 */
/* 0x001e220000000c00 */
/*05a0*/ FSETP.GT.AND P0, PT, R4, R3, PT ; /* 0x000000030400720b */
/* 0x002fda0003f04000 */
/*05b0*/ @P0 F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400040305 */
/* 0x000e70000020f100 */
/*05c0*/ @P0 I2F R3, R4 ; /* 0x0000000400030306 */
/* 0x002e640000201400 */
/*05d0*/ FSETP.GT.AND P0, PT, R5, R3, PT ; /* 0x000000030500720b */
/* 0x002fda0003f04000 */
/*05e0*/ @P0 F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500050305 */
/* 0x000e70000020f100 */
/*05f0*/ @P0 I2F R3, R5 ; /* 0x0000000500030306 */
/* 0x002e640000201400 */
/*0600*/ FSETP.GT.AND P0, PT, R6, R3, PT ; /* 0x000000030600720b */
/* 0x002fda0003f04000 */
/*0610*/ @P0 F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600060305 */
/* 0x000e70000020f100 */
/*0620*/ @P0 I2F R3, R6 ; /* 0x0000000600030306 */
/* 0x002e640000201400 */
/*0630*/ FSETP.GT.AND P0, PT, R7, R3, PT ; /* 0x000000030700720b */
/* 0x002fda0003f04000 */
/*0640*/ @P0 F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700070305 */
/* 0x000e70000020f100 */
/*0650*/ @P0 I2F R3, R7 ; /* 0x0000000700030306 */
/* 0x0022240000201400 */
/*0660*/ LDS.128 R4, [0x30] ; /* 0x00003000ff047984 */
/* 0x002e620000000c00 */
/*0670*/ FSETP.GT.AND P0, PT, R8, R3, PT ; /* 0x000000030800720b */
/* 0x001fda0003f04000 */
/*0680*/ @P0 F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800080305 */
/* 0x000e30000020f100 */
/*0690*/ @P0 I2F R3, R8 ; /* 0x0000000800030306 */
/* 0x001e240000201400 */
/*06a0*/ FSETP.GT.AND P0, PT, R9, R3, PT ; /* 0x000000030900720b */
/* 0x001fda0003f04000 */
/*06b0*/ @P0 F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900090305 */
/* 0x000e30000020f100 */
/*06c0*/ @P0 I2F R3, R9 ; /* 0x0000000900030306 */
/* 0x0010a40000201400 */
/*06d0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x001e220000002500 */
/*06e0*/ FSETP.GT.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720b */
/* 0x004fda0003f04000 */
/*06f0*/ @P0 F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a0305 */
/* 0x000ea2000020f100 */
/*0700*/ IMAD R9, R0, 0x10, R9 ; /* 0x0000001000097824 */
/* 0x001fc800078e0209 */
/*0710*/ IMAD.WIDE.U32 R8, R9, R2, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fc600078e0002 */
/*0720*/ @P0 I2F R3, R10 ; /* 0x0000000a00030306 */
/* 0x004e240000201400 */
/*0730*/ FSETP.GT.AND P0, PT, R11, R3, PT ; /* 0x000000030b00720b */
/* 0x001fda0003f04000 */
/*0740*/ @P0 F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b0305 */
/* 0x000e30000020f100 */
/*0750*/ @P0 I2F R3, R11 ; /* 0x0000000b00030306 */
/* 0x001e640000201400 */
/*0760*/ FSETP.GT.AND P0, PT, R4, R3, PT ; /* 0x000000030400720b */
/* 0x002fda0003f04000 */
/*0770*/ @P0 F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400040305 */
/* 0x000e30000020f100 */
/*0780*/ @P0 I2F R3, R4 ; /* 0x0000000400030306 */
/* 0x001e240000201400 */
/*0790*/ FSETP.GT.AND P0, PT, R5, R3, PT ; /* 0x000000030500720b */
/* 0x001fda0003f04000 */
/*07a0*/ @P0 F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500050305 */
/* 0x000e30000020f100 */
/*07b0*/ @P0 I2F R3, R5 ; /* 0x0000000500030306 */
/* 0x001e240000201400 */
/*07c0*/ FSETP.GT.AND P0, PT, R6, R3, PT ; /* 0x000000030600720b */
/* 0x001fda0003f04000 */
/*07d0*/ @P0 F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600060305 */
/* 0x000e30000020f100 */
/*07e0*/ @P0 I2F R3, R6 ; /* 0x0000000600030306 */
/* 0x001e240000201400 */
/*07f0*/ FSETP.GT.AND P0, PT, R7, R3, PT ; /* 0x000000030700720b */
/* 0x001fda0003f04000 */
/*0800*/ @P0 F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700070305 */
/* 0x000e30000020f100 */
/*0810*/ @P0 I2F R3, R7 ; /* 0x0000000700030306 */
/* 0x001e240000201400 */
/*0820*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x001fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Find BLANK and replace your own code.
* And submit report why do you replace the blank that way.
*/
#include<stdlib.h>
#include<iostream>
#include<fstream>
#include<vector>
#include<string>
#define TILE_WIDTH 16 /* set TILE_WIDTH 16 for the evaluation! */
#define MAXPOOL_INPUT_FILENAME "input.txt"
#define A_FILENAME "a.txt"
#define B_FILENAME "b.txt"
#define C_FILENAME "c.txt"
using namespace std;
__global__ void maxpool(float *input, float *output, const int input_size, const int filter_size) {
// input : input_matrix address
// output : output buffer address
// input_size : width, height of input matrix
// filter_size : filter_size of maxpolling
// all input, output matrices are vectorized
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
int large = 0;
__shared__ float s_large[TILE_WIDTH];
if(threadIdx.x == 0){
large = input[input_size*row];
for(int i = 1; i < TILE_WIDTH; i++){
if (large < input[input_size*row+i]){
large = input[input_size*row+i];
}
}
s_large[threadIdx.y] = large;
}else{
return;
}
__syncthreads();
if(threadIdx.x == 0 && threadIdx.y == 0){
for(int i = 1; i < TILE_WIDTH; i++){
if(large < s_large[i]){
large = s_large[i];
}
}
output[blockIdx.y*TILE_WIDTH + blockIdx.x] = large;
}else{
return;
}
}
// a, b, c : input matrix address
// alpha, beta : input constant
// output : output buffer address
// input_size : width, height of input matrix
// all input, output matrices are vectorized
__global__ void gemm(float *a, float *b, float *c, const float alpha, const float beta, float *output, const int input_s){
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int row = by*blockDim.y + ty;
int col = bx*blockDim.x + tx;
int input_size = input_s;
int a_default = input_size*row +tx;
int b_default = input_size*ty + col;
//if(row>=input_size ||col>=input_size) { return; }
// allocate 2D tiles in __shared__ memory
__shared__ float s_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float s_b[TILE_WIDTH][TILE_WIDTH];
float result = 0;
for(int p = 0; p < input_size / TILE_WIDTH + 1; ++p){
s_a[ty][tx] = a[a_default + p*TILE_WIDTH];
s_b[ty][tx] = b[b_default + p*input_size*TILE_WIDTH];
if(col >= input_size || p*TILE_WIDTH + ty >= input_size){
s_b[ty][tx] = 0;
}
if(row >= input_size || p*TILE_WIDTH + tx >= input_size){
s_a[ty][tx] = 0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH;i++){
result += (s_a[ty][i]*s_b[i][tx]);
}
__syncthreads();
}
if(col < input_size && row < input_size){
output[row*input_size + col] = alpha * result + beta * c[row*input_size + col];
}
}
int main(int argc, char **argv) {
if(argc < 4) {
cout << "usage : " << argv[0] << " input_size filter_size alpha beta\n" << "example : " << argv[0] << " 100 2 0.5 0.8\n";
return 1;
}
const int input_size = stoi(argv[1]);
const int filter_size = stoi(argv[2]); // used for maxpooling
const float alpha = stof(argv[3]);
const float beta = stof(argv[4]);
const int maxpool_output_size = input_size/filter_size;
// check input_size is power of 2
if(input_size == 0 && (input_size & (input_size-1))){
cout << "input_size must be power of 2\n";
return 1;
}
if(filter_size == 0){
cout << "filter_size cannot be 0\n";
return 1;
}
float maxpool_input[input_size*input_size];
float a[input_size*input_size];
float b[input_size*input_size];
float c[input_size*input_size];
// read input matrices
ifstream input_in(MAXPOOL_INPUT_FILENAME);
ifstream a_in(A_FILENAME);
ifstream b_in(B_FILENAME);
ifstream c_in(C_FILENAME);
for (int i = 0; i < input_size*input_size; ++i) {
input_in >> maxpool_input[i];
a_in >> a[i];
b_in >> b[i];
c_in >> c[i];
}
// prints inputs for debugging.
cout<<"filter size : "<<filter_size;
cout<<"\n========== MAXPOOL_INPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<maxpool_input[i]<<" ";
}
cout<<"\nalpha : "<<alpha<<'\n';
cout<<"========== A ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<a[i]<<" ";
}
cout<<"\n========== B ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<b[i]<<" ";
}
cout<<"\nbeta : "<<beta<<'\n';
cout<<"========== C ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<c[i]<<" ";
}
cout<<'\n';
// set thread, block dimensions
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
cout<<block_size.x;
const dim3 num_of_maxpool_blocks(input_size / block_size.x, input_size/ block_size.y);
const dim3 num_of_blocks(input_size/block_size.x+1, input_size/block_size.y+1);
// memory allocation for the device
float *dev_mem_a, *dev_mem_b, *dev_mem_c, *dev_mem_input, *gemm_output, *maxpool_output;
cudaMalloc(&dev_mem_a, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_b, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_c, sizeof(float) * input_size * input_size);
cudaMalloc(&gemm_output, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_input, sizeof(float) * input_size * input_size);
cudaMalloc(&maxpool_output, sizeof(float) * maxpool_output_size * maxpool_output_size);
// copy variable to device memory
cudaMemcpy(dev_mem_a, &a, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_b, &b, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_c, &c, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_input, &maxpool_input, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaEvent_t gemm_start, gemm_stop, maxpool_start, maxpool_stop;
cudaEventCreate(&gemm_start);
cudaEventCreate(&gemm_stop);
cudaEventCreate(&maxpool_start);
cudaEventCreate(&maxpool_stop);
// launch CUDA kernels
// First launch gemm kernel
cudaEventRecord(gemm_start);
gemm<<<num_of_blocks, block_size>>>(dev_mem_a, dev_mem_b, dev_mem_c, alpha, beta, gemm_output, input_size);
cudaEventRecord(gemm_stop);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(gemm_stop);
float gemm_t = 0;
cudaEventElapsedTime(&gemm_t,gemm_start,gemm_stop);
// Then run maxpooling
cudaEventRecord(maxpool_start);
maxpool<<<num_of_maxpool_blocks, block_size>>>(dev_mem_input, maxpool_output, input_size, filter_size);
cudaEventRecord(maxpool_stop);
cudaDeviceSynchronize();
//cudaError_t error = cudaGetLastError();
error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(maxpool_stop);
float maxpool_t = 0;
cudaEventElapsedTime(&maxpool_t, maxpool_start, maxpool_stop);
// allocate output buf in main memory
float *gemm_output_buf = (float*) malloc (sizeof(float)*input_size*input_size);
float *maxpool_output_buf = (float*) malloc (sizeof(float)*maxpool_output_size*maxpool_output_size);
// copy results from device to host
cudaMemcpy(gemm_output_buf, gemm_output, sizeof(float)*input_size*input_size, cudaMemcpyDeviceToHost);
cudaMemcpy(maxpool_output_buf, maxpool_output, sizeof(float)*maxpool_output_size*maxpool_output_size, cudaMemcpyDeviceToHost);
// prints the results
cout<<"\n========== GEMM OUTPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<gemm_output_buf[i]<<" ";
}
cout<<'\n';
cout<<"gemm time: " << gemm_t;
cout<<"\n========== MAXPOOL OUTPUT ==========\n";
for (int i = 0; i < maxpool_output_size * maxpool_output_size; ++i) {
if(i%maxpool_output_size==0) cout<<"\n";
cout<<maxpool_output_buf[i]<<" ";
}
cout<<'\n';
cout <<"maxpool time: " <<maxpool_t;
cudaFree(dev_mem_a);
cudaFree(dev_mem_b);
cudaFree(dev_mem_c);
cudaFree(gemm_output);
cudaFree(dev_mem_input);
cudaFree(maxpool_output);
free(gemm_output_buf);
free(maxpool_output_buf);
return 0;
} | .file "tmpxft_00049808_00000000-6_hw6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4166:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4166:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii
.type _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii, @function
_Z30__device_stub__Z7maxpoolPfS_iiPfS_ii:
.LFB4188:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7maxpoolPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4188:
.size _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii, .-_Z30__device_stub__Z7maxpoolPfS_iiPfS_ii
.globl _Z7maxpoolPfS_ii
.type _Z7maxpoolPfS_ii, @function
_Z7maxpoolPfS_ii:
.LFB4189:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4189:
.size _Z7maxpoolPfS_ii, .-_Z7maxpoolPfS_ii
.globl _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i
.type _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i, @function
_Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i:
.LFB4190:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z4gemmPfS_S_ffS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4190:
.size _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i, .-_Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i
.globl _Z4gemmPfS_S_ffS_i
.type _Z4gemmPfS_S_ffS_i, @function
_Z4gemmPfS_S_ffS_i:
.LFB4191:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4191:
.size _Z4gemmPfS_S_ffS_i, .-_Z4gemmPfS_S_ffS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4gemmPfS_S_ffS_i"
.LC1:
.string "_Z7maxpoolPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4193:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4gemmPfS_S_ffS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7maxpoolPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4193:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4267:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4267
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rcx
cmpq %rbp, %rcx
je .L35
cmpl $34, (%rbx)
je .L24
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L24
testq %r12, %r12
je .L27
subq %rbp, %rcx
movq %rcx, (%r12)
.L27:
cmpl $0, (%rbx)
jne .L21
movl %r15d, (%rbx)
.L21:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L37
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L37:
call __stack_chk_fail@PLT
.L24:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L38
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L33:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L30
movl %r15d, (%rbx)
.L30:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L31
call __stack_chk_fail@PLT
.L38:
call __stack_chk_fail@PLT
.L31:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4267:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4267:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4267-.LLSDACSB4267
.LLSDACSB4267:
.uleb128 .LEHB0-.LFB4267
.uleb128 .LEHE0-.LEHB0
.uleb128 .L33-.LFB4267
.uleb128 0
.uleb128 .LEHB1-.LFB4267
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4267:
.section .text._ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .text._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB4312:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4312
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbp
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r13d
movl $0, (%rax)
movq %rsp, %rsi
movq %rbp, %rdi
.LEHB2:
call *%r15
movq (%rsp), %rax
cmpq %rbp, %rax
je .L52
cmpl $34, (%rbx)
je .L53
testq %r12, %r12
je .L44
subq %rbp, %rax
movq %rax, (%r12)
.L44:
cmpl $0, (%rbx)
jne .L39
movl %r13d, (%rbx)
.L39:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L55
movq %r14, %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L50:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L47
movl %r13d, (%rbx)
.L47:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L55:
call __stack_chk_fail@PLT
.L53:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L56
movq %r14, %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE2:
.L56:
call __stack_chk_fail@PLT
.L48:
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4312:
.section .gcc_except_table._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA4312:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4312-.LLSDACSB4312
.LLSDACSB4312:
.uleb128 .LEHB2-.LFB4312
.uleb128 .LEHE2-.LEHB2
.uleb128 .L50-.LFB4312
.uleb128 0
.uleb128 .LEHB3-.LFB4312
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4312:
.section .text._ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4511:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L66
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L67
cmpq $1, %rax
jne .L62
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L63:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L69
leaq .LC2(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L69:
call __stack_chk_fail@PLT
.L67:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L61:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L63
.L62:
testq %rax, %rax
je .L63
jmp .L61
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4511:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC3:
.string "usage : "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string " input_size filter_size alpha beta\n"
.section .rodata.str1.1
.LC5:
.string "example : "
.LC6:
.string " 100 2 0.5 0.8\n"
.LC7:
.string "stoi"
.LC8:
.string "stof"
.LC9:
.string "filter_size cannot be 0\n"
.LC10:
.string "input.txt"
.LC11:
.string "a.txt"
.LC12:
.string "b.txt"
.LC13:
.string "c.txt"
.LC14:
.string "filter size : "
.section .rodata.str1.8
.align 8
.LC15:
.string "\n========== MAXPOOL_INPUT ==========\n"
.section .rodata.str1.1
.LC16:
.string "\n"
.LC17:
.string " "
.LC18:
.string "\nalpha : "
.LC19:
.string "========== A ==========\n"
.LC20:
.string "\n========== B ==========\n"
.LC21:
.string "\nbeta : "
.LC22:
.string "========== C ==========\n"
.LC23:
.string "ERROR %s\n"
.section .rodata.str1.8
.align 8
.LC25:
.string "\n========== GEMM OUTPUT ==========\n"
.section .rodata.str1.1
.LC26:
.string "gemm time: "
.section .rodata.str1.8
.align 8
.LC27:
.string "\n========== MAXPOOL OUTPUT ==========\n"
.section .rodata.str1.1
.LC28:
.string "maxpool time: "
.text
.globl main
.type main, @function
main:
.LFB4163:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4163
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $2328, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $3, %edi
jle .L145
leaq -2172(%rbp), %rdx
movq 8(%rsi), %rsi
leaq -576(%rbp), %rdi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $10, %r8d
movl $0, %ecx
movq -576(%rbp), %rdx
leaq .LC7(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
jmp .L146
.L145:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB6:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ebx
jmp .L70
.L146:
movl %eax, %r15d
leaq -576(%rbp), %r12
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -2172(%rbp), %rdx
movq 16(%rbx), %rsi
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $10, %r8d
movl $0, %ecx
movq -576(%rbp), %rdx
leaq .LC7(%rip), %rsi
movq __isoc23_strtol@GOTPCREL(%rip), %rdi
.LEHB7:
call _ZN9__gnu_cxx6__stoaIlicJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE7:
movl %eax, %r14d
movl %eax, -2352(%rbp)
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -2172(%rbp), %rdx
movq 24(%rbx), %rsi
movq %r12, %rdi
.LEHB8:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE8:
movl $0, %ecx
movq -576(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq strtof@GOTPCREL(%rip), %rdi
.LEHB9:
call _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE9:
movss %xmm0, -2356(%rbp)
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq -2172(%rbp), %rdx
movq 32(%rbx), %rsi
movq %r12, %rdi
.LEHB10:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE10:
movl $0, %ecx
movq -576(%rbp), %rdx
leaq .LC8(%rip), %rsi
movq strtof@GOTPCREL(%rip), %rdi
.LEHB11:
call _ZN9__gnu_cxx6__stoaIffcJEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE11:
movss %xmm0, -2360(%rbp)
movq %r12, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
testl %r14d, %r14d
je .L147
movl %r15d, %eax
imull %r15d, %eax
movl %eax, -2348(%rbp)
cltq
movq %rax, -2296(%rbp)
salq $2, %rax
movq %rax, -2336(%rbp)
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L74:
cmpq %rdx, %rsp
je .L75
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L74
.L147:
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB12:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %ebx
jmp .L70
.L75:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L76
orq $0, -8(%rsp,%rax)
.L76:
movq %rsp, -2304(%rbp)
movq -2336(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L77:
cmpq %rdx, %rsp
je .L78
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L77
.L78:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L79
orq $0, -8(%rsp,%rax)
.L79:
movq %rsp, -2312(%rbp)
movq -2336(%rbp), %rax
addq $15, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L80:
cmpq %rdx, %rsp
je .L81
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L80
.L81:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L82
orq $0, -8(%rsp,%rax)
.L82:
movq %rsp, -2320(%rbp)
movq -2336(%rbp), %rax
addq $15, %rax
movq %rax, %rdx
andq $-16, %rdx
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L83:
cmpq %rcx, %rsp
je .L84
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L83
.L84:
movq %rdx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L85
orq $0, -8(%rsp,%rax)
.L85:
movq %rsp, %r12
movq %r12, -2328(%rbp)
leaq -2160(%rbp), %rdi
movl $8, %edx
leaq .LC10(%rip), %rsi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE12:
leaq -1632(%rbp), %rdi
movl $8, %edx
leaq .LC11(%rip), %rsi
.LEHB13:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE13:
leaq -1104(%rbp), %rdi
movl $8, %edx
leaq .LC12(%rip), %rsi
.LEHB14:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE14:
leaq -576(%rbp), %rdi
movl $8, %edx
leaq .LC13(%rip), %rsi
.LEHB15:
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE15:
cmpl $0, -2348(%rbp)
jle .L86
movq -2304(%rbp), %rcx
movq %rcx, %rbx
movq -2320(%rbp), %r14
movq -2312(%rbp), %r13
movq -2336(%rbp), %rax
addq %rcx, %rax
movq %rax, -2336(%rbp)
leaq -2160(%rbp), %rax
movq %rax, -2344(%rbp)
jmp .L87
.L148:
leaq -1632(%rbp), %rdi
movq %r13, %rsi
.LEHB16:
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq -1104(%rbp), %rdi
movq %r14, %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
leaq -576(%rbp), %rdi
movq %r12, %rsi
call _ZNSi10_M_extractIfEERSiRT_@PLT
addq $4, %rbx
addq $4, %r12
addq $4, %r14
addq $4, %r13
movq -2336(%rbp), %rax
cmpq %rax, %rbx
je .L86
.L87:
movq %rbx, %rsi
movq -2344(%rbp), %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L148
.L86:
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl -2352(%rbp), %esi
call _ZNSolsEi@PLT
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -2348(%rbp)
jle .L88
movl $0, %ebx
leaq .LC16(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC17(%rip), %r13
jmp .L90
.L89:
movq -2304(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, -2296(%rbp)
je .L88
.L90:
movl %ebx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .L89
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L89
.L88:
leaq .LC18(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -2356(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -2348(%rbp)
jle .L91
movl $0, %ebx
leaq .LC16(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC17(%rip), %r13
jmp .L93
.L92:
movq -2312(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, -2296(%rbp)
je .L91
.L93:
movl %ebx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .L92
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L92
.L91:
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -2348(%rbp)
jle .L94
movl $0, %ebx
leaq .LC16(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC17(%rip), %r13
jmp .L96
.L95:
movq -2320(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, -2296(%rbp)
je .L94
.L96:
movl %ebx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .L95
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L95
.L94:
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -2360(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC22(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -2348(%rbp)
jle .L97
movl $0, %ebx
leaq .LC16(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC17(%rip), %r13
jmp .L99
.L98:
movq -2328(%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, -2296(%rbp)
je .L97
.L99:
movl %ebx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .L98
movl $1, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L98
.L97:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $1, -2188(%rbp)
movl $16, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movl %r15d, %eax
shrl $4, %eax
movl %eax, -2184(%rbp)
movl %eax, -2180(%rbp)
movl $1, -2176(%rbp)
addl $1, %eax
movl %eax, -2172(%rbp)
movl %eax, -2168(%rbp)
movl $1, -2164(%rbp)
movslq %r15d, %rbx
imulq %rbx, %rbx
salq $2, %rbx
leaq -2280(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -2272(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -2264(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -2248(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -2256(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %r15d, %eax
cltd
idivl -2352(%rbp)
movl %eax, -2344(%rbp)
movl %eax, -2336(%rbp)
cltq
imulq %rax, %rax
leaq 0(,%rax,4), %r12
leaq -2240(%rbp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -2312(%rbp), %rsi
movq -2280(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -2320(%rbp), %rsi
movq -2272(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -2328(%rbp), %rsi
movq -2264(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq -2304(%rbp), %rsi
movq -2256(%rbp), %rdi
call cudaMemcpy@PLT
leaq -2232(%rbp), %rdi
call cudaEventCreate@PLT
leaq -2224(%rbp), %rdi
call cudaEventCreate@PLT
leaq -2216(%rbp), %rdi
call cudaEventCreate@PLT
leaq -2208(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -2232(%rbp), %rdi
call cudaEventRecord@PLT
movl $16, -2196(%rbp)
movl $16, -2192(%rbp)
movl -2188(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -2196(%rbp), %rdx
movq -2172(%rbp), %rdi
movl -2164(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L100
movl %r15d, %r8d
movq -2248(%rbp), %rcx
movss -2360(%rbp), %xmm1
movss -2356(%rbp), %xmm0
movq -2264(%rbp), %rdx
movq -2272(%rbp), %rsi
movq -2280(%rbp), %rdi
call _Z32__device_stub__Z4gemmPfS_S_ffS_iPfS_S_ffS_i
.L100:
movl $0, %esi
movq -2224(%rbp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L149
movq -2224(%rbp), %rdi
call cudaEventSynchronize@PLT
jmp .L150
.L149:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L151
.L150:
movl $0x00000000, -2288(%rbp)
leaq -2288(%rbp), %rdi
movq -2224(%rbp), %rdx
movq -2232(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -2216(%rbp), %rdi
call cudaEventRecord@PLT
movl -2188(%rbp), %ecx
movl $0, %r9d
movl $0, %r8d
movq -2196(%rbp), %rdx
movq -2184(%rbp), %rdi
movl -2176(%rbp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L103
movl -2352(%rbp), %ecx
movl %r15d, %edx
movq -2240(%rbp), %rsi
movq -2256(%rbp), %rdi
call _Z30__device_stub__Z7maxpoolPfS_iiPfS_ii
.L103:
movl $0, %esi
movq -2208(%rbp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L152
movq -2208(%rbp), %rdi
call cudaEventSynchronize@PLT
jmp .L153
.L152:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC23(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L154
.L153:
movl $0x00000000, -2284(%rbp)
leaq -2284(%rbp), %rdi
movq -2208(%rbp), %rdx
movq -2216(%rbp), %rsi
call cudaEventElapsedTime@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movq %rbx, %rdx
movq -2248(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq %r12, %rdx
movq -2240(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC25(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -2348(%rbp)
jle .L105
movl $0, %ebx
leaq _ZSt4cout(%rip), %r12
jmp .L107
.L106:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
addq $1, %rbx
cmpq %rbx, -2296(%rbp)
je .L105
.L107:
movl %ebx, %eax
cltd
idivl %r15d
testl %edx, %edx
jne .L106
leaq .LC16(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L106
.L105:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC26(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -2288(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
leaq .LC27(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl -2344(%rbp), %r15d
imull %r15d, %r15d
testl %r15d, %r15d
jle .L108
movslq %r15d, %r12
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
jmp .L110
.L109:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r15, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
addq $1, %rbx
cmpq %r12, %rbx
je .L108
.L110:
movl %ebx, %eax
cltd
idivl -2336(%rbp)
testl %edx, %edx
jne .L109
leaq .LC16(%rip), %rsi
movq %r15, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L109
.L108:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC28(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -2284(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq -2280(%rbp), %rdi
call cudaFree@PLT
movq -2272(%rbp), %rdi
call cudaFree@PLT
movq -2264(%rbp), %rdi
call cudaFree@PLT
movq -2248(%rbp), %rdi
call cudaFree@PLT
movq -2256(%rbp), %rdi
call cudaFree@PLT
movq -2240(%rbp), %rdi
call cudaFree@PLT
.LEHE16:
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movl $0, %ebx
.L102:
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -1104(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -1632(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq -2160(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L70:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L155
movl %ebx, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L151:
.cfi_restore_state
movl $1, %ebx
jmp .L102
.L154:
movl $1, %ebx
jmp .L102
.L127:
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L112
call __stack_chk_fail@PLT
.L112:
movq %rbx, %rdi
.LEHB17:
call _Unwind_Resume@PLT
.L128:
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L114
call __stack_chk_fail@PLT
.L114:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L129:
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L116
call __stack_chk_fail@PLT
.L116:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L130:
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L118
call __stack_chk_fail@PLT
.L118:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L134:
endbr64
movq %rax, %rbx
leaq -576(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L120:
leaq -1104(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L121:
leaq -1632(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L122:
leaq -2160(%rbp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
je .L123
call __stack_chk_fail@PLT
.L133:
endbr64
movq %rax, %rbx
jmp .L120
.L132:
endbr64
movq %rax, %rbx
jmp .L121
.L131:
endbr64
movq %rax, %rbx
jmp .L122
.L123:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE17:
.L155:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4163:
.section .gcc_except_table,"a",@progbits
.LLSDA4163:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4163-.LLSDACSB4163
.LLSDACSB4163:
.uleb128 .LEHB4-.LFB4163
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB4163
.uleb128 .LEHE5-.LEHB5
.uleb128 .L127-.LFB4163
.uleb128 0
.uleb128 .LEHB6-.LFB4163
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB4163
.uleb128 .LEHE7-.LEHB7
.uleb128 .L128-.LFB4163
.uleb128 0
.uleb128 .LEHB8-.LFB4163
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB4163
.uleb128 .LEHE9-.LEHB9
.uleb128 .L129-.LFB4163
.uleb128 0
.uleb128 .LEHB10-.LFB4163
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB4163
.uleb128 .LEHE11-.LEHB11
.uleb128 .L130-.LFB4163
.uleb128 0
.uleb128 .LEHB12-.LFB4163
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.uleb128 .LEHB13-.LFB4163
.uleb128 .LEHE13-.LEHB13
.uleb128 .L131-.LFB4163
.uleb128 0
.uleb128 .LEHB14-.LFB4163
.uleb128 .LEHE14-.LEHB14
.uleb128 .L132-.LFB4163
.uleb128 0
.uleb128 .LEHB15-.LFB4163
.uleb128 .LEHE15-.LEHB15
.uleb128 .L133-.LFB4163
.uleb128 0
.uleb128 .LEHB16-.LFB4163
.uleb128 .LEHE16-.LEHB16
.uleb128 .L134-.LFB4163
.uleb128 0
.uleb128 .LEHB17-.LFB4163
.uleb128 .LEHE17-.LEHB17
.uleb128 0
.uleb128 0
.LLSDACSE4163:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Find BLANK and replace your own code.
* And submit report why do you replace the blank that way.
*/
#include<stdlib.h>
#include<iostream>
#include<fstream>
#include<vector>
#include<string>
#define TILE_WIDTH 16 /* set TILE_WIDTH 16 for the evaluation! */
#define MAXPOOL_INPUT_FILENAME "input.txt"
#define A_FILENAME "a.txt"
#define B_FILENAME "b.txt"
#define C_FILENAME "c.txt"
using namespace std;
__global__ void maxpool(float *input, float *output, const int input_size, const int filter_size) {
// input : input_matrix address
// output : output buffer address
// input_size : width, height of input matrix
// filter_size : filter_size of maxpolling
// all input, output matrices are vectorized
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
int large = 0;
__shared__ float s_large[TILE_WIDTH];
if(threadIdx.x == 0){
large = input[input_size*row];
for(int i = 1; i < TILE_WIDTH; i++){
if (large < input[input_size*row+i]){
large = input[input_size*row+i];
}
}
s_large[threadIdx.y] = large;
}else{
return;
}
__syncthreads();
if(threadIdx.x == 0 && threadIdx.y == 0){
for(int i = 1; i < TILE_WIDTH; i++){
if(large < s_large[i]){
large = s_large[i];
}
}
output[blockIdx.y*TILE_WIDTH + blockIdx.x] = large;
}else{
return;
}
}
// a, b, c : input matrix address
// alpha, beta : input constant
// output : output buffer address
// input_size : width, height of input matrix
// all input, output matrices are vectorized
__global__ void gemm(float *a, float *b, float *c, const float alpha, const float beta, float *output, const int input_s){
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int row = by*blockDim.y + ty;
int col = bx*blockDim.x + tx;
int input_size = input_s;
int a_default = input_size*row +tx;
int b_default = input_size*ty + col;
//if(row>=input_size ||col>=input_size) { return; }
// allocate 2D tiles in __shared__ memory
__shared__ float s_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float s_b[TILE_WIDTH][TILE_WIDTH];
float result = 0;
for(int p = 0; p < input_size / TILE_WIDTH + 1; ++p){
s_a[ty][tx] = a[a_default + p*TILE_WIDTH];
s_b[ty][tx] = b[b_default + p*input_size*TILE_WIDTH];
if(col >= input_size || p*TILE_WIDTH + ty >= input_size){
s_b[ty][tx] = 0;
}
if(row >= input_size || p*TILE_WIDTH + tx >= input_size){
s_a[ty][tx] = 0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH;i++){
result += (s_a[ty][i]*s_b[i][tx]);
}
__syncthreads();
}
if(col < input_size && row < input_size){
output[row*input_size + col] = alpha * result + beta * c[row*input_size + col];
}
}
int main(int argc, char **argv) {
if(argc < 4) {
cout << "usage : " << argv[0] << " input_size filter_size alpha beta\n" << "example : " << argv[0] << " 100 2 0.5 0.8\n";
return 1;
}
const int input_size = stoi(argv[1]);
const int filter_size = stoi(argv[2]); // used for maxpooling
const float alpha = stof(argv[3]);
const float beta = stof(argv[4]);
const int maxpool_output_size = input_size/filter_size;
// check input_size is power of 2
if(input_size == 0 && (input_size & (input_size-1))){
cout << "input_size must be power of 2\n";
return 1;
}
if(filter_size == 0){
cout << "filter_size cannot be 0\n";
return 1;
}
float maxpool_input[input_size*input_size];
float a[input_size*input_size];
float b[input_size*input_size];
float c[input_size*input_size];
// read input matrices
ifstream input_in(MAXPOOL_INPUT_FILENAME);
ifstream a_in(A_FILENAME);
ifstream b_in(B_FILENAME);
ifstream c_in(C_FILENAME);
for (int i = 0; i < input_size*input_size; ++i) {
input_in >> maxpool_input[i];
a_in >> a[i];
b_in >> b[i];
c_in >> c[i];
}
// prints inputs for debugging.
cout<<"filter size : "<<filter_size;
cout<<"\n========== MAXPOOL_INPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<maxpool_input[i]<<" ";
}
cout<<"\nalpha : "<<alpha<<'\n';
cout<<"========== A ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<a[i]<<" ";
}
cout<<"\n========== B ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<b[i]<<" ";
}
cout<<"\nbeta : "<<beta<<'\n';
cout<<"========== C ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<c[i]<<" ";
}
cout<<'\n';
// set thread, block dimensions
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
cout<<block_size.x;
const dim3 num_of_maxpool_blocks(input_size / block_size.x, input_size/ block_size.y);
const dim3 num_of_blocks(input_size/block_size.x+1, input_size/block_size.y+1);
// memory allocation for the device
float *dev_mem_a, *dev_mem_b, *dev_mem_c, *dev_mem_input, *gemm_output, *maxpool_output;
cudaMalloc(&dev_mem_a, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_b, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_c, sizeof(float) * input_size * input_size);
cudaMalloc(&gemm_output, sizeof(float) * input_size * input_size);
cudaMalloc(&dev_mem_input, sizeof(float) * input_size * input_size);
cudaMalloc(&maxpool_output, sizeof(float) * maxpool_output_size * maxpool_output_size);
// copy variable to device memory
cudaMemcpy(dev_mem_a, &a, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_b, &b, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_c, &c, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_mem_input, &maxpool_input, sizeof(float) * input_size * input_size, cudaMemcpyHostToDevice);
cudaEvent_t gemm_start, gemm_stop, maxpool_start, maxpool_stop;
cudaEventCreate(&gemm_start);
cudaEventCreate(&gemm_stop);
cudaEventCreate(&maxpool_start);
cudaEventCreate(&maxpool_stop);
// launch CUDA kernels
// First launch gemm kernel
cudaEventRecord(gemm_start);
gemm<<<num_of_blocks, block_size>>>(dev_mem_a, dev_mem_b, dev_mem_c, alpha, beta, gemm_output, input_size);
cudaEventRecord(gemm_stop);
cudaDeviceSynchronize();
cudaError_t error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(gemm_stop);
float gemm_t = 0;
cudaEventElapsedTime(&gemm_t,gemm_start,gemm_stop);
// Then run maxpooling
cudaEventRecord(maxpool_start);
maxpool<<<num_of_maxpool_blocks, block_size>>>(dev_mem_input, maxpool_output, input_size, filter_size);
cudaEventRecord(maxpool_stop);
cudaDeviceSynchronize();
//cudaError_t error = cudaGetLastError();
error = cudaGetLastError();
if(error!=cudaSuccess) {
fprintf(stderr, "ERROR %s\n", cudaGetErrorString(error));
return 1;
}
cudaEventSynchronize(maxpool_stop);
float maxpool_t = 0;
cudaEventElapsedTime(&maxpool_t, maxpool_start, maxpool_stop);
// allocate output buf in main memory
float *gemm_output_buf = (float*) malloc (sizeof(float)*input_size*input_size);
float *maxpool_output_buf = (float*) malloc (sizeof(float)*maxpool_output_size*maxpool_output_size);
// copy results from device to host
cudaMemcpy(gemm_output_buf, gemm_output, sizeof(float)*input_size*input_size, cudaMemcpyDeviceToHost);
cudaMemcpy(maxpool_output_buf, maxpool_output, sizeof(float)*maxpool_output_size*maxpool_output_size, cudaMemcpyDeviceToHost);
// prints the results
cout<<"\n========== GEMM OUTPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<gemm_output_buf[i]<<" ";
}
cout<<'\n';
cout<<"gemm time: " << gemm_t;
cout<<"\n========== MAXPOOL OUTPUT ==========\n";
for (int i = 0; i < maxpool_output_size * maxpool_output_size; ++i) {
if(i%maxpool_output_size==0) cout<<"\n";
cout<<maxpool_output_buf[i]<<" ";
}
cout<<'\n';
cout <<"maxpool time: " <<maxpool_t;
cudaFree(dev_mem_a);
cudaFree(dev_mem_b);
cudaFree(dev_mem_c);
cudaFree(gemm_output);
cudaFree(dev_mem_input);
cudaFree(maxpool_output);
free(gemm_output_buf);
free(maxpool_output_buf);
return 0;
} | /*
* Find BLANK and replace your own code.
* And submit report why do you replace the blank that way.
*/
#include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
#include<fstream>
#include<vector>
#include<string>
#define TILE_WIDTH 16 /* set TILE_WIDTH 16 for the evaluation! */
#define MAXPOOL_INPUT_FILENAME "input.txt"
#define A_FILENAME "a.txt"
#define B_FILENAME "b.txt"
#define C_FILENAME "c.txt"
using namespace std;
__global__ void maxpool(float *input, float *output, const int input_size, const int filter_size) {
// input : input_matrix address
// output : output buffer address
// input_size : width, height of input matrix
// filter_size : filter_size of maxpolling
// all input, output matrices are vectorized
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
int large = 0;
__shared__ float s_large[TILE_WIDTH];
if(threadIdx.x == 0){
large = input[input_size*row];
for(int i = 1; i < TILE_WIDTH; i++){
if (large < input[input_size*row+i]){
large = input[input_size*row+i];
}
}
s_large[threadIdx.y] = large;
}else{
return;
}
__syncthreads();
if(threadIdx.x == 0 && threadIdx.y == 0){
for(int i = 1; i < TILE_WIDTH; i++){
if(large < s_large[i]){
large = s_large[i];
}
}
output[blockIdx.y*TILE_WIDTH + blockIdx.x] = large;
}else{
return;
}
}
// a, b, c : input matrix address
// alpha, beta : input constant
// output : output buffer address
// input_size : width, height of input matrix
// all input, output matrices are vectorized
__global__ void gemm(float *a, float *b, float *c, const float alpha, const float beta, float *output, const int input_s){
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int row = by*blockDim.y + ty;
int col = bx*blockDim.x + tx;
int input_size = input_s;
int a_default = input_size*row +tx;
int b_default = input_size*ty + col;
//if(row>=input_size ||col>=input_size) { return; }
// allocate 2D tiles in __shared__ memory
__shared__ float s_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float s_b[TILE_WIDTH][TILE_WIDTH];
float result = 0;
for(int p = 0; p < input_size / TILE_WIDTH + 1; ++p){
s_a[ty][tx] = a[a_default + p*TILE_WIDTH];
s_b[ty][tx] = b[b_default + p*input_size*TILE_WIDTH];
if(col >= input_size || p*TILE_WIDTH + ty >= input_size){
s_b[ty][tx] = 0;
}
if(row >= input_size || p*TILE_WIDTH + tx >= input_size){
s_a[ty][tx] = 0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH;i++){
result += (s_a[ty][i]*s_b[i][tx]);
}
__syncthreads();
}
if(col < input_size && row < input_size){
output[row*input_size + col] = alpha * result + beta * c[row*input_size + col];
}
}
int main(int argc, char **argv) {
if(argc < 4) {
cout << "usage : " << argv[0] << " input_size filter_size alpha beta\n" << "example : " << argv[0] << " 100 2 0.5 0.8\n";
return 1;
}
const int input_size = stoi(argv[1]);
const int filter_size = stoi(argv[2]); // used for maxpooling
const float alpha = stof(argv[3]);
const float beta = stof(argv[4]);
const int maxpool_output_size = input_size/filter_size;
// check input_size is power of 2
if(input_size == 0 && (input_size & (input_size-1))){
cout << "input_size must be power of 2\n";
return 1;
}
if(filter_size == 0){
cout << "filter_size cannot be 0\n";
return 1;
}
float maxpool_input[input_size*input_size];
float a[input_size*input_size];
float b[input_size*input_size];
float c[input_size*input_size];
// read input matrices
ifstream input_in(MAXPOOL_INPUT_FILENAME);
ifstream a_in(A_FILENAME);
ifstream b_in(B_FILENAME);
ifstream c_in(C_FILENAME);
for (int i = 0; i < input_size*input_size; ++i) {
input_in >> maxpool_input[i];
a_in >> a[i];
b_in >> b[i];
c_in >> c[i];
}
// prints inputs for debugging.
cout<<"filter size : "<<filter_size;
cout<<"\n========== MAXPOOL_INPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<maxpool_input[i]<<" ";
}
cout<<"\nalpha : "<<alpha<<'\n';
cout<<"========== A ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<a[i]<<" ";
}
cout<<"\n========== B ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<b[i]<<" ";
}
cout<<"\nbeta : "<<beta<<'\n';
cout<<"========== C ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<c[i]<<" ";
}
cout<<'\n';
// set thread, block dimensions
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
cout<<block_size.x;
const dim3 num_of_maxpool_blocks(input_size / block_size.x, input_size/ block_size.y);
const dim3 num_of_blocks(input_size/block_size.x+1, input_size/block_size.y+1);
// memory allocation for the device
float *dev_mem_a, *dev_mem_b, *dev_mem_c, *dev_mem_input, *gemm_output, *maxpool_output;
hipMalloc(&dev_mem_a, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_b, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_c, sizeof(float) * input_size * input_size);
hipMalloc(&gemm_output, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_input, sizeof(float) * input_size * input_size);
hipMalloc(&maxpool_output, sizeof(float) * maxpool_output_size * maxpool_output_size);
// copy variable to device memory
hipMemcpy(dev_mem_a, &a, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_b, &b, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_c, &c, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_input, &maxpool_input, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipEvent_t gemm_start, gemm_stop, maxpool_start, maxpool_stop;
hipEventCreate(&gemm_start);
hipEventCreate(&gemm_stop);
hipEventCreate(&maxpool_start);
hipEventCreate(&maxpool_stop);
// launch CUDA kernels
// First launch gemm kernel
hipEventRecord(gemm_start);
gemm<<<num_of_blocks, block_size>>>(dev_mem_a, dev_mem_b, dev_mem_c, alpha, beta, gemm_output, input_size);
hipEventRecord(gemm_stop);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error!=hipSuccess) {
fprintf(stderr, "ERROR %s\n", hipGetErrorString(error));
return 1;
}
hipEventSynchronize(gemm_stop);
float gemm_t = 0;
hipEventElapsedTime(&gemm_t,gemm_start,gemm_stop);
// Then run maxpooling
hipEventRecord(maxpool_start);
maxpool<<<num_of_maxpool_blocks, block_size>>>(dev_mem_input, maxpool_output, input_size, filter_size);
hipEventRecord(maxpool_stop);
hipDeviceSynchronize();
//cudaError_t error = cudaGetLastError();
error = hipGetLastError();
if(error!=hipSuccess) {
fprintf(stderr, "ERROR %s\n", hipGetErrorString(error));
return 1;
}
hipEventSynchronize(maxpool_stop);
float maxpool_t = 0;
hipEventElapsedTime(&maxpool_t, maxpool_start, maxpool_stop);
// allocate output buf in main memory
float *gemm_output_buf = (float*) malloc (sizeof(float)*input_size*input_size);
float *maxpool_output_buf = (float*) malloc (sizeof(float)*maxpool_output_size*maxpool_output_size);
// copy results from device to host
hipMemcpy(gemm_output_buf, gemm_output, sizeof(float)*input_size*input_size, hipMemcpyDeviceToHost);
hipMemcpy(maxpool_output_buf, maxpool_output, sizeof(float)*maxpool_output_size*maxpool_output_size, hipMemcpyDeviceToHost);
// prints the results
cout<<"\n========== GEMM OUTPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<gemm_output_buf[i]<<" ";
}
cout<<'\n';
cout<<"gemm time: " << gemm_t;
cout<<"\n========== MAXPOOL OUTPUT ==========\n";
for (int i = 0; i < maxpool_output_size * maxpool_output_size; ++i) {
if(i%maxpool_output_size==0) cout<<"\n";
cout<<maxpool_output_buf[i]<<" ";
}
cout<<'\n';
cout <<"maxpool time: " <<maxpool_t;
hipFree(dev_mem_a);
hipFree(dev_mem_b);
hipFree(dev_mem_c);
hipFree(gemm_output);
hipFree(dev_mem_input);
hipFree(maxpool_output);
free(gemm_output_buf);
free(maxpool_output_buf);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Find BLANK and replace your own code.
* And submit report why do you replace the blank that way.
*/
#include <hip/hip_runtime.h>
#include<stdlib.h>
#include<iostream>
#include<fstream>
#include<vector>
#include<string>
#define TILE_WIDTH 16 /* set TILE_WIDTH 16 for the evaluation! */
#define MAXPOOL_INPUT_FILENAME "input.txt"
#define A_FILENAME "a.txt"
#define B_FILENAME "b.txt"
#define C_FILENAME "c.txt"
using namespace std;
__global__ void maxpool(float *input, float *output, const int input_size, const int filter_size) {
// input : input_matrix address
// output : output buffer address
// input_size : width, height of input matrix
// filter_size : filter_size of maxpolling
// all input, output matrices are vectorized
int col = blockDim.x * blockIdx.x + threadIdx.x;
int row = blockDim.y * blockIdx.y + threadIdx.y;
int large = 0;
__shared__ float s_large[TILE_WIDTH];
if(threadIdx.x == 0){
large = input[input_size*row];
for(int i = 1; i < TILE_WIDTH; i++){
if (large < input[input_size*row+i]){
large = input[input_size*row+i];
}
}
s_large[threadIdx.y] = large;
}else{
return;
}
__syncthreads();
if(threadIdx.x == 0 && threadIdx.y == 0){
for(int i = 1; i < TILE_WIDTH; i++){
if(large < s_large[i]){
large = s_large[i];
}
}
output[blockIdx.y*TILE_WIDTH + blockIdx.x] = large;
}else{
return;
}
}
// a, b, c : input matrix address
// alpha, beta : input constant
// output : output buffer address
// input_size : width, height of input matrix
// all input, output matrices are vectorized
__global__ void gemm(float *a, float *b, float *c, const float alpha, const float beta, float *output, const int input_s){
int tx = threadIdx.x, ty = threadIdx.y;
int bx = blockIdx.x, by = blockIdx.y;
int row = by*blockDim.y + ty;
int col = bx*blockDim.x + tx;
int input_size = input_s;
int a_default = input_size*row +tx;
int b_default = input_size*ty + col;
//if(row>=input_size ||col>=input_size) { return; }
// allocate 2D tiles in __shared__ memory
__shared__ float s_a[TILE_WIDTH][TILE_WIDTH];
__shared__ float s_b[TILE_WIDTH][TILE_WIDTH];
float result = 0;
for(int p = 0; p < input_size / TILE_WIDTH + 1; ++p){
s_a[ty][tx] = a[a_default + p*TILE_WIDTH];
s_b[ty][tx] = b[b_default + p*input_size*TILE_WIDTH];
if(col >= input_size || p*TILE_WIDTH + ty >= input_size){
s_b[ty][tx] = 0;
}
if(row >= input_size || p*TILE_WIDTH + tx >= input_size){
s_a[ty][tx] = 0;
}
__syncthreads();
for(int i = 0; i < TILE_WIDTH;i++){
result += (s_a[ty][i]*s_b[i][tx]);
}
__syncthreads();
}
if(col < input_size && row < input_size){
output[row*input_size + col] = alpha * result + beta * c[row*input_size + col];
}
}
int main(int argc, char **argv) {
if(argc < 4) {
cout << "usage : " << argv[0] << " input_size filter_size alpha beta\n" << "example : " << argv[0] << " 100 2 0.5 0.8\n";
return 1;
}
const int input_size = stoi(argv[1]);
const int filter_size = stoi(argv[2]); // used for maxpooling
const float alpha = stof(argv[3]);
const float beta = stof(argv[4]);
const int maxpool_output_size = input_size/filter_size;
// check input_size is power of 2
if(input_size == 0 && (input_size & (input_size-1))){
cout << "input_size must be power of 2\n";
return 1;
}
if(filter_size == 0){
cout << "filter_size cannot be 0\n";
return 1;
}
float maxpool_input[input_size*input_size];
float a[input_size*input_size];
float b[input_size*input_size];
float c[input_size*input_size];
// read input matrices
ifstream input_in(MAXPOOL_INPUT_FILENAME);
ifstream a_in(A_FILENAME);
ifstream b_in(B_FILENAME);
ifstream c_in(C_FILENAME);
for (int i = 0; i < input_size*input_size; ++i) {
input_in >> maxpool_input[i];
a_in >> a[i];
b_in >> b[i];
c_in >> c[i];
}
// prints inputs for debugging.
cout<<"filter size : "<<filter_size;
cout<<"\n========== MAXPOOL_INPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<maxpool_input[i]<<" ";
}
cout<<"\nalpha : "<<alpha<<'\n';
cout<<"========== A ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<a[i]<<" ";
}
cout<<"\n========== B ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<b[i]<<" ";
}
cout<<"\nbeta : "<<beta<<'\n';
cout<<"========== C ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<c[i]<<" ";
}
cout<<'\n';
// set thread, block dimensions
const dim3 block_size(TILE_WIDTH, TILE_WIDTH);
cout<<block_size.x;
const dim3 num_of_maxpool_blocks(input_size / block_size.x, input_size/ block_size.y);
const dim3 num_of_blocks(input_size/block_size.x+1, input_size/block_size.y+1);
// memory allocation for the device
float *dev_mem_a, *dev_mem_b, *dev_mem_c, *dev_mem_input, *gemm_output, *maxpool_output;
hipMalloc(&dev_mem_a, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_b, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_c, sizeof(float) * input_size * input_size);
hipMalloc(&gemm_output, sizeof(float) * input_size * input_size);
hipMalloc(&dev_mem_input, sizeof(float) * input_size * input_size);
hipMalloc(&maxpool_output, sizeof(float) * maxpool_output_size * maxpool_output_size);
// copy variable to device memory
hipMemcpy(dev_mem_a, &a, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_b, &b, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_c, &c, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipMemcpy(dev_mem_input, &maxpool_input, sizeof(float) * input_size * input_size, hipMemcpyHostToDevice);
hipEvent_t gemm_start, gemm_stop, maxpool_start, maxpool_stop;
hipEventCreate(&gemm_start);
hipEventCreate(&gemm_stop);
hipEventCreate(&maxpool_start);
hipEventCreate(&maxpool_stop);
// launch CUDA kernels
// First launch gemm kernel
hipEventRecord(gemm_start);
gemm<<<num_of_blocks, block_size>>>(dev_mem_a, dev_mem_b, dev_mem_c, alpha, beta, gemm_output, input_size);
hipEventRecord(gemm_stop);
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error!=hipSuccess) {
fprintf(stderr, "ERROR %s\n", hipGetErrorString(error));
return 1;
}
hipEventSynchronize(gemm_stop);
float gemm_t = 0;
hipEventElapsedTime(&gemm_t,gemm_start,gemm_stop);
// Then run maxpooling
hipEventRecord(maxpool_start);
maxpool<<<num_of_maxpool_blocks, block_size>>>(dev_mem_input, maxpool_output, input_size, filter_size);
hipEventRecord(maxpool_stop);
hipDeviceSynchronize();
//cudaError_t error = cudaGetLastError();
error = hipGetLastError();
if(error!=hipSuccess) {
fprintf(stderr, "ERROR %s\n", hipGetErrorString(error));
return 1;
}
hipEventSynchronize(maxpool_stop);
float maxpool_t = 0;
hipEventElapsedTime(&maxpool_t, maxpool_start, maxpool_stop);
// allocate output buf in main memory
float *gemm_output_buf = (float*) malloc (sizeof(float)*input_size*input_size);
float *maxpool_output_buf = (float*) malloc (sizeof(float)*maxpool_output_size*maxpool_output_size);
// copy results from device to host
hipMemcpy(gemm_output_buf, gemm_output, sizeof(float)*input_size*input_size, hipMemcpyDeviceToHost);
hipMemcpy(maxpool_output_buf, maxpool_output, sizeof(float)*maxpool_output_size*maxpool_output_size, hipMemcpyDeviceToHost);
// prints the results
cout<<"\n========== GEMM OUTPUT ==========\n";
for (int i = 0; i < input_size * input_size; ++i) {
if(i%input_size==0) cout<<"\n";
cout<<gemm_output_buf[i]<<" ";
}
cout<<'\n';
cout<<"gemm time: " << gemm_t;
cout<<"\n========== MAXPOOL OUTPUT ==========\n";
for (int i = 0; i < maxpool_output_size * maxpool_output_size; ++i) {
if(i%maxpool_output_size==0) cout<<"\n";
cout<<maxpool_output_buf[i]<<" ";
}
cout<<'\n';
cout <<"maxpool time: " <<maxpool_t;
hipFree(dev_mem_a);
hipFree(dev_mem_b);
hipFree(dev_mem_c);
hipFree(gemm_output);
hipFree(dev_mem_input);
hipFree(maxpool_output);
free(gemm_output_buf);
free(maxpool_output_buf);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7maxpoolPfS_ii
.globl _Z7maxpoolPfS_ii
.p2align 8
.type _Z7maxpoolPfS_ii,@function
_Z7maxpoolPfS_ii:
v_and_b32_e32 v1, 0x3ff, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_mov_b64 s[2:3], 4
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v3, v3
.LBB0_2:
v_add_co_u32 v4, vcc_lo, v1, s2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v2, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 64
global_load_b32 v4, v[4:5], off
v_cvt_f32_i32_e32 v5, v3
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, v4, v5
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v3
v_lshlrev_b32_e32 v2, 2, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_mov_b32 s2, 4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v0, s2
v_cvt_f32_i32_e32 v1, v3
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 64
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
v_cvt_i32_f32_e32 v2, v0
v_cmp_gt_f32_e32 vcc_lo, v0, v1
v_cndmask_b32_e32 v3, v3, v2, vcc_lo
s_cbranch_scc0 .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b32 s2, s15, 4
s_mov_b32 s3, 0
s_add_i32 s2, s2, s14
v_cvt_f32_i32_e32 v0, v3
s_lshl_b64 s[2:3], s[2:3], 2
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7maxpoolPfS_ii
.amdhsa_group_segment_fixed_size 64
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7maxpoolPfS_ii, .Lfunc_end0-_Z7maxpoolPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4gemmPfS_S_ffS_i
.globl _Z4gemmPfS_S_ffS_i
.p2align 8
.type _Z4gemmPfS_S_ffS_i,@function
_Z4gemmPfS_S_ffS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x28
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s3, v[4:5]
v_and_b32_e32 v3, 0x3ff, v0
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s8, -15
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v1, v2, s8
s_cbranch_scc1 .LBB1_8
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v5, 2, v3
s_ashr_i32 s2, s8, 31
v_dual_mov_b32 v11, 0 :: v_dual_lshlrev_b32 v6, 6, v4
s_lshr_b32 s2, s2, 28
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x400, v5
s_add_i32 s3, s8, s2
v_cmp_gt_i32_e64 s2, s8, v2
v_add_nc_u32_e32 v8, v1, v3
v_add_nc_u32_e32 v9, v6, v5
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v10, v7, v6
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_ashr_i32 s9, s3, 4
s_mov_b32 s11, 0
s_xor_b32 s10, s2, -1
.LBB1_2:
s_lshl_b32 s3, s11, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v16, s3, v4
v_add_nc_u32_e32 v14, s3, v8
v_mad_u64_u32 v[12:13], null, v16, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s2, s6, v12
v_add_co_ci_u32_e64 v13, s2, s7, v13, s2
v_add_co_u32 v14, s2, s4, v14
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v15, s2, s5, v15, s2
v_cmp_gt_i32_e64 s2, s8, v16
global_load_b32 v12, v[12:13], off
global_load_b32 v13, v[14:15], off
v_add_nc_u32_e32 v14, s3, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s3, s8, v14
s_or_b32 s3, s10, s3
s_waitcnt vmcnt(1)
v_cndmask_b32_e64 v12, 0, v12, s2
s_waitcnt vmcnt(0)
ds_store_b32 v9, v13
ds_store_b32 v10, v12
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_4
ds_store_b32 v9, v11
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v12, v7
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB1_5:
v_add_nc_u32_e32 v13, s2, v6
s_add_i32 s2, s2, 4
ds_load_b32 v14, v12
ds_load_b32 v13, v13
v_add_nc_u32_e32 v12, 64, v12
s_cmp_eq_u32 s2, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, v13, v14
s_cbranch_scc0 .LBB1_5
s_add_i32 s2, s11, 1
s_cmp_eq_u32 s11, s9
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_8
s_mov_b32 s11, s2
s_branch .LBB1_2
.LBB1_8:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v2, v0
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB1_10
s_load_b64 s[4:5], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
s_load_b128 s[0:3], s[0:1], 0x18
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v5
global_store_b32 v[0:1], v2, off
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4gemmPfS_S_ffS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4gemmPfS_S_ffS_i, .Lfunc_end1-_Z4gemmPfS_S_ffS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 64
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7maxpoolPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7maxpoolPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4gemmPfS_S_ffS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4gemmPfS_S_ffS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <algorithm>
#include <string>
#include <cstdio>
#include <cstdlib>
//#include <ctime>
#include <vector>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
//#include "../lib/cuPrintf.cu"
using namespace std;
typedef double TNum;
#define CSC(call) do { \
cudaError_t e = call; \
if (e != cudaSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n"\
, __FILE__, __LINE__, cudaGetErrorString(e)); \
exit(0); \
} \
} while(0)
//#define EPS .0000001;
struct Comparator {
__host__ __device__ bool operator()(TNum a, TNum b) {
return a < b;
}
};
__constant__ uint32_t SIZE_N[1];
__constant__ uint32_t SIZE_M[1];
__constant__ uint32_t SIZE_K[1];
struct Position {
int32_t Row;
int32_t Col;
};
__device__ __host__ Position SetPosition(int32_t i, int32_t j) {
Position pos;
pos.Row = i;
pos.Col = j;
return pos;
}
__device__ __host__ Position SetPosition(uint32_t i, uint32_t j) {
return SetPosition((int32_t) i, (int32_t) j);
}
__device__ __host__ bool IsCorrectPos(Position pos, uint32_t height, uint32_t width) {
return (pos.Row >= 0 && pos.Col >= 0 && pos.Row < (int32_t) height && pos.Col < (int32_t) width);
}
__device__ __host__ int32_t GetLinearPosition(Position pos, uint32_t height, uint32_t width) {
return (IsCorrectPos(pos, height, width)) ? (pos.Col * (int32_t) height + pos.Row) : -1;
}
__device__ __host__ bool IsCorrectPos(uint32_t i, uint32_t j, uint32_t height, uint32_t width) {
return (i < height && j < width);
}
__device__ __host__ int32_t GetLinearPosition(uint32_t i, uint32_t j, uint32_t height, uint32_t width) {
return (IsCorrectPos(i, j, height, width) ? ((int32_t) j * (int32_t) height + (int32_t) i) : -1);
}
/*__global__ void SwapVector(TNum *a, TNum *b, uint32_t length, uint32_t shift) {
uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x + shift;
uint32_t offset = gridDim.x * blockDim.x;
TNum tmp;
for (uint32_t i = begin, i < length, i += offset) {
}
}*/
__global__ void SwapRows(TNum *a, TNum *b, uint32_t row1, uint32_t row2, uint32_t shift) {
//uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x;
//uint32_t offset = gridDim.x * blockDim.x;
uint32_t col;
TNum tmp;
for (col = (blockDim.x * blockIdx.x + threadIdx.x) + shift; col < *SIZE_M; col += gridDim.x * blockDim.x) {
tmp = a[GetLinearPosition(row1, col, *SIZE_N, *SIZE_M)];
a[GetLinearPosition(row1, col, *SIZE_N, *SIZE_M)] = a[GetLinearPosition(row2, col, *SIZE_N, *SIZE_M)];
a[GetLinearPosition(row2, col, *SIZE_N, *SIZE_M)] = tmp;
}
for (col = blockDim.x * blockIdx.x + threadIdx.x; col < *SIZE_K; col += gridDim.x * blockDim.x) {
tmp = b[GetLinearPosition(row1, col, *SIZE_N, *SIZE_K)];
b[GetLinearPosition(row1, col, *SIZE_N, *SIZE_K)] = b[GetLinearPosition(row2, col, *SIZE_N, *SIZE_K)];
b[GetLinearPosition(row2, col, *SIZE_N, *SIZE_K)] = tmp;
}
}
__global__ void Normalize(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
if (!(abs(a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
return;
}
//uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x;
//uint32_t offset = gridDim.x * blockDim.x;
uint32_t col;
for (col = (blockDim.x * blockIdx.x + threadIdx.x) + shift + 1; col < *SIZE_M; col += gridDim.x * blockDim.x) {
a[GetLinearPosition(row, col, *SIZE_N, *SIZE_M)] /=
a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)];
}
for (col = blockDim.x * blockIdx.x + threadIdx.x; col < *SIZE_K; col += gridDim.x * blockDim.x) {
b[GetLinearPosition(row, col, *SIZE_N, *SIZE_K)] /=
a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)];
}
}
__global__ void GaussFirst(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
if (!(abs(a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
return;
}
/*Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);*/
//Position curr = begin;
/*int32_t beginRow = blockDim.x * blockIdx.x + threadIdx.x;
int32_t beginCol = blockDim.y * blockIdx.y + threadIdx.y;
int32_t offsetRow = blockDim.x * gridDim.x;
int32_t offsetCol = blockDim.y * gridDim.y;*/
Position curr;
//TNum head;
for (curr.Row = (blockDim.x * blockIdx.x + threadIdx.x) + row + 1; curr.Row < *SIZE_N; curr.Row += blockDim.x * gridDim.x) {
//head = a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
if (!(abs(a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
continue;
}
for (curr.Col = (blockDim.y * blockIdx.y + threadIdx.y) + shift + 1; curr.Col < *SIZE_M; curr.Col += blockDim.y * gridDim.y) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
for (curr.Col = blockDim.y * blockIdx.y + threadIdx.y; curr.Col < *SIZE_K; curr.Col += blockDim.y * gridDim.y) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}
__global__ void GaussSecond(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
/*Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);*/
/*int32_t beginRow = blockDim.x * blockIdx.x + threadIdx.x;
int32_t beginCol = blockDim.y * blockIdx.y + threadIdx.y;
int32_t offsetRow = blockDim.x * gridDim.x;
int32_t offsetCol = blockDim.y * gridDim.y;*/
Position curr;
for (curr.Row = row - 1 - (blockDim.x * blockIdx.x + threadIdx.x); curr.Row >= 0; curr.Row -= blockDim.x * gridDim.x) {
/*for (curr.Col = begin.Col + shift; curr.Col < *SIZE_M; curr.Col += offset.Col) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}*/
for (curr.Col = blockDim.y * blockIdx.y + threadIdx.y; curr.Col < *SIZE_K; curr.Col += blockDim.y * gridDim.y) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}
/*__host__ void GaussSecondCPU(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
Position curr;
for (curr.Row = row - 1; curr.Row >= 0; curr.Row--) {
for (curr.Col = shift; curr.Col >= 0; curr.Col -= offset.Col) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
for (curr.Col = begin.Col; curr.Col >= 0; curr.Col -= offset.Col) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}*/
/*__global__ void GetResult(TNum *b, TNum *x, uint32_t *shifts, uint32_t rows) {
Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);
Position curr;
for (curr.Row = begin.Row; curr.Row < rows; curr.Rows++) {
for (curr.Col = begin.Col; curr.Col < *SIZE_K; curr.Col++) {
}
}
}*/
__host__ void InputMatrix(TNum *matrix, uint32_t height, uint32_t width) {
for (uint32_t i = 0; i < height; i++) {
for (uint32_t j = 0; j < width; j++) {
cin >> matrix[GetLinearPosition(i, j, height, width)];
}
}
}
__host__ void PrintMatrix(TNum *matrix, uint32_t height, uint32_t width) {
for (uint32_t i = 0; i < height; i++) {
for (uint32_t j = 0; j < width; j++) {
if (j > 0) {
cout << " ";
}
cout << scientific << matrix[GetLinearPosition(SetPosition(i, j), height, width)];
}
cout << endl;
}
}
__host__ int main(void) {
Comparator cmp;
uint32_t n, m, k;
cin >> n >> m >> k;
CSC(cudaMemcpyToSymbol(SIZE_N, &n, sizeof(uint32_t)));
CSC(cudaMemcpyToSymbol(SIZE_M, &m, sizeof(uint32_t)));
CSC(cudaMemcpyToSymbol(SIZE_K, &k, sizeof(uint32_t)));
TNum *a = new TNum[n * m];
TNum *b = new TNum[n * k];
InputMatrix(a, n, m);
InputMatrix(b, n, k);
TNum *cuda_a;
TNum *cuda_b;
CSC(cudaMalloc((void**) &cuda_a, sizeof(TNum) * n * m));
CSC(cudaMalloc((void**) &cuda_b, sizeof(TNum) * n * k));
CSC(cudaMemcpy(cuda_a, a, sizeof(TNum) * n * m, cudaMemcpyHostToDevice));
CSC(cudaMemcpy(cuda_b, b, sizeof(TNum) * n * k, cudaMemcpyHostToDevice));
uint32_t row = 0;
uint32_t *shifts = new uint32_t[n];
memset(shifts, 0, n * sizeof(uint32_t));
for (uint32_t col = 0; col < m && row < n; col++) {
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "___" << endl;*/
if (row < n - 1) {
thrust::device_ptr <TNum> cuda_a_begin = thrust::device_pointer_cast(cuda_a);
thrust::device_ptr <TNum> cuda_a_max = thrust::max_element(
cuda_a_begin + GetLinearPosition(row, col, n, m),
cuda_a_begin + (col + 1) * n, cmp);
uint32_t row_max_pos = cuda_a_max - cuda_a_begin - GetLinearPosition(0, col, n, m);
TNum row_value, max_value;
//cout << sizeof(TNum) << endl;
//cout << cuda_a << " : " << cuda_a + n * m * sizeof(TNum) << endl;
//cout << cuda_a + sizeof(TNum) * GetLinearPosition(row, col, n, m) << " : " <<
//cuda_a + sizeof(TNum) * GetLinearPosition(row_max_pos, col, n, m) << endl;
CSC(cudaMemcpy(&row_value, cuda_a + GetLinearPosition(row, col, n, m),
sizeof(TNum), cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(&max_value, cuda_a + GetLinearPosition(row_max_pos, col, n, m),
sizeof(TNum), cudaMemcpyDeviceToHost));
TNum curr = row_value;
//cout << curr << " : " << max_value << endl;
if (row_max_pos != row && row_value < max_value) {
SwapRows<<<dim3(1024), dim3(1024)>>>(cuda_a, cuda_b, row, row_max_pos, col);
curr = max_value;
}
if (!(abs(curr) > .0000001)) {
//cout << "CURR = " << curr << endl;
//cout << "OUT1" << endl;
continue;
}
} else {
TNum curr;
//cout << GetLinearPosition(row, col, n, m) << endl;
//cout << row << ":" << col << endl;
CSC(cudaMemcpy(&curr, cuda_a + GetLinearPosition(row, col, n, m),
sizeof(TNum), cudaMemcpyDeviceToHost));
if (!(abs(curr) > .0000001)) {
//cout << "OUT2" << endl;
continue;
}
}
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
cout << "Col: " << col << endl;
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "~~~" << endl;*/
//cudaPrintfInit();
Normalize<<<dim3(1024), dim3(1024)>>>(cuda_a, cuda_b, row, col);
//cudaPrintfDisplay(stdout, true);
//cudaPrintfEnd();
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "+++" << endl;*/
if (row < n - 1) {
GaussFirst<<<dim3(32, 32), dim3(32, 32)>>>(cuda_a, cuda_b, row, col);
}
//cout << shifts[row] << " -> " << col << endl;
shifts[row] = col;
row++;
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
}
/*cout << "NEXT!!" << endl;
CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
for (uint32_t i = row; i > 0; i--) {
uint32_t row_curr = i - 1;
if (row_curr > 0) {
GaussSecond<<<dim3(32, 32), dim3(32, 32)>>>(cuda_a, cuda_b, row_curr, shifts[row_curr]);
}
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
}
//uint32_t *cuda_shifts;
//cudaMalloc((void**) &cuda_shifts, sizeof(uint32_t) * row);
//cudaMemcpy(cuda_shifts, shifts, sizeof(uint32_t) * row, cudaMemcpyHostToDevice);
//GetResult<<<dim3(32, 32), dim3(32, 32)>>>(cuda_b, cuda_x, cuda_shifts, row, );
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaEventDestroy(syncEvent);
//Calculating end
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
CSC(cudaFree(cuda_a));
CSC(cudaFree(cuda_b));
//cudaFree(cuda_x);
//PrintMatrix(cuda_b, shifts, m, k);
TNum zero = 0.;
uint32_t untill = 0;
if (row > 0) {
untill = shifts[0];
}
uint32_t rows_cnt = 0;
for (uint32_t i = 0; i < untill; i++) {
for (uint32_t j = 0; j < k; j++) {
//cout << "1: " << shifts[0] << "::" << i << ":" << j << endl;
if (j > 0) {
cout << " ";
}
cout << scientific << zero;
}
rows_cnt++;
cout << endl;
}
//cout << row << endl;
for (uint32_t i = 0; i < row; i++) {
if (i > 0) {
for (uint32_t ii = 0; ii < shifts[i] - shifts[i - 1] - 1; ii++) {
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "2: " << i << ":" << j << endl;
cout << scientific << zero;
}
rows_cnt++;
cout << endl;
}
}
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "3: " << i << ":" << j << endl;
cout << scientific << b[GetLinearPosition(i, j, n, k)];
}
rows_cnt++;
cout << endl;
}
//cout << "TEST0" << endl;
//cout << shifts[0] << endl;
//untill = m - shifts[max(0, (int32_t) row - 1)];
for (uint32_t i = 0; i < m - rows_cnt; i++) {
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "4: " << i << ":" << j << endl;
cout << scientific << zero;
}
cout << endl;
}
//cout << "TEST1" << endl;
/*cout << "SHIFTS:\n";
for (uint32_t i = 0; i < row; i++) {
cout << shifts[i] << endl;
}*/
delete [] shifts;
delete [] a;
delete [] b;
//delete [] cuda_x;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <algorithm>
#include <string>
#include <cstdio>
#include <cstdlib>
//#include <ctime>
#include <vector>
#include <thrust/extrema.h>
#include <thrust/device_vector.h>
//#include "../lib/cuPrintf.cu"
using namespace std;
typedef double TNum;
#define CSC(call) do { \
hipError_t e = call; \
if (e != hipSuccess) { \
fprintf(stderr, "CUDA Error in %s:%d: %s\n"\
, __FILE__, __LINE__, hipGetErrorString(e)); \
exit(0); \
} \
} while(0)
//#define EPS .0000001;
struct Comparator {
__host__ __device__ bool operator()(TNum a, TNum b) {
return a < b;
}
};
__constant__ uint32_t SIZE_N[1];
__constant__ uint32_t SIZE_M[1];
__constant__ uint32_t SIZE_K[1];
struct Position {
int32_t Row;
int32_t Col;
};
__device__ __host__ Position SetPosition(int32_t i, int32_t j) {
Position pos;
pos.Row = i;
pos.Col = j;
return pos;
}
__device__ __host__ Position SetPosition(uint32_t i, uint32_t j) {
return SetPosition((int32_t) i, (int32_t) j);
}
__device__ __host__ bool IsCorrectPos(Position pos, uint32_t height, uint32_t width) {
return (pos.Row >= 0 && pos.Col >= 0 && pos.Row < (int32_t) height && pos.Col < (int32_t) width);
}
__device__ __host__ int32_t GetLinearPosition(Position pos, uint32_t height, uint32_t width) {
return (IsCorrectPos(pos, height, width)) ? (pos.Col * (int32_t) height + pos.Row) : -1;
}
__device__ __host__ bool IsCorrectPos(uint32_t i, uint32_t j, uint32_t height, uint32_t width) {
return (i < height && j < width);
}
__device__ __host__ int32_t GetLinearPosition(uint32_t i, uint32_t j, uint32_t height, uint32_t width) {
return (IsCorrectPos(i, j, height, width) ? ((int32_t) j * (int32_t) height + (int32_t) i) : -1);
}
/*__global__ void SwapVector(TNum *a, TNum *b, uint32_t length, uint32_t shift) {
uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x + shift;
uint32_t offset = gridDim.x * blockDim.x;
TNum tmp;
for (uint32_t i = begin, i < length, i += offset) {
}
}*/
__global__ void SwapRows(TNum *a, TNum *b, uint32_t row1, uint32_t row2, uint32_t shift) {
//uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x;
//uint32_t offset = gridDim.x * blockDim.x;
uint32_t col;
TNum tmp;
for (col = (blockDim.x * blockIdx.x + threadIdx.x) + shift; col < *SIZE_M; col += gridDim.x * blockDim.x) {
tmp = a[GetLinearPosition(row1, col, *SIZE_N, *SIZE_M)];
a[GetLinearPosition(row1, col, *SIZE_N, *SIZE_M)] = a[GetLinearPosition(row2, col, *SIZE_N, *SIZE_M)];
a[GetLinearPosition(row2, col, *SIZE_N, *SIZE_M)] = tmp;
}
for (col = blockDim.x * blockIdx.x + threadIdx.x; col < *SIZE_K; col += gridDim.x * blockDim.x) {
tmp = b[GetLinearPosition(row1, col, *SIZE_N, *SIZE_K)];
b[GetLinearPosition(row1, col, *SIZE_N, *SIZE_K)] = b[GetLinearPosition(row2, col, *SIZE_N, *SIZE_K)];
b[GetLinearPosition(row2, col, *SIZE_N, *SIZE_K)] = tmp;
}
}
__global__ void Normalize(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
if (!(abs(a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
return;
}
//uint32_t begin = blockDim.x * blockIdx.x + threadIdx.x;
//uint32_t offset = gridDim.x * blockDim.x;
uint32_t col;
for (col = (blockDim.x * blockIdx.x + threadIdx.x) + shift + 1; col < *SIZE_M; col += gridDim.x * blockDim.x) {
a[GetLinearPosition(row, col, *SIZE_N, *SIZE_M)] /=
a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)];
}
for (col = blockDim.x * blockIdx.x + threadIdx.x; col < *SIZE_K; col += gridDim.x * blockDim.x) {
b[GetLinearPosition(row, col, *SIZE_N, *SIZE_K)] /=
a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)];
}
}
__global__ void GaussFirst(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
if (!(abs(a[GetLinearPosition(row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
return;
}
/*Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);*/
//Position curr = begin;
/*int32_t beginRow = blockDim.x * blockIdx.x + threadIdx.x;
int32_t beginCol = blockDim.y * blockIdx.y + threadIdx.y;
int32_t offsetRow = blockDim.x * gridDim.x;
int32_t offsetCol = blockDim.y * gridDim.y;*/
Position curr;
//TNum head;
for (curr.Row = (blockDim.x * blockIdx.x + threadIdx.x) + row + 1; curr.Row < *SIZE_N; curr.Row += blockDim.x * gridDim.x) {
//head = a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
if (!(abs(a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)]) > .0000001)) {
continue;
}
for (curr.Col = (blockDim.y * blockIdx.y + threadIdx.y) + shift + 1; curr.Col < *SIZE_M; curr.Col += blockDim.y * gridDim.y) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
for (curr.Col = blockDim.y * blockIdx.y + threadIdx.y; curr.Col < *SIZE_K; curr.Col += blockDim.y * gridDim.y) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}
__global__ void GaussSecond(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
/*Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);*/
/*int32_t beginRow = blockDim.x * blockIdx.x + threadIdx.x;
int32_t beginCol = blockDim.y * blockIdx.y + threadIdx.y;
int32_t offsetRow = blockDim.x * gridDim.x;
int32_t offsetCol = blockDim.y * gridDim.y;*/
Position curr;
for (curr.Row = row - 1 - (blockDim.x * blockIdx.x + threadIdx.x); curr.Row >= 0; curr.Row -= blockDim.x * gridDim.x) {
/*for (curr.Col = begin.Col + shift; curr.Col < *SIZE_M; curr.Col += offset.Col) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}*/
for (curr.Col = blockDim.y * blockIdx.y + threadIdx.y; curr.Col < *SIZE_K; curr.Col += blockDim.y * gridDim.y) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}
/*__host__ void GaussSecondCPU(TNum *a, TNum *b, uint32_t row, uint32_t shift) {
Position curr;
for (curr.Row = row - 1; curr.Row >= 0; curr.Row--) {
for (curr.Col = shift; curr.Col >= 0; curr.Col -= offset.Col) {
a[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_M)] -=
a[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_M)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
for (curr.Col = begin.Col; curr.Col >= 0; curr.Col -= offset.Col) {
b[GetLinearPosition(curr.Row, curr.Col, *SIZE_N, *SIZE_K)] -=
b[GetLinearPosition(row, curr.Col, *SIZE_N, *SIZE_K)] *
a[GetLinearPosition(curr.Row, shift, *SIZE_N, *SIZE_M)];
}
}
}*/
/*__global__ void GetResult(TNum *b, TNum *x, uint32_t *shifts, uint32_t rows) {
Position begin = SetPosition(blockDim.x * blockIdx.x + threadIdx.x,
blockDim.y * blockIdx.y + threadIdx.y);
Position offset = SetPosition(blockDim.x * gridDim.x, blockDim.y * gridDim.y);
Position curr;
for (curr.Row = begin.Row; curr.Row < rows; curr.Rows++) {
for (curr.Col = begin.Col; curr.Col < *SIZE_K; curr.Col++) {
}
}
}*/
__host__ void InputMatrix(TNum *matrix, uint32_t height, uint32_t width) {
for (uint32_t i = 0; i < height; i++) {
for (uint32_t j = 0; j < width; j++) {
cin >> matrix[GetLinearPosition(i, j, height, width)];
}
}
}
__host__ void PrintMatrix(TNum *matrix, uint32_t height, uint32_t width) {
for (uint32_t i = 0; i < height; i++) {
for (uint32_t j = 0; j < width; j++) {
if (j > 0) {
cout << " ";
}
cout << scientific << matrix[GetLinearPosition(SetPosition(i, j), height, width)];
}
cout << endl;
}
}
__host__ int main(void) {
Comparator cmp;
uint32_t n, m, k;
cin >> n >> m >> k;
CSC(hipMemcpyToSymbol(HIP_SYMBOL(SIZE_N), &n, sizeof(uint32_t)));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(SIZE_M), &m, sizeof(uint32_t)));
CSC(hipMemcpyToSymbol(HIP_SYMBOL(SIZE_K), &k, sizeof(uint32_t)));
TNum *a = new TNum[n * m];
TNum *b = new TNum[n * k];
InputMatrix(a, n, m);
InputMatrix(b, n, k);
TNum *cuda_a;
TNum *cuda_b;
CSC(hipMalloc((void**) &cuda_a, sizeof(TNum) * n * m));
CSC(hipMalloc((void**) &cuda_b, sizeof(TNum) * n * k));
CSC(hipMemcpy(cuda_a, a, sizeof(TNum) * n * m, hipMemcpyHostToDevice));
CSC(hipMemcpy(cuda_b, b, sizeof(TNum) * n * k, hipMemcpyHostToDevice));
uint32_t row = 0;
uint32_t *shifts = new uint32_t[n];
memset(shifts, 0, n * sizeof(uint32_t));
for (uint32_t col = 0; col < m && row < n; col++) {
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "___" << endl;*/
if (row < n - 1) {
thrust::device_ptr <TNum> cuda_a_begin = thrust::device_pointer_cast(cuda_a);
thrust::device_ptr <TNum> cuda_a_max = thrust::max_element(
cuda_a_begin + GetLinearPosition(row, col, n, m),
cuda_a_begin + (col + 1) * n, cmp);
uint32_t row_max_pos = cuda_a_max - cuda_a_begin - GetLinearPosition(0, col, n, m);
TNum row_value, max_value;
//cout << sizeof(TNum) << endl;
//cout << cuda_a << " : " << cuda_a + n * m * sizeof(TNum) << endl;
//cout << cuda_a + sizeof(TNum) * GetLinearPosition(row, col, n, m) << " : " <<
//cuda_a + sizeof(TNum) * GetLinearPosition(row_max_pos, col, n, m) << endl;
CSC(hipMemcpy(&row_value, cuda_a + GetLinearPosition(row, col, n, m),
sizeof(TNum), hipMemcpyDeviceToHost));
CSC(hipMemcpy(&max_value, cuda_a + GetLinearPosition(row_max_pos, col, n, m),
sizeof(TNum), hipMemcpyDeviceToHost));
TNum curr = row_value;
//cout << curr << " : " << max_value << endl;
if (row_max_pos != row && row_value < max_value) {
SwapRows<<<dim3(1024), dim3(1024)>>>(cuda_a, cuda_b, row, row_max_pos, col);
curr = max_value;
}
if (!(abs(curr) > .0000001)) {
//cout << "CURR = " << curr << endl;
//cout << "OUT1" << endl;
continue;
}
} else {
TNum curr;
//cout << GetLinearPosition(row, col, n, m) << endl;
//cout << row << ":" << col << endl;
CSC(hipMemcpy(&curr, cuda_a + GetLinearPosition(row, col, n, m),
sizeof(TNum), hipMemcpyDeviceToHost));
if (!(abs(curr) > .0000001)) {
//cout << "OUT2" << endl;
continue;
}
}
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
cout << "Col: " << col << endl;
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "~~~" << endl;*/
//cudaPrintfInit();
Normalize<<<dim3(1024), dim3(1024)>>>(cuda_a, cuda_b, row, col);
//cudaPrintfDisplay(stdout, true);
//cudaPrintfEnd();
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "+++" << endl;*/
if (row < n - 1) {
GaussFirst<<<dim3(32, 32), dim3(32, 32)>>>(cuda_a, cuda_b, row, col);
}
//cout << shifts[row] << " -> " << col << endl;
shifts[row] = col;
row++;
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
}
/*cout << "NEXT!!" << endl;
CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
for (uint32_t i = row; i > 0; i--) {
uint32_t row_curr = i - 1;
if (row_curr > 0) {
GaussSecond<<<dim3(32, 32), dim3(32, 32)>>>(cuda_a, cuda_b, row_curr, shifts[row_curr]);
}
/*CSC(cudaMemcpy(a, cuda_a, sizeof(TNum) * n * m, cudaMemcpyDeviceToHost));
CSC(cudaMemcpy(b, cuda_b, sizeof(TNum) * n * k, cudaMemcpyDeviceToHost));
PrintMatrix(a, n, m);
cout << "---" << endl;
PrintMatrix(b, n, k);
cout << "===" << endl << endl;*/
}
//uint32_t *cuda_shifts;
//cudaMalloc((void**) &cuda_shifts, sizeof(uint32_t) * row);
//cudaMemcpy(cuda_shifts, shifts, sizeof(uint32_t) * row, cudaMemcpyHostToDevice);
//GetResult<<<dim3(32, 32), dim3(32, 32)>>>(cuda_b, cuda_x, cuda_shifts, row, );
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipEventDestroy(syncEvent);
//Calculating end
CSC(hipMemcpy(b, cuda_b, sizeof(TNum) * n * k, hipMemcpyDeviceToHost));
CSC(hipFree(cuda_a));
CSC(hipFree(cuda_b));
//cudaFree(cuda_x);
//PrintMatrix(cuda_b, shifts, m, k);
TNum zero = 0.;
uint32_t untill = 0;
if (row > 0) {
untill = shifts[0];
}
uint32_t rows_cnt = 0;
for (uint32_t i = 0; i < untill; i++) {
for (uint32_t j = 0; j < k; j++) {
//cout << "1: " << shifts[0] << "::" << i << ":" << j << endl;
if (j > 0) {
cout << " ";
}
cout << scientific << zero;
}
rows_cnt++;
cout << endl;
}
//cout << row << endl;
for (uint32_t i = 0; i < row; i++) {
if (i > 0) {
for (uint32_t ii = 0; ii < shifts[i] - shifts[i - 1] - 1; ii++) {
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "2: " << i << ":" << j << endl;
cout << scientific << zero;
}
rows_cnt++;
cout << endl;
}
}
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "3: " << i << ":" << j << endl;
cout << scientific << b[GetLinearPosition(i, j, n, k)];
}
rows_cnt++;
cout << endl;
}
//cout << "TEST0" << endl;
//cout << shifts[0] << endl;
//untill = m - shifts[max(0, (int32_t) row - 1)];
for (uint32_t i = 0; i < m - rows_cnt; i++) {
for (uint32_t j = 0; j < k; j++) {
if (j > 0) {
cout << " ";
}
//cout << "4: " << i << ":" << j << endl;
cout << scientific << zero;
}
cout << endl;
}
//cout << "TEST1" << endl;
/*cout << "SHIFTS:\n";
for (uint32_t i = 0; i < row; i++) {
cout << shifts[i] << endl;
}*/
delete [] shifts;
delete [] a;
delete [] b;
//delete [] cuda_x;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
cudaMalloc((void**)&ary1 , 100000*sizeof(int));
cudaMalloc((void**)&ary2 , 100000*sizeof(int));
cudaMalloc((void**)&ary3 , 100000*sizeof(int));
cudaMemcpy(ary2, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(ary1, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
cudaMemcpy(b, ary3 ,100000*sizeof(int),cudaMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
cudaFree(ary1);
cudaFree(ary2);
cudaFree(ary3);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
cudaMalloc((void**)&ary1 , 100000*sizeof(int));
cudaMalloc((void**)&ary2 , 100000*sizeof(int));
cudaMalloc((void**)&ary3 , 100000*sizeof(int));
cudaMemcpy(ary2, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(ary1, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
cudaMemcpy(b, ary3 ,100000*sizeof(int),cudaMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
cudaFree(ary1);
cudaFree(ary2);
cudaFree(ary3);
return 0;
} | .file "tmpxft_000a2dd1_00000000-6_example3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -798720(%rsp), %r11
.cfi_def_cfa 11, 798736
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1328, %rsp
.cfi_def_cfa_offset 800064
movq %fs:40, %rax
movq %rax, 800040(%rsp)
xorl %eax, %eax
.L4:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L4
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L5:
movq 16(%rsp), %rdx
movl (%rdx,%rax), %edx
movq 8(%rsp), %rcx
addl (%rcx,%rax), %edx
movq 24(%rsp), %rcx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L5
leaq 400032(%rsp), %rdi
movl $2, %ecx
movl $400000, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
.L9:
leal 499(%rbx), %eax
cmpl $998, %eax
jbe .L14
addl $1, %ebx
cmpl $100000, %ebx
jne .L9
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 800040(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $800048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
jmp .L9
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
cudaMalloc((void**)&ary1 , 100000*sizeof(int));
cudaMalloc((void**)&ary2 , 100000*sizeof(int));
cudaMalloc((void**)&ary3 , 100000*sizeof(int));
cudaMemcpy(ary2, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(ary1, a, 100000*sizeof(int),cudaMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
cudaMemcpy(b, ary3 ,100000*sizeof(int),cudaMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
cudaFree(ary1);
cudaFree(ary2);
cudaFree(ary3);
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
hipMalloc((void**)&ary1 , 100000*sizeof(int));
hipMalloc((void**)&ary2 , 100000*sizeof(int));
hipMalloc((void**)&ary3 , 100000*sizeof(int));
hipMemcpy(ary2, a, 100000*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(ary1, a, 100000*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
hipMemcpy(b, ary3 ,100000*sizeof(int),hipMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
hipFree(ary1);
hipFree(ary2);
hipFree(ary3);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
hipMalloc((void**)&ary1 , 100000*sizeof(int));
hipMalloc((void**)&ary2 , 100000*sizeof(int));
hipMalloc((void**)&ary3 , 100000*sizeof(int));
hipMemcpy(ary2, a, 100000*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(ary1, a, 100000*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
hipMemcpy(b, ary3 ,100000*sizeof(int),hipMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
hipFree(ary1);
hipFree(ary2);
hipFree(ary3);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <stdio.h>
int main(void)
{
int a[100000];
int b[100000];
int *ary1;
int *ary2;
int *ary3;
for(int i=0;i<100000;i++)
{
a[i] = i;
}
hipMalloc((void**)&ary1 , 100000*sizeof(int));
hipMalloc((void**)&ary2 , 100000*sizeof(int));
hipMalloc((void**)&ary3 , 100000*sizeof(int));
hipMemcpy(ary2, a, 100000*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(ary1, a, 100000*sizeof(int),hipMemcpyHostToDevice);
for(int i=0;i<100000;i++)
{
ary3[i] = ary1[i] + ary2[i];
}
hipMemcpy(b, ary3 ,100000*sizeof(int),hipMemcpyDeviceToHost);
for(int i =0; i < 100000; i++)
{
if(i/500 ==0)
{
printf("%d ",i);
}
}
hipFree(ary1);
hipFree(ary2);
hipFree(ary3);
return 0;
} | .text
.file "example3.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $800032, %rsp # imm = 0xC3520
.cfi_def_cfa_offset 800048
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, 32(%rsp,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 16(%rsp), %rdi
leaq 32(%rsp), %rbx
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%rcx,%rdx,4), %edi
addl (%rax,%rdx,4), %edi
movl %edi, (%rsi,%rdx,4)
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB0_3
# %bb.4:
movq 8(%rsp), %rsi
leaq 400032(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_5 Depth=1
incl %ebx
cmpl $100000, %ebx # imm = 0x186A0
je .LBB0_8
.LBB0_5: # =>This Inner Loop Header: Depth=1
cmpl $499, %ebx # imm = 0x1F3
ja .LBB0_7
# %bb.6: # in Loop: Header=BB0_5 Depth=1
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_7
.LBB0_8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $800032, %rsp # imm = 0xC3520
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
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