system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a2dd1_00000000-6_example3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -798720(%rsp), %r11
.cfi_def_cfa 11, 798736
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1328, %rsp
.cfi_def_cfa_offset 800064
movq %fs:40, %rax
movq %rax, 800040(%rsp)
xorl %eax, %eax
.L4:
movl %eax, 32(%rsp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L4
leaq 8(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rbx
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %eax
.L5:
movq 16(%rsp), %rdx
movl (%rdx,%rax), %edx
movq 8(%rsp), %rcx
addl (%rcx,%rax), %edx
movq 24(%rsp), %rcx
movl %edx, (%rcx,%rax)
addq $4, %rax
cmpq $400000, %rax
jne .L5
leaq 400032(%rsp), %rdi
movl $2, %ecx
movl $400000, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
.L9:
leal 499(%rbx), %eax
cmpl $998, %eax
jbe .L14
addl $1, %ebx
cmpl $100000, %ebx
jne .L9
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 800040(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $800048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
jmp .L9
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "example3.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $800032, %rsp # imm = 0xC3520
.cfi_def_cfa_offset 800048
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %eax, 32(%rsp,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB0_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 16(%rsp), %rdi
leaq 32(%rsp), %rbx
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
xorl %edx, %edx
movq 8(%rsp), %rsi
.p2align 4, 0x90
.LBB0_3: # =>This Inner Loop Header: Depth=1
movl (%rcx,%rdx,4), %edi
addl (%rax,%rdx,4), %edi
movl %edi, (%rsi,%rdx,4)
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB0_3
# %bb.4:
movq 8(%rsp), %rsi
leaq 400032(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_5 Depth=1
incl %ebx
cmpl $100000, %ebx # imm = 0x186A0
je .LBB0_8
.LBB0_5: # =>This Inner Loop Header: Depth=1
cmpl $499, %ebx # imm = 0x1F3
ja .LBB0_7
# %bb.6: # in Loop: Header=BB0_5 Depth=1
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
jmp .LBB0_7
.LBB0_8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $800032, %rsp # imm = 0xC3520
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} | code for sm_80
Function : _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fda0003f01270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ IADD3 R0, R3.reuse, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R4, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003047a10 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00d0*/ LOP3.LUT R0, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303007812 */
/* 0x040fe200078ec0ff */
/*00e0*/ IMAD R3, R3, c[0x0][0x184], RZ ; /* 0x0000610003037a24 */
/* 0x000fe200078e02ff */
/*00f0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R5, -R0, c[0x0][0x188], RZ ; /* 0x0000620000057a10 */
/* 0x000fc40007ffe1ff */
/*0110*/ IABS R9, c[0x0][0x180] ; /* 0x0000600000097a13 */
/* 0x000fc80000000000 */
/*0120*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x001e300000209400 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x002064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0170*/ IADD3 R10, RZ, -R7, RZ ; /* 0x80000007ff0a7210 */
/* 0x002fca0007ffe0ff */
/*0180*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R10, R2 ; /* 0x00000002000a7213 */
/* 0x000fc60000000000 */
/*01a0*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fe200078e0006 */
/*01b0*/ LOP3.LUT R6, R2, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600002067a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f66270 */
/*01d0*/ IMAD.HI.U32 R7, R7, R10, RZ ; /* 0x0000000a07077227 */
/* 0x000fe200078e00ff */
/*01e0*/ MOV R6, c[0x0][0x188] ; /* 0x0000620000067a02 */
/* 0x000fc80000000f00 */
/*01f0*/ IADD3 R8, -R7, RZ, RZ ; /* 0x000000ff07087210 */
/* 0x000fca0007ffe1ff */
/*0200*/ IMAD R8, R9, R8, R10 ; /* 0x0000000809087224 */
/* 0x000fca00078e020a */
/*0210*/ ISETP.GT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f44070 */
/*0220*/ @!P2 IMAD.IADD R8, R8, 0x1, -R9 ; /* 0x000000010808a824 */
/* 0x000fe200078e0a09 */
/*0230*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0270*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fd400078e0a07 */
/*0280*/ @!P0 BRA 0xfe0 ; /* 0x00000d5000008947 */
/* 0x02cfea0003800000 */
/*0290*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f66270 */
/*02a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*02b0*/ ISETP.GT.U32.AND P2, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe40003f44070 */
/*02c0*/ IADD3 R9, R8, -R9, RZ ; /* 0x8000000908097210 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f05270 */
/*02e0*/ SEL R9, R9, R8, !P2 ; /* 0x0000000809097207 */
/* 0x000fe40005000000 */
/*02f0*/ LOP3.LUT R6, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff067a12 */
/* 0x000fe200078e33ff */
/*0300*/ IMAD.WIDE R12, R2, R13, c[0x0][0x168] ; /* 0x00005a00020c7625 */
/* 0x000fc600078e020d */
/*0310*/ SEL R8, R6, R7, !P0 ; /* 0x0000000706087207 */
/* 0x000fe20004000000 */
/*0320*/ @!P3 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09b224 */
/* 0x000fe400078e0a09 */
/*0330*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0340*/ SEL R9, R6, R9, !P0 ; /* 0x0000000906097207 */
/* 0x000fe20004000000 */
/*0350*/ IMAD R6, R8, c[0x0][0x184], RZ ; /* 0x0000610008067a24 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD R8, R3, R8, R9.reuse ; /* 0x0000000803087224 */
/* 0x100fe400078e0209 */
/*0370*/ IMAD R9, R6, c[0x0][0x188], R9 ; /* 0x0000620006097a24 */
/* 0x000fe400078e0209 */
/*0380*/ IADD3 R18, R6, R7.reuse, RZ ; /* 0x0000000706127210 */
/* 0x080fe20007ffe0ff */
/*0390*/ IMAD R10, R4, R7, RZ ; /* 0x00000007040a7224 */
/* 0x000fe200078e02ff */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R18, R18, c[0x0][0x188], RZ ; /* 0x0000620012127a24 */
/* 0x000fe200078e02ff */
/*03d0*/ ISETP.GE.AND P2, PT, R7, c[0x0][0x184], PT ; /* 0x0000610007007a0c */
/* 0x000fe20003f46270 */
/*03e0*/ @!P1 BRA 0xe50 ; /* 0x00000a6000009947 */
/* 0x02ffea0003800000 */
/*03f0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*0400*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0410*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R21, R8, R10, RZ ; /* 0x0000000a08157210 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0460*/ MOV R20, c[0x0][0x174] ; /* 0x00005d0000147a02 */
/* 0x000fe20000000f00 */
/*0470*/ IMAD.WIDE R14, R18, R15, c[0x0][0x178] ; /* 0x00005e00120e7625 */
/* 0x000fcc00078e020f */
/*0480*/ @!P0 BRA 0xc90 ; /* 0x0000080000008947 */
/* 0x001fea0003800000 */
/*0490*/ ISETP.GT.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f64270 */
/*04a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04b0*/ @!P3 BRA 0x990 ; /* 0x000004d00000b947 */
/* 0x000fea0003800000 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04d0*/ MOV R16, R19 ; /* 0x0000001300107202 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R17, RZ, RZ, R20 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0014 */
/*04f0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea6000c1e1900 */
/*0500*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0510*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x026fca0000000019 */
/*0530*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0570*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*05b0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*05d0*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e24000c1e1900 */
/*05e0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*05f0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0600*/ LDG.E R22, [R16.64+0x10] ; /* 0x0000100410167981 */
/* 0x000e68000c1e1900 */
/*0610*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000e64000c1e1900 */
/*0620*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0630*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0640*/ LDG.E R22, [R16.64+0x14] ; /* 0x0000140410167981 */
/* 0x000ea8000c1e1900 */
/*0650*/ LDG.E R24, [R14.64+0x14] ; /* 0x000014040e187981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0670*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R22, [R16.64+0x18] ; /* 0x0000180410167981 */
/* 0x000e28000c1e1900 */
/*0690*/ LDG.E R24, [R14.64+0x18] ; /* 0x000018040e187981 */
/* 0x000e24000c1e1900 */
/*06a0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*06b0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R22, [R16.64+0x1c] ; /* 0x00001c0410167981 */
/* 0x000e68000c1e1900 */
/*06d0*/ LDG.E R24, [R14.64+0x1c] ; /* 0x00001c040e187981 */
/* 0x000e64000c1e1900 */
/*06e0*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*06f0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0700*/ LDG.E R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R24, [R14.64+0x20] ; /* 0x000020040e187981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0730*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0740*/ LDG.E R22, [R16.64+0x24] ; /* 0x0000240410167981 */
/* 0x000e28000c1e1900 */
/*0750*/ LDG.E R24, [R14.64+0x24] ; /* 0x000024040e187981 */
/* 0x000e24000c1e1900 */
/*0760*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0770*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0780*/ LDG.E R22, [R16.64+0x28] ; /* 0x0000280410167981 */
/* 0x000e68000c1e1900 */
/*0790*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000e64000c1e1900 */
/*07a0*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*07b0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*07c0*/ LDG.E R22, [R16.64+0x2c] ; /* 0x00002c0410167981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R24, [R14.64+0x2c] ; /* 0x00002c040e187981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*07f0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0800*/ LDG.E R22, [R16.64+0x30] ; /* 0x0000300410167981 */
/* 0x000e28000c1e1900 */
/*0810*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000e24000c1e1900 */
/*0820*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0830*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R22, [R16.64+0x34] ; /* 0x0000340410167981 */
/* 0x000e68000c1e1900 */
/*0850*/ LDG.E R24, [R14.64+0x34] ; /* 0x000034040e187981 */
/* 0x000e64000c1e1900 */
/*0860*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0870*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0880*/ LDG.E R22, [R16.64+0x38] ; /* 0x0000380410167981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*08b0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0003e8000c101904 */
/*08c0*/ LDG.E R22, [R16.64+0x3c] ; /* 0x00003c0410167981 */
/* 0x000e28000c1e1900 */
/*08d0*/ LDG.E R24, [R14.64+0x3c] ; /* 0x00003c040e187981 */
/* 0x000e22000c1e1900 */
/*08e0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GT.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f64270 */
/*0900*/ IADD3 R19, P4, R19, 0x40, RZ ; /* 0x0000004013137810 */
/* 0x000fe40007f9e0ff */
/*0910*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc60007ffe0ff */
/*0920*/ IMAD.X R20, RZ, RZ, R20, P4 ; /* 0x000000ffff147224 */
/* 0x000fe400020e0614 */
/*0930*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0940*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e2000c101904 */
/*0950*/ IADD3 R22, P5, R14, 0x40, RZ ; /* 0x000000400e167810 */
/* 0x000fc80007fbe0ff */
/*0960*/ IADD3.X R15, RZ, R15, RZ, P5, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe40002ffe4ff */
/*0970*/ MOV R14, R22 ; /* 0x00000016000e7202 */
/* 0x000fe20000000f00 */
/*0980*/ @P3 BRA 0x4d0 ; /* 0xfffffb4000003947 */
/* 0x000fea000383ffff */
/*0990*/ ISETP.GT.AND P3, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f64270 */
/*09a0*/ @!P3 BRA 0xc70 ; /* 0x000002c00000b947 */
/* 0x000fea0003800000 */
/*09b0*/ MOV R17, R20 ; /* 0x0000001400117202 */
/* 0x000fe20000000f00 */
/*09c0*/ IMAD.MOV.U32 R16, RZ, RZ, R19 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0013 */
/*09d0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea6000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*09f0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea4000c1e1900 */
/*0a00*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x026fca0000000019 */
/*0a10*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0a20*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0a50*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0a60*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0a70*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0a90*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0aa0*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*0ab0*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e24000c1e1900 */
/*0ac0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0ad0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0ae0*/ LDG.E R22, [R16.64+0x10] ; /* 0x0000100410167981 */
/* 0x000e68000c1e1900 */
/*0af0*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000e64000c1e1900 */
/*0b00*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0b10*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0b20*/ LDG.E R22, [R16.64+0x14] ; /* 0x0000140410167981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R24, [R14.64+0x14] ; /* 0x000014040e187981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0b50*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0b60*/ LDG.E R22, [R16.64+0x18] ; /* 0x0000180410167981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R24, [R14.64+0x18] ; /* 0x000018040e187981 */
/* 0x000ee4000c1e1900 */
/*0b80*/ FFMA R22, R22, R24, R29 ; /* 0x0000001816167223 */
/* 0x008fca000000001d */
/*0b90*/ STG.E [R12.64], R22 ; /* 0x000000160c007986 */
/* 0x0005e8000c101904 */
/*0ba0*/ LDG.E R25, [R16.64+0x1c] ; /* 0x00001c0410197981 */
/* 0x001ee8000c1e1900 */
/*0bb0*/ LDG.E R24, [R14.64+0x1c] ; /* 0x00001c040e187981 */
/* 0x000ee2000c1e1900 */
/*0bc0*/ IADD3 R19, P3, R19, 0x20, RZ ; /* 0x0000002013137810 */
/* 0x000fe40007f7e0ff */
/*0bd0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0be0*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0c00*/ IADD3.X R20, RZ, R20, RZ, P3, !PT ; /* 0x00000014ff147210 */
/* 0x000fe20001ffe4ff */
/*0c10*/ FFMA R25, R25, R24, R22 ; /* 0x0000001819197223 */
/* 0x008fca0000000016 */
/*0c20*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0005e2000c101904 */
/*0c30*/ IADD3 R24, P4, R14, 0x20, RZ ; /* 0x000000200e187810 */
/* 0x000fca0007f9e0ff */
/*0c40*/ IMAD.X R27, RZ, RZ, R15, P4 ; /* 0x000000ffff1b7224 */
/* 0x002fe400020e060f */
/*0c50*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0018 */
/*0c60*/ MOV R15, R27 ; /* 0x0000001b000f7202 */
/* 0x000fe40000000f00 */
/*0c70*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0c80*/ @!P0 BRA 0xe50 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0c90*/ MOV R17, R20 ; /* 0x0000001400117202 */
/* 0x000fe20000000f00 */
/*0ca0*/ IMAD.MOV.U32 R16, RZ, RZ, R19 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0013 */
/*0cb0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ee6000c1e1900 */
/*0cc0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0cd0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x004ee4000c1e1900 */
/*0ce0*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x02afca0000000019 */
/*0cf0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0d00*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0d10*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0d20*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0d30*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0d40*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0d50*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*0d60*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0d70*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0003e8000c101904 */
/*0d80*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*0d90*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e22000c1e1900 */
/*0da0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0dc0*/ IADD3 R19, P3, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007f7e0ff */
/*0dd0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ IADD3.X R20, RZ, R20, RZ, P3, !PT ; /* 0x00000014ff147210 */
/* 0x000fe20001ffe4ff */
/*0df0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0e00*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e2000c101904 */
/*0e10*/ IADD3 R22, P4, R14, 0x10, RZ ; /* 0x000000100e167810 */
/* 0x000fca0007f9e0ff */
/*0e20*/ IMAD.X R15, RZ, RZ, R15, P4 ; /* 0x000000ffff0f7224 */
/* 0x000fe400020e060f */
/*0e30*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0016 */
/*0e40*/ @P0 BRA 0xc90 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 BRA 0xfd0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0e70*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0e80*/ IADD3 R10, R23, R9, R10 ; /* 0x00000009170a7210 */
/* 0x000fe20007ffe00a */
/*0e90*/ IMAD.IADD R14, R18, 0x1, R23 ; /* 0x00000001120e7824 */
/* 0x000fe400078e0217 */
/*0ea0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000eec000c1e1900 */
/*0eb0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e020f */
/*0ec0*/ IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fe200078e020f */
/*0ed0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee8000c1e1900 */
/*0ee0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000ee2000c1e1900 */
/*0ef0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*0f00*/ FFMA R19, R16, R17, R18 ; /* 0x0000001110137223 */
/* 0x008fca0000000012 */
/*0f10*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001ee000c101904 */
/*0f20*/ @!P0 BRA 0xfd0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0f30*/ LDG.E R16, [R10.64+0x4] ; /* 0x000004040a107981 */
/* 0x000ee8000c1e1900 */
/*0f40*/ LDG.E R17, [R14.64+0x4] ; /* 0x000004040e117981 */
/* 0x000ee2000c1e1900 */
/*0f50*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0f60*/ FFMA R17, R16, R17, R19 ; /* 0x0000001110117223 */
/* 0x008fca0000000013 */
/*0f70*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0007ee000c101904 */
/*0f80*/ @!P0 BRA 0xfd0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0f90*/ LDG.E R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f28000c1e1900 */
/*0fa0*/ LDG.E R15, [R14.64+0x8] ; /* 0x000008040e0f7981 */
/* 0x000f24000c1e1900 */
/*0fb0*/ FFMA R17, R10, R15, R17 ; /* 0x0000000f0a117223 */
/* 0x018fca0000000011 */
/*0fc0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0007e4000c101904 */
/*0fd0*/ @!P2 BRA 0x380 ; /* 0xfffff3a00000a947 */
/* 0x000fea000383ffff */
/*0fe0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*0ff0*/ IMAD R2, R7, c[0x0][0xc], R2 ; /* 0x0000030007027a24 */
/* 0x000fca00078e0202 */
/*1000*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*1010*/ @P0 CALL.REL.NOINC 0x1030 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*1020*/ BRA 0x110 ; /* 0xfffff0e000007947 */
/* 0x000fea000383ffff */
/*1030*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1040*/ BRA 0x1040; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} | .file "tmpxft_000a1fb9_00000000-6_conv_horizontal_naive_gradParam.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
.type _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii, @function
_Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii, .-_Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, @function
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, .-_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 8
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii,@function
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s17, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x28
s_load_b32 s3, s[2:3], 0x0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s10, s0
s_mul_i32 s3, s3, s17
s_add_i32 s1, s1, -1
s_cmp_gt_i32 s11, 0
s_cselect_b32 s13, -1, 0
s_cmp_gt_i32 s0, 0
s_cselect_b32 s14, -1, 0
s_ashr_i32 s15, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s16, s10, s15
s_xor_b32 s16, s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s16
s_sub_i32 s18, 0, s16
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v1
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v5, v2, v4
v_xor_b32_e32 v4, s15, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, v0, 0
v_mul_lo_u32 v2, v3, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v5, v2
v_subrev_nc_u32_e32 v6, s16, v2
v_cmp_le_u32_e32 vcc_lo, s16, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s16, v2
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v5, vcc_lo
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_mul_lo_u32 v3, v2, s11
v_mul_lo_u32 v4, v2, s10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v4, v1, v4
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_nc_u32_e32 v5, v3, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v5, s1, v5
v_add_nc_u32_e32 v3, s0, v3
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s17, s11
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
global_load_b32 v2, v[7:8], off
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s18, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
.p2align 6
.LBB0_8:
global_load_b32 v4, v[11:12], off
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_add_i32 s18, s18, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v4, v6
global_store_b32 v[7:8], v2, off
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, .Lfunc_end0-_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void conv_horizontal_naive_gradParam(const int n, float *dw, const float *x, const float *dy, const int kL, const int oH, const int oW)
{
for (int i = blockIdx.x*blockDim.x+threadIdx.x; i < n; i += blockDim.x*gridDim.x) {
int iW = oW + kL - 1;
int dy_offset = (i/kL)*oH*oW;
int x_offset = (i/kL)*oH*oW + i%kL;
for (int j = 0; j < oH; j++) {
for (int k = 0; k < oW; k++) {
dw[i] += dy[dy_offset + j*oW + k]*x[x_offset + j*iW + k];
}
}
}
} | .text
.file "conv_horizontal_naive_gradParam.hip"
.globl _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii # -- Begin function _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 4, 0x90
.type _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii,@function
_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii: # @_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii, .Lfunc_end0-_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii,@object # @_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .rodata,"a",@progbits
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 3, 0x0
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
.quad _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fda0003f01270 */
/*0070*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff037624 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00a0*/ IADD3 R0, R3.reuse, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R4, R3.reuse, c[0x0][0x180], RZ ; /* 0x0000600003047a10 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f26070 */
/*00d0*/ LOP3.LUT R0, R3.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303007812 */
/* 0x040fe200078ec0ff */
/*00e0*/ IMAD R3, R3, c[0x0][0x184], RZ ; /* 0x0000610003037a24 */
/* 0x000fe200078e02ff */
/*00f0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0100*/ IADD3 R5, -R0, c[0x0][0x188], RZ ; /* 0x0000620000057a10 */
/* 0x000fc40007ffe1ff */
/*0110*/ IABS R9, c[0x0][0x180] ; /* 0x0000600000097a13 */
/* 0x000fc80000000000 */
/*0120*/ I2F.RP R8, R9 ; /* 0x0000000900087306 */
/* 0x001e300000209400 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x002064000021f000 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe200078e00ff */
/*0170*/ IADD3 R10, RZ, -R7, RZ ; /* 0x80000007ff0a7210 */
/* 0x002fca0007ffe0ff */
/*0180*/ IMAD R11, R10, R9, RZ ; /* 0x000000090a0b7224 */
/* 0x000fe200078e02ff */
/*0190*/ IABS R10, R2 ; /* 0x00000002000a7213 */
/* 0x000fc60000000000 */
/*01a0*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fe200078e0006 */
/*01b0*/ LOP3.LUT R6, R2, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600002067a12 */
/* 0x000fc800078e3cff */
/*01c0*/ ISETP.GE.AND P3, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f66270 */
/*01d0*/ IMAD.HI.U32 R7, R7, R10, RZ ; /* 0x0000000a07077227 */
/* 0x000fe200078e00ff */
/*01e0*/ MOV R6, c[0x0][0x188] ; /* 0x0000620000067a02 */
/* 0x000fc80000000f00 */
/*01f0*/ IADD3 R8, -R7, RZ, RZ ; /* 0x000000ff07087210 */
/* 0x000fca0007ffe1ff */
/*0200*/ IMAD R8, R9, R8, R10 ; /* 0x0000000809087224 */
/* 0x000fca00078e020a */
/*0210*/ ISETP.GT.U32.AND P2, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x000fda0003f44070 */
/*0220*/ @!P2 IMAD.IADD R8, R8, 0x1, -R9 ; /* 0x000000010808a824 */
/* 0x000fe200078e0a09 */
/*0230*/ @!P2 IADD3 R7, R7, 0x1, RZ ; /* 0x000000010707a810 */
/* 0x000fc80007ffe0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fda0003f06070 */
/*0250*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0270*/ @!P3 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07b224 */
/* 0x000fd400078e0a07 */
/*0280*/ @!P0 BRA 0xfe0 ; /* 0x00000d5000008947 */
/* 0x02cfea0003800000 */
/*0290*/ ISETP.GE.AND P3, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f66270 */
/*02a0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*02b0*/ ISETP.GT.U32.AND P2, PT, R9, R8.reuse, PT ; /* 0x000000080900720c */
/* 0x080fe40003f44070 */
/*02c0*/ IADD3 R9, R8, -R9, RZ ; /* 0x8000000908097210 */
/* 0x000fe40007ffe0ff */
/*02d0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f05270 */
/*02e0*/ SEL R9, R9, R8, !P2 ; /* 0x0000000809097207 */
/* 0x000fe40005000000 */
/*02f0*/ LOP3.LUT R6, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff067a12 */
/* 0x000fe200078e33ff */
/*0300*/ IMAD.WIDE R12, R2, R13, c[0x0][0x168] ; /* 0x00005a00020c7625 */
/* 0x000fc600078e020d */
/*0310*/ SEL R8, R6, R7, !P0 ; /* 0x0000000706087207 */
/* 0x000fe20004000000 */
/*0320*/ @!P3 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09b224 */
/* 0x000fe400078e0a09 */
/*0330*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc600078e00ff */
/*0340*/ SEL R9, R6, R9, !P0 ; /* 0x0000000906097207 */
/* 0x000fe20004000000 */
/*0350*/ IMAD R6, R8, c[0x0][0x184], RZ ; /* 0x0000610008067a24 */
/* 0x000fc800078e02ff */
/*0360*/ IMAD R8, R3, R8, R9.reuse ; /* 0x0000000803087224 */
/* 0x100fe400078e0209 */
/*0370*/ IMAD R9, R6, c[0x0][0x188], R9 ; /* 0x0000620006097a24 */
/* 0x000fe400078e0209 */
/*0380*/ IADD3 R18, R6, R7.reuse, RZ ; /* 0x0000000706127210 */
/* 0x080fe20007ffe0ff */
/*0390*/ IMAD R10, R4, R7, RZ ; /* 0x00000007040a7224 */
/* 0x000fe200078e02ff */
/*03a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe400078e00ff */
/*03c0*/ IMAD R18, R18, c[0x0][0x188], RZ ; /* 0x0000620012127a24 */
/* 0x000fe200078e02ff */
/*03d0*/ ISETP.GE.AND P2, PT, R7, c[0x0][0x184], PT ; /* 0x0000610007007a0c */
/* 0x000fe20003f46270 */
/*03e0*/ @!P1 BRA 0xe50 ; /* 0x00000a6000009947 */
/* 0x02ffea0003800000 */
/*03f0*/ LDG.E R25, [R12.64] ; /* 0x000000040c197981 */
/* 0x000162000c1e1900 */
/*0400*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*0410*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0420*/ IADD3 R21, R8, R10, RZ ; /* 0x0000000a08157210 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD.MOV.U32 R19, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff137624 */
/* 0x000fe200078e00ff */
/*0440*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fe20000000f00 */
/*0450*/ IMAD.MOV.U32 R11, RZ, RZ, R5 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0005 */
/*0460*/ MOV R20, c[0x0][0x174] ; /* 0x00005d0000147a02 */
/* 0x000fe20000000f00 */
/*0470*/ IMAD.WIDE R14, R18, R15, c[0x0][0x178] ; /* 0x00005e00120e7625 */
/* 0x000fcc00078e020f */
/*0480*/ @!P0 BRA 0xc90 ; /* 0x0000080000008947 */
/* 0x001fea0003800000 */
/*0490*/ ISETP.GT.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f64270 */
/*04a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*04b0*/ @!P3 BRA 0x990 ; /* 0x000004d00000b947 */
/* 0x000fea0003800000 */
/*04c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04d0*/ MOV R16, R19 ; /* 0x0000001300107202 */
/* 0x000fe20000000f00 */
/*04e0*/ IMAD.MOV.U32 R17, RZ, RZ, R20 ; /* 0x000000ffff117224 */
/* 0x000fe200078e0014 */
/*04f0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea6000c1e1900 */
/*0500*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0510*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea4000c1e1900 */
/*0520*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x026fca0000000019 */
/*0530*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0540*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0560*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0570*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0580*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*05b0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*05d0*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e24000c1e1900 */
/*05e0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*05f0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0600*/ LDG.E R22, [R16.64+0x10] ; /* 0x0000100410167981 */
/* 0x000e68000c1e1900 */
/*0610*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000e64000c1e1900 */
/*0620*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0630*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0640*/ LDG.E R22, [R16.64+0x14] ; /* 0x0000140410167981 */
/* 0x000ea8000c1e1900 */
/*0650*/ LDG.E R24, [R14.64+0x14] ; /* 0x000014040e187981 */
/* 0x000ea4000c1e1900 */
/*0660*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0670*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R22, [R16.64+0x18] ; /* 0x0000180410167981 */
/* 0x000e28000c1e1900 */
/*0690*/ LDG.E R24, [R14.64+0x18] ; /* 0x000018040e187981 */
/* 0x000e24000c1e1900 */
/*06a0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*06b0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*06c0*/ LDG.E R22, [R16.64+0x1c] ; /* 0x00001c0410167981 */
/* 0x000e68000c1e1900 */
/*06d0*/ LDG.E R24, [R14.64+0x1c] ; /* 0x00001c040e187981 */
/* 0x000e64000c1e1900 */
/*06e0*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*06f0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0700*/ LDG.E R22, [R16.64+0x20] ; /* 0x0000200410167981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R24, [R14.64+0x20] ; /* 0x000020040e187981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0730*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0740*/ LDG.E R22, [R16.64+0x24] ; /* 0x0000240410167981 */
/* 0x000e28000c1e1900 */
/*0750*/ LDG.E R24, [R14.64+0x24] ; /* 0x000024040e187981 */
/* 0x000e24000c1e1900 */
/*0760*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0770*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0780*/ LDG.E R22, [R16.64+0x28] ; /* 0x0000280410167981 */
/* 0x000e68000c1e1900 */
/*0790*/ LDG.E R24, [R14.64+0x28] ; /* 0x000028040e187981 */
/* 0x000e64000c1e1900 */
/*07a0*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*07b0*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*07c0*/ LDG.E R22, [R16.64+0x2c] ; /* 0x00002c0410167981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R24, [R14.64+0x2c] ; /* 0x00002c040e187981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*07f0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0800*/ LDG.E R22, [R16.64+0x30] ; /* 0x0000300410167981 */
/* 0x000e28000c1e1900 */
/*0810*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000e24000c1e1900 */
/*0820*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0830*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R22, [R16.64+0x34] ; /* 0x0000340410167981 */
/* 0x000e68000c1e1900 */
/*0850*/ LDG.E R24, [R14.64+0x34] ; /* 0x000034040e187981 */
/* 0x000e64000c1e1900 */
/*0860*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0870*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0880*/ LDG.E R22, [R16.64+0x38] ; /* 0x0000380410167981 */
/* 0x000ea8000c1e1900 */
/*0890*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*08b0*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0003e8000c101904 */
/*08c0*/ LDG.E R22, [R16.64+0x3c] ; /* 0x00003c0410167981 */
/* 0x000e28000c1e1900 */
/*08d0*/ LDG.E R24, [R14.64+0x3c] ; /* 0x00003c040e187981 */
/* 0x000e22000c1e1900 */
/*08e0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GT.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f64270 */
/*0900*/ IADD3 R19, P4, R19, 0x40, RZ ; /* 0x0000004013137810 */
/* 0x000fe40007f9e0ff */
/*0910*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fc60007ffe0ff */
/*0920*/ IMAD.X R20, RZ, RZ, R20, P4 ; /* 0x000000ffff147224 */
/* 0x000fe400020e0614 */
/*0930*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0940*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e2000c101904 */
/*0950*/ IADD3 R22, P5, R14, 0x40, RZ ; /* 0x000000400e167810 */
/* 0x000fc80007fbe0ff */
/*0960*/ IADD3.X R15, RZ, R15, RZ, P5, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe40002ffe4ff */
/*0970*/ MOV R14, R22 ; /* 0x00000016000e7202 */
/* 0x000fe20000000f00 */
/*0980*/ @P3 BRA 0x4d0 ; /* 0xfffffb4000003947 */
/* 0x000fea000383ffff */
/*0990*/ ISETP.GT.AND P3, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f64270 */
/*09a0*/ @!P3 BRA 0xc70 ; /* 0x000002c00000b947 */
/* 0x000fea0003800000 */
/*09b0*/ MOV R17, R20 ; /* 0x0000001400117202 */
/* 0x000fe20000000f00 */
/*09c0*/ IMAD.MOV.U32 R16, RZ, RZ, R19 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0013 */
/*09d0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ea6000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*09f0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000ea4000c1e1900 */
/*0a00*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x026fca0000000019 */
/*0a10*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0a20*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0a40*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0a50*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0a60*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0a70*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*0a80*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0a90*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0aa0*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*0ab0*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e24000c1e1900 */
/*0ac0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0ad0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0ae0*/ LDG.E R22, [R16.64+0x10] ; /* 0x0000100410167981 */
/* 0x000e68000c1e1900 */
/*0af0*/ LDG.E R24, [R14.64+0x10] ; /* 0x000010040e187981 */
/* 0x000e64000c1e1900 */
/*0b00*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x002fca0000000019 */
/*0b10*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0b20*/ LDG.E R22, [R16.64+0x14] ; /* 0x0000140410167981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R24, [R14.64+0x14] ; /* 0x000014040e187981 */
/* 0x000ea4000c1e1900 */
/*0b40*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0b50*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0005e8000c101904 */
/*0b60*/ LDG.E R22, [R16.64+0x18] ; /* 0x0000180410167981 */
/* 0x000ee8000c1e1900 */
/*0b70*/ LDG.E R24, [R14.64+0x18] ; /* 0x000018040e187981 */
/* 0x000ee4000c1e1900 */
/*0b80*/ FFMA R22, R22, R24, R29 ; /* 0x0000001816167223 */
/* 0x008fca000000001d */
/*0b90*/ STG.E [R12.64], R22 ; /* 0x000000160c007986 */
/* 0x0005e8000c101904 */
/*0ba0*/ LDG.E R25, [R16.64+0x1c] ; /* 0x00001c0410197981 */
/* 0x001ee8000c1e1900 */
/*0bb0*/ LDG.E R24, [R14.64+0x1c] ; /* 0x00001c040e187981 */
/* 0x000ee2000c1e1900 */
/*0bc0*/ IADD3 R19, P3, R19, 0x20, RZ ; /* 0x0000002013137810 */
/* 0x000fe40007f7e0ff */
/*0bd0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0be0*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fe40007ffe0ff */
/*0bf0*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe40007ffe0ff */
/*0c00*/ IADD3.X R20, RZ, R20, RZ, P3, !PT ; /* 0x00000014ff147210 */
/* 0x000fe20001ffe4ff */
/*0c10*/ FFMA R25, R25, R24, R22 ; /* 0x0000001819197223 */
/* 0x008fca0000000016 */
/*0c20*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0005e2000c101904 */
/*0c30*/ IADD3 R24, P4, R14, 0x20, RZ ; /* 0x000000200e187810 */
/* 0x000fca0007f9e0ff */
/*0c40*/ IMAD.X R27, RZ, RZ, R15, P4 ; /* 0x000000ffff1b7224 */
/* 0x002fe400020e060f */
/*0c50*/ IMAD.MOV.U32 R14, RZ, RZ, R24 ; /* 0x000000ffff0e7224 */
/* 0x000fc600078e0018 */
/*0c60*/ MOV R15, R27 ; /* 0x0000001b000f7202 */
/* 0x000fe40000000f00 */
/*0c70*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0c80*/ @!P0 BRA 0xe50 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0c90*/ MOV R17, R20 ; /* 0x0000001400117202 */
/* 0x000fe20000000f00 */
/*0ca0*/ IMAD.MOV.U32 R16, RZ, RZ, R19 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0013 */
/*0cb0*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000ee6000c1e1900 */
/*0cc0*/ IMAD.WIDE R16, R21, 0x4, R16 ; /* 0x0000000415107825 */
/* 0x000fca00078e0210 */
/*0cd0*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x004ee4000c1e1900 */
/*0ce0*/ FFMA R25, R22, R24, R25 ; /* 0x0000001816197223 */
/* 0x02afca0000000019 */
/*0cf0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0001e8000c101904 */
/*0d00*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040410167981 */
/* 0x000ea8000c1e1900 */
/*0d10*/ LDG.E R24, [R14.64+0x4] ; /* 0x000004040e187981 */
/* 0x000ea4000c1e1900 */
/*0d20*/ FFMA R27, R22, R24, R25 ; /* 0x00000018161b7223 */
/* 0x004fca0000000019 */
/*0d30*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0003e8000c101904 */
/*0d40*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080410167981 */
/* 0x000ea8000c1e1900 */
/*0d50*/ LDG.E R24, [R14.64+0x8] ; /* 0x000008040e187981 */
/* 0x000ea4000c1e1900 */
/*0d60*/ FFMA R29, R22, R24, R27 ; /* 0x00000018161d7223 */
/* 0x004fca000000001b */
/*0d70*/ STG.E [R12.64], R29 ; /* 0x0000001d0c007986 */
/* 0x0003e8000c101904 */
/*0d80*/ LDG.E R22, [R16.64+0xc] ; /* 0x00000c0410167981 */
/* 0x000e28000c1e1900 */
/*0d90*/ LDG.E R24, [R14.64+0xc] ; /* 0x00000c040e187981 */
/* 0x000e22000c1e1900 */
/*0da0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fc80007ffe0ff */
/*0db0*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f05270 */
/*0dc0*/ IADD3 R19, P3, R19, 0x10, RZ ; /* 0x0000001013137810 */
/* 0x000fe40007f7e0ff */
/*0dd0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ IADD3.X R20, RZ, R20, RZ, P3, !PT ; /* 0x00000014ff147210 */
/* 0x000fe20001ffe4ff */
/*0df0*/ FFMA R25, R22, R24, R29 ; /* 0x0000001816197223 */
/* 0x001fca000000001d */
/*0e00*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e2000c101904 */
/*0e10*/ IADD3 R22, P4, R14, 0x10, RZ ; /* 0x000000100e167810 */
/* 0x000fca0007f9e0ff */
/*0e20*/ IMAD.X R15, RZ, RZ, R15, P4 ; /* 0x000000ffff0f7224 */
/* 0x000fe400020e060f */
/*0e30*/ IMAD.MOV.U32 R14, RZ, RZ, R22 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0016 */
/*0e40*/ @P0 BRA 0xc90 ; /* 0xfffffe4000000947 */
/* 0x002fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 BRA 0xfd0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0e70*/ HFMA2.MMA R15, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0f7435 */
/* 0x000fe200000001ff */
/*0e80*/ IADD3 R10, R23, R9, R10 ; /* 0x00000009170a7210 */
/* 0x000fe20007ffe00a */
/*0e90*/ IMAD.IADD R14, R18, 0x1, R23 ; /* 0x00000001120e7824 */
/* 0x000fe400078e0217 */
/*0ea0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000eec000c1e1900 */
/*0eb0*/ IMAD.WIDE R10, R10, R15, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc800078e020f */
/*0ec0*/ IMAD.WIDE R14, R14, R15, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fe200078e020f */
/*0ed0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee8000c1e1900 */
/*0ee0*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000ee2000c1e1900 */
/*0ef0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f05270 */
/*0f00*/ FFMA R19, R16, R17, R18 ; /* 0x0000001110137223 */
/* 0x008fca0000000012 */
/*0f10*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001ee000c101904 */
/*0f20*/ @!P0 BRA 0xfd0 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*0f30*/ LDG.E R16, [R10.64+0x4] ; /* 0x000004040a107981 */
/* 0x000ee8000c1e1900 */
/*0f40*/ LDG.E R17, [R14.64+0x4] ; /* 0x000004040e117981 */
/* 0x000ee2000c1e1900 */
/*0f50*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f05270 */
/*0f60*/ FFMA R17, R16, R17, R19 ; /* 0x0000001110117223 */
/* 0x008fca0000000013 */
/*0f70*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0007ee000c101904 */
/*0f80*/ @!P0 BRA 0xfd0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0f90*/ LDG.E R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f28000c1e1900 */
/*0fa0*/ LDG.E R15, [R14.64+0x8] ; /* 0x000008040e0f7981 */
/* 0x000f24000c1e1900 */
/*0fb0*/ FFMA R17, R10, R15, R17 ; /* 0x0000000f0a117223 */
/* 0x018fca0000000011 */
/*0fc0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0007e4000c101904 */
/*0fd0*/ @!P2 BRA 0x380 ; /* 0xfffff3a00000a947 */
/* 0x000fea000383ffff */
/*0fe0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*0ff0*/ IMAD R2, R7, c[0x0][0xc], R2 ; /* 0x0000030007027a24 */
/* 0x000fca00078e0202 */
/*1000*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*1010*/ @P0 CALL.REL.NOINC 0x1030 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*1020*/ BRA 0x110 ; /* 0xfffff0e000007947 */
/* 0x000fea000383ffff */
/*1030*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1040*/ BRA 0x1040; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 8
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii,@function
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s17, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x28
s_load_b32 s3, s[2:3], 0x0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s10, s0
s_mul_i32 s3, s3, s17
s_add_i32 s1, s1, -1
s_cmp_gt_i32 s11, 0
s_cselect_b32 s13, -1, 0
s_cmp_gt_i32 s0, 0
s_cselect_b32 s14, -1, 0
s_ashr_i32 s15, s10, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s16, s10, s15
s_xor_b32 s16, s16, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s16
s_sub_i32 s18, 0, s16
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s18, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
v_add_nc_u32_e32 v1, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s12, v1
s_or_b32 s2, vcc_lo, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_9
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v1
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v5, v2, v4
v_xor_b32_e32 v4, s15, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v5, v0, 0
v_mul_lo_u32 v2, v3, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v5, v2
v_subrev_nc_u32_e32 v6, s16, v2
v_cmp_le_u32_e32 vcc_lo, s16, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_add_nc_u32 v5, 1, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s16, v2
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v3, v5, vcc_lo
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_mul_lo_u32 v3, v2, s11
v_mul_lo_u32 v4, v2, s10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[7:8], 2, v[1:2]
v_mul_lo_u32 v3, v3, s0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v4, v1, v4
v_add_co_u32 v7, vcc_lo, s4, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
v_add_nc_u32_e32 v5, v3, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v5, s1, v5
v_add_nc_u32_e32 v3, s0, v3
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s17, s11
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_5
global_load_b32 v2, v[7:8], off
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s18, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[5:6]
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
.p2align 6
.LBB0_8:
global_load_b32 v4, v[11:12], off
global_load_b32 v6, v[9:10], off
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
s_add_i32 s18, s18, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v4, v6
global_store_b32 v[7:8], v2, off
s_cbranch_scc0 .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, .Lfunc_end0-_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1fb9_00000000-6_conv_horizontal_naive_gradParam.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
.type _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii, @function
_Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii, .-_Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, @function
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z61__device_stub__Z31conv_horizontal_naive_gradParamiPfPKfS1_iiiiPfPKfS1_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, .-_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conv_horizontal_naive_gradParam.hip"
.globl _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii # -- Begin function _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 4, 0x90
.type _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii,@function
_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii: # @_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii, .Lfunc_end0-_Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii,@object # @_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.section .rodata,"a",@progbits
.globl _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.p2align 3, 0x0
_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii:
.quad _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.size _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31conv_horizontal_naive_gradParamiPfPKfS1_iii"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__conv_horizontal_naive_gradParamiPfPKfS1_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31conv_horizontal_naive_gradParamiPfPKfS1_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float* var_20,float var_21,float var_22) {
if (comp < (var_1 + (-1.0618E-14f + var_2))) {
comp = (var_4 + tanhf((-0.0f + -0.0f)));
comp = log10f(+1.6829E16f);
comp = (var_5 * (var_6 / (var_7 - (var_8 - (+1.9521E-36f * -1.7751E35f)))));
if (comp <= (var_9 + (-1.0013E-44f + cosf((+1.5759E-43f + var_10))))) {
float tmp_1 = -1.6744E-30f;
float tmp_2 = (var_11 + floorf(asinf(-1.1162E-2f / var_12 * ceilf((var_13 - var_14 + var_15)))));
comp = tmp_2 / tmp_1 - (var_16 / (-1.8482E-42f + ceilf(-1.3313E-44f)));
comp += (var_17 + -1.8945E20f + +1.7824E-36f - var_18 + var_19);
}
for (int i=0; i < var_3; ++i) {
var_20[i] = +1.9524E-42f;
float tmp_3 = -1.1483E-36f;
comp += tmp_3 - var_20[i] + +1.0162E15f * var_21;
comp += var_22 / +1.2242E36f + -0.0f / -1.6344E-44f;
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float* tmp_21 = initPointer( atof(argv[21]) );
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0019d3ca_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
.type _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff, @function
_Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff:
.LFB2083:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movl %edi, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 320(%rsp), %rax
movq %rax, 184(%rsp)
leaq 328(%rsp), %rax
movq %rax, 192(%rsp)
leaq 336(%rsp), %rax
movq %rax, 200(%rsp)
leaq 344(%rsp), %rax
movq %rax, 208(%rsp)
leaq 352(%rsp), %rax
movq %rax, 216(%rsp)
leaq 360(%rsp), %rax
movq %rax, 224(%rsp)
leaq 368(%rsp), %rax
movq %rax, 232(%rsp)
leaq 376(%rsp), %rax
movq %rax, 240(%rsp)
leaq 384(%rsp), %rax
movq %rax, 248(%rsp)
leaq 392(%rsp), %rax
movq %rax, 256(%rsp)
leaq 400(%rsp), %rax
movq %rax, 264(%rsp)
movq %rsp, %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 328
pushq 56(%rsp)
.cfi_def_cfa_offset 336
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefffiffffffffffffffffPfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff, .-_Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
.globl _Z7computefffiffffffffffffffffPfff
.type _Z7computefffiffffffffffffffffPfff, @function
_Z7computefffiffffffffffffffffPfff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffiffffffffffffffffPfff, .-_Z7computefffiffffffffffffffffPfff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $208, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 352
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r12, %rsi
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
movl %ebp, %edi
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
call _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
addq $112, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffiffffffffffffffffPfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffiffffffffffffffffPfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float* var_20,float var_21,float var_22) {
if (comp < (var_1 + (-1.0618E-14f + var_2))) {
comp = (var_4 + tanhf((-0.0f + -0.0f)));
comp = log10f(+1.6829E16f);
comp = (var_5 * (var_6 / (var_7 - (var_8 - (+1.9521E-36f * -1.7751E35f)))));
if (comp <= (var_9 + (-1.0013E-44f + cosf((+1.5759E-43f + var_10))))) {
float tmp_1 = -1.6744E-30f;
float tmp_2 = (var_11 + floorf(asinf(-1.1162E-2f / var_12 * ceilf((var_13 - var_14 + var_15)))));
comp = tmp_2 / tmp_1 - (var_16 / (-1.8482E-42f + ceilf(-1.3313E-44f)));
comp += (var_17 + -1.8945E20f + +1.7824E-36f - var_18 + var_19);
}
for (int i=0; i < var_3; ++i) {
var_20[i] = +1.9524E-42f;
float tmp_3 = -1.1483E-36f;
comp += tmp_3 - var_20[i] + +1.0162E15f * var_21;
comp += var_22 / +1.2242E36f + -0.0f / -1.6344E-44f;
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float* tmp_21 = initPointer( atof(argv[21]) );
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float* var_20,float var_21,float var_22) {
if (comp < (var_1 + (-1.0618E-14f + var_2))) {
comp = (var_4 + tanhf((-0.0f + -0.0f)));
comp = log10f(+1.6829E16f);
comp = (var_5 * (var_6 / (var_7 - (var_8 - (+1.9521E-36f * -1.7751E35f)))));
if (comp <= (var_9 + (-1.0013E-44f + cosf((+1.5759E-43f + var_10))))) {
float tmp_1 = -1.6744E-30f;
float tmp_2 = (var_11 + floorf(asinf(-1.1162E-2f / var_12 * ceilf((var_13 - var_14 + var_15)))));
comp = tmp_2 / tmp_1 - (var_16 / (-1.8482E-42f + ceilf(-1.3313E-44f)));
comp += (var_17 + -1.8945E20f + +1.7824E-36f - var_18 + var_19);
}
for (int i=0; i < var_3; ++i) {
var_20[i] = +1.9524E-42f;
float tmp_3 = -1.1483E-36f;
comp += tmp_3 - var_20[i] + +1.0162E15f * var_21;
comp += var_22 / +1.2242E36f + -0.0f / -1.6344E-44f;
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float* tmp_21 = initPointer( atof(argv[21]) );
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float* var_20,float var_21,float var_22) {
if (comp < (var_1 + (-1.0618E-14f + var_2))) {
comp = (var_4 + tanhf((-0.0f + -0.0f)));
comp = log10f(+1.6829E16f);
comp = (var_5 * (var_6 / (var_7 - (var_8 - (+1.9521E-36f * -1.7751E35f)))));
if (comp <= (var_9 + (-1.0013E-44f + cosf((+1.5759E-43f + var_10))))) {
float tmp_1 = -1.6744E-30f;
float tmp_2 = (var_11 + floorf(asinf(-1.1162E-2f / var_12 * ceilf((var_13 - var_14 + var_15)))));
comp = tmp_2 / tmp_1 - (var_16 / (-1.8482E-42f + ceilf(-1.3313E-44f)));
comp += (var_17 + -1.8945E20f + +1.7824E-36f - var_18 + var_19);
}
for (int i=0; i < var_3; ++i) {
var_20[i] = +1.9524E-42f;
float tmp_3 = -1.1483E-36f;
comp += tmp_3 - var_20[i] + +1.0162E15f * var_21;
comp += var_22 / +1.2242E36f + -0.0f / -1.6344E-44f;
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float* tmp_21 = initPointer( atof(argv[21]) );
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefffiffffffffffffffffPfff # -- Begin function _Z22__device_stub__computefffiffffffffffffffffPfff
.p2align 4, 0x90
.type _Z22__device_stub__computefffiffffffffffffffffPfff,@function
_Z22__device_stub__computefffiffffffffffffffffPfff: # @_Z22__device_stub__computefffiffffffffffffffffPfff
.cfi_startproc
# %bb.0:
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 288
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movl %edi, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 288(%rsp), %rax
movq %rax, 168(%rsp)
leaq 296(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefffiffffffffffffffffPfff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $296, %rsp # imm = 0x128
.cfi_adjust_cfa_offset -296
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffiffffffffffffffffPfff, .Lfunc_end0-_Z22__device_stub__computefffiffffffffffffffffPfff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 8(%rsp)
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movl %ebx, %edi
movss 144(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 136(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r15, %rsi
callq _Z22__device_stub__computefffiffffffffffffffffPfff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffiffffffffffffffffPfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffiffffffffffffffffPfff,@object # @_Z7computefffiffffffffffffffffPfff
.section .rodata,"a",@progbits
.globl _Z7computefffiffffffffffffffffPfff
.p2align 3, 0x0
_Z7computefffiffffffffffffffffPfff:
.quad _Z22__device_stub__computefffiffffffffffffffffPfff
.size _Z7computefffiffffffffffffffffPfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffiffffffffffffffffPfff"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffiffffffffffffffffPfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffiffffffffffffffffPfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d3ca_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
.type _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff, @function
_Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff:
.LFB2083:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movl %edi, 32(%rsp)
movss %xmm3, 28(%rsp)
movss %xmm4, 24(%rsp)
movss %xmm5, 20(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 320(%rsp), %rax
movq %rax, 184(%rsp)
leaq 328(%rsp), %rax
movq %rax, 192(%rsp)
leaq 336(%rsp), %rax
movq %rax, 200(%rsp)
leaq 344(%rsp), %rax
movq %rax, 208(%rsp)
leaq 352(%rsp), %rax
movq %rax, 216(%rsp)
leaq 360(%rsp), %rax
movq %rax, 224(%rsp)
leaq 368(%rsp), %rax
movq %rax, 232(%rsp)
leaq 376(%rsp), %rax
movq %rax, 240(%rsp)
leaq 384(%rsp), %rax
movq %rax, 248(%rsp)
leaq 392(%rsp), %rax
movq %rax, 256(%rsp)
leaq 400(%rsp), %rax
movq %rax, 264(%rsp)
movq %rsp, %rax
movq %rax, 272(%rsp)
leaq 408(%rsp), %rax
movq %rax, 280(%rsp)
leaq 416(%rsp), %rax
movq %rax, 288(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 328
pushq 56(%rsp)
.cfi_def_cfa_offset 336
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computefffiffffffffffffffffPfff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff, .-_Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
.globl _Z7computefffiffffffffffffffffPfff
.type _Z7computefffiffffffffffffffffPfff, @function
_Z7computefffiffffffffffffffffPfff:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movss 224(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 168(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
addq $120, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefffiffffffffffffffffPfff, .-_Z7computefffiffffffffffffffffPfff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $208, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r12
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 196(%rsp)
movl $1, 200(%rsp)
movl $1, 184(%rsp)
movl $1, 188(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 196(%rsp), %rdx
movl $1, %ecx
movq 184(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $208, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 168(%rsp), %xmm0
subq $112, %rsp
.cfi_def_cfa_offset 352
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 160(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r12, %rsi
pxor %xmm7, %xmm7
cvtsd2ss 224(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 232(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 240(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 248(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 256(%rsp), %xmm3
movl %ebp, %edi
pxor %xmm2, %xmm2
cvtsd2ss 264(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
call _Z48__device_stub__Z7computefffiffffffffffffffffPffffffiffffffffffffffffPfff
addq $112, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefffiffffffffffffffffPfff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefffiffffffffffffffffPfff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefffiffffffffffffffffPfff # -- Begin function _Z22__device_stub__computefffiffffffffffffffffPfff
.p2align 4, 0x90
.type _Z22__device_stub__computefffiffffffffffffffffPfff,@function
_Z22__device_stub__computefffiffffffffffffffffPfff: # @_Z22__device_stub__computefffiffffffffffffffffPfff
.cfi_startproc
# %bb.0:
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 288
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movl %edi, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %rsi, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 96(%rsp)
leaq 32(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 288(%rsp), %rax
movq %rax, 168(%rsp)
leaq 296(%rsp), %rax
movq %rax, 176(%rsp)
leaq 304(%rsp), %rax
movq %rax, 184(%rsp)
leaq 312(%rsp), %rax
movq %rax, 192(%rsp)
leaq 320(%rsp), %rax
movq %rax, 200(%rsp)
leaq 328(%rsp), %rax
movq %rax, 208(%rsp)
leaq 336(%rsp), %rax
movq %rax, 216(%rsp)
leaq 344(%rsp), %rax
movq %rax, 224(%rsp)
leaq 352(%rsp), %rax
movq %rax, 232(%rsp)
leaq 360(%rsp), %rax
movq %rax, 240(%rsp)
leaq 368(%rsp), %rax
movq %rax, 248(%rsp)
leaq 88(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computefffiffffffffffffffffPfff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $296, %rsp # imm = 0x128
.cfi_adjust_cfa_offset -296
retq
.Lfunc_end0:
.size _Z22__device_stub__computefffiffffffffffffffffPfff, .Lfunc_end0-_Z22__device_stub__computefffiffffffffffffffffPfff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 16(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 24(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 40(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 48(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 56(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 64(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 72(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 80(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 88(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 96(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 104(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 112(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 120(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 128(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 136(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 144(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 152(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 160(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 168(%r14), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 112(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r15
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq $10, %r12
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 176(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 184(%r14), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 120(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 112(%rsp) # 4-byte Spill
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 128(%rsp) # 4-byte Spill
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 136(%rsp) # 4-byte Spill
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 144(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 96(%rsp)
movss %xmm9, 88(%rsp)
movss %xmm10, 80(%rsp)
movss %xmm11, 72(%rsp)
movss %xmm12, 64(%rsp)
movss %xmm13, 56(%rsp)
movss %xmm14, 48(%rsp)
movss %xmm15, 40(%rsp)
movss %xmm4, 32(%rsp)
movss %xmm5, 24(%rsp)
movss %xmm6, 16(%rsp)
movss %xmm7, 8(%rsp)
movss 120(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movl %ebx, %edi
movss 144(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 136(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 128(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 112(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r15, %rsi
callq _Z22__device_stub__computefffiffffffffffffffffPfff
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefffiffffffffffffffffPfff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefffiffffffffffffffffPfff,@object # @_Z7computefffiffffffffffffffffPfff
.section .rodata,"a",@progbits
.globl _Z7computefffiffffffffffffffffPfff
.p2align 3, 0x0
_Z7computefffiffffffffffffffffPfff:
.quad _Z22__device_stub__computefffiffffffffffffffffPfff
.size _Z7computefffiffffffffffffffffPfff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefffiffffffffffffffffPfff"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefffiffffffffffffffffPfff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefffiffffffffffffffffPfff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <cstdio>
#include <curand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
using namespace std;
__global__ void setup_kernel (curandState * state, unsigned long seed )
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
curand_init (seed, i, 0, &state[i]);
}
__global__ void randomColouring (curandState* globalState, int *degreeCount, int n, int limit){
int i= blockDim.x * blockIdx.x + threadIdx.x;
curandState localState = globalState[i];
float RANDOM = curand_uniform( &localState );
globalState[i] = localState;
RANDOM *= (limit - 1 + 0.999999);
RANDOM += 1;
degreeCount[i] = (int) RANDOM;
}
__global__ void conflictDetection (int *vertexArray, int *neighbourArray, int *degreeCount, int n, int m, int *detectConflict){
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i>=n){
return;
}
int myColour = degreeCount[i];
int start = -1, stop = -1;
start = vertexArray[i];
if (i==n-1){
stop = 2*m;
}
else{
stop = vertexArray[i+1];
}
for (int j=start; j<stop; j++){
if (degreeCount[neighbourArray[j]-1] == myColour){
// detectConflict[i]=1;
// break;
if (i < neighbourArray[j]-1){
if (detectConflict[i]!=1){
detectConflict[i]=1;
}
}
else if (detectConflict[neighbourArray[j]-1]!=1){
detectConflict[neighbourArray[j]-1]=1;
}
// if (detectConflict[i]!=1){
// detectConflict[i]=1;
// }
//
// if (detectConflict[neighbourArray[j]-1]!=1){
// detectConflict[neighbourArray[j]-1]=1;
// }
}
}
}
__global__ void degreeCalc (int *vertexArray, int *neighbourArray, int *degreeCount, int n, int m){
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i>=n){
return;
}
int start = -1, stop = -1;
int diff=0;
start = vertexArray[i];
if (i==n-1){
stop = 2*m;
}
else{
stop = vertexArray[i+1];
}
diff = stop-start;
degreeCount[i]=diff;
}
void edgesPrint (int vertexArray[], int neighbourArray[], int n, int m){
for (int i=0; i<n-1; i++){
for (int j = vertexArray[i]; j < vertexArray[i+1]; ++j){
cout<<"e "<<i+1<<" "<<neighbourArray[j]<<endl;
/* code */
}
}
for (int j = vertexArray[n-1]; j < m; ++j)
{
cout<<"e "<<n<<" "<<neighbourArray[j]<<endl;
/* code */
}
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
// cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
int *h_vertexArray = new int [n];
int *h_neighbourArray = new int [2*m];
int *h_degreeCount = new int [n];
int *h_detectConflict = new int [n];
int *d_vertexArray = NULL;
cudaMalloc((void **)&d_vertexArray, n*sizeof(int));
int *d_neighbourArray = NULL;
cudaMalloc((void **)&d_neighbourArray, 2*m*sizeof(int));
int *d_detectConflict = NULL;
cudaMalloc((void **)&d_detectConflict, (n)*sizeof(int));
cudaMemset((void *)d_detectConflict, 0, (n)*sizeof(int));
int *d_degreeCount = NULL;
cudaMalloc((void **)&d_degreeCount, (n)*sizeof(int));
cudaMemset((void *)d_degreeCount, 0, (n)*sizeof(int));
curandState* devStates;
cudaMalloc ( &devStates, n*sizeof( curandState ) );
for (int i = 0; i < n; ++i)
{
/* code */
h_vertexArray[i]=2*m;
}
int offset = 0;
int current = 0;
int mark = 1;
for (int i = 0; i < 2*m; ++i)
{
/* code */
int start;
int end;
cin>>start>>end;
// Uncomment for SNAP graph datasets with nodes indexed from 0 to n-1
// cin>>start>>end;
// start++;
// end++;
if (start!=mark){
if (start == mark+1 && h_vertexArray[mark-1]!=2*m){
}
else{
for (int j = mark; j<start; j++){
h_vertexArray[j-1]=offset;
// h_neighbourArray[offset]=0;
// offset++;
}
}
mark = start;
}
if (start==current){
h_neighbourArray[offset]=end;
offset++;
}
else {
current = start;
h_vertexArray[current-1]=offset;
h_neighbourArray[offset]=end;
offset++;
}
}
cudaMemcpy(d_vertexArray, h_vertexArray, n*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_neighbourArray, h_neighbourArray, 2*m*sizeof(int), cudaMemcpyHostToDevice);
int threadsPerBlock = 512;
int blocksPerGrid = (n + threadsPerBlock -1)/threadsPerBlock;
//cout<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
degreeCalc<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m);
cudaMemcpy(h_degreeCount, d_degreeCount, n*sizeof(int), cudaMemcpyDeviceToHost);
for (int i=0; i<n; i++){
cout<<h_degreeCount[i]<<endl;
}
thrust::device_ptr<int> d_ptr = thrust::device_pointer_cast(d_degreeCount);
int max = *(thrust::max_element(d_ptr, d_ptr + n));
// int result = thrust::reduce(h_degreeCount, h_degreeCount + n,
// -1,
// thrust::maximum<int>());
// cout<<"Result: "<<result<<endl<<max;
cout<<"Max = "<<max<<endl;
setup_kernel <<<blocksPerGrid, threadsPerBlock>>> ( devStates, time(NULL) );
// Except for Cliques and Odd Cycles, Brook's theorem states that only Max Degree colours are enough at most
randomColouring<<<blocksPerGrid, threadsPerBlock>>>(devStates, d_degreeCount, n, max);
cudaMemcpy(h_degreeCount, d_degreeCount, n*sizeof(int), cudaMemcpyDeviceToHost);
// for (int i=0; i<n; i++){
// cout<<h_degreeCount[i]<<endl;
// }
conflictDetection<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m, d_detectConflict);
thrust::device_ptr<int> d_detectConflict_ptr = thrust::device_pointer_cast(d_detectConflict);
int count1 = thrust::reduce(d_detectConflict_ptr, d_detectConflict_ptr + n);
cudaMemcpy(h_detectConflict, d_detectConflict, n*sizeof(int), cudaMemcpyDeviceToHost);
// for (int i=0; i<n; i++){
// cout<<i+1<<": "<<h_detectConflict[i]<<endl;
// }
cout<<"Count: "<<count1<<endl;
int countnew=0;
for (int i=0; i<n-1; i++){
if (h_detectConflict[i]==0){
continue;
}
countnew++;
bool usedColours[max+1];
fill(usedColours, usedColours+max+1, false);
// if (flag){
// flag = false;
// for (int j=0; j<n; j++){
// cout<<usedColours[i]<<endl;
// }
// }
int start = -1, stop = -1;
start = h_vertexArray[i];
stop = h_vertexArray[i+1];
// cout<<"My id: "<<i<<endl;
//
// cout<<"My colour: "<<h_degreeCount[i]<<endl;
//
// cout<<"Neighbours"<<endl;
//
for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
usedColours[h_degreeCount[h_neighbourArray[j]-1]-1] = true;
}
// cout<<endl;
for (int j=0; j<max+1; j++){
if (usedColours[j]==false){
h_degreeCount[i]=j+1;
// cout<<"My new Colour: "<<j+1<<endl;
break;
}
}
}
if (h_detectConflict[n-1]!=0){
bool usedColours[max+1];
countnew++;
fill(usedColours, usedColours+max+1, false);
int start = -1, stop = -1;
start = h_vertexArray[n-1];
stop = 2*m;
for (int j=start; j<stop; j++){
usedColours[h_degreeCount[h_neighbourArray[j]-1]-1] = true;
}
for (int j=0; j<max+1; j++){
if (usedColours[j]==false){
h_degreeCount[n-1]=j+1;
break;
}
}
}
// cout<<"SHAMILASADJKAJSDKLJASHDKJASHLDKASJKD";
// for (int i=0; i<n; i++){
// cout<<h_degreeCount[i]<<endl;
// }
// for (int i=0; i<n-1; i++){
//
// int start = -1, stop = -1;
//
// start = h_vertexArray[i];
//
// stop = h_vertexArray[i+1];
//
// cout<<"My id: "<<i<<endl;
//
// cout<<"My colour: "<<h_degreeCount[i]<<endl;
//
// cout<<"Neighbours"<<endl;
//
// for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
// }
// }
//
//
//
// if (h_detectConflict[n-1]!=0){
// int start = -1, stop = -1;
//
// start = h_vertexArray[n-1];
//
// stop = m;
//
// cout<<"My id: "<<n-1<<endl;
//
// cout<<"My colour: "<<h_degreeCount[n-1]<<endl;
//
// cout<<"Neighbours"<<endl;
//
// for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
// }
// }
cout<<"Shamil"<<endl;
cudaMemset((void *)d_detectConflict, 0, (n)*sizeof(int));
cudaMemcpy(d_degreeCount, h_degreeCount, n*sizeof(int), cudaMemcpyHostToDevice);
conflictDetection<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m, d_detectConflict);
count1 = thrust::reduce(d_detectConflict_ptr, d_detectConflict_ptr + n);
cout<<"Count: "<<count1<<" "<<countnew<<endl;
// for (int i=0; i<n; i++){
// if (h_degreeCount[i] == max+1){
// cout<<"BUHAHAHAHAHAHHAHAHAHHAHA"<<endl;
// }
//
// else if (h_degreeCount[i] == 1){
// cout<<"LALLLALALALALALALALALLALA"<<endl;
// }
// cout<<h_degreeCount[i]<<endl;
// }
// for (int i=0; i<n; i++){
// cout<<i+1<<": "<<h_detectConflict[i]<<endl;
// }
//edgesPrint(h_vertexArray, h_neighbourArray, n, m);
//delete[] h_vertexArray;
//delete[] h_neighbourArray;
//delete[] h_degreeCount;
delete[] h_vertexArray;
delete[] h_neighbourArray;
delete[] h_degreeCount;
delete[] h_detectConflict;
cudaFree(d_neighbourArray);
cudaFree(d_vertexArray);
cudaFree(d_degreeCount);
cudaFree(d_detectConflict);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cstdlib>
#include <cstdio>
#include <hiprand/hiprand_kernel.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <thrust/execution_policy.h>
#include <thrust/extrema.h>
#include <thrust/device_ptr.h>
using namespace std;
__global__ void setup_kernel (hiprandState * state, unsigned long seed )
{
int i= blockDim.x * blockIdx.x + threadIdx.x;
hiprand_init (seed, i, 0, &state[i]);
}
__global__ void randomColouring (hiprandState* globalState, int *degreeCount, int n, int limit){
int i= blockDim.x * blockIdx.x + threadIdx.x;
hiprandState localState = globalState[i];
float RANDOM = hiprand_uniform( &localState );
globalState[i] = localState;
RANDOM *= (limit - 1 + 0.999999);
RANDOM += 1;
degreeCount[i] = (int) RANDOM;
}
__global__ void conflictDetection (int *vertexArray, int *neighbourArray, int *degreeCount, int n, int m, int *detectConflict){
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i>=n){
return;
}
int myColour = degreeCount[i];
int start = -1, stop = -1;
start = vertexArray[i];
if (i==n-1){
stop = 2*m;
}
else{
stop = vertexArray[i+1];
}
for (int j=start; j<stop; j++){
if (degreeCount[neighbourArray[j]-1] == myColour){
// detectConflict[i]=1;
// break;
if (i < neighbourArray[j]-1){
if (detectConflict[i]!=1){
detectConflict[i]=1;
}
}
else if (detectConflict[neighbourArray[j]-1]!=1){
detectConflict[neighbourArray[j]-1]=1;
}
// if (detectConflict[i]!=1){
// detectConflict[i]=1;
// }
//
// if (detectConflict[neighbourArray[j]-1]!=1){
// detectConflict[neighbourArray[j]-1]=1;
// }
}
}
}
__global__ void degreeCalc (int *vertexArray, int *neighbourArray, int *degreeCount, int n, int m){
int i= blockDim.x * blockIdx.x + threadIdx.x;
if (i>=n){
return;
}
int start = -1, stop = -1;
int diff=0;
start = vertexArray[i];
if (i==n-1){
stop = 2*m;
}
else{
stop = vertexArray[i+1];
}
diff = stop-start;
degreeCount[i]=diff;
}
void edgesPrint (int vertexArray[], int neighbourArray[], int n, int m){
for (int i=0; i<n-1; i++){
for (int j = vertexArray[i]; j < vertexArray[i+1]; ++j){
cout<<"e "<<i+1<<" "<<neighbourArray[j]<<endl;
/* code */
}
}
for (int j = vertexArray[n-1]; j < m; ++j)
{
cout<<"e "<<n<<" "<<neighbourArray[j]<<endl;
/* code */
}
}
int main(int argc, char const *argv[])
{
/* code */
string a, b;
int n, m;
cin>>a>>b>>n>>m;
// cout<<a<<" "<<b<<" "<<n<<" "<<m<<endl;
int *h_vertexArray = new int [n];
int *h_neighbourArray = new int [2*m];
int *h_degreeCount = new int [n];
int *h_detectConflict = new int [n];
int *d_vertexArray = NULL;
hipMalloc((void **)&d_vertexArray, n*sizeof(int));
int *d_neighbourArray = NULL;
hipMalloc((void **)&d_neighbourArray, 2*m*sizeof(int));
int *d_detectConflict = NULL;
hipMalloc((void **)&d_detectConflict, (n)*sizeof(int));
hipMemset((void *)d_detectConflict, 0, (n)*sizeof(int));
int *d_degreeCount = NULL;
hipMalloc((void **)&d_degreeCount, (n)*sizeof(int));
hipMemset((void *)d_degreeCount, 0, (n)*sizeof(int));
hiprandState* devStates;
hipMalloc ( &devStates, n*sizeof( hiprandState ) );
for (int i = 0; i < n; ++i)
{
/* code */
h_vertexArray[i]=2*m;
}
int offset = 0;
int current = 0;
int mark = 1;
for (int i = 0; i < 2*m; ++i)
{
/* code */
int start;
int end;
cin>>start>>end;
// Uncomment for SNAP graph datasets with nodes indexed from 0 to n-1
// cin>>start>>end;
// start++;
// end++;
if (start!=mark){
if (start == mark+1 && h_vertexArray[mark-1]!=2*m){
}
else{
for (int j = mark; j<start; j++){
h_vertexArray[j-1]=offset;
// h_neighbourArray[offset]=0;
// offset++;
}
}
mark = start;
}
if (start==current){
h_neighbourArray[offset]=end;
offset++;
}
else {
current = start;
h_vertexArray[current-1]=offset;
h_neighbourArray[offset]=end;
offset++;
}
}
hipMemcpy(d_vertexArray, h_vertexArray, n*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_neighbourArray, h_neighbourArray, 2*m*sizeof(int), hipMemcpyHostToDevice);
int threadsPerBlock = 512;
int blocksPerGrid = (n + threadsPerBlock -1)/threadsPerBlock;
//cout<<threadsPerBlock<<" "<<blocksPerGrid<<endl;
degreeCalc<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m);
hipMemcpy(h_degreeCount, d_degreeCount, n*sizeof(int), hipMemcpyDeviceToHost);
for (int i=0; i<n; i++){
cout<<h_degreeCount[i]<<endl;
}
thrust::device_ptr<int> d_ptr = thrust::device_pointer_cast(d_degreeCount);
int max = *(thrust::max_element(d_ptr, d_ptr + n));
// int result = thrust::reduce(h_degreeCount, h_degreeCount + n,
// -1,
// thrust::maximum<int>());
// cout<<"Result: "<<result<<endl<<max;
cout<<"Max = "<<max<<endl;
setup_kernel <<<blocksPerGrid, threadsPerBlock>>> ( devStates, time(NULL) );
// Except for Cliques and Odd Cycles, Brook's theorem states that only Max Degree colours are enough at most
randomColouring<<<blocksPerGrid, threadsPerBlock>>>(devStates, d_degreeCount, n, max);
hipMemcpy(h_degreeCount, d_degreeCount, n*sizeof(int), hipMemcpyDeviceToHost);
// for (int i=0; i<n; i++){
// cout<<h_degreeCount[i]<<endl;
// }
conflictDetection<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m, d_detectConflict);
thrust::device_ptr<int> d_detectConflict_ptr = thrust::device_pointer_cast(d_detectConflict);
int count1 = thrust::reduce(d_detectConflict_ptr, d_detectConflict_ptr + n);
hipMemcpy(h_detectConflict, d_detectConflict, n*sizeof(int), hipMemcpyDeviceToHost);
// for (int i=0; i<n; i++){
// cout<<i+1<<": "<<h_detectConflict[i]<<endl;
// }
cout<<"Count: "<<count1<<endl;
int countnew=0;
for (int i=0; i<n-1; i++){
if (h_detectConflict[i]==0){
continue;
}
countnew++;
bool usedColours[max+1];
fill(usedColours, usedColours+max+1, false);
// if (flag){
// flag = false;
// for (int j=0; j<n; j++){
// cout<<usedColours[i]<<endl;
// }
// }
int start = -1, stop = -1;
start = h_vertexArray[i];
stop = h_vertexArray[i+1];
// cout<<"My id: "<<i<<endl;
//
// cout<<"My colour: "<<h_degreeCount[i]<<endl;
//
// cout<<"Neighbours"<<endl;
//
for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
usedColours[h_degreeCount[h_neighbourArray[j]-1]-1] = true;
}
// cout<<endl;
for (int j=0; j<max+1; j++){
if (usedColours[j]==false){
h_degreeCount[i]=j+1;
// cout<<"My new Colour: "<<j+1<<endl;
break;
}
}
}
if (h_detectConflict[n-1]!=0){
bool usedColours[max+1];
countnew++;
fill(usedColours, usedColours+max+1, false);
int start = -1, stop = -1;
start = h_vertexArray[n-1];
stop = 2*m;
for (int j=start; j<stop; j++){
usedColours[h_degreeCount[h_neighbourArray[j]-1]-1] = true;
}
for (int j=0; j<max+1; j++){
if (usedColours[j]==false){
h_degreeCount[n-1]=j+1;
break;
}
}
}
// cout<<"SHAMILASADJKAJSDKLJASHDKJASHLDKASJKD";
// for (int i=0; i<n; i++){
// cout<<h_degreeCount[i]<<endl;
// }
// for (int i=0; i<n-1; i++){
//
// int start = -1, stop = -1;
//
// start = h_vertexArray[i];
//
// stop = h_vertexArray[i+1];
//
// cout<<"My id: "<<i<<endl;
//
// cout<<"My colour: "<<h_degreeCount[i]<<endl;
//
// cout<<"Neighbours"<<endl;
//
// for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
// }
// }
//
//
//
// if (h_detectConflict[n-1]!=0){
// int start = -1, stop = -1;
//
// start = h_vertexArray[n-1];
//
// stop = m;
//
// cout<<"My id: "<<n-1<<endl;
//
// cout<<"My colour: "<<h_degreeCount[n-1]<<endl;
//
// cout<<"Neighbours"<<endl;
//
// for (int j=start; j<stop; j++){
// cout<<h_degreeCount[h_neighbourArray[j]-1]<<" ";
// }
// }
cout<<"Shamil"<<endl;
hipMemset((void *)d_detectConflict, 0, (n)*sizeof(int));
hipMemcpy(d_degreeCount, h_degreeCount, n*sizeof(int), hipMemcpyHostToDevice);
conflictDetection<<<blocksPerGrid, threadsPerBlock>>>(d_vertexArray, d_neighbourArray, d_degreeCount, n, m, d_detectConflict);
count1 = thrust::reduce(d_detectConflict_ptr, d_detectConflict_ptr + n);
cout<<"Count: "<<count1<<" "<<countnew<<endl;
// for (int i=0; i<n; i++){
// if (h_degreeCount[i] == max+1){
// cout<<"BUHAHAHAHAHAHHAHAHAHHAHA"<<endl;
// }
//
// else if (h_degreeCount[i] == 1){
// cout<<"LALLLALALALALALALALALLALA"<<endl;
// }
// cout<<h_degreeCount[i]<<endl;
// }
// for (int i=0; i<n; i++){
// cout<<i+1<<": "<<h_detectConflict[i]<<endl;
// }
//edgesPrint(h_vertexArray, h_neighbourArray, n, m);
//delete[] h_vertexArray;
//delete[] h_neighbourArray;
//delete[] h_degreeCount;
delete[] h_vertexArray;
delete[] h_neighbourArray;
delete[] h_degreeCount;
delete[] h_detectConflict;
hipFree(d_neighbourArray);
hipFree(d_vertexArray);
hipFree(d_degreeCount);
hipFree(d_detectConflict);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
cudaMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(DArray, HArray, num * sizeof(long long int) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(HArray, DArray, num * sizeof(long long int) , cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} | code for sm_80
Function : _Z3XORPxii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e740000002100 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fc400078e0203 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff097624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.EQ.AND P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */
/* 0x000fc80004702270 */
/*00f0*/ ISETP.GE.OR P0, PT, R0, R9, P0 ; /* 0x000000090000720c */
/* 0x000fda0000706670 */
/*0100*/ @P0 BRA 0x170 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.WIDE R6, R9, 0x8, R2 ; /* 0x0000000809067825 */
/* 0x000fe200078e0202 */
/*0120*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000eaa000c1e1b00 */
/*0130*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1b00 */
/*0140*/ LOP3.LUT R4, R6, R4, RZ, 0x3c, !PT ; /* 0x0000000406047212 */
/* 0x004fe400078e3cff */
/*0150*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x000fca00078e3cff */
/*0160*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e4000c101b04 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f05270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ LEA.HI R5, R9.reuse, R9, RZ, 0x1 ; /* 0x0000000909057211 */
/* 0x041fe400078f08ff */
/*01c0*/ LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109047812 */
/* 0x000fc800078ec0ff */
/*01d0*/ LEA.HI.SX32 R9, R5, R4, 0x1f ; /* 0x0000000405097211 */
/* 0x000fc800078ffaff */
/*01e0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 BRA 0xb0 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
cudaMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(DArray, HArray, num * sizeof(long long int) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(HArray, DArray, num * sizeof(long long int) , cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} | .file "tmpxft_000d2435_00000000-6_qn2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3XORPxiiPxii
.type _Z24__device_stub__Z3XORPxiiPxii, @function
_Z24__device_stub__Z3XORPxiiPxii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3XORPxii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3XORPxiiPxii, .-_Z24__device_stub__Z3XORPxiiPxii
.globl _Z3XORPxii
.type _Z3XORPxii, @function
_Z3XORPxii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3XORPxiiPxii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3XORPxii, .-_Z3XORPxii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Not Correct Number of Arguments"
.section .rodata.str1.1
.LC2:
.string "malloc"
.LC3:
.string "%lld "
.LC4:
.string "^ "
.LC5:
.string "cudaMalloc"
.LC6:
.string "Cuda Error: '%s' for %s\n"
.LC7:
.string "cudaMemcpy"
.LC8:
.string "kernel invocation"
.LC9:
.string "memcpy"
.section .rodata.str1.8
.align 8
.LC10:
.string "\nTotal time = %ld microsecs Processsing =%ld microsecs\n"
.section .rodata.str1.1
.LC11:
.string "XOR: %lld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L12
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbp
testq %rbp, %rbp
movl $10000000, %eax
cmove %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
testq %rbx, %rbx
movl $29783, %eax
cmove %rax, %rbx
leaq 0(,%rbp,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L35
movl %ebx, %edi
call srand@PLT
movl $0, %ebx
.L18:
call random@PLT
movq %rax, 0(%r13,%rbx,8)
movq %rbx, %r12
addq $1, %rbx
cmpq %rbx, %rbp
jne .L18
movl $0, %ebp
leaq .LC3(%rip), %r14
jmp .L20
.L12:
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L35:
leaq .LC2(%rip), %rdi
call perror@PLT
movl $-1, %edi
call exit@PLT
.L37:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
leaq 1(%rbp), %rax
cmpq %r12, %rbp
je .L36
movq %rax, %rbp
.L20:
movq 0(%r13,%rbp,8), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq %r12, %rbp
jnb .L19
jmp .L37
.L36:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %eax
testl $1023, %ebx
je .L23
leal 1(%rbx), %eax
testb $1, %bl
je .L23
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
.L25:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movq 64(%rsp), %rdx
subq 48(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 72(%rsp), %rdx
subq 56(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 0(%r13), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
leaq 2(%r12), %rsi
shrq %rsi
movl $1, %edx
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3XORPxiiPxii
jmp .L24
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
je .L25
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movq %rbx, %rsi
shrq %rsi
movl $0, %edx
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3XORPxiiPxii
jmp .L26
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z3XORPxii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3XORPxii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
cudaMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(DArray, HArray, num * sizeof(long long int) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(HArray, DArray, num * sizeof(long long int) , cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
hipMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(DArray, HArray, num * sizeof(long long int) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(HArray, DArray, num * sizeof(long long int) , hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
hipMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(DArray, HArray, num * sizeof(long long int) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(HArray, DArray, num * sizeof(long long int) , hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3XORPxii
.globl _Z3XORPxii
.p2align 8
.type _Z3XORPxii,@function
_Z3XORPxii:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_12
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB0_4
.LBB0_2:
s_cmp_eq_u32 s1, 0
s_mov_b32 s4, s1
s_cselect_b32 s5, -1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_12
.LBB0_4:
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_add_i32 s5, s4, -1
s_cmp_lg_u32 s0, 1
v_cmp_ne_u32_e32 vcc_lo, s5, v1
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v5, v5, v7
v_xor_b32_e32 v4, v4, v6
global_store_b64 v[2:3], v[4:5], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_eq_u32 s4, 1
s_mov_b32 s5, -1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_bitcmp0_b32 s4, 0
s_cbranch_scc1 .LBB0_10
s_lshr_b32 s0, s4, 31
s_mov_b32 s5, 0
s_add_i32 s0, s4, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 1
s_mov_b32 s0, 1
s_add_i32 s1, s1, 1
.LBB0_10:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s1, s4, 1
s_mov_b32 s0, 0
s_branch .LBB0_2
.LBB0_12:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3XORPxii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3XORPxii, .Lfunc_end0-_Z3XORPxii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3XORPxii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3XORPxii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#define SEED 0x7457
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__global__ void XOR(long long int *Data, int Size, int Odd)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
int size = Size;
int Bool= Odd;
while(size!=0){
if( tid < size )
if( tid == size -1 && Bool == 1 ){
// Do Nothing
}
else{
Data[tid] = Data[tid] ^ Data[ tid + size ];
}
__syncthreads();
// To avoid Infinite While Loop
if (size==1)
{
return;
}
// Odd Number Case
if( size % 2){
size = size/2 +1;
Bool = 1;
}
else{
Bool = 0;
size = size / 2;
}
}
}
int main(int argc, char **argv)
{
struct timeval start, end, t_start, t_end;
long long int *HArray;
long long int *DArray;
unsigned long num = NUM; /*Default value of num from MACRO*/
// int blocks;
unsigned long Seed = SEED; /*Default value of Seed from MACRO*/
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
Seed= atoi(argv[2]);
if(Seed <= 0)
Seed = SEED;
}
else{
printf("%d", argc);
printf("Not Correct Number of Arguments");
return -1;
}
/* Allocate host (CPU) memory and initialize*/
HArray = (long long int*) malloc(num * sizeof(long long int) );
if(!HArray){
perror("malloc");
exit(-1);
}
srand(Seed);
for(int i=0;i<num;i++){
HArray[i]= random();
}
for(int i=0;i<num;i++){
printf("%lld ", HArray[i] );
if (i<num-1)
printf("^ ");
}
gettimeofday(&t_start, NULL);
/* Allocate GPU memory and copy from CPU --> GPU*/
hipMalloc(&DArray, num * sizeof(long long int));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(DArray, HArray, num * sizeof(long long int) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
int blocks = num;
if(num % 1024)
++blocks;
// XOR<<<1, (num + num%2)/2>>>(DArray, num%2);
if( num%2 ){
XOR<<<blocks, 1024>>>(DArray, (num + 1)/2, 1);
CUDA_ERROR_EXIT("kernel invocation");
}
else{
XOR<<<blocks, 1024>>>(DArray, num/2, 0);
CUDA_ERROR_EXIT("kernel invocation");
}
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(HArray, DArray, num * sizeof(long long int) , hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
printf("\nTotal time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(DArray);
/*Print the last element for sanity check*/
printf("XOR: %lld\n", HArray[0]);
free(HArray);
} | .text
.file "qn2.hip"
.globl _Z18__device_stub__XORPxii # -- Begin function _Z18__device_stub__XORPxii
.p2align 4, 0x90
.type _Z18__device_stub__XORPxii,@function
_Z18__device_stub__XORPxii: # @_Z18__device_stub__XORPxii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3XORPxii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__XORPxii, .Lfunc_end0-_Z18__device_stub__XORPxii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB1_25
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
movl $10000000, %ebp # imm = 0x989680
cmovnel %eax, %ebp
movslq %ebp, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leaq (,%r12,8), %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB1_26
# %bb.2:
movq %rax, %rbx
movq %r14, 112(%rsp) # 8-byte Spill
testl %r15d, %r15d
movl $29783, %edi # imm = 0x7457
cmovnel %r15d, %edi
callq srand
cmpl $2, %ebp
movl $1, %r15d
cmovael %ebp, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
callq random
movq %rax, (%rbx,%r14,8)
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %.preheader
leaq -1(%r12), %r13
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r13
jbe .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_25:
movl %edi, %eax
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $-1, %r15d
jmp .LBB1_24
.LBB1_8:
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 16(%rsp), %rdi
movq 112(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.11:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebp, %eax
andl $1023, %eax # imm = 0x3FF
cmpq $1, %rax
movl %ebp, %edi
sbbl $-1, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r12b
jne .LBB1_14
# %bb.19:
testl %eax, %eax
jne .LBB1_17
# %bb.20:
movq 16(%rsp), %rax
sarl %ebp
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movl $0, 8(%rsp)
jmp .LBB1_16
.LBB1_14:
testl %eax, %eax
jne .LBB1_17
# %bb.15:
movq 16(%rsp), %rax
incq %r12
shrq %r12
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl $1, 8(%rsp)
.LBB1_16:
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3XORPxii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_18
# %bb.21:
xorl %r15d, %r15d
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_22
# %bb.23:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rsi
subq 120(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 128(%rsp), %rsi
addq %rax, %rsi
movq 80(%rsp), %rax
movq 88(%rsp), %rdx
subq 136(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 144(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq (%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
.LBB1_24:
movl %r15d, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 208
movl $.L.str.2, %edi
callq perror
movl $-1, %edi
callq exit
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.6, %edx
jmp .LBB1_10
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.7, %edx
jmp .LBB1_10
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.8, %edx
jmp .LBB1_10
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.9, %edx
.LBB1_10:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3XORPxii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3XORPxii,@object # @_Z3XORPxii
.section .rodata,"a",@progbits
.globl _Z3XORPxii
.p2align 3, 0x0
_Z3XORPxii:
.quad _Z18__device_stub__XORPxii
.size _Z3XORPxii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Not Correct Number of Arguments"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "malloc"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lld "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "^ "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "kernel invocation"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "memcpy"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nTotal time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.10, 56
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "XOR: %lld\n"
.size .L.str.11, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3XORPxii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__XORPxii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3XORPxii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3XORPxii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05270 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e740000002100 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe200078e00ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fc400078e0203 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff097624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff047624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*00c0*/ BSSY B0, 0x180 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*00d0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ ISETP.EQ.AND P0, PT, R0, R5, !P0 ; /* 0x000000050000720c */
/* 0x000fc80004702270 */
/*00f0*/ ISETP.GE.OR P0, PT, R0, R9, P0 ; /* 0x000000090000720c */
/* 0x000fda0000706670 */
/*0100*/ @P0 BRA 0x170 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.WIDE R6, R9, 0x8, R2 ; /* 0x0000000809067825 */
/* 0x000fe200078e0202 */
/*0120*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000eaa000c1e1b00 */
/*0130*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1b00 */
/*0140*/ LOP3.LUT R4, R6, R4, RZ, 0x3c, !PT ; /* 0x0000000406047212 */
/* 0x004fe400078e3cff */
/*0150*/ LOP3.LUT R5, R7, R5, RZ, 0x3c, !PT ; /* 0x0000000507057212 */
/* 0x000fca00078e3cff */
/*0160*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e4000c101b04 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f05270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ LEA.HI R5, R9.reuse, R9, RZ, 0x1 ; /* 0x0000000909057211 */
/* 0x041fe400078f08ff */
/*01c0*/ LOP3.LUT R4, R9, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109047812 */
/* 0x000fc800078ec0ff */
/*01d0*/ LEA.HI.SX32 R9, R5, R4, 0x1f ; /* 0x0000000405097211 */
/* 0x000fc800078ffaff */
/*01e0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*01f0*/ @P0 BRA 0xb0 ; /* 0xfffffeb000000947 */
/* 0x000fea000383ffff */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3XORPxii
.globl _Z3XORPxii
.p2align 8
.type _Z3XORPxii,@function
_Z3XORPxii:
s_load_b32 s4, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB0_12
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB0_4
.LBB0_2:
s_cmp_eq_u32 s1, 0
s_mov_b32 s4, s1
s_cselect_b32 s5, -1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_12
.LBB0_4:
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_7
s_add_i32 s5, s4, -1
s_cmp_lg_u32 s0, 1
v_cmp_ne_u32_e32 vcc_lo, s5, v1
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b64 v[6:7], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_xor_b32_e32 v5, v5, v7
v_xor_b32_e32 v4, v4, v6
global_store_b64 v[2:3], v[4:5], off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s1
s_cmp_eq_u32 s4, 1
s_mov_b32 s5, -1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_bitcmp0_b32 s4, 0
s_cbranch_scc1 .LBB0_10
s_lshr_b32 s0, s4, 31
s_mov_b32 s5, 0
s_add_i32 s0, s4, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 1
s_mov_b32 s0, 1
s_add_i32 s1, s1, 1
.LBB0_10:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s1, s4, 1
s_mov_b32 s0, 0
s_branch .LBB0_2
.LBB0_12:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3XORPxii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3XORPxii, .Lfunc_end0-_Z3XORPxii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3XORPxii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3XORPxii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d2435_00000000-6_qn2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3XORPxiiPxii
.type _Z24__device_stub__Z3XORPxiiPxii, @function
_Z24__device_stub__Z3XORPxiiPxii:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3XORPxii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3XORPxiiPxii, .-_Z24__device_stub__Z3XORPxiiPxii
.globl _Z3XORPxii
.type _Z3XORPxii, @function
_Z3XORPxii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3XORPxiiPxii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3XORPxii, .-_Z3XORPxii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Not Correct Number of Arguments"
.section .rodata.str1.1
.LC2:
.string "malloc"
.LC3:
.string "%lld "
.LC4:
.string "^ "
.LC5:
.string "cudaMalloc"
.LC6:
.string "Cuda Error: '%s' for %s\n"
.LC7:
.string "cudaMemcpy"
.LC8:
.string "kernel invocation"
.LC9:
.string "memcpy"
.section .rodata.str1.8
.align 8
.LC10:
.string "\nTotal time = %ld microsecs Processsing =%ld microsecs\n"
.section .rodata.str1.1
.LC11:
.string "XOR: %lld\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L12
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbp
testq %rbp, %rbp
movl $10000000, %eax
cmove %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
testq %rbx, %rbx
movl $29783, %eax
cmove %rax, %rbx
leaq 0(,%rbp,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L35
movl %ebx, %edi
call srand@PLT
movl $0, %ebx
.L18:
call random@PLT
movq %rax, 0(%r13,%rbx,8)
movq %rbx, %r12
addq $1, %rbx
cmpq %rbx, %rbp
jne .L18
movl $0, %ebp
leaq .LC3(%rip), %r14
jmp .L20
.L12:
movl %edi, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L11
.L35:
leaq .LC2(%rip), %rdi
call perror@PLT
movl $-1, %edi
call exit@PLT
.L37:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L19:
leaq 1(%rbp), %rax
cmpq %r12, %rbp
je .L36
movq %rax, %rbp
.L20:
movq 0(%r13,%rbp,8), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq %r12, %rbp
jnb .L19
jmp .L37
.L36:
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl %ebx, %eax
testl $1023, %ebx
je .L23
leal 1(%rbx), %eax
testb $1, %bl
je .L23
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L40
.L24:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L41
.L25:
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r15, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 32(%rsp), %rcx
subq 16(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 40(%rsp), %rcx
subq 24(%rsp), %rcx
movq 64(%rsp), %rdx
subq 48(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 72(%rsp), %rdx
subq 56(%rsp), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 0(%r13), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movl $0, %eax
.L11:
movq 88(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
leaq 2(%r12), %rsi
shrq %rsi
movl $1, %edx
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3XORPxiiPxii
jmp .L24
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L26:
call cudaGetLastError@PLT
testl %eax, %eax
je .L25
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L44:
movq %rbx, %rsi
shrq %rsi
movl $0, %edx
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3XORPxiiPxii
jmp .L26
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rcx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z3XORPxii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z3XORPxii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "qn2.hip"
.globl _Z18__device_stub__XORPxii # -- Begin function _Z18__device_stub__XORPxii
.p2align 4, 0x90
.type _Z18__device_stub__XORPxii,@function
_Z18__device_stub__XORPxii: # @_Z18__device_stub__XORPxii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3XORPxii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__XORPxii, .Lfunc_end0-_Z18__device_stub__XORPxii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jne .LBB1_25
# %bb.1:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
movl $10000000, %ebp # imm = 0x989680
cmovnel %eax, %ebp
movslq %ebp, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
leaq (,%r12,8), %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB1_26
# %bb.2:
movq %rax, %rbx
movq %r14, 112(%rsp) # 8-byte Spill
testl %r15d, %r15d
movl $29783, %edi # imm = 0x7457
cmovnel %r15d, %edi
callq srand
cmpl $2, %ebp
movl $1, %r15d
cmovael %ebp, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
callq random
movq %rax, (%rbx,%r14,8)
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %.preheader
leaq -1(%r12), %r13
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq %r14, %r15
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq (%rbx,%r14,8), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpq %r14, %r13
jbe .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_25:
movl %edi, %eax
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $-1, %r15d
jmp .LBB1_24
.LBB1_8:
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 16(%rsp), %rdi
movq 112(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_9
# %bb.11:
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_12
# %bb.13:
leaq 136(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %ebp, %eax
andl $1023, %eax # imm = 0x3FF
cmpq $1, %rax
movl %ebp, %edi
sbbl $-1, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r12b
jne .LBB1_14
# %bb.19:
testl %eax, %eax
jne .LBB1_17
# %bb.20:
movq 16(%rsp), %rax
sarl %ebp
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
movl $0, 8(%rsp)
jmp .LBB1_16
.LBB1_14:
testl %eax, %eax
jne .LBB1_17
# %bb.15:
movq 16(%rsp), %rax
incq %r12
shrq %r12
movq %rax, 72(%rsp)
movl %r12d, 12(%rsp)
movl $1, 8(%rsp)
.LBB1_16:
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3XORPxii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_18
# %bb.21:
xorl %r15d, %r15d
leaq 80(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_22
# %bb.23:
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 24(%rsp), %rax
movq 32(%rsp), %rsi
subq 120(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 128(%rsp), %rsi
addq %rax, %rsi
movq 80(%rsp), %rax
movq 88(%rsp), %rdx
subq 136(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 144(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq (%rbx), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
.LBB1_24:
movl %r15d, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_26:
.cfi_def_cfa_offset 208
movl $.L.str.2, %edi
callq perror
movl $-1, %edi
callq exit
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.6, %edx
jmp .LBB1_10
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.7, %edx
jmp .LBB1_10
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.8, %edx
jmp .LBB1_10
.LBB1_22:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.9, %edx
.LBB1_10:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3XORPxii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3XORPxii,@object # @_Z3XORPxii
.section .rodata,"a",@progbits
.globl _Z3XORPxii
.p2align 3, 0x0
_Z3XORPxii:
.quad _Z18__device_stub__XORPxii
.size _Z3XORPxii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Not Correct Number of Arguments"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "malloc"
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%lld "
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "^ "
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMemcpy"
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "kernel invocation"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "memcpy"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nTotal time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.10, 56
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "XOR: %lld\n"
.size .L.str.11, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3XORPxii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__XORPxii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3XORPxii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
} | code for sm_80
Function : _Z5d_mulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5d_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
} | .file "tmpxft_001a6139_00000000-6_cudafunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5d_addPfS_S_iPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
.globl _Z5d_addPfS_S_i
.type _Z5d_addPfS_S_i, @function
_Z5d_addPfS_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5d_addPfS_S_i, .-_Z5d_addPfS_S_i
.globl _Z3addPfS_i
.type _Z3addPfS_i, @function
_Z3addPfS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %rsi, %r14
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z3addPfS_i, .-_Z3addPfS_i
.globl _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_mulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
.globl _Z5d_mulPfS_S_i
.type _Z5d_mulPfS_S_i, @function
_Z5d_mulPfS_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z5d_mulPfS_S_i, .-_Z5d_mulPfS_S_i
.globl _Z3mulPfS_i
.type _Z3mulPfS_i, @function
_Z3mulPfS_i:
.LFB2028:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %rsi, %r14
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L27
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L27:
cvttss2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size _Z3mulPfS_i, .-_Z3mulPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z5d_mulPfS_S_i"
.LC6:
.string "_Z5d_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_mulPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
cudaMalloc( (void**)&d_x, size);
cudaMalloc( (void**)&d_y, size);
cudaMalloc( (void**)&d_z, size);
// copy vector from host to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
cudaMemcpy(x, d_z, size, cudaMemcpyDeviceToHost);
// free device mem
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
} | #include <hip/hip_runtime.h>
// Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5d_addPfS_S_i
.globl _Z5d_addPfS_S_i
.p2align 8
.type _Z5d_addPfS_S_i,@function
_Z5d_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5d_addPfS_S_i, .Lfunc_end0-_Z5d_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5d_mulPfS_S_i
.globl _Z5d_mulPfS_S_i
.p2align 8
.type _Z5d_mulPfS_S_i,@function
_Z5d_mulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_mulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5d_mulPfS_S_i, .Lfunc_end1-_Z5d_mulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_mulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_mulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Dan Rolfe
#define BLOCKSIZE 32
/**
* cuda vector add function
**/
// there is a problem here, running this ruins the add
__global__ void d_add( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] + y[index];
}
void add( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_add<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
// hope for the best
}
/**
* mul:
* cuda vector multiply function
**/
__global__ void d_mul( float *x, float *y, float *z, int size)
{
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < size)
z[index] = x[index] * y[index];
}
void mul( float *x, float *y, int length)
{
float *d_x, *d_y, *d_z; // device copies of x and y and a result z
int size = length * sizeof(float); // need space for total number of floats
// allocate device space
hipMalloc( (void**)&d_x, size);
hipMalloc( (void**)&d_y, size);
hipMalloc( (void**)&d_z, size);
// copy vector from host to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// launch the kernel, eat some chicken
d_mul<<< ceil((float)length/(float)BLOCKSIZE), BLOCKSIZE >>>(d_x, d_y, d_z, size);
// copy the result back to the host
hipMemcpy(x, d_z, size, hipMemcpyDeviceToHost);
// free device mem
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
} | .text
.file "cudafunctions.hip"
.globl _Z20__device_stub__d_addPfS_S_i # -- Begin function _Z20__device_stub__d_addPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__d_addPfS_S_i,@function
_Z20__device_stub__d_addPfS_S_i: # @_Z20__device_stub__d_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__d_addPfS_S_i, .Lfunc_end0-_Z20__device_stub__d_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3addPfS_i
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z3addPfS_i
.p2align 4, 0x90
.type _Z3addPfS_i,@function
_Z3addPfS_i: # @_Z3addPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %rbx
leal (,%r15,4), %ebp
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5d_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3addPfS_i, .Lfunc_end1-_Z3addPfS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__d_mulPfS_S_i # -- Begin function _Z20__device_stub__d_mulPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__d_mulPfS_S_i,@function
_Z20__device_stub__d_mulPfS_S_i: # @_Z20__device_stub__d_mulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_mulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__d_mulPfS_S_i, .Lfunc_end2-_Z20__device_stub__d_mulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3mulPfS_i
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z3mulPfS_i
.p2align 4, 0x90
.type _Z3mulPfS_i,@function
_Z3mulPfS_i: # @_Z3mulPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %rbx
leal (,%r15,4), %ebp
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5d_mulPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z3mulPfS_i, .Lfunc_end3-_Z3mulPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_mulPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5d_addPfS_S_i,@object # @_Z5d_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5d_addPfS_S_i
.p2align 3, 0x0
_Z5d_addPfS_S_i:
.quad _Z20__device_stub__d_addPfS_S_i
.size _Z5d_addPfS_S_i, 8
.type _Z5d_mulPfS_S_i,@object # @_Z5d_mulPfS_S_i
.globl _Z5d_mulPfS_S_i
.p2align 3, 0x0
_Z5d_mulPfS_S_i:
.quad _Z20__device_stub__d_mulPfS_S_i
.size _Z5d_mulPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5d_addPfS_S_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5d_mulPfS_S_i"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__d_addPfS_S_i
.addrsig_sym _Z20__device_stub__d_mulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5d_addPfS_S_i
.addrsig_sym _Z5d_mulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5d_mulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5d_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5d_addPfS_S_i
.globl _Z5d_addPfS_S_i
.p2align 8
.type _Z5d_addPfS_S_i,@function
_Z5d_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_addPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5d_addPfS_S_i, .Lfunc_end0-_Z5d_addPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5d_mulPfS_S_i
.globl _Z5d_mulPfS_S_i
.p2align 8
.type _Z5d_mulPfS_S_i,@function
_Z5d_mulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5d_mulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5d_mulPfS_S_i, .Lfunc_end1-_Z5d_mulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_addPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_addPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5d_mulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5d_mulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6139_00000000-6_cudafunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5d_addPfS_S_iPfS_S_i:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_addPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
.globl _Z5d_addPfS_S_i
.type _Z5d_addPfS_S_i, @function
_Z5d_addPfS_S_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z5d_addPfS_S_i, .-_Z5d_addPfS_S_i
.globl _Z3addPfS_i
.type _Z3addPfS_i, @function
_Z3addPfS_i:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %rsi, %r14
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5d_addPfS_S_iPfS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z3addPfS_i, .-_Z3addPfS_i
.globl _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
.type _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i, @function
_Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L23
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5d_mulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i, .-_Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
.globl _Z5d_mulPfS_S_i
.type _Z5d_mulPfS_S_i, @function
_Z5d_mulPfS_S_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z5d_mulPfS_S_i, .-_Z5d_mulPfS_S_i
.globl _Z3mulPfS_i
.type _Z3mulPfS_i, @function
_Z3mulPfS_i:
.LFB2028:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %rsi, %r14
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %r13d
movslq %r13d, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L27
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L27:
cvttss2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl %r13d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z5d_mulPfS_S_iPfS_S_i
jmp .L28
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size _Z3mulPfS_i, .-_Z3mulPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z5d_mulPfS_S_i"
.LC6:
.string "_Z5d_addPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_mulPfS_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z5d_addPfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1023410176
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudafunctions.hip"
.globl _Z20__device_stub__d_addPfS_S_i # -- Begin function _Z20__device_stub__d_addPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__d_addPfS_S_i,@function
_Z20__device_stub__d_addPfS_S_i: # @_Z20__device_stub__d_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_addPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__d_addPfS_S_i, .Lfunc_end0-_Z20__device_stub__d_addPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3addPfS_i
.LCPI1_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z3addPfS_i
.p2align 4, 0x90
.type _Z3addPfS_i,@function
_Z3addPfS_i: # @_Z3addPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %rbx
leal (,%r15,4), %ebp
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5d_addPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z3addPfS_i, .Lfunc_end1-_Z3addPfS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__d_mulPfS_S_i # -- Begin function _Z20__device_stub__d_mulPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__d_mulPfS_S_i,@function
_Z20__device_stub__d_mulPfS_S_i: # @_Z20__device_stub__d_mulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5d_mulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__d_mulPfS_S_i, .Lfunc_end2-_Z20__device_stub__d_mulPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3mulPfS_i
.LCPI3_0:
.long 0x3d000000 # float 0.03125
.text
.globl _Z3mulPfS_i
.p2align 4, 0x90
.type _Z3mulPfS_i,@function
_Z3mulPfS_i: # @_Z3mulPfS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %rbx
leal (,%r15,4), %ebp
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $32, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5d_mulPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z3mulPfS_i, .Lfunc_end3-_Z3mulPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_addPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5d_mulPfS_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5d_addPfS_S_i,@object # @_Z5d_addPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5d_addPfS_S_i
.p2align 3, 0x0
_Z5d_addPfS_S_i:
.quad _Z20__device_stub__d_addPfS_S_i
.size _Z5d_addPfS_S_i, 8
.type _Z5d_mulPfS_S_i,@object # @_Z5d_mulPfS_S_i
.globl _Z5d_mulPfS_S_i
.p2align 3, 0x0
_Z5d_mulPfS_S_i:
.quad _Z20__device_stub__d_mulPfS_S_i
.size _Z5d_mulPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5d_addPfS_S_i"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5d_mulPfS_S_i"
.size .L__unnamed_2, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__d_addPfS_S_i
.addrsig_sym _Z20__device_stub__d_mulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5d_addPfS_S_i
.addrsig_sym _Z5d_mulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
cudaMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
cudaFree(gpu_warp);
cudaFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} | code for sm_80
Function : _Z13what_is_my_idPjS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F.U32.RP R0, 0x20 ; /* 0x0000002000007906 */
/* 0x000e220000209000 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0030*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e660000002500 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R11, R15, c[0x0][0x0], R10 ; /* 0x000000000f0b7a24 */
/* 0x002fe200078e020a */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fc60007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R6, R11, R8, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fc600078e0008 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ LEA R5, -R3, RZ, 0x5 ; /* 0x000000ff03057211 */
/* 0x002fd200078e29ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*00e0*/ IMAD.WIDE.U32 R4, R11, R8, c[0x0][0x168] ; /* 0x00005a000b047625 */
/* 0x000fc800078e0008 */
/*00f0*/ IMAD.HI.U32 R13, R3, R10, RZ ; /* 0x0000000a030d7227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R3, R13, -0x20, R10 ; /* 0xffffffe00d037824 */
/* 0x000fca00078e020a */
/*0110*/ ISETP.GE.U32.AND P0, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R3, R3, -0x20, RZ ; /* 0xffffffe003030810 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d0810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fe20003f26070 */
/*0150*/ IMAD.WIDE.U32 R2, R11, R8, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fc800078e0008 */
/*0160*/ IMAD.WIDE.U32 R8, R11, R8, c[0x0][0x178] ; /* 0x00005e000b087625 */
/* 0x000fe200078e0008 */
/*0170*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe6000c101904 */
/*0190*/ @P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d1810 */
/* 0x000fca0007ffe0ff */
/*01a0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
cudaMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
cudaFree(gpu_warp);
cudaFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} | .file "tmpxft_001348ec_00000000-6_Main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
.type _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_, @function
_Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13what_is_my_idPjS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_, .-_Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
.globl _Z13what_is_my_idPjS_S_S_
.type _Z13what_is_my_idPjS_S_S_, @function
_Z13what_is_my_idPjS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13what_is_my_idPjS_S_S_, .-_Z13what_is_my_idPjS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $512, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
leaq cpu_warp(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
leaq cpu_calc_thread(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq cpu_thread(%rip), %r14
leaq cpu_warp(%rip), %r13
leaq cpu_block(%rip), %r12
leaq cpu_calc_thread(%rip), %rbp
.L13:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movl (%r14,%rbx), %r9d
movl 0(%r13,%rbx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $512, %rbx
jne .L13
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13what_is_my_idPjS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13what_is_my_idPjS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cpu_calc_thread
.bss
.align 32
.type cpu_calc_thread, @object
.size cpu_calc_thread, 512
cpu_calc_thread:
.zero 512
.globl cpu_warp
.align 32
.type cpu_warp, @object
.size cpu_warp, 512
cpu_warp:
.zero 512
.globl cpu_thread
.align 32
.type cpu_thread, @object
.size cpu_thread, 512
cpu_thread:
.zero 512
.globl cpu_block
.align 32
.type cpu_block, @object
.size cpu_block, 512
cpu_block:
.zero 512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
cudaMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
cudaMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
cudaMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, cudaMemcpyDeviceToHost);
cudaFree(gpu_block);
cudaFree(gpu_thread);
cudaFree(gpu_warp);
cudaFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
hipMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
hipFree(gpu_warp);
hipFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
hipMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
hipFree(gpu_warp);
hipFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13what_is_my_idPjS_S_S_
.globl _Z13what_is_my_idPjS_S_S_
.p2align 8
.type _Z13what_is_my_idPjS_S_S_,@function
_Z13what_is_my_idPjS_S_S_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v10, s15
v_lshrrev_b32_e32 v11, 5, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[4:5], v10, off
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v11, off
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13what_is_my_idPjS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13what_is_my_idPjS_S_S_, .Lfunc_end0-_Z13what_is_my_idPjS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13what_is_my_idPjS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13what_is_my_idPjS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void what_is_my_id(unsigned int * const block,
unsigned int * const thread,
unsigned int * const warp,
unsigned int * const calc_thread)
{
// Thread_ID is block_index * block_size + thread_index inside this block
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
block[idx] = blockIdx.x;
thread[idx] = threadIdx.x;
warp[idx] = threadIdx.x / warpSize; // Use build in variable warpSize=32 to calculate actual warp
calc_thread[idx] = idx;
}
#define ARRAY_SIZE 128
#define ARRAY_SIZE_IN_BYTES (sizeof(unsigned int) * (ARRAY_SIZE))
unsigned int cpu_block[ARRAY_SIZE];
unsigned int cpu_thread[ARRAY_SIZE];
unsigned int cpu_warp[ARRAY_SIZE];
unsigned int cpu_calc_thread[ARRAY_SIZE];
int main(void){
// Total threads: 64 * 2 = 128
const unsigned int num_blocks = 2;
const unsigned int num_threads = 64;
// Declare pointers for GPU based params
unsigned int * gpu_block;
unsigned int * gpu_thread;
unsigned int * gpu_warp;
unsigned int * gpu_calc_thread;
// Declaration of loop iterator
unsigned int i;
// Allocate four arrays on GPU
hipMalloc((void **)&gpu_block, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_thread, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_warp, ARRAY_SIZE_IN_BYTES);
hipMalloc((void **)&gpu_calc_thread, ARRAY_SIZE_IN_BYTES);
// Execute kernel
what_is_my_id<<<num_blocks, num_threads>>>(gpu_block, gpu_thread, gpu_warp, gpu_calc_thread);
hipMemcpy(cpu_block, gpu_block, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_thread, gpu_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_warp, gpu_warp, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipMemcpy(cpu_calc_thread, gpu_calc_thread, ARRAY_SIZE_IN_BYTES, hipMemcpyDeviceToHost);
hipFree(gpu_block);
hipFree(gpu_thread);
hipFree(gpu_warp);
hipFree(gpu_calc_thread);
for(i=0;i<ARRAY_SIZE;i++){
printf("Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n",
cpu_calc_thread[i], cpu_block[i], cpu_warp[i], cpu_thread[i]);
}
} | .text
.file "Main.hip"
.globl _Z28__device_stub__what_is_my_idPjS_S_S_ # -- Begin function _Z28__device_stub__what_is_my_idPjS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__what_is_my_idPjS_S_S_,@function
_Z28__device_stub__what_is_my_idPjS_S_S_: # @_Z28__device_stub__what_is_my_idPjS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13what_is_my_idPjS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__what_is_my_idPjS_S_S_, .Lfunc_end0-_Z28__device_stub__what_is_my_idPjS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13what_is_my_idPjS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movl $cpu_block, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $cpu_thread, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $cpu_warp, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_calc_thread, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq $-512, %rbx # imm = 0xFE00
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl cpu_calc_thread+512(%rbx), %esi
movl cpu_block+512(%rbx), %edx
movl cpu_warp+512(%rbx), %ecx
movl cpu_thread+512(%rbx), %r8d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $4, %rbx
jne .LBB1_3
# %bb.4:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13what_is_my_idPjS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13what_is_my_idPjS_S_S_,@object # @_Z13what_is_my_idPjS_S_S_
.section .rodata,"a",@progbits
.globl _Z13what_is_my_idPjS_S_S_
.p2align 3, 0x0
_Z13what_is_my_idPjS_S_S_:
.quad _Z28__device_stub__what_is_my_idPjS_S_S_
.size _Z13what_is_my_idPjS_S_S_, 8
.type cpu_block,@object # @cpu_block
.bss
.globl cpu_block
.p2align 4, 0x0
cpu_block:
.zero 512
.size cpu_block, 512
.type cpu_thread,@object # @cpu_thread
.globl cpu_thread
.p2align 4, 0x0
cpu_thread:
.zero 512
.size cpu_thread, 512
.type cpu_warp,@object # @cpu_warp
.globl cpu_warp
.p2align 4, 0x0
cpu_warp:
.zero 512
.size cpu_warp, 512
.type cpu_calc_thread,@object # @cpu_calc_thread
.globl cpu_calc_thread
.p2align 4, 0x0
cpu_calc_thread:
.zero 512
.size cpu_calc_thread, 512
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n"
.size .L.str, 64
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13what_is_my_idPjS_S_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__what_is_my_idPjS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13what_is_my_idPjS_S_S_
.addrsig_sym cpu_block
.addrsig_sym cpu_thread
.addrsig_sym cpu_warp
.addrsig_sym cpu_calc_thread
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13what_is_my_idPjS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F.U32.RP R0, 0x20 ; /* 0x0000002000007906 */
/* 0x000e220000209000 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0030*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e660000002500 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R11, R15, c[0x0][0x0], R10 ; /* 0x000000000f0b7a24 */
/* 0x002fe200078e020a */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fc60007ffe0ff */
/*0090*/ IMAD.WIDE.U32 R6, R11, R8, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fc600078e0008 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ LEA R5, -R3, RZ, 0x5 ; /* 0x000000ff03057211 */
/* 0x002fd200078e29ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fc800078e0002 */
/*00e0*/ IMAD.WIDE.U32 R4, R11, R8, c[0x0][0x168] ; /* 0x00005a000b047625 */
/* 0x000fc800078e0008 */
/*00f0*/ IMAD.HI.U32 R13, R3, R10, RZ ; /* 0x0000000a030d7227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R3, R13, -0x20, R10 ; /* 0xffffffe00d037824 */
/* 0x000fca00078e020a */
/*0110*/ ISETP.GE.U32.AND P0, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R3, R3, -0x20, RZ ; /* 0xffffffe003030810 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d0810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fe20003f26070 */
/*0150*/ IMAD.WIDE.U32 R2, R11, R8, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fc800078e0008 */
/*0160*/ IMAD.WIDE.U32 R8, R11, R8, c[0x0][0x178] ; /* 0x00005e000b087625 */
/* 0x000fe200078e0008 */
/*0170*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x000fe8000c101904 */
/*0180*/ STG.E [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x000fe6000c101904 */
/*0190*/ @P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d1810 */
/* 0x000fca0007ffe0ff */
/*01a0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13what_is_my_idPjS_S_S_
.globl _Z13what_is_my_idPjS_S_S_
.p2align 8
.type _Z13what_is_my_idPjS_S_S_,@function
_Z13what_is_my_idPjS_S_S_:
s_clause 0x1
s_load_b32 s8, s[0:1], 0x2c
s_load_b256 s[0:7], s[0:1], 0x0
v_mov_b32_e32 v10, s15
v_lshrrev_b32_e32 v11, 5, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_store_b32 v[4:5], v10, off
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v11, off
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13what_is_my_idPjS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13what_is_my_idPjS_S_S_, .Lfunc_end0-_Z13what_is_my_idPjS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13what_is_my_idPjS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13what_is_my_idPjS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001348ec_00000000-6_Main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
.type _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_, @function
_Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13what_is_my_idPjS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_, .-_Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
.globl _Z13what_is_my_idPjS_S_S_
.type _Z13what_is_my_idPjS_S_S_, @function
_Z13what_is_my_idPjS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13what_is_my_idPjS_S_S_, .-_Z13what_is_my_idPjS_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $64, 44(%rsp)
movl $1, 48(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $512, %edx
movq (%rsp), %rsi
leaq cpu_block(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
leaq cpu_thread(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
leaq cpu_warp(%rip), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
leaq cpu_calc_thread(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq cpu_thread(%rip), %r14
leaq cpu_warp(%rip), %r13
leaq cpu_block(%rip), %r12
leaq cpu_calc_thread(%rip), %rbp
.L13:
movl (%r12,%rbx), %ecx
movl 0(%rbp,%rbx), %edx
movl (%r14,%rbx), %r9d
movl 0(%r13,%rbx), %r8d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $512, %rbx
jne .L13
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z13what_is_my_idPjS_S_S_PjS_S_S_
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13what_is_my_idPjS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13what_is_my_idPjS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl cpu_calc_thread
.bss
.align 32
.type cpu_calc_thread, @object
.size cpu_calc_thread, 512
cpu_calc_thread:
.zero 512
.globl cpu_warp
.align 32
.type cpu_warp, @object
.size cpu_warp, 512
cpu_warp:
.zero 512
.globl cpu_thread
.align 32
.type cpu_thread, @object
.size cpu_thread, 512
cpu_thread:
.zero 512
.globl cpu_block
.align 32
.type cpu_block, @object
.size cpu_block, 512
cpu_block:
.zero 512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Main.hip"
.globl _Z28__device_stub__what_is_my_idPjS_S_S_ # -- Begin function _Z28__device_stub__what_is_my_idPjS_S_S_
.p2align 4, 0x90
.type _Z28__device_stub__what_is_my_idPjS_S_S_,@function
_Z28__device_stub__what_is_my_idPjS_S_S_: # @_Z28__device_stub__what_is_my_idPjS_S_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13what_is_my_idPjS_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__what_is_my_idPjS_S_S_, .Lfunc_end0-_Z28__device_stub__what_is_my_idPjS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rsi, 80(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13what_is_my_idPjS_S_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 24(%rsp), %rsi
movl $cpu_block, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
movl $cpu_thread, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $cpu_warp, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $cpu_calc_thread, %edi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq $-512, %rbx # imm = 0xFE00
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl cpu_calc_thread+512(%rbx), %esi
movl cpu_block+512(%rbx), %edx
movl cpu_warp+512(%rbx), %ecx
movl cpu_thread+512(%rbx), %r8d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
addq $4, %rbx
jne .LBB1_3
# %bb.4:
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13what_is_my_idPjS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13what_is_my_idPjS_S_S_,@object # @_Z13what_is_my_idPjS_S_S_
.section .rodata,"a",@progbits
.globl _Z13what_is_my_idPjS_S_S_
.p2align 3, 0x0
_Z13what_is_my_idPjS_S_S_:
.quad _Z28__device_stub__what_is_my_idPjS_S_S_
.size _Z13what_is_my_idPjS_S_S_, 8
.type cpu_block,@object # @cpu_block
.bss
.globl cpu_block
.p2align 4, 0x0
cpu_block:
.zero 512
.size cpu_block, 512
.type cpu_thread,@object # @cpu_thread
.globl cpu_thread
.p2align 4, 0x0
cpu_thread:
.zero 512
.size cpu_thread, 512
.type cpu_warp,@object # @cpu_warp
.globl cpu_warp
.p2align 4, 0x0
cpu_warp:
.zero 512
.size cpu_warp, 512
.type cpu_calc_thread,@object # @cpu_calc_thread
.globl cpu_calc_thread
.p2align 4, 0x0
cpu_calc_thread:
.zero 512
.size cpu_calc_thread, 512
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Calculcated thread: %3u | Block: %3u | Warp: %3u | Thread: %3u\n"
.size .L.str, 64
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13what_is_my_idPjS_S_S_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__what_is_my_idPjS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13what_is_my_idPjS_S_S_
.addrsig_sym cpu_block
.addrsig_sym cpu_thread
.addrsig_sym cpu_warp
.addrsig_sym cpu_calc_thread
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
cudaMalloc((void **)&d_a, nBytes);
cudaMalloc((void **)&d_b, nBytes);
cudaMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
cudaMemcpy(d_a, h_a, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, nBytes, cudaMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
cudaMemcpy(h_c, d_c, nBytes, cudaMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} | code for sm_80
Function : _Z15soma_matriz_GPUiiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x164], R3 ; /* 0x0000590000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
cudaMalloc((void **)&d_a, nBytes);
cudaMalloc((void **)&d_b, nBytes);
cudaMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
cudaMemcpy(d_a, h_a, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, nBytes, cudaMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
cudaMemcpy(h_c, d_c, nBytes, cudaMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} | .file "tmpxft_00029f58_00000000-6_exemplo_matriz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15soma_matriz_CPUiiPiS_S_
.type _Z15soma_matriz_CPUiiPiS_S_, @function
_Z15soma_matriz_CPUiiPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %r9d
testl %edi, %edi
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %esi, %r10d
movq %rdx, %rsi
movq %rcx, %rdi
movl $0, %ebx
movl $0, %r11d
movslq %r10d, %rbp
jmp .L5
.L7:
movslq %ebx, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%rdi,%rax), %edx
addl (%rsi,%rax), %edx
movl %edx, (%r8,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r11d
addl %r10d, %ebx
cmpl %r11d, %r9d
je .L3
.L5:
testl %r10d, %r10d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z15soma_matriz_CPUiiPiS_S_, .-_Z15soma_matriz_CPUiiPiS_S_
.globl _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
.type _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_, @function
_Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15soma_matriz_GPUiiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_, .-_Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
.globl _Z15soma_matriz_GPUiiPiS_S_
.type _Z15soma_matriz_GPUiiPiS_S_, @function
_Z15soma_matriz_GPUiiPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15soma_matriz_GPUiiPiS_S_, .-_Z15soma_matriz_GPUiiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Resultado errado"
.LC1:
.string "Resultado correto"
.LC2:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rsi
movq %rbx, %rcx
movl $0, %r8d
.L23:
movl %r8d, %edi
movl $0, %eax
.L24:
leal (%rdi,%rax), %edx
movl %edx, (%rsi,%rax,4)
movl %edx, (%rcx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L24
addl $1, %r8d
addq $4096, %rsi
addq $4096, %rcx
cmpl $1024, %r8d
jne .L23
movq %r12, %r8
movq %rbx, %rcx
movq %rbp, %rdx
movl $1024, %esi
movl $1024, %edi
call _Z15soma_matriz_CPUiiPiS_S_
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %r12, %rcx
movl $0, %r8d
movl $1, %edi
jmp .L27
.L38:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, %esi
movl $1024, %edi
call _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
jmp .L26
.L40:
movl %eax, %edx
addq $1, %rax
cmpl $1023, %edx
jg .L39
.L29:
movl -4(%rcx,%rax,4), %edx
cmpl %edx, -4(%rsi,%rax,4)
je .L40
movl %edi, %eax
.L28:
addl $1, %r8d
addq $4096, %rsi
addq $4096, %rcx
cmpl $1023, %r8d
jg .L30
testb %al, %al
jne .L30
.L27:
movl $1, %eax
jmp .L29
.L39:
movl $0, %eax
jmp .L28
.L30:
testb %al, %al
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z15soma_matriz_GPUiiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15soma_matriz_GPUiiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
cudaMalloc((void **)&d_a, nBytes);
cudaMalloc((void **)&d_b, nBytes);
cudaMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
cudaMemcpy(d_a, h_a, nBytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, nBytes, cudaMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
cudaMemcpy(h_c, d_c, nBytes, cudaMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
hipMalloc((void **)&d_a, nBytes);
hipMalloc((void **)&d_b, nBytes);
hipMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
hipMemcpy(d_a, h_a, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, nBytes, hipMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
hipMemcpy(h_c, d_c, nBytes, hipMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
hipMalloc((void **)&d_a, nBytes);
hipMalloc((void **)&d_b, nBytes);
hipMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
hipMemcpy(d_a, h_a, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, nBytes, hipMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
hipMemcpy(h_c, d_c, nBytes, hipMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15soma_matriz_GPUiiPiS_S_
.globl _Z15soma_matriz_GPUiiPiS_S_
.p2align 8
.type _Z15soma_matriz_GPUiiPiS_S_,@function
_Z15soma_matriz_GPUiiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15soma_matriz_GPUiiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15soma_matriz_GPUiiPiS_S_, .Lfunc_end0-_Z15soma_matriz_GPUiiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15soma_matriz_GPUiiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15soma_matriz_GPUiiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Exemplo 17: Soma de matrizes
// Usa grid e blocos bidimensionais
// Para compilar: nvcc ex17.cu -o ex17
// Para executar: ./ex17
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
void soma_matriz_CPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j;
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j]; // Célula c[i][j]
}
// Kernel executado na GPU por todas as threads de todos os blocos
__global__ void soma_matriz_GPU(int nLinhas, int nColunas, int *a, int *b, int *c)
{
int i, j; // id GLOBAL da thread
i = blockIdx.x * blockDim.x + threadIdx.x;
j = blockIdx.y * blockDim.y + threadIdx.y;
if ((i < nLinhas) && (j < nColunas))
c[i * nColunas + j] = a[i * nColunas + j] + b[i * nColunas + j];
}
// Programa principal: execução inicia no host
int main(void)
{
int nLinhas = 1024,
nColunas = 1024,
nBytes = nLinhas * nColunas * sizeof(int),
i, j,
*h_a, *h_b, *h_c, // Variáveis do host
*d_a, *d_b, *d_c, // Variáveis da GPU (device)
*c_referencia;
// Aloca matrizes no host
h_a = (int *) malloc(nBytes);
h_b = (int *) malloc(nBytes);
h_c = (int *) malloc(nBytes);
c_referencia = (int *) malloc(nBytes);
// Inicializa variáveis do host
for (i = 0; i < nLinhas; i++)
for (j = 0; j < nColunas; j++)
{
h_a[i * nColunas + j] = i + j; // Célula h_a[i][j]
h_b[i * nColunas + j] = i + j; // Célula h_b[i][j]
}
// Soma matrizes na CPU
soma_matriz_CPU(nLinhas, nColunas, h_a, h_b, c_referencia);
// Aloca matrizes na memória global da GPU
hipMalloc((void **)&d_a, nBytes);
hipMalloc((void **)&d_b, nBytes);
hipMalloc((void **)&d_c, nBytes);
// Copia dados de entrada do host para memória global da GPU
hipMemcpy(d_a, h_a, nBytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, nBytes, hipMemcpyHostToDevice);
// Determina nBlocos em função de nLinhas e NColunas
dim3 nThreadsBloco(32,32);
dim3 nBlocos((nLinhas + (nThreadsBloco.x - 1)) / nThreadsBloco.x, (nColunas + (nThreadsBloco.y - 1)) / nThreadsBloco.y);
// Soma matrizes na GPU
// Grid bidimensaional com blocos bidimensionais
soma_matriz_GPU<<<nBlocos, nThreadsBloco>>>(nLinhas, nColunas, d_a, d_b, d_c);
// Copia resultados da memória global da GPU para host
hipMemcpy(h_c, d_c, nBytes, hipMemcpyDeviceToHost);
// Checa resultado
i = 0;
bool erro = false;
while (i < nLinhas && !erro)
{
j = 0;
while (j < nColunas && !erro)
{
if (h_c[i * nColunas + j] != c_referencia[i * nColunas + j])
erro = true;
j++;
}
i++;
}
printf("%s\n", (erro ? "Resultado errado" : "Resultado correto"));
// Libera matrizes na memória global da GPU
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// Libera matrizes no host
free(h_a);
free(h_b);
free(h_c);
free(c_referencia);
return 0;
} | .text
.file "exemplo_matriz.hip"
.globl _Z15soma_matriz_CPUiiPiS_S_ # -- Begin function _Z15soma_matriz_CPUiiPiS_S_
.p2align 4, 0x90
.type _Z15soma_matriz_CPUiiPiS_S_,@function
_Z15soma_matriz_CPUiiPiS_S_: # @_Z15soma_matriz_CPUiiPiS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %eax
movl %esi, %edi
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %esi, %r9d
cmpq %rax, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %esi, %esi
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r14d
leaq (%r8,%r14,4), %r11
leaq (%rcx,%r14,4), %rbx
leaq (%rdx,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ebp
addl (%r14,%r15,4), %ebp
movl %ebp, (%r11,%r15,4)
incq %r15
cmpq %r15, %rdi
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge21
retq
.Lfunc_end0:
.size _Z15soma_matriz_CPUiiPiS_S_, .Lfunc_end0-_Z15soma_matriz_CPUiiPiS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__soma_matriz_GPUiiPiS_S_ # -- Begin function _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__soma_matriz_GPUiiPiS_S_,@function
_Z30__device_stub__soma_matriz_GPUiiPiS_S_: # @_Z30__device_stub__soma_matriz_GPUiiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15soma_matriz_GPUiiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__soma_matriz_GPUiiPiS_S_, .Lfunc_end1-_Z30__device_stub__soma_matriz_GPUiiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB2_1: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rcx,%rsi,4)
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.4: # %.preheader.i.preheader
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
movq %r12, %rsi
.p2align 4, 0x90
.LBB2_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rdi,4), %r8d
addl (%rcx,%rdi,4), %r8d
movl %r8d, (%rsi,%rdi,4)
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB2_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB2_5 Depth=1
incq %rax
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB2_5
# %bb.8: # %_Z15soma_matriz_CPUiiPiS_S_.exit
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $1, %ebp
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, 36(%rsp) # imm = 0x400
movl $1024, 32(%rsp) # imm = 0x400
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15soma_matriz_GPUiiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movq %r15, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
testb $1, %sil
jne .LBB2_15
# %bb.12: # %.lr.ph
# in Loop: Header=BB2_11 Depth=1
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdi,4), %r8d
cmpl (%rdx,%rdi,4), %r8d
movzbl %sil, %esi
cmovnel %ebp, %esi
cmpq $1022, %rdi # imm = 0x3FE
ja .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=2
incq %rdi
movl %esi, %r8d
andb $1, %r8b
je .LBB2_13
.LBB2_15: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
cmpq $1022, %rax # imm = 0x3FE
ja .LBB2_17
# %bb.16: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
incq %rax
movl %esi, %edi
andb $1, %dil
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
testb %dil, %dil
je .LBB2_11
.LBB2_17:
testb $1, %sil
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15soma_matriz_GPUiiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15soma_matriz_GPUiiPiS_S_,@object # @_Z15soma_matriz_GPUiiPiS_S_
.section .rodata,"a",@progbits
.globl _Z15soma_matriz_GPUiiPiS_S_
.p2align 3, 0x0
_Z15soma_matriz_GPUiiPiS_S_:
.quad _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.size _Z15soma_matriz_GPUiiPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Resultado errado"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Resultado correto"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15soma_matriz_GPUiiPiS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15soma_matriz_GPUiiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15soma_matriz_GPUiiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x164], R3 ; /* 0x0000590000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0207 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15soma_matriz_GPUiiPiS_S_
.globl _Z15soma_matriz_GPUiiPiS_S_
.p2align 8
.type _Z15soma_matriz_GPUiiPiS_S_,@function
_Z15soma_matriz_GPUiiPiS_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15soma_matriz_GPUiiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15soma_matriz_GPUiiPiS_S_, .Lfunc_end0-_Z15soma_matriz_GPUiiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15soma_matriz_GPUiiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15soma_matriz_GPUiiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00029f58_00000000-6_exemplo_matriz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15soma_matriz_CPUiiPiS_S_
.type _Z15soma_matriz_CPUiiPiS_S_, @function
_Z15soma_matriz_CPUiiPiS_S_:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %r9d
testl %edi, %edi
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movl %esi, %r10d
movq %rdx, %rsi
movq %rcx, %rdi
movl $0, %ebx
movl $0, %r11d
movslq %r10d, %rbp
jmp .L5
.L7:
movslq %ebx, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%rdi,%rax), %edx
addl (%rsi,%rax), %edx
movl %edx, (%r8,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r11d
addl %r10d, %ebx
cmpl %r11d, %r9d
je .L3
.L5:
testl %r10d, %r10d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size _Z15soma_matriz_CPUiiPiS_S_, .-_Z15soma_matriz_CPUiiPiS_S_
.globl _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
.type _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_, @function
_Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15soma_matriz_GPUiiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_, .-_Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
.globl _Z15soma_matriz_GPUiiPiS_S_
.type _Z15soma_matriz_GPUiiPiS_S_, @function
_Z15soma_matriz_GPUiiPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z15soma_matriz_GPUiiPiS_S_, .-_Z15soma_matriz_GPUiiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Resultado errado"
.LC1:
.string "Resultado correto"
.LC2:
.string "%s\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r13
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rsi
movq %rbx, %rcx
movl $0, %r8d
.L23:
movl %r8d, %edi
movl $0, %eax
.L24:
leal (%rdi,%rax), %edx
movl %edx, (%rsi,%rax,4)
movl %edx, (%rcx,%rax,4)
addq $1, %rax
cmpq $1024, %rax
jne .L24
addl $1, %r8d
addq $4096, %rsi
addq $4096, %rcx
cmpl $1024, %r8d
jne .L23
movq %r12, %r8
movq %rbx, %rcx
movq %rbp, %rdx
movl $1024, %esi
movl $1024, %edi
call _Z15soma_matriz_CPUiiPiS_S_
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $32, 48(%rsp)
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L26:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %r12, %rcx
movl $0, %r8d
movl $1, %edi
jmp .L27
.L38:
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, %esi
movl $1024, %edi
call _Z41__device_stub__Z15soma_matriz_GPUiiPiS_S_iiPiS_S_
jmp .L26
.L40:
movl %eax, %edx
addq $1, %rax
cmpl $1023, %edx
jg .L39
.L29:
movl -4(%rcx,%rax,4), %edx
cmpl %edx, -4(%rsi,%rax,4)
je .L40
movl %edi, %eax
.L28:
addl $1, %r8d
addq $4096, %rsi
addq $4096, %rcx
cmpl $1023, %r8d
jg .L30
testb %al, %al
jne .L30
.L27:
movl $1, %eax
jmp .L29
.L39:
movl $0, %eax
jmp .L28
.L30:
testb %al, %al
leaq .LC1(%rip), %rdx
leaq .LC0(%rip), %rax
cmovne %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z15soma_matriz_GPUiiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z15soma_matriz_GPUiiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exemplo_matriz.hip"
.globl _Z15soma_matriz_CPUiiPiS_S_ # -- Begin function _Z15soma_matriz_CPUiiPiS_S_
.p2align 4, 0x90
.type _Z15soma_matriz_CPUiiPiS_S_,@function
_Z15soma_matriz_CPUiiPiS_S_: # @_Z15soma_matriz_CPUiiPiS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %eax
movl %esi, %edi
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %esi, %r9d
cmpq %rax, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %esi, %esi
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r14d
leaq (%r8,%r14,4), %r11
leaq (%rcx,%r14,4), %rbx
leaq (%rdx,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ebp
addl (%r14,%r15,4), %ebp
movl %ebp, (%r11,%r15,4)
incq %r15
cmpq %r15, %rdi
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge21
retq
.Lfunc_end0:
.size _Z15soma_matriz_CPUiiPiS_S_, .Lfunc_end0-_Z15soma_matriz_CPUiiPiS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__soma_matriz_GPUiiPiS_S_ # -- Begin function _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__soma_matriz_GPUiiPiS_S_,@function
_Z30__device_stub__soma_matriz_GPUiiPiS_S_: # @_Z30__device_stub__soma_matriz_GPUiiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15soma_matriz_GPUiiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z30__device_stub__soma_matriz_GPUiiPiS_S_, .Lfunc_end1-_Z30__device_stub__soma_matriz_GPUiiPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r12
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB2_1: # %.preheader77
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rcx,%rsi,4)
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $1024, %rsi # imm = 0x400
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
incq %rax
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.4: # %.preheader.i.preheader
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
movq %r12, %rsi
.p2align 4, 0x90
.LBB2_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%rdi,4), %r8d
addl (%rcx,%rdi,4), %r8d
movl %r8d, (%rsi,%rdi,4)
incq %rdi
cmpq $1024, %rdi # imm = 0x400
jne .LBB2_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB2_5 Depth=1
incq %rax
addq $4096, %rsi # imm = 0x1000
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
cmpq $1024, %rax # imm = 0x400
jne .LBB2_5
# %bb.8: # %_Z15soma_matriz_CPUiiPiS_S_.exit
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movl $1, %ebp
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, 36(%rsp) # imm = 0x400
movl $1024, 32(%rsp) # imm = 0x400
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 104(%rsp), %rax
movq %rax, 128(%rsp)
leaq 96(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15soma_matriz_GPUiiPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movq %r15, %rcx
movq %r12, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_13 Depth 2
testb $1, %sil
jne .LBB2_15
# %bb.12: # %.lr.ph
# in Loop: Header=BB2_11 Depth=1
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_13: # Parent Loop BB2_11 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rcx,%rdi,4), %r8d
cmpl (%rdx,%rdi,4), %r8d
movzbl %sil, %esi
cmovnel %ebp, %esi
cmpq $1022, %rdi # imm = 0x3FE
ja .LBB2_15
# %bb.14: # in Loop: Header=BB2_13 Depth=2
incq %rdi
movl %esi, %r8d
andb $1, %r8b
je .LBB2_13
.LBB2_15: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
cmpq $1022, %rax # imm = 0x3FE
ja .LBB2_17
# %bb.16: # %._crit_edge
# in Loop: Header=BB2_11 Depth=1
incq %rax
movl %esi, %edi
andb $1, %dil
addq $4096, %rdx # imm = 0x1000
addq $4096, %rcx # imm = 0x1000
testb %dil, %dil
je .LBB2_11
.LBB2_17:
testb $1, %sil
movl $.L.str.2, %eax
movl $.L.str.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15soma_matriz_GPUiiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15soma_matriz_GPUiiPiS_S_,@object # @_Z15soma_matriz_GPUiiPiS_S_
.section .rodata,"a",@progbits
.globl _Z15soma_matriz_GPUiiPiS_S_
.p2align 3, 0x0
_Z15soma_matriz_GPUiiPiS_S_:
.quad _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.size _Z15soma_matriz_GPUiiPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Resultado errado"
.size .L.str.1, 17
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Resultado correto"
.size .L.str.2, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15soma_matriz_GPUiiPiS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__soma_matriz_GPUiiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15soma_matriz_GPUiiPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
cudaMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
cudaMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
cudaMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), cudaMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
cudaFree(matrix_a_dev);
cudaFree(matrix_b_dev);
cudaFree(matrix_c_dev);
return 1;
} | code for sm_80
Function : _Z25matrixs_1D_multiplicationPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R8, 0x1, P0 ; /* 0x000000010800780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R2, R9, c[0x0][0x178], R0 ; /* 0x00005e0009027a24 */
/* 0x000fe200078e0200 */
/*0120*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc80000000f00 */
/*0130*/ IMAD.WIDE R2, R2, R11, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fce00078e020b */
/*0140*/ @!P0 BRA 0xce0 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R12, -R8, c[0x0][0x17c], RZ ; /* 0x00005f00080c7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R13, R9, c[0x0][0x17c], RZ ; /* 0x00005f00090d7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020b */
/*01b0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*01c0*/ @!P0 BRA 0xb00 ; /* 0x0000093000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7b0 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R15, c[0x0][0x178] ; /* 0x00005e00000f7a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD R21, R14, R16, R17 ; /* 0x000000100e157224 */
/* 0x024fc800078e0211 */
/*0280*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fe200078e0204 */
/*0290*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x004fc400078e0215 */
/*02d0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*02e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea4000c1e1900 */
/*0310*/ IMAD R25, R4, R5, R23 ; /* 0x0000000504197224 */
/* 0x004fc400078e0217 */
/*0320*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0330*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000e22000c1e1900 */
/*0360*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc800078e0204 */
/*0370*/ IMAD R21, R14, R20, R25 ; /* 0x000000140e157224 */
/* 0x001fca00078e0219 */
/*0380*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*03a0*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*03b0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*03c0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*03d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*0410*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0420*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0440*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000e24000c1e1900 */
/*0450*/ IMAD R21, R14, R16, R25 ; /* 0x000000100e157224 */
/* 0x001fc400078e0219 */
/*0460*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0470*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0490*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0406127981 */
/* 0x000e64000c1e1900 */
/*04a0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*04b0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*04c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*0500*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0520*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0530*/ LDG.E R16, [R6.64+0x24] ; /* 0x0000240406107981 */
/* 0x000e24000c1e1900 */
/*0540*/ IMAD R21, R14, R16, R25 ; /* 0x000000100e157224 */
/* 0x001fc400078e0219 */
/*0550*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0560*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0570*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0580*/ LDG.E R18, [R6.64+0x28] ; /* 0x0000280406127981 */
/* 0x000e64000c1e1900 */
/*0590*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*05a0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*05b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*05c0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*05f0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0600*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x000ea4000c1e1900 */
/*0630*/ IMAD R27, R14, R16, R25 ; /* 0x000000100e1b7224 */
/* 0x004fc400078e0219 */
/*0640*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0650*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0660*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e28000c1e1900 */
/*0670*/ LDG.E R18, [R6.64+0x34] ; /* 0x0000340406127981 */
/* 0x000e24000c1e1900 */
/*0680*/ IMAD R23, R14, R18, R27 ; /* 0x000000120e177224 */
/* 0x001fc400078e021b */
/*0690*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*06a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*06b0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000e68000c1e1900 */
/*06c0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000e62000c1e1900 */
/*06d0*/ IMAD.WIDE R20, R15, 0x4, R18 ; /* 0x000000040f147825 */
/* 0x000fe200078e0212 */
/*06e0*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x002fca00078e0217 */
/*0700*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0710*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee2000c1e1900 */
/*0730*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe20003f24270 */
/*0740*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0750*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0760*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0770*/ IMAD R17, R4, R5, R25 ; /* 0x0000000504117224 */
/* 0x008fe400078e0219 */
/*0780*/ IMAD.WIDE R4, R15, 0x4, R20 ; /* 0x000000040f047825 */
/* 0x000fc600078e0214 */
/*0790*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e4000c101904 */
/*07a0*/ @P1 BRA 0x210 ; /* 0xfffffa6000001947 */
/* 0x000fea000383ffff */
/*07b0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*07c0*/ @!P1 BRA 0xae0 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0800*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0810*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee2000c1e1900 */
/*0820*/ MOV R15, c[0x0][0x178] ; /* 0x00005e00000f7a02 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R21, R14, R16, R17 ; /* 0x000000100e157224 */
/* 0x028fc800078e0211 */
/*0840*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x004fe200078e0204 */
/*0850*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x004fc400078e0215 */
/*0890*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*08a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*08b0*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea4000c1e1900 */
/*08d0*/ IMAD R25, R4, R5, R23 ; /* 0x0000000504197224 */
/* 0x004fc400078e0217 */
/*08e0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*08f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0900*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0910*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000e22000c1e1900 */
/*0920*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc800078e0204 */
/*0930*/ IMAD R21, R14, R20, R25 ; /* 0x000000140e157224 */
/* 0x001fca00078e0219 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0960*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*0970*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*0980*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*09d0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*09f0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x001fc800078e0204 */
/*0a20*/ IMAD R27, R14, R16, R25 ; /* 0x000000100e1b7224 */
/* 0x004fca00078e0219 */
/*0a30*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0a40*/ LDG.E R17, [R6.64+0x1c] ; /* 0x00001c0406117981 */
/* 0x000ea8000c1e1900 */
/*0a50*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1900 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a80*/ IMAD.WIDE R4, R15, 0x4, R20 ; /* 0x000000040f047825 */
/* 0x000fe200078e0214 */
/*0a90*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0aa0*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R17, R14, R17, R27 ; /* 0x000000110e117224 */
/* 0x004fca00078e021b */
/*0ad0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0af0*/ @!P0 BRA 0xce0 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0b00*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0b10*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0b20*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b30*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0b40*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0b50*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R17, R14, R15, R17 ; /* 0x0000000f0e117224 */
/* 0x02efc800078e0211 */
/*0b70*/ IMAD.WIDE R14, R19.reuse, 0x4, R4 ; /* 0x00000004130e7825 */
/* 0x040fe200078e0204 */
/*0b80*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0b90*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R20, R19, 0x4, R14 ; /* 0x0000000413147825 */
/* 0x000fc800078e020e */
/*0bc0*/ IMAD R25, R16, R18, R17 ; /* 0x0000001210197224 */
/* 0x004fca00078e0211 */
/*0bd0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0be0*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1900 */
/*0bf0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ IMAD.WIDE R22, R19, 0x4, R20 ; /* 0x0000000413167825 */
/* 0x000fe200078e0214 */
/*0c10*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fc60007ffe0ff */
/*0c20*/ IMAD R27, R4, R5, R25 ; /* 0x00000005041b7224 */
/* 0x004fca00078e0219 */
/*0c30*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0c40*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x001ea8000c1e1900 */
/*0c50*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0c70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c80*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ca0*/ IMAD R17, R4, R17, R27 ; /* 0x0000001104117224 */
/* 0x004fe400078e021b */
/*0cb0*/ IMAD.WIDE R4, R19, 0x4, R22 ; /* 0x0000000413047825 */
/* 0x000fc600078e0216 */
/*0cc0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e4000c101904 */
/*0cd0*/ @P0 BRA 0xb00 ; /* 0xfffffe2000000947 */
/* 0x002fea000383ffff */
/*0ce0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cf0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d00*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0d10*/ IMAD R4, R9, c[0x0][0x17c], R10 ; /* 0x00005f0009047a24 */
/* 0x000fe400078e020a */
/*0d20*/ IMAD R0, R10, c[0x0][0x178], R0 ; /* 0x00005e000a007a24 */
/* 0x000fe400078e0200 */
/*0d30*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*0d40*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0d50*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0d60*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x001fc800078e020b */
/*0d70*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0d80*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010e2000c1e1900 */
/*0d90*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0da0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0db0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0dc0*/ MOV R11, c[0x0][0x178] ; /* 0x00005e00000b7a02 */
/* 0x000fe40000000f00 */
/*0dd0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0de0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0df0*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc600078e0204 */
/*0e00*/ IADD3.X R10, RZ, R10, RZ, P1, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fe20000ffe4ff */
/*0e10*/ IMAD R13, R0, R6, R13 ; /* 0x00000006000d7224 */
/* 0x028fca00078e020d */
/*0e20*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0e30*/ @P0 BRA 0xd70 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0e40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e50*/ BRA 0xe50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
cudaMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
cudaMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
cudaMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), cudaMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
cudaFree(matrix_a_dev);
cudaFree(matrix_b_dev);
cudaFree(matrix_c_dev);
return 1;
} | .file "tmpxft_00151ad9_00000000-6_asyncAPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
.type _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii, @function
_Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixs_1D_multiplicationPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii, .-_Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.type _Z25matrixs_1D_multiplicationPiS_S_ii, @function
_Z25matrixs_1D_multiplicationPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25matrixs_1D_multiplicationPiS_S_ii, .-_Z25matrixs_1D_multiplicationPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n-------------Matrix a-----------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.LC2:
.string "\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\n-------------Matrix c-----------------\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %r14
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
movl $5, %ecx
movl $0, %esi
.L12:
movl %esi, %eax
movq %rdi, %rdx
.L13:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L13
addl $1, %esi
addq $20, %rdi
addl $1, %ecx
cmpl $4, %esi
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L16
.L15:
addq $1, %rbx
cmpq $20, %rbx
je .L29
.L16:
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L15
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L29:
movq %r14, %rcx
movl $0, %edi
jmp .L17
.L30:
addl $1, %edi
addq $16, %rcx
cmpl $5, %edi
je .L19
.L17:
movl %edi, %esi
movl $0, %eax
.L18:
leal (%rsi,%rax), %edx
movl %edx, (%rcx,%rax,4)
addq $1, %rax
cmpq $4, %rax
jne .L18
jmp .L30
.L19:
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $4, 44(%rsp)
movl $5, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L22
.L31:
movl $5, %r8d
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
jmp .L20
.L21:
addq $1, %rbx
cmpq $16, %rbx
je .L32
.L22:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
jne .L21
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L32:
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $1, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z25matrixs_1D_multiplicationPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixs_1D_multiplicationPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
cudaMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
cudaMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
cudaMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), cudaMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
cudaMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), cudaMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
cudaFree(matrix_a_dev);
cudaFree(matrix_b_dev);
cudaFree(matrix_c_dev);
return 1;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
hipMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
hipMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
hipMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), hipMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
hipFree(matrix_a_dev);
hipFree(matrix_b_dev);
hipFree(matrix_c_dev);
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
hipMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
hipMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
hipMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), hipMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
hipFree(matrix_a_dev);
hipFree(matrix_b_dev);
hipFree(matrix_c_dev);
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25matrixs_1D_multiplicationPiS_S_ii
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.p2align 8
.type _Z25matrixs_1D_multiplicationPiS_S_ii,@function
_Z25matrixs_1D_multiplicationPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_gt_i32 s5, 0
s_cselect_b32 s2, -1, 0
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mul_lo_u32 v4, v1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25matrixs_1D_multiplicationPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25matrixs_1D_multiplicationPiS_S_ii, .Lfunc_end0-_Z25matrixs_1D_multiplicationPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25matrixs_1D_multiplicationPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25matrixs_1D_multiplicationPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matrixs_1D_multiplication(int *matrix_a_dev,int *matrix_b_dev,int *matrix_c_dev,int row,int col)//记住这里的row和col直接对应global里面的数值，不能有误
{
int j = threadIdx.x+blockIdx.x * blockDim.x;
int i = threadIdx.y+blockIdx.y * blockDim.y;
if(i< row &&j < row)
{
for(int k = 0; k < col; k++)
{
matrix_c_dev[row *i + j] += matrix_a_dev[i* col + k] * matrix_b_dev[row*k + j];
}
}
}
int main()
{
int row = 4;
int col = 5;
int *matrix_a_host;
int *matrix_b_host;
int *matrix_c_host;
matrix_a_host = (int *)malloc(row*col*sizeof(int));
matrix_b_host = (int *)malloc(row*col*sizeof(int));
matrix_c_host = (int *)malloc(row*row*sizeof(int));
for(int i = 0; i<row; i++)
{
for(int j = 0; j < col; j++)
{
matrix_a_host[i*col +j] = i+j;
}
}
printf("\n-------------Matrix a-----------------\n");
for(int i = 0; i < row*col; i++)
{
printf("%d ",*(matrix_a_host + i));
if(i%col==col-1) printf("\n");//每输出3个换行。
}
for(int i = 0; i<col; i++)
{
for(int j = 0; j < row; j++)
{
matrix_b_host[i*row +j] = i+j;
}
}
// ------------------GPU--------------------------
int *matrix_a_dev;
int *matrix_b_dev;
int *matrix_c_dev;
hipMalloc((void**) &matrix_a_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_b_dev, row*col*sizeof(int));
hipMalloc((void**) &matrix_c_dev, row*row*sizeof(int));
hipMemcpy(matrix_a_dev, matrix_a_host, row*col*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(matrix_b_dev, matrix_b_host, row*col*sizeof(int), hipMemcpyHostToDevice);
dim3 dimGrid(1, 2, 1);
dim3 dimBlock(4, 5, 1);//记住这里的row和col直接对应global里面的数值，不能有误
matrixs_1D_multiplication<<<dimGrid, dimBlock>>>(matrix_a_dev, matrix_b_dev, matrix_c_dev, row,col);
hipMemcpy(matrix_c_host, matrix_c_dev, row*row*sizeof(int), hipMemcpyDeviceToHost);
printf("\n-------------Matrix c-----------------\n");
for(int i = 0; i < row*row; i++)
{
printf("%d ",*(matrix_c_host + i));
if(i%row==row-1) printf("\n");//每输出4个换行。
}
free(matrix_a_host);
free(matrix_b_host);
free(matrix_c_host);
hipFree(matrix_a_dev);
hipFree(matrix_b_dev);
hipFree(matrix_c_dev);
return 1;
} | .text
.file "asyncAPI.hip"
.globl _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii # -- Begin function _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.p2align 4, 0x90
.type _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii,@function
_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii: # @_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii, .Lfunc_end0-_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB1_1: # %.preheader84
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
movl %esi, (%rcx,%rdx,4)
incq %rdx
cmpq $5, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $20, %rcx
cmpq $4, %rax
jne .LBB1_1
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $20, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r12, %rax
mulq %r13
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl %r12d, %ebp
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8: # %.preheader.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
movl %esi, (%rcx,%rdx,4)
incq %rdx
cmpq $4, %rdx
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
incq %rax
addq $16, %rcx
cmpq $5, %rax
jne .LBB1_9
# %bb.12:
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $21474836484, %rdx # imm = 0x500000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_15 Depth=1
incq %r12
cmpq $16, %r12
je .LBB1_18
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl %r12d, %eax
notl %eax
testb $3, %al
jne .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_17
.LBB1_18:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25matrixs_1D_multiplicationPiS_S_ii,@object # @_Z25matrixs_1D_multiplicationPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.p2align 3, 0x0
_Z25matrixs_1D_multiplicationPiS_S_ii:
.quad _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.size _Z25matrixs_1D_multiplicationPiS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25matrixs_1D_multiplicationPiS_S_ii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n-------------Matrix a-----------------"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n-------------Matrix c-----------------"
.size .Lstr.1, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25matrixs_1D_multiplicationPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25matrixs_1D_multiplicationPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R9, R9, c[0x0][0x4], R2 ; /* 0x0000010009097a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R8, 0x1, P0 ; /* 0x000000010800780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R2, R9, c[0x0][0x178], R0 ; /* 0x00005e0009027a24 */
/* 0x000fe200078e0200 */
/*0120*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc80000000f00 */
/*0130*/ IMAD.WIDE R2, R2, R11, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fce00078e020b */
/*0140*/ @!P0 BRA 0xce0 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R12, -R8, c[0x0][0x17c], RZ ; /* 0x00005f00080c7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ LDG.E R17, [R2.64] ; /* 0x0000000402117981 */
/* 0x000162000c1e1900 */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R13, R9, c[0x0][0x17c], RZ ; /* 0x00005f00090d7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe200078e020b */
/*01b0*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*01c0*/ @!P0 BRA 0xb00 ; /* 0x0000093000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7b0 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R15, c[0x0][0x178] ; /* 0x00005e00000f7a02 */
/* 0x000fe20000000f00 */
/*0270*/ IMAD R21, R14, R16, R17 ; /* 0x000000100e157224 */
/* 0x024fc800078e0211 */
/*0280*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fe200078e0204 */
/*0290*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*02a0*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x004fc400078e0215 */
/*02d0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*02e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea4000c1e1900 */
/*0310*/ IMAD R25, R4, R5, R23 ; /* 0x0000000504197224 */
/* 0x004fc400078e0217 */
/*0320*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0330*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000e22000c1e1900 */
/*0360*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc800078e0204 */
/*0370*/ IMAD R21, R14, R20, R25 ; /* 0x000000140e157224 */
/* 0x001fca00078e0219 */
/*0380*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0390*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*03a0*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*03b0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*03c0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*03d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*03e0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*0410*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0420*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0440*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000e24000c1e1900 */
/*0450*/ IMAD R21, R14, R16, R25 ; /* 0x000000100e157224 */
/* 0x001fc400078e0219 */
/*0460*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0470*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0480*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0490*/ LDG.E R18, [R6.64+0x1c] ; /* 0x00001c0406127981 */
/* 0x000e64000c1e1900 */
/*04a0*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*04b0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*04c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*04e0*/ LDG.E R4, [R6.64+0x20] ; /* 0x0000200406047981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*0500*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0510*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0520*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0530*/ LDG.E R16, [R6.64+0x24] ; /* 0x0000240406107981 */
/* 0x000e24000c1e1900 */
/*0540*/ IMAD R21, R14, R16, R25 ; /* 0x000000100e157224 */
/* 0x001fc400078e0219 */
/*0550*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0560*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0570*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0580*/ LDG.E R18, [R6.64+0x28] ; /* 0x0000280406127981 */
/* 0x000e64000c1e1900 */
/*0590*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*05a0*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*05b0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*05c0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R4, [R6.64+0x2c] ; /* 0x00002c0406047981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*05f0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*0600*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0610*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0620*/ LDG.E R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x000ea4000c1e1900 */
/*0630*/ IMAD R27, R14, R16, R25 ; /* 0x000000100e1b7224 */
/* 0x004fc400078e0219 */
/*0640*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc600078e0204 */
/*0650*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0005e8000c101904 */
/*0660*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e28000c1e1900 */
/*0670*/ LDG.E R18, [R6.64+0x34] ; /* 0x0000340406127981 */
/* 0x000e24000c1e1900 */
/*0680*/ IMAD R23, R14, R18, R27 ; /* 0x000000120e177224 */
/* 0x001fc400078e021b */
/*0690*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*06a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*06b0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000e68000c1e1900 */
/*06c0*/ LDG.E R4, [R6.64+0x38] ; /* 0x0000380406047981 */
/* 0x000e62000c1e1900 */
/*06d0*/ IMAD.WIDE R20, R15, 0x4, R18 ; /* 0x000000040f147825 */
/* 0x000fe200078e0212 */
/*06e0*/ IADD3 R12, R12, -0x10, RZ ; /* 0xfffffff00c0c7810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x002fca00078e0217 */
/*0700*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0710*/ LDG.E R5, [R6.64+0x3c] ; /* 0x00003c0406057981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ee2000c1e1900 */
/*0730*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fe20003f24270 */
/*0740*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0750*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0760*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0770*/ IMAD R17, R4, R5, R25 ; /* 0x0000000504117224 */
/* 0x008fe400078e0219 */
/*0780*/ IMAD.WIDE R4, R15, 0x4, R20 ; /* 0x000000040f047825 */
/* 0x000fc600078e0214 */
/*0790*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0005e4000c101904 */
/*07a0*/ @P1 BRA 0x210 ; /* 0xfffffa6000001947 */
/* 0x000fea000383ffff */
/*07b0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*07c0*/ @!P1 BRA 0xae0 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07e0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*07f0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0800*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0810*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee2000c1e1900 */
/*0820*/ MOV R15, c[0x0][0x178] ; /* 0x00005e00000f7a02 */
/* 0x000fe20000000f00 */
/*0830*/ IMAD R21, R14, R16, R17 ; /* 0x000000100e157224 */
/* 0x028fc800078e0211 */
/*0840*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x004fe200078e0204 */
/*0850*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*0870*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x004fc400078e0215 */
/*0890*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*08a0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*08b0*/ LDG.E R4, [R18.64] ; /* 0x0000000412047981 */
/* 0x000ea8000c1e1900 */
/*08c0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea4000c1e1900 */
/*08d0*/ IMAD R25, R4, R5, R23 ; /* 0x0000000504197224 */
/* 0x004fc400078e0217 */
/*08e0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*08f0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0900*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000e28000c1e1900 */
/*0910*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000e22000c1e1900 */
/*0920*/ IMAD.WIDE R16, R15, 0x4, R4 ; /* 0x000000040f107825 */
/* 0x000fc800078e0204 */
/*0930*/ IMAD R21, R14, R20, R25 ; /* 0x000000140e157224 */
/* 0x001fca00078e0219 */
/*0940*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000e68000c1e1900 */
/*0960*/ LDG.E R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000e64000c1e1900 */
/*0970*/ IMAD R23, R14, R18, R21 ; /* 0x000000120e177224 */
/* 0x002fc400078e0215 */
/*0980*/ IMAD.WIDE R18, R15, 0x4, R16 ; /* 0x000000040f127825 */
/* 0x000fc600078e0210 */
/*0990*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09a0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R4, [R6.64+0x14] ; /* 0x0000140406047981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ IMAD R25, R14, R4, R23 ; /* 0x000000040e197224 */
/* 0x004fc400078e0217 */
/*09d0*/ IMAD.WIDE R4, R15, 0x4, R18 ; /* 0x000000040f047825 */
/* 0x000fc600078e0212 */
/*09e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*09f0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0a00*/ LDG.E R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000ea2000c1e1900 */
/*0a10*/ IMAD.WIDE R20, R15, 0x4, R4 ; /* 0x000000040f147825 */
/* 0x001fc800078e0204 */
/*0a20*/ IMAD R27, R14, R16, R25 ; /* 0x000000100e1b7224 */
/* 0x004fca00078e0219 */
/*0a30*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0a40*/ LDG.E R17, [R6.64+0x1c] ; /* 0x00001c0406117981 */
/* 0x000ea8000c1e1900 */
/*0a50*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1900 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a80*/ IMAD.WIDE R4, R15, 0x4, R20 ; /* 0x000000040f047825 */
/* 0x000fe200078e0214 */
/*0a90*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0aa0*/ IADD3 R12, R12, -0x8, RZ ; /* 0xfffffff80c0c7810 */
/* 0x000fe20007ffe0ff */
/*0ab0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ac0*/ IMAD R17, R14, R17, R27 ; /* 0x000000110e117224 */
/* 0x004fca00078e021b */
/*0ad0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ ISETP.NE.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fda0000705670 */
/*0af0*/ @!P0 BRA 0xce0 ; /* 0x000001e000008947 */
/* 0x000fea0003800000 */
/*0b00*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0b10*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1900 */
/*0b20*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b30*/ IMAD.WIDE R6, R13, 0x4, R6 ; /* 0x000000040d067825 */
/* 0x000fca00078e0206 */
/*0b40*/ LDG.E R15, [R6.64] ; /* 0x00000004060f7981 */
/* 0x000ee2000c1e1900 */
/*0b50*/ MOV R19, c[0x0][0x178] ; /* 0x00005e0000137a02 */
/* 0x000fe20000000f00 */
/*0b60*/ IMAD R17, R14, R15, R17 ; /* 0x0000000f0e117224 */
/* 0x02efc800078e0211 */
/*0b70*/ IMAD.WIDE R14, R19.reuse, 0x4, R4 ; /* 0x00000004130e7825 */
/* 0x040fe200078e0204 */
/*0b80*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0001e8000c101904 */
/*0b90*/ LDG.E R18, [R6.64+0x4] ; /* 0x0000040406127981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R20, R19, 0x4, R14 ; /* 0x0000000413147825 */
/* 0x000fc800078e020e */
/*0bc0*/ IMAD R25, R16, R18, R17 ; /* 0x0000001210197224 */
/* 0x004fca00078e0211 */
/*0bd0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0be0*/ LDG.E R4, [R20.64] ; /* 0x0000000414047981 */
/* 0x000ea8000c1e1900 */
/*0bf0*/ LDG.E R5, [R6.64+0x8] ; /* 0x0000080406057981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ IMAD.WIDE R22, R19, 0x4, R20 ; /* 0x0000000413167825 */
/* 0x000fe200078e0214 */
/*0c10*/ IADD3 R12, R12, -0x4, RZ ; /* 0xfffffffc0c0c7810 */
/* 0x000fc60007ffe0ff */
/*0c20*/ IMAD R27, R4, R5, R25 ; /* 0x00000005041b7224 */
/* 0x004fca00078e0219 */
/*0c30*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x0003e8000c101904 */
/*0c40*/ LDG.E R17, [R6.64+0xc] ; /* 0x00000c0406117981 */
/* 0x001ea8000c1e1900 */
/*0c50*/ LDG.E R4, [R22.64] ; /* 0x0000000416047981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05270 */
/*0c70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c80*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ca0*/ IMAD R17, R4, R17, R27 ; /* 0x0000001104117224 */
/* 0x004fe400078e021b */
/*0cb0*/ IMAD.WIDE R4, R19, 0x4, R22 ; /* 0x0000000413047825 */
/* 0x000fc600078e0216 */
/*0cc0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0003e4000c101904 */
/*0cd0*/ @P0 BRA 0xb00 ; /* 0xfffffe2000000947 */
/* 0x002fea000383ffff */
/*0ce0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cf0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d00*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0d10*/ IMAD R4, R9, c[0x0][0x17c], R10 ; /* 0x00005f0009047a24 */
/* 0x000fe400078e020a */
/*0d20*/ IMAD R0, R10, c[0x0][0x178], R0 ; /* 0x00005e000a007a24 */
/* 0x000fe400078e0200 */
/*0d30*/ IMAD.WIDE R4, R4, R11, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e020b */
/*0d40*/ MOV R9, R4 ; /* 0x0000000400097202 */
/* 0x000fe40000000f00 */
/*0d50*/ MOV R10, R5 ; /* 0x00000005000a7202 */
/* 0x000fe20000000f00 */
/*0d60*/ IMAD.WIDE R4, R0, R11, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x001fc800078e020b */
/*0d70*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fe20000000f00 */
/*0d80*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010e2000c1e1900 */
/*0d90*/ MOV R7, R10 ; /* 0x0000000a00077202 */
/* 0x000fca0000000f00 */
/*0da0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1900 */
/*0db0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0dc0*/ MOV R11, c[0x0][0x178] ; /* 0x00005e00000b7a02 */
/* 0x000fe40000000f00 */
/*0dd0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0de0*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007f3e0ff */
/*0df0*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fc600078e0204 */
/*0e00*/ IADD3.X R10, RZ, R10, RZ, P1, !PT ; /* 0x0000000aff0a7210 */
/* 0x000fe20000ffe4ff */
/*0e10*/ IMAD R13, R0, R6, R13 ; /* 0x00000006000d7224 */
/* 0x028fca00078e020d */
/*0e20*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0e30*/ @P0 BRA 0xd70 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0e40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e50*/ BRA 0xe50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25matrixs_1D_multiplicationPiS_S_ii
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.p2align 8
.type _Z25matrixs_1D_multiplicationPiS_S_ii,@function
_Z25matrixs_1D_multiplicationPiS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_cmp_gt_i32 s5, 0
s_cselect_b32 s2, -1, 0
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mul_lo_u32 v4, v1, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25matrixs_1D_multiplicationPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25matrixs_1D_multiplicationPiS_S_ii, .Lfunc_end0-_Z25matrixs_1D_multiplicationPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25matrixs_1D_multiplicationPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25matrixs_1D_multiplicationPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00151ad9_00000000-6_asyncAPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
.type _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii, @function
_Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25matrixs_1D_multiplicationPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii, .-_Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.type _Z25matrixs_1D_multiplicationPiS_S_ii, @function
_Z25matrixs_1D_multiplicationPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z25matrixs_1D_multiplicationPiS_S_ii, .-_Z25matrixs_1D_multiplicationPiS_S_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\n-------------Matrix a-----------------\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%d "
.LC2:
.string "\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\n-------------Matrix c-----------------\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $80, %edi
call malloc@PLT
movq %rax, %rbp
movl $80, %edi
call malloc@PLT
movq %rax, %r14
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
movl $5, %ecx
movl $0, %esi
.L12:
movl %esi, %eax
movq %rdi, %rdx
.L13:
movl %eax, (%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L13
addl $1, %esi
addq $20, %rdi
addl $1, %ecx
cmpl $4, %esi
jne .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L16
.L15:
addq $1, %rbx
cmpq $20, %rbx
je .L29
.L16:
movl 0(%rbp,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L15
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L29:
movq %r14, %rcx
movl $0, %edi
jmp .L17
.L30:
addl $1, %edi
addq $16, %rcx
cmpl $5, %edi
je .L19
.L17:
movl %edi, %esi
movl $0, %eax
.L18:
leal (%rsi,%rax), %edx
movl %edx, (%rcx,%rax,4)
addq $1, %rax
cmpq $4, %rax
jne .L18
jmp .L30
.L19:
leaq 8(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $80, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $80, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $80, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $4, 44(%rsp)
movl $5, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L20:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r15
jmp .L22
.L31:
movl $5, %r8d
movl $4, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z51__device_stub__Z25matrixs_1D_multiplicationPiS_S_iiPiS_S_ii
jmp .L20
.L21:
addq $1, %rbx
cmpq $16, %rbx
je .L32
.L22:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
sarl $31, %edx
shrl $30, %edx
leal (%rdx,%rbx), %eax
andl $3, %eax
subl %edx, %eax
cmpl $3, %eax
jne .L21
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L21
.L32:
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $1, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z25matrixs_1D_multiplicationPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z25matrixs_1D_multiplicationPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "asyncAPI.hip"
.globl _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii # -- Begin function _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.p2align 4, 0x90
.type _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii,@function
_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii: # @_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii, .Lfunc_end0-_Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $80, %edi
callq malloc
movq %rax, %rbx
movl $80, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB1_1: # %.preheader84
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
movl %esi, (%rcx,%rdx,4)
incq %rdx
cmpq $5, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $20, %rcx
cmpq $4, %rax
jne .LBB1_1
# %bb.4:
movl $.Lstr, %edi
callq puts@PLT
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
xorl %r12d, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $20, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %r12, %rax
mulq %r13
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movl (%rbx,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
cmpl %r12d, %ebp
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8: # %.preheader.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rdx), %esi
movl %esi, (%rcx,%rdx,4)
incq %rdx
cmpq $4, %rdx
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=1
incq %rax
addq $16, %rcx
cmpq $5, %rax
jne .LBB1_9
# %bb.12:
leaq 24(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $80, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $80, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $80, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
movabsq $21474836484, %rdx # imm = 0x500000004
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4, 36(%rsp)
movl $5, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_14:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_15 Depth=1
incq %r12
cmpq $16, %r12
je .LBB1_18
.LBB1_15: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl %r12d, %eax
notl %eax
testb $3, %al
jne .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_17
.LBB1_18:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25matrixs_1D_multiplicationPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25matrixs_1D_multiplicationPiS_S_ii,@object # @_Z25matrixs_1D_multiplicationPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z25matrixs_1D_multiplicationPiS_S_ii
.p2align 3, 0x0
_Z25matrixs_1D_multiplicationPiS_S_ii:
.quad _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.size _Z25matrixs_1D_multiplicationPiS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z25matrixs_1D_multiplicationPiS_S_ii"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n-------------Matrix a-----------------"
.size .Lstr, 40
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n-------------Matrix c-----------------"
.size .Lstr.1, 40
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__matrixs_1D_multiplicationPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25matrixs_1D_multiplicationPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z8sumOnGpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00010994_00000000-6_VectSumClassExample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8sumOnCpuPiS_S_i
.type _Z8sumOnCpuPiS_S_i, @function
_Z8sumOnCpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z8sumOnCpuPiS_S_i, .-_Z8sumOnCpuPiS_S_i
.globl _Z13randomNumbersPii
.type _Z13randomNumbersPii, @function
_Z13randomNumbersPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z13randomNumbersPii, .-_Z13randomNumbersPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Different values at a[%i] = %i and b[%i] = %i \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "args are the same \n"
.LC2:
.string "args are different \n"
.text
.globl _Z7comparePiS_i
.type _Z7comparePiS_i, @function
_Z7comparePiS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %edx, %edx
jle .L16
movq %rdi, %r12
movq %rsi, %r13
movslq %edx, %rbp
movl $0, %ebx
movl $1, %r14d
leaq .LC0(%rip), %r15
jmp .L18
.L17:
addq $1, %rbx
cmpq %rbx, %rbp
je .L23
.L18:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %ecx
je .L17
movl %ebx, %edx
movl %ebx, %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
jmp .L17
.L23:
testl %r14d, %r14d
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r14d
.L15:
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7comparePiS_i, .-_Z7comparePiS_i
.globl _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sumOnGpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
.globl _Z8sumOnGpuPiS_S_i
.type _Z8sumOnGpuPiS_S_i, @function
_Z8sumOnGpuPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8sumOnGpuPiS_S_i, .-_Z8sumOnGpuPiS_S_i
.section .rodata.str1.1
.LC4:
.string "time on GPU %f \n"
.LC5:
.string "time on CPU %f \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $16777216, %esi
movq %rbp, %rdi
call _Z13randomNumbersPii
movl $16777216, %esi
movq %rbx, %rdi
call _Z13randomNumbersPii
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $32768, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r12, %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
call clock@PLT
movq %rax, %r14
movl $16777216, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z8sumOnCpuPiS_S_i
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r14, %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $16777216, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z7comparePiS_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $16777216, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8sumOnGpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sumOnGpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
cudaMalloc((void**)&d_a, size);
cudaMalloc((void**)&d_b, size);
cudaMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sumOnGpuPiS_S_i
.globl _Z8sumOnGpuPiS_S_i
.p2align 8
.type _Z8sumOnGpuPiS_S_i,@function
_Z8sumOnGpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sumOnGpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sumOnGpuPiS_S_i, .Lfunc_end0-_Z8sumOnGpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sumOnGpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sumOnGpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define N (4096*4096)
#define THREADS_PER_BLOCK 512
__global__ void sumOnGpu(int *a, int *b, int *c, int n){
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n){
c[index] = a[index] + b[index];
}
}
void sumOnCpu(int *a, int *b, int *c, int n){
for(int i = 0; i < n; i++){
c[i] = a[i] + b[i];
}
}
void randomNumbers(int *a, int n){
for(int i = 0; i < n; i++){
a[i] = rand()%100000;
}
}
int compare(int *a, int *b, int n){
int pass = 1;
for(int i = 0; i < n; i++){
if(a[i] != b[i]){
printf("Different values at a[%i] = %i and b[%i] = %i \n", i, a[i], i, b[i]);
pass = 0;
}
}
if (pass)
printf("args are the same \n");
else
printf("args are different \n");
return pass;
}
int main(){
int *a, *b, *c;
int *d_a, *d_b, *d_c;
int size = N * sizeof(int);
a = (int*)malloc(size);
b = (int*)malloc(size);
c = (int*)malloc(size);
hipMalloc((void**)&d_a, size);
hipMalloc((void**)&d_b, size);
hipMalloc((void**)&d_c, size);
randomNumbers(a, N);
randomNumbers(b, N);
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
clock_t timeOnGpu = clock();
sumOnGpu<<<N/THREADS_PER_BLOCK, THREADS_PER_BLOCK>>>(d_a, d_b, d_c, N);
printf("time on GPU %f \n", ((double)clock() - timeOnGpu)/CLOCKS_PER_SEC);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
int* c_h;
c_h = (int*)malloc(size);
clock_t i = clock();
sumOnCpu(a, b, c_h, N);
printf("time on CPU %f \n", ((double)clock() - i)/CLOCKS_PER_SEC);
compare(c, c_h, N);
free(a);
free(b);
free(c);
free(c_h);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "VectSumClassExample.hip"
.globl _Z23__device_stub__sumOnGpuPiS_S_i # -- Begin function _Z23__device_stub__sumOnGpuPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__sumOnGpuPiS_S_i,@function
_Z23__device_stub__sumOnGpuPiS_S_i: # @_Z23__device_stub__sumOnGpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sumOnGpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__sumOnGpuPiS_S_i, .Lfunc_end0-_Z23__device_stub__sumOnGpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z8sumOnCpuPiS_S_i # -- Begin function _Z8sumOnCpuPiS_S_i
.p2align 4, 0x90
.type _Z8sumOnCpuPiS_S_i,@function
_Z8sumOnCpuPiS_S_i: # @_Z8sumOnCpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8sumOnCpuPiS_S_i, .Lfunc_end1-_Z8sumOnCpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13randomNumbersPii # -- Begin function _Z13randomNumbersPii
.p2align 4, 0x90
.type _Z13randomNumbersPii,@function
_Z13randomNumbersPii: # @_Z13randomNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13randomNumbersPii, .Lfunc_end2-_Z13randomNumbersPii
.cfi_endproc
# -- End function
.globl _Z7comparePiS_i # -- Begin function _Z7comparePiS_i
.p2align 4, 0x90
.type _Z7comparePiS_i,@function
_Z7comparePiS_i: # @_Z7comparePiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %r13d
movl $1, %ebx
xorl %r12d, %r12d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=1
incq %r12
cmpq %r12, %r13
je .LBB3_2
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl (%r14,%r12,4), %r8d
cmpl %r8d, %edx
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r12d, %esi
movl %r12d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB3_6
.LBB3_1:
movl $1, %ebx
.LBB3_2: # %._crit_edge
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7comparePiS_i, .Lfunc_end3-_Z7comparePiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB4_1
# %bb.2: # %.lr.ph.i27.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB4_3
# %bb.4: # %_Z13randomNumbersPii.exit31
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 32256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16777216, 36(%rsp) # imm = 0x1000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8sumOnGpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq clock
cvtsi2sd %rax, %xmm0
cvtsi2sd %r12, %xmm1
subsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i32
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %eax
addl (%rbx,%rbp,4), %eax
movl %eax, (%r12,%rbp,4)
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
jne .LBB4_7
# %bb.8: # %_Z8sumOnCpuPiS_S_i.exit
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
subsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $1, %ebp
xorl %r13d, %r13d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
incq %r13
cmpq $16777216, %r13 # imm = 0x1000000
je .LBB4_12
.LBB4_9: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %edx
movl (%r12,%r13,4), %r8d
cmpl %r8d, %edx
je .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
xorl %ebp, %ebp
movl $.L.str, %edi
movl %r13d, %esi
movl %r13d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB4_11
.LBB4_12: # %._crit_edge.i
testl %ebp, %ebp
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sumOnGpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sumOnGpuPiS_S_i,@object # @_Z8sumOnGpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8sumOnGpuPiS_S_i
.p2align 3, 0x0
_Z8sumOnGpuPiS_S_i:
.quad _Z23__device_stub__sumOnGpuPiS_S_i
.size _Z8sumOnGpuPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Different values at a[%i] = %i and b[%i] = %i \n"
.size .L.str, 48
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time on GPU %f \n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time on CPU %f \n"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sumOnGpuPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "args are different "
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "args are the same "
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sumOnGpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sumOnGpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8sumOnGpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8sumOnGpuPiS_S_i
.globl _Z8sumOnGpuPiS_S_i
.p2align 8
.type _Z8sumOnGpuPiS_S_i,@function
_Z8sumOnGpuPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8sumOnGpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8sumOnGpuPiS_S_i, .Lfunc_end0-_Z8sumOnGpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8sumOnGpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8sumOnGpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00010994_00000000-6_VectSumClassExample.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8sumOnCpuPiS_S_i
.type _Z8sumOnCpuPiS_S_i, @function
_Z8sumOnCpuPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z8sumOnCpuPiS_S_i, .-_Z8sumOnCpuPiS_S_i
.globl _Z13randomNumbersPii
.type _Z13randomNumbersPii, @function
_Z13randomNumbersPii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L12
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $351843721, %rdx, %rdx
sarq $45, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100000, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2058:
.size _Z13randomNumbersPii, .-_Z13randomNumbersPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Different values at a[%i] = %i and b[%i] = %i \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "args are the same \n"
.LC2:
.string "args are different \n"
.text
.globl _Z7comparePiS_i
.type _Z7comparePiS_i, @function
_Z7comparePiS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %edx, %edx
jle .L16
movq %rdi, %r12
movq %rsi, %r13
movslq %edx, %rbp
movl $0, %ebx
movl $1, %r14d
leaq .LC0(%rip), %r15
jmp .L18
.L17:
addq $1, %rbx
cmpq %rbx, %rbp
je .L23
.L18:
movl (%r12,%rbx,4), %ecx
movl 0(%r13,%rbx,4), %r9d
cmpl %r9d, %ecx
je .L17
movl %ebx, %edx
movl %ebx, %r8d
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
jmp .L17
.L23:
testl %r14d, %r14d
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L16:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r14d
.L15:
movl %r14d, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7comparePiS_i, .-_Z7comparePiS_i
.globl _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8sumOnGpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
.globl _Z8sumOnGpuPiS_S_i
.type _Z8sumOnGpuPiS_S_i, @function
_Z8sumOnGpuPiS_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z8sumOnGpuPiS_S_i, .-_Z8sumOnGpuPiS_S_i
.section .rodata.str1.1
.LC4:
.string "time on GPU %f \n"
.LC5:
.string "time on CPU %f \n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbx
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $16777216, %esi
movq %rbp, %rdi
call _Z13randomNumbersPii
movl $16777216, %esi
movq %rbx, %rdi
call _Z13randomNumbersPii
movl $1, %ecx
movl $67108864, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $32768, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L33:
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r12, %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $67108864, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
call clock@PLT
movq %rax, %r14
movl $16777216, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z8sumOnCpuPiS_S_i
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %r14, %xmm1
subsd %xmm1, %xmm0
divsd .LC3(%rip), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $16777216, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z7comparePiS_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $16777216, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8sumOnGpuPiS_S_iPiS_S_i
jmp .L33
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8sumOnGpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8sumOnGpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectSumClassExample.hip"
.globl _Z23__device_stub__sumOnGpuPiS_S_i # -- Begin function _Z23__device_stub__sumOnGpuPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__sumOnGpuPiS_S_i,@function
_Z23__device_stub__sumOnGpuPiS_S_i: # @_Z23__device_stub__sumOnGpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8sumOnGpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__sumOnGpuPiS_S_i, .Lfunc_end0-_Z23__device_stub__sumOnGpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z8sumOnCpuPiS_S_i # -- Begin function _Z8sumOnCpuPiS_S_i
.p2align 4, 0x90
.type _Z8sumOnCpuPiS_S_i,@function
_Z8sumOnCpuPiS_S_i: # @_Z8sumOnCpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8sumOnCpuPiS_S_i, .Lfunc_end1-_Z8sumOnCpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13randomNumbersPii # -- Begin function _Z13randomNumbersPii
.p2align 4, 0x90
.type _Z13randomNumbersPii,@function
_Z13randomNumbersPii: # @_Z13randomNumbersPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13randomNumbersPii, .Lfunc_end2-_Z13randomNumbersPii
.cfi_endproc
# -- End function
.globl _Z7comparePiS_i # -- Begin function _Z7comparePiS_i
.p2align 4, 0x90
.type _Z7comparePiS_i,@function
_Z7comparePiS_i: # @_Z7comparePiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movq %rsi, %r14
movq %rdi, %r15
movl %edx, %r13d
movl $1, %ebx
xorl %r12d, %r12d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=1
incq %r12
cmpq %r12, %r13
je .LBB3_2
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl (%r14,%r12,4), %r8d
cmpl %r8d, %edx
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
movl %r12d, %esi
movl %r12d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB3_6
.LBB3_1:
movl $1, %ebx
.LBB3_2: # %._crit_edge
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7comparePiS_i, .Lfunc_end3-_Z7comparePiS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB4_1
# %bb.2: # %.lr.ph.i27.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_3: # %.lr.ph.i27
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $351843721, %rax, %rcx # imm = 0x14F8B589
movq %rcx, %rdx
shrq $63, %rdx
sarq $45, %rcx
addl %edx, %ecx
imull $100000, %ecx, %ecx # imm = 0x186A0
subl %ecx, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $16777216, %r12 # imm = 0x1000000
jne .LBB4_3
# %bb.4: # %_Z13randomNumbersPii.exit31
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r12
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 32256(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16777216, 36(%rsp) # imm = 0x1000000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8sumOnGpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
callq clock
cvtsi2sd %rax, %xmm0
cvtsi2sd %r12, %xmm1
subsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r12
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB4_7: # %.lr.ph.i32
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbp,4), %eax
addl (%rbx,%rbp,4), %eax
movl %eax, (%r12,%rbp,4)
incq %rbp
cmpq $16777216, %rbp # imm = 0x1000000
jne .LBB4_7
# %bb.8: # %_Z8sumOnCpuPiS_S_i.exit
callq clock
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r13, %xmm1
subsd %xmm1, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $1, %ebp
xorl %r13d, %r13d
jmp .LBB4_9
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_9 Depth=1
incq %r13
cmpq $16777216, %r13 # imm = 0x1000000
je .LBB4_12
.LBB4_9: # %.lr.ph.i36
# =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %edx
movl (%r12,%r13,4), %r8d
cmpl %r8d, %edx
je .LBB4_11
# %bb.10: # in Loop: Header=BB4_9 Depth=1
xorl %ebp, %ebp
movl $.L.str, %edi
movl %r13d, %esi
movl %r13d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB4_11
.LBB4_12: # %._crit_edge.i
testl %ebp, %ebp
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8sumOnGpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8sumOnGpuPiS_S_i,@object # @_Z8sumOnGpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8sumOnGpuPiS_S_i
.p2align 3, 0x0
_Z8sumOnGpuPiS_S_i:
.quad _Z23__device_stub__sumOnGpuPiS_S_i
.size _Z8sumOnGpuPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Different values at a[%i] = %i and b[%i] = %i \n"
.size .L.str, 48
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time on GPU %f \n"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "time on CPU %f \n"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8sumOnGpuPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "args are different "
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "args are the same "
.size .Lstr.1, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__sumOnGpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8sumOnGpuPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>
struct RenderSettings {
uint32_t *outputBuffer;
int width;
int height;
double zoom;
double xoffset;
double yoffset;
unsigned int iterations;
uint32_t *deviceBuffer;
};
uint32_t *deviceBuffer;
char cudaInitialized = 0;
__global__ void mandelbrotCalc(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
double y1 = rs.yoffset + 2.0 / rs.zoom;
double pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
float y1 = rs.yoffset + 2.0 / rs.zoom;
float pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
extern "C" void freeCUDA() {
if (cudaInitialized == 1) {
cudaFree(deviceBuffer);
cudaInitialized = 0;
}
}
extern "C" void initCUDA(struct RenderSettings rs) {
// allocates device buffer on first run
// destroys and re-allocates buffer if window dimensions change
static int width = 0;
static int height = 0;
if (cudaInitialized == 0) {
cudaMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
width = rs.width;
height = rs.height;
cudaInitialized = 1;
} else {
if (rs.width != width || rs.height != height) {
freeCUDA();
initCUDA(rs);
}
}
}
extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalc<<<2048, 1024>>>(rs);
cudaDeviceSynchronize();
cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
}
extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalcSP<<<2048, 1024>>>(rs);
cudaDeviceSynchronize();
cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
} | .file "tmpxft_000c3747_00000000-6_mandelcuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl freeCUDA
.type freeCUDA, @function
freeCUDA:
.LFB2070:
.cfi_startproc
endbr64
cmpb $1, cudaInitialized(%rip)
je .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq deviceBuffer(%rip), %rdi
call cudaFree@PLT
movb $0, cudaInitialized(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size freeCUDA, .-freeCUDA
.globl initCUDA
.type initCUDA, @function
initCUDA:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
cmpb $0, cudaInitialized(%rip)
je .L15
cmpl %ebx, _ZZ8initCUDAE5width(%rip)
jne .L13
cmpl %ebp, _ZZ8initCUDAE6height(%rip)
je .L10
.L13:
call freeCUDA
subq $64, %rsp
.cfi_def_cfa_offset 96
movdqu 96(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 112(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 128(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 144(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
addq $64, %rsp
.cfi_def_cfa_offset 32
.L10:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
imull %ebp, %esi
sall $2, %esi
movslq %esi, %rsi
leaq deviceBuffer(%rip), %rdi
call cudaMalloc@PLT
movl %ebx, _ZZ8initCUDAE5width(%rip)
movl %ebp, _ZZ8initCUDAE6height(%rip)
movb $1, cudaInitialized(%rip)
jmp .L10
.cfi_endproc
.LFE2071:
.size initCUDA, .-initCUDA
.globl _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
.type _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, @function
_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings:
.LFB2098:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14mandelbrotCalc14RenderSettings(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, .-_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
.globl _Z14mandelbrotCalc14RenderSettings
.type _Z14mandelbrotCalc14RenderSettings, @function
_Z14mandelbrotCalc14RenderSettings:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z14mandelbrotCalc14RenderSettings, .-_Z14mandelbrotCalc14RenderSettings
.globl mandelbrotCUDA
.type mandelbrotCUDA, @function
mandelbrotCUDA:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movdqu 192(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 208(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 224(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
movq 192(%rsp), %rbx
movq deviceBuffer(%rip), %rbp
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $2048, 72(%rsp)
movl $1, 76(%rsp)
addq $64, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
call cudaDeviceSynchronize@PLT
movl 136(%rsp), %edx
imull 140(%rsp), %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq deviceBuffer(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq %rbp, 176(%rsp)
movdqu 128(%rsp), %xmm3
movaps %xmm3, 32(%rsp)
movdqu 144(%rsp), %xmm4
movaps %xmm4, 48(%rsp)
movdqu 160(%rsp), %xmm5
movaps %xmm5, 64(%rsp)
movq %rbp, 80(%rsp)
leaq 32(%rsp), %rdi
call _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size mandelbrotCUDA, .-mandelbrotCUDA
.globl _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
.type _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, @function
_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings:
.LFB2100:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16mandelbrotCalcSP14RenderSettings(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, .-_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
.globl _Z16mandelbrotCalcSP14RenderSettings
.type _Z16mandelbrotCalcSP14RenderSettings, @function
_Z16mandelbrotCalcSP14RenderSettings:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z16mandelbrotCalcSP14RenderSettings, .-_Z16mandelbrotCalcSP14RenderSettings
.globl mandelbrotCUDAsp
.type mandelbrotCUDAsp, @function
mandelbrotCUDAsp:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movdqu 192(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 208(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 224(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
movq 192(%rsp), %rbx
movq deviceBuffer(%rip), %rbp
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $2048, 72(%rsp)
movl $1, 76(%rsp)
addq $64, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L39:
call cudaDeviceSynchronize@PLT
movl 136(%rsp), %edx
imull 140(%rsp), %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq deviceBuffer(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq %rbp, 176(%rsp)
movdqu 128(%rsp), %xmm3
movaps %xmm3, 32(%rsp)
movdqu 144(%rsp), %xmm4
movaps %xmm4, 48(%rsp)
movdqu 160(%rsp), %xmm5
movaps %xmm5, 64(%rsp)
movq %rbp, 80(%rsp)
leaq 32(%rsp), %rdi
call _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
jmp .L39
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size mandelbrotCUDAsp, .-mandelbrotCUDAsp
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16mandelbrotCalcSP14RenderSettings"
.align 8
.LC1:
.string "_Z14mandelbrotCalc14RenderSettings"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16mandelbrotCalcSP14RenderSettings(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mandelbrotCalc14RenderSettings(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8initCUDAE6height
.comm _ZZ8initCUDAE6height,4,4
.local _ZZ8initCUDAE5width
.comm _ZZ8initCUDAE5width,4,4
.globl cudaInitialized
.bss
.type cudaInitialized, @object
.size cudaInitialized, 1
cudaInitialized:
.zero 1
.globl deviceBuffer
.align 8
.type deviceBuffer, @object
.size deviceBuffer, 8
deviceBuffer:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>
struct RenderSettings {
uint32_t *outputBuffer;
int width;
int height;
double zoom;
double xoffset;
double yoffset;
unsigned int iterations;
uint32_t *deviceBuffer;
};
uint32_t *deviceBuffer;
char cudaInitialized = 0;
__global__ void mandelbrotCalc(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
double y1 = rs.yoffset + 2.0 / rs.zoom;
double pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
float y1 = rs.yoffset + 2.0 / rs.zoom;
float pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
extern "C" void freeCUDA() {
if (cudaInitialized == 1) {
cudaFree(deviceBuffer);
cudaInitialized = 0;
}
}
extern "C" void initCUDA(struct RenderSettings rs) {
// allocates device buffer on first run
// destroys and re-allocates buffer if window dimensions change
static int width = 0;
static int height = 0;
if (cudaInitialized == 0) {
cudaMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
width = rs.width;
height = rs.height;
cudaInitialized = 1;
} else {
if (rs.width != width || rs.height != height) {
freeCUDA();
initCUDA(rs);
}
}
}
extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalc<<<2048, 1024>>>(rs);
cudaDeviceSynchronize();
cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
}
extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalcSP<<<2048, 1024>>>(rs);
cudaDeviceSynchronize();
cudaMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, cudaMemcpyDeviceToHost);
} | #include <hip/hip_runtime.h>
#include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>
struct RenderSettings {
uint32_t *outputBuffer;
int width;
int height;
double zoom;
double xoffset;
double yoffset;
unsigned int iterations;
uint32_t *deviceBuffer;
};
uint32_t *deviceBuffer;
char cudaInitialized = 0;
__global__ void mandelbrotCalc(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
double y1 = rs.yoffset + 2.0 / rs.zoom;
double pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
float y1 = rs.yoffset + 2.0 / rs.zoom;
float pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
extern "C" void freeCUDA() {
if (cudaInitialized == 1) {
hipFree(deviceBuffer);
cudaInitialized = 0;
}
}
extern "C" void initCUDA(struct RenderSettings rs) {
// allocates device buffer on first run
// destroys and re-allocates buffer if window dimensions change
static int width = 0;
static int height = 0;
if (cudaInitialized == 0) {
hipMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
width = rs.width;
height = rs.height;
cudaInitialized = 1;
} else {
if (rs.width != width || rs.height != height) {
freeCUDA();
initCUDA(rs);
}
}
}
extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalc<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
}
extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalcSP<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>
struct RenderSettings {
uint32_t *outputBuffer;
int width;
int height;
double zoom;
double xoffset;
double yoffset;
unsigned int iterations;
uint32_t *deviceBuffer;
};
uint32_t *deviceBuffer;
char cudaInitialized = 0;
__global__ void mandelbrotCalc(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
double y1 = rs.yoffset + 2.0 / rs.zoom;
double pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
float y1 = rs.yoffset + 2.0 / rs.zoom;
float pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
extern "C" void freeCUDA() {
if (cudaInitialized == 1) {
hipFree(deviceBuffer);
cudaInitialized = 0;
}
}
extern "C" void initCUDA(struct RenderSettings rs) {
// allocates device buffer on first run
// destroys and re-allocates buffer if window dimensions change
static int width = 0;
static int height = 0;
if (cudaInitialized == 0) {
hipMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
width = rs.width;
height = rs.height;
cudaInitialized = 1;
} else {
if (rs.width != width || rs.height != height) {
freeCUDA();
initCUDA(rs);
}
}
}
extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalc<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
}
extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalcSP<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14mandelbrotCalc14RenderSettings
.globl _Z14mandelbrotCalc14RenderSettings
.p2align 8
.type _Z14mandelbrotCalc14RenderSettings,@function
_Z14mandelbrotCalc14RenderSettings:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s6, s0, 56
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_14
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x10
s_load_b64 s[16:17], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[12:13], s[12:13], 2.0
v_div_scale_f64 v[8:9], vcc_lo, 2.0, s[12:13], 2.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[8:9], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
v_cvt_f64_i32_e32 v[7:8], s2
v_div_fixup_f64 v[5:6], v[2:3], s[12:13], 2.0
v_cvt_f64_i32_e32 v[2:3], s3
s_clause 0x1
s_load_b32 s3, s[0:1], 0x28
s_load_b64 s[4:5], s[0:1], 0x30
s_load_b32 s6, s[6:7], 0x0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
s_cselect_b32 s1, -1, 0
s_ashr_i32 s9, s2, 31
s_mul_i32 s6, s6, s11
s_add_i32 s0, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s0, s9
v_cvt_f32_u32_e32 v0, s10
s_sub_i32 s0, 0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_rcp_iflag_f32_e32 v0, v0
v_mul_f64 v[9:10], v[5:6], v[7:8]
v_add_f64 v[5:6], v[5:6], s[16:17]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v0
v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[2:3], v[9:10]
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
v_mul_f64 v[15:16], v[17:18], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[9:10], v[11:12], v[2:3], v[9:10]
v_mul_lo_u32 v2, s0, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v0, v0, v2
v_add_f64 v[3:4], s[14:15], -v[9:10]
v_add_f64 v[9:10], s[14:15], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], -v[3:4]
v_div_scale_f64 v[11:12], null, v[7:8], v[7:8], v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_div_fixup_f64 v[7:8], v[11:12], v[7:8], v[9:10]
v_cvt_f64_u32_e32 v[9:10], s3
s_branch .LBB0_4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s0, s4, v11
v_add_co_ci_u32_e64 v12, s0, s5, v12, s0
s_or_b32 s7, vcc_lo, s7
global_store_b32 v[11:12], v19, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB0_14
.LBB0_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, v1, v2
v_xor_b32_e32 v11, v11, v2
v_xor_b32_e32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v12, v11, v0
v_mul_lo_u32 v13, v12, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v13
v_add_nc_u32_e32 v13, 1, v12
v_subrev_nc_u32_e32 v14, s10, v11
v_cmp_le_u32_e32 vcc_lo, s10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v12, v12, v13 :: v_dual_cndmask_b32 v11, v11, v14
v_add_nc_u32_e32 v13, 1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v11
v_cndmask_b32_e32 v11, v12, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v11, v11, v2
v_sub_nc_u32_e32 v2, v11, v2
v_mov_b32_e32 v11, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 0, v2
v_mul_lo_u32 v11, v2, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v1, v11
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[11:12], v11
v_cvt_f64_i32_e32 v[13:14], v2
s_mov_b32 s0, 0
s_mov_b32 s14, 0
v_fma_f64 v[11:12], v[7:8], v[11:12], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[13:14], -v[7:8], v[13:14], v[5:6]
v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v18, v14 :: v_dual_mov_b32 v17, v13
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s16, exec_lo, s13
v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v2, s14
s_or_b32 s0, s16, s0
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s14, s12, exec_lo
s_or_b32 s11, s11, s14
s_mov_b32 s14, s15
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB0_11
.LBB0_9:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[15:16], v[15:16]
s_or_b32 s12, s12, exec_lo
s_or_b32 s13, s13, exec_lo
s_mov_b32 s16, exec_lo
v_fma_f64 v[21:22], v[17:18], v[17:18], v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nlt_f64_e32 4.0, v[21:22]
s_cbranch_execz .LBB0_8
v_mul_f64 v[21:22], v[17:18], v[17:18]
v_mul_f64 v[15:16], v[17:18], v[15:16]
v_add_f64 v[19:20], v[11:12], v[19:20]
s_add_i32 s15, s14, 1
s_movk_i32 s17, 0xff
s_cmp_eq_u32 s3, s15
s_cselect_b32 s18, -1, 0
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s18, s18, exec_lo
s_and_not1_b32 s12, s12, exec_lo
s_or_b32 s13, s13, s18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[15:16], 2.0, v[13:14]
v_add_f64 v[15:16], v[19:20], -v[21:22]
s_branch .LBB0_8
.LBB0_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_2
v_cvt_f64_i32_e32 v[11:12], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[11:12], 0x407fe000
v_div_scale_f64 v[13:14], null, v[9:10], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[15:16], v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
v_div_scale_f64 v[17:18], vcc_lo, v[11:12], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[19:20], v[17:18], v[15:16]
v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
v_div_fixup_f64 v[11:12], v[13:14], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[11:12]
v_cndmask_b32_e32 v12, 0x406fe000, v12, vcc_lo
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cvt_i32_f64_e32 v2, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v12, 8, v2
v_lshlrev_b32_e32 v11, 24, v2
v_lshl_or_b32 v2, v2, 16, v11
s_delay_alu instid0(VALU_DEP_1)
v_or3_b32 v19, v2, v12, 0xff
s_branch .LBB0_2
.LBB0_13:
v_mov_b32_e32 v19, 0xff
s_branch .LBB0_3
.LBB0_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14mandelbrotCalc14RenderSettings
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14mandelbrotCalc14RenderSettings, .Lfunc_end0-_Z14mandelbrotCalc14RenderSettings
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16mandelbrotCalcSP14RenderSettings
.globl _Z16mandelbrotCalcSP14RenderSettings
.p2align 8
.type _Z16mandelbrotCalcSP14RenderSettings,@function
_Z16mandelbrotCalcSP14RenderSettings:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x44
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s6, s0, 56
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_14
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b32 s6, s[6:7], 0x0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[12:13], s[12:13], 2.0
v_div_scale_f64 v[8:9], vcc_lo, 2.0, s[12:13], 2.0
s_mul_i32 s6, s6, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[8:9], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
v_cvt_f64_i32_e32 v[4:5], s2
v_cvt_f64_i32_e32 v[6:7], s3
s_load_b32 s3, s[0:1], 0x28
v_div_fixup_f64 v[2:3], v[2:3], s[12:13], 2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[2:3], v[4:5]
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[4:5]
v_div_scale_f64 v[14:15], vcc_lo, v[4:5], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
v_div_fixup_f64 v[4:5], v[8:9], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[6:7], s[14:15], -v[4:5]
v_add_f64 v[4:5], s[14:15], v[4:5]
v_cvt_f32_f64_e32 v0, v[6:7]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_f64_e32 v4, v[4:5]
v_add_f64 v[5:6], v[2:3], s[4:5]
s_load_b64 s[4:5], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s3, 0
v_cvt_f32_i32_e32 v2, s2
s_cselect_b32 s1, -1, 0
s_ashr_i32 s9, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s2, s9
s_xor_b32 s10, s0, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, s10
s_sub_i32 s0, 0, s10
v_rcp_iflag_f32_e32 v10, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, 0x4f7ffffe, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v10, v10
v_mul_lo_u32 v13, s0, v10
v_sub_f32_e32 v7, v4, v0
v_cvt_f64_u32_e32 v[3:4], s3
v_cvt_f32_f64_e32 v5, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v8, null, v2, v2, v7
v_div_scale_f32 v6, vcc_lo, v7, v2, v7
v_rcp_f32_e32 v9, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v8, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v11, v9
v_mul_f32_e32 v11, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v8, v11, v6
v_fmac_f32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v8, v11, v6
v_mul_hi_u32 v8, v10, v13
v_div_fmas_f32 v9, v6, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, v10, v8
v_div_fixup_f32 v7, v9, v2, v7
s_branch .LBB1_4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
.LBB1_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_nc_u32_e32 v1, s6, v1
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v8, s0, s4, v8
v_add_co_ci_u32_e64 v9, s0, s5, v9, s0
s_or_b32 s7, vcc_lo, s7
global_store_b32 v[8:9], v11, off
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execz .LBB1_14
.LBB1_4:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v1, v2
v_xor_b32_e32 v8, v8, v2
v_xor_b32_e32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v9, v8, v6
v_mul_lo_u32 v10, v9, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v8, v10
v_add_nc_u32_e32 v10, 1, v9
v_subrev_nc_u32_e32 v11, s10, v8
v_cmp_le_u32_e32 vcc_lo, s10, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v9, v9, v10 :: v_dual_cndmask_b32 v8, v8, v11
v_add_nc_u32_e32 v10, 1, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s10, v8
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v8, v8, v2
v_sub_nc_u32_e32 v2, v8, v2
v_mov_b32_e32 v8, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 0, v2
v_mul_lo_u32 v8, v2, s2
s_delay_alu instid0(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v1, v8
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB1_13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v8, v8
v_cvt_f32_i32_e32 v9, v2
s_mov_b32 s0, 0
s_mov_b32 s14, 0
v_fma_f32 v2, v7, v8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v7, v9, v5
v_dual_mov_b32 v9, v2 :: v_dual_mov_b32 v10, v8
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_9
.p2align 6
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_and_b32 s16, exec_lo, s13
v_dual_mov_b32 v11, s17 :: v_dual_mov_b32 v12, s14
s_or_b32 s0, s16, s0
s_and_not1_b32 s11, s11, exec_lo
s_and_b32 s14, s12, exec_lo
s_or_b32 s11, s11, s14
s_mov_b32 s14, s15
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_11
.LBB1_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, v9, v9
s_or_b32 s12, s12, exec_lo
s_or_b32 s13, s13, exec_lo
s_mov_b32 s16, exec_lo
v_fma_f32 v12, v10, v10, v11
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_nlt_f32_e32 4.0, v12
s_cbranch_execz .LBB1_8
v_mul_f32_e32 v12, v10, v10
v_mul_f32_e32 v9, v10, v9
v_add_f32_e32 v11, v2, v11
s_add_i32 s15, s14, 1
s_movk_i32 s17, 0xff
s_cmp_eq_u32 s3, s15
v_fma_f32 v10, 2.0, v9, v8
s_cselect_b32 s18, -1, 0
v_sub_f32_e32 v9, v11, v12
s_and_not1_b32 s13, s13, exec_lo
s_and_b32 s18, s18, exec_lo
s_and_not1_b32 s12, s12, exec_lo
s_or_b32 s13, s13, s18
s_branch .LBB1_8
.LBB1_11:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB1_2
v_cvt_f64_i32_e32 v[8:9], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], 0x407fe000
v_div_scale_f64 v[10:11], null, v[3:4], v[3:4], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_div_scale_f64 v[14:15], vcc_lo, v[8:9], v[3:4], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[14:15], v[12:13]
v_fma_f64 v[10:11], -v[10:11], v[16:17], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[16:17]
v_div_fixup_f64 v[8:9], v[10:11], v[3:4], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_nlt_f64_e32 vcc_lo, 0x406fe000, v[8:9]
v_cndmask_b32_e32 v9, 0x406fe000, v9, vcc_lo
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cvt_i32_f64_e32 v2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v9, 8, v2
v_lshlrev_b32_e32 v8, 24, v2
v_lshl_or_b32 v2, v2, 16, v8
s_delay_alu instid0(VALU_DEP_1)
v_or3_b32 v11, v2, v9, 0xff
s_branch .LBB1_2
.LBB1_13:
v_mov_b32_e32 v11, 0xff
s_branch .LBB1_3
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16mandelbrotCalcSP14RenderSettings
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16mandelbrotCalcSP14RenderSettings, .Lfunc_end1-_Z16mandelbrotCalcSP14RenderSettings
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 56
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14mandelbrotCalc14RenderSettings
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z14mandelbrotCalc14RenderSettings.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 56
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16mandelbrotCalcSP14RenderSettings
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z16mandelbrotCalcSP14RenderSettings.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <bits/stdint-uintn.h>
#include <stdio.h>
#include <sys/param.h>
struct RenderSettings {
uint32_t *outputBuffer;
int width;
int height;
double zoom;
double xoffset;
double yoffset;
unsigned int iterations;
uint32_t *deviceBuffer;
};
uint32_t *deviceBuffer;
char cudaInitialized = 0;
__global__ void mandelbrotCalc(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
double cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
double x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
double x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
double y1 = rs.yoffset + 2.0 / rs.zoom;
double pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
__global__ void mandelbrotCalcSP(struct RenderSettings rs) {
int *deviceBuffer = (int *)rs.deviceBuffer;
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
float cReal, cImag, zReal, zImag, z2Real, z2Imag, zrzi;
int color;
int colorbias;
float x1 = rs.xoffset - 2.0 / rs.zoom * rs.width / rs.height;
float x2 = rs.xoffset + 2.0 / rs.zoom * rs.width / rs.height;
float y1 = rs.yoffset + 2.0 / rs.zoom;
float pixel_pitch = (x2 - x1) / rs.width;
int x, y;
for (int w = index; w < rs.height * rs.width; w += stride) {
y = w / rs.width;
if (y > 0) {
x = w % rs.width;
} else {
x = w;
}
cImag = y1 - pixel_pitch * y;
cReal = x1 + pixel_pitch * x;
zReal = cReal;
zImag = cImag;
color = 0x000000FF; // black as default for values that converge to 0
for (int i = 0; i < rs.iterations; i++) {
z2Real = zReal * zReal;
z2Imag = zImag * zImag;
zrzi = zReal * zImag;
zReal = cReal + z2Real - z2Imag;
zImag = zrzi + zrzi + cImag;
if (z2Real + z2Imag > 4.0f) {
colorbias = MIN(255, i * 510.0 / rs.iterations);
color = (color | (colorbias << 24) | (colorbias << 16) | colorbias << 8);
break;
}
}
deviceBuffer[w] = color;
}
}
extern "C" void freeCUDA() {
if (cudaInitialized == 1) {
hipFree(deviceBuffer);
cudaInitialized = 0;
}
}
extern "C" void initCUDA(struct RenderSettings rs) {
// allocates device buffer on first run
// destroys and re-allocates buffer if window dimensions change
static int width = 0;
static int height = 0;
if (cudaInitialized == 0) {
hipMalloc((void **)&deviceBuffer, rs.width * rs.height * 4);
width = rs.width;
height = rs.height;
cudaInitialized = 1;
} else {
if (rs.width != width || rs.height != height) {
freeCUDA();
initCUDA(rs);
}
}
}
extern "C" void mandelbrotCUDA(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalc<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
}
extern "C" void mandelbrotCUDAsp(struct RenderSettings rs) {
initCUDA(rs);
uint32_t *screenBuffer = rs.outputBuffer;
rs.deviceBuffer = deviceBuffer;
mandelbrotCalcSP<<<2048, 1024>>>(rs);
hipDeviceSynchronize();
hipMemcpy(screenBuffer, deviceBuffer, rs.width * rs.height * 4, hipMemcpyDeviceToHost);
} | .text
.file "mandelcuda.hip"
.globl _Z29__device_stub__mandelbrotCalc14RenderSettings # -- Begin function _Z29__device_stub__mandelbrotCalc14RenderSettings
.p2align 4, 0x90
.type _Z29__device_stub__mandelbrotCalc14RenderSettings,@function
_Z29__device_stub__mandelbrotCalc14RenderSettings: # @_Z29__device_stub__mandelbrotCalc14RenderSettings
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z14mandelbrotCalc14RenderSettings, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__mandelbrotCalc14RenderSettings, .Lfunc_end0-_Z29__device_stub__mandelbrotCalc14RenderSettings
.cfi_endproc
# -- End function
.globl _Z31__device_stub__mandelbrotCalcSP14RenderSettings # -- Begin function _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.p2align 4, 0x90
.type _Z31__device_stub__mandelbrotCalcSP14RenderSettings,@function
_Z31__device_stub__mandelbrotCalcSP14RenderSettings: # @_Z31__device_stub__mandelbrotCalcSP14RenderSettings
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z16mandelbrotCalcSP14RenderSettings, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z31__device_stub__mandelbrotCalcSP14RenderSettings, .Lfunc_end1-_Z31__device_stub__mandelbrotCalcSP14RenderSettings
.cfi_endproc
# -- End function
.globl freeCUDA # -- Begin function freeCUDA
.p2align 4, 0x90
.type freeCUDA,@function
freeCUDA: # @freeCUDA
.cfi_startproc
# %bb.0:
cmpb $1, cudaInitialized(%rip)
jne .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
movq deviceBuffer(%rip), %rdi
callq hipFree
movb $0, cudaInitialized(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size freeCUDA, .Lfunc_end2-freeCUDA
.cfi_endproc
# -- End function
.globl initCUDA # -- Begin function initCUDA
.p2align 4, 0x90
.type initCUDA,@function
initCUDA: # @initCUDA
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 80(%rsp), %rbx
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_8: # %freeCUDA.exit
# in Loop: Header=BB3_1 Depth=1
movq 48(%rbx), %rax
movq %rax, 48(%rsp)
movups (%rbx), %xmm0
movups 16(%rbx), %xmm1
movups 32(%rbx), %xmm2
movaps %xmm2, 32(%rsp)
movaps %xmm1, 16(%rsp)
movaps %xmm0, (%rsp)
.LBB3_1: # %tailrecurse
# =>This Inner Loop Header: Depth=1
movzbl cudaInitialized(%rip), %eax
movl 8(%rbx), %ebp
testb %al, %al
je .LBB3_2
# %bb.4: # in Loop: Header=BB3_1 Depth=1
cmpl _ZZ8initCUDAE5width(%rip), %ebp
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl 12(%rbx), %ecx
cmpl _ZZ8initCUDAE6height(%rip), %ecx
je .LBB3_3
.LBB3_6: # in Loop: Header=BB3_1 Depth=1
cmpb $1, %al
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movq deviceBuffer(%rip), %rdi
callq hipFree
movb $0, cudaInitialized(%rip)
jmp .LBB3_8
.LBB3_2:
movl 12(%rbx), %ebx
movl %ebp, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %rsi
movl $deviceBuffer, %edi
callq hipMalloc
movl %ebp, _ZZ8initCUDAE5width(%rip)
movl %ebx, _ZZ8initCUDAE6height(%rip)
movb $1, cudaInitialized(%rip)
.LBB3_3:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size initCUDA, .Lfunc_end3-initCUDA
.cfi_endproc
# -- End function
.globl mandelbrotCUDA # -- Begin function mandelbrotCUDA
.p2align 4, 0x90
.type mandelbrotCUDA,@function
mandelbrotCUDA: # @mandelbrotCUDA
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 208(%rsp), %r14
movq 256(%rsp), %rax
movq %rax, 48(%rsp)
movaps 208(%rsp), %xmm0
movaps 224(%rsp), %xmm1
movaps 240(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
callq initCUDA
movq 208(%rsp), %rbx
movq deviceBuffer(%rip), %rax
movq %rax, 256(%rsp)
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1024(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 48(%r14), %rax
movq %rax, 176(%rsp)
movups (%r14), %xmm0
movups 16(%r14), %xmm1
movups 32(%r14), %xmm2
movaps %xmm2, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 64(%rsp), %r9
movl $_Z14mandelbrotCalc14RenderSettings, %edi
callq hipLaunchKernel
.LBB4_2:
callq hipDeviceSynchronize
movq deviceBuffer(%rip), %rsi
movl 8(%r14), %eax
imull 12(%r14), %eax
shll $2, %eax
movslq %eax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size mandelbrotCUDA, .Lfunc_end4-mandelbrotCUDA
.cfi_endproc
# -- End function
.globl mandelbrotCUDAsp # -- Begin function mandelbrotCUDAsp
.p2align 4, 0x90
.type mandelbrotCUDAsp,@function
mandelbrotCUDAsp: # @mandelbrotCUDAsp
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 208(%rsp), %r14
movq 256(%rsp), %rax
movq %rax, 48(%rsp)
movaps 208(%rsp), %xmm0
movaps 224(%rsp), %xmm1
movaps 240(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
callq initCUDA
movq 208(%rsp), %rbx
movq deviceBuffer(%rip), %rax
movq %rax, 256(%rsp)
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1024(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 48(%r14), %rax
movq %rax, 176(%rsp)
movups (%r14), %xmm0
movups 16(%r14), %xmm1
movups 32(%r14), %xmm2
movaps %xmm2, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 64(%rsp), %r9
movl $_Z16mandelbrotCalcSP14RenderSettings, %edi
callq hipLaunchKernel
.LBB5_2:
callq hipDeviceSynchronize
movq deviceBuffer(%rip), %rsi
movl 8(%r14), %eax
imull 12(%r14), %eax
shll $2, %eax
movslq %eax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size mandelbrotCUDAsp, .Lfunc_end5-mandelbrotCUDAsp
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mandelbrotCalc14RenderSettings, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16mandelbrotCalcSP14RenderSettings, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type deviceBuffer,@object # @deviceBuffer
.bss
.globl deviceBuffer
.p2align 3, 0x0
deviceBuffer:
.quad 0
.size deviceBuffer, 8
.type cudaInitialized,@object # @cudaInitialized
.globl cudaInitialized
cudaInitialized:
.byte 0 # 0x0
.size cudaInitialized, 1
.type _Z14mandelbrotCalc14RenderSettings,@object # @_Z14mandelbrotCalc14RenderSettings
.section .rodata,"a",@progbits
.globl _Z14mandelbrotCalc14RenderSettings
.p2align 3, 0x0
_Z14mandelbrotCalc14RenderSettings:
.quad _Z29__device_stub__mandelbrotCalc14RenderSettings
.size _Z14mandelbrotCalc14RenderSettings, 8
.type _Z16mandelbrotCalcSP14RenderSettings,@object # @_Z16mandelbrotCalcSP14RenderSettings
.globl _Z16mandelbrotCalcSP14RenderSettings
.p2align 3, 0x0
_Z16mandelbrotCalcSP14RenderSettings:
.quad _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.size _Z16mandelbrotCalcSP14RenderSettings, 8
.type _ZZ8initCUDAE5width,@object # @_ZZ8initCUDAE5width
.local _ZZ8initCUDAE5width
.comm _ZZ8initCUDAE5width,4,4
.type _ZZ8initCUDAE6height,@object # @_ZZ8initCUDAE6height
.local _ZZ8initCUDAE6height
.comm _ZZ8initCUDAE6height,4,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14mandelbrotCalc14RenderSettings"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16mandelbrotCalcSP14RenderSettings"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mandelbrotCalc14RenderSettings
.addrsig_sym _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceBuffer
.addrsig_sym _Z14mandelbrotCalc14RenderSettings
.addrsig_sym _Z16mandelbrotCalcSP14RenderSettings
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3747_00000000-6_mandelcuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl freeCUDA
.type freeCUDA, @function
freeCUDA:
.LFB2070:
.cfi_startproc
endbr64
cmpb $1, cudaInitialized(%rip)
je .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movq deviceBuffer(%rip), %rdi
call cudaFree@PLT
movb $0, cudaInitialized(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size freeCUDA, .-freeCUDA
.globl initCUDA
.type initCUDA, @function
initCUDA:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
cmpb $0, cudaInitialized(%rip)
je .L15
cmpl %ebx, _ZZ8initCUDAE5width(%rip)
jne .L13
cmpl %ebp, _ZZ8initCUDAE6height(%rip)
je .L10
.L13:
call freeCUDA
subq $64, %rsp
.cfi_def_cfa_offset 96
movdqu 96(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 112(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 128(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 144(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
addq $64, %rsp
.cfi_def_cfa_offset 32
.L10:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
imull %ebp, %esi
sall $2, %esi
movslq %esi, %rsi
leaq deviceBuffer(%rip), %rdi
call cudaMalloc@PLT
movl %ebx, _ZZ8initCUDAE5width(%rip)
movl %ebp, _ZZ8initCUDAE6height(%rip)
movb $1, cudaInitialized(%rip)
jmp .L10
.cfi_endproc
.LFE2071:
.size initCUDA, .-initCUDA
.globl _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
.type _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, @function
_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings:
.LFB2098:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14mandelbrotCalc14RenderSettings(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings, .-_Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
.globl _Z14mandelbrotCalc14RenderSettings
.type _Z14mandelbrotCalc14RenderSettings, @function
_Z14mandelbrotCalc14RenderSettings:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z14mandelbrotCalc14RenderSettings, .-_Z14mandelbrotCalc14RenderSettings
.globl mandelbrotCUDA
.type mandelbrotCUDA, @function
mandelbrotCUDA:
.LFB2072:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movdqu 192(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 208(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 224(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
movq 192(%rsp), %rbx
movq deviceBuffer(%rip), %rbp
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $2048, 72(%rsp)
movl $1, 76(%rsp)
addq $64, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L25:
call cudaDeviceSynchronize@PLT
movl 136(%rsp), %edx
imull 140(%rsp), %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq deviceBuffer(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq %rbp, 176(%rsp)
movdqu 128(%rsp), %xmm3
movaps %xmm3, 32(%rsp)
movdqu 144(%rsp), %xmm4
movaps %xmm4, 48(%rsp)
movdqu 160(%rsp), %xmm5
movaps %xmm5, 64(%rsp)
movq %rbp, 80(%rsp)
leaq 32(%rsp), %rdi
call _Z48__device_stub__Z14mandelbrotCalc14RenderSettingsR14RenderSettings
jmp .L25
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size mandelbrotCUDA, .-mandelbrotCUDA
.globl _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
.type _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, @function
_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings:
.LFB2100:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16mandelbrotCalcSP14RenderSettings(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings, .-_Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
.globl _Z16mandelbrotCalcSP14RenderSettings
.type _Z16mandelbrotCalcSP14RenderSettings, @function
_Z16mandelbrotCalcSP14RenderSettings:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 16(%rsp), %rdi
call _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z16mandelbrotCalcSP14RenderSettings, .-_Z16mandelbrotCalcSP14RenderSettings
.globl mandelbrotCUDAsp
.type mandelbrotCUDAsp, @function
mandelbrotCUDAsp:
.LFB2073:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movdqu 192(%rsp), %xmm0
movups %xmm0, (%rsp)
movdqu 208(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movdqu 224(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movq 240(%rsp), %rax
movq %rax, 48(%rsp)
call initCUDA
movq 192(%rsp), %rbx
movq deviceBuffer(%rip), %rbp
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $2048, 72(%rsp)
movl $1, 76(%rsp)
addq $64, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L39:
call cudaDeviceSynchronize@PLT
movl 136(%rsp), %edx
imull 140(%rsp), %edx
sall $2, %edx
movslq %edx, %rdx
movl $2, %ecx
movq deviceBuffer(%rip), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq %rbp, 176(%rsp)
movdqu 128(%rsp), %xmm3
movaps %xmm3, 32(%rsp)
movdqu 144(%rsp), %xmm4
movaps %xmm4, 48(%rsp)
movdqu 160(%rsp), %xmm5
movaps %xmm5, 64(%rsp)
movq %rbp, 80(%rsp)
leaq 32(%rsp), %rdi
call _Z50__device_stub__Z16mandelbrotCalcSP14RenderSettingsR14RenderSettings
jmp .L39
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2073:
.size mandelbrotCUDAsp, .-mandelbrotCUDAsp
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z16mandelbrotCalcSP14RenderSettings"
.align 8
.LC1:
.string "_Z14mandelbrotCalc14RenderSettings"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16mandelbrotCalcSP14RenderSettings(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14mandelbrotCalc14RenderSettings(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ8initCUDAE6height
.comm _ZZ8initCUDAE6height,4,4
.local _ZZ8initCUDAE5width
.comm _ZZ8initCUDAE5width,4,4
.globl cudaInitialized
.bss
.type cudaInitialized, @object
.size cudaInitialized, 1
cudaInitialized:
.zero 1
.globl deviceBuffer
.align 8
.type deviceBuffer, @object
.size deviceBuffer, 8
deviceBuffer:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mandelcuda.hip"
.globl _Z29__device_stub__mandelbrotCalc14RenderSettings # -- Begin function _Z29__device_stub__mandelbrotCalc14RenderSettings
.p2align 4, 0x90
.type _Z29__device_stub__mandelbrotCalc14RenderSettings,@function
_Z29__device_stub__mandelbrotCalc14RenderSettings: # @_Z29__device_stub__mandelbrotCalc14RenderSettings
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z14mandelbrotCalc14RenderSettings, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__mandelbrotCalc14RenderSettings, .Lfunc_end0-_Z29__device_stub__mandelbrotCalc14RenderSettings
.cfi_endproc
# -- End function
.globl _Z31__device_stub__mandelbrotCalcSP14RenderSettings # -- Begin function _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.p2align 4, 0x90
.type _Z31__device_stub__mandelbrotCalcSP14RenderSettings,@function
_Z31__device_stub__mandelbrotCalcSP14RenderSettings: # @_Z31__device_stub__mandelbrotCalcSP14RenderSettings
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z16mandelbrotCalcSP14RenderSettings, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z31__device_stub__mandelbrotCalcSP14RenderSettings, .Lfunc_end1-_Z31__device_stub__mandelbrotCalcSP14RenderSettings
.cfi_endproc
# -- End function
.globl freeCUDA # -- Begin function freeCUDA
.p2align 4, 0x90
.type freeCUDA,@function
freeCUDA: # @freeCUDA
.cfi_startproc
# %bb.0:
cmpb $1, cudaInitialized(%rip)
jne .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
movq deviceBuffer(%rip), %rdi
callq hipFree
movb $0, cudaInitialized(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size freeCUDA, .Lfunc_end2-freeCUDA
.cfi_endproc
# -- End function
.globl initCUDA # -- Begin function initCUDA
.p2align 4, 0x90
.type initCUDA,@function
initCUDA: # @initCUDA
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 80(%rsp), %rbx
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_8: # %freeCUDA.exit
# in Loop: Header=BB3_1 Depth=1
movq 48(%rbx), %rax
movq %rax, 48(%rsp)
movups (%rbx), %xmm0
movups 16(%rbx), %xmm1
movups 32(%rbx), %xmm2
movaps %xmm2, 32(%rsp)
movaps %xmm1, 16(%rsp)
movaps %xmm0, (%rsp)
.LBB3_1: # %tailrecurse
# =>This Inner Loop Header: Depth=1
movzbl cudaInitialized(%rip), %eax
movl 8(%rbx), %ebp
testb %al, %al
je .LBB3_2
# %bb.4: # in Loop: Header=BB3_1 Depth=1
cmpl _ZZ8initCUDAE5width(%rip), %ebp
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl 12(%rbx), %ecx
cmpl _ZZ8initCUDAE6height(%rip), %ecx
je .LBB3_3
.LBB3_6: # in Loop: Header=BB3_1 Depth=1
cmpb $1, %al
jne .LBB3_8
# %bb.7: # in Loop: Header=BB3_1 Depth=1
movq deviceBuffer(%rip), %rdi
callq hipFree
movb $0, cudaInitialized(%rip)
jmp .LBB3_8
.LBB3_2:
movl 12(%rbx), %ebx
movl %ebp, %eax
imull %ebx, %eax
shll $2, %eax
movslq %eax, %rsi
movl $deviceBuffer, %edi
callq hipMalloc
movl %ebp, _ZZ8initCUDAE5width(%rip)
movl %ebx, _ZZ8initCUDAE6height(%rip)
movb $1, cudaInitialized(%rip)
.LBB3_3:
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size initCUDA, .Lfunc_end3-initCUDA
.cfi_endproc
# -- End function
.globl mandelbrotCUDA # -- Begin function mandelbrotCUDA
.p2align 4, 0x90
.type mandelbrotCUDA,@function
mandelbrotCUDA: # @mandelbrotCUDA
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 208(%rsp), %r14
movq 256(%rsp), %rax
movq %rax, 48(%rsp)
movaps 208(%rsp), %xmm0
movaps 224(%rsp), %xmm1
movaps 240(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
callq initCUDA
movq 208(%rsp), %rbx
movq deviceBuffer(%rip), %rax
movq %rax, 256(%rsp)
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1024(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 48(%r14), %rax
movq %rax, 176(%rsp)
movups (%r14), %xmm0
movups 16(%r14), %xmm1
movups 32(%r14), %xmm2
movaps %xmm2, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 64(%rsp), %r9
movl $_Z14mandelbrotCalc14RenderSettings, %edi
callq hipLaunchKernel
.LBB4_2:
callq hipDeviceSynchronize
movq deviceBuffer(%rip), %rsi
movl 8(%r14), %eax
imull 12(%r14), %eax
shll $2, %eax
movslq %eax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size mandelbrotCUDA, .Lfunc_end4-mandelbrotCUDA
.cfi_endproc
# -- End function
.globl mandelbrotCUDAsp # -- Begin function mandelbrotCUDAsp
.p2align 4, 0x90
.type mandelbrotCUDAsp,@function
mandelbrotCUDAsp: # @mandelbrotCUDAsp
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 208(%rsp), %r14
movq 256(%rsp), %rax
movq %rax, 48(%rsp)
movaps 208(%rsp), %xmm0
movaps 224(%rsp), %xmm1
movaps 240(%rsp), %xmm2
movups %xmm2, 32(%rsp)
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
callq initCUDA
movq 208(%rsp), %rbx
movq deviceBuffer(%rip), %rax
movq %rax, 256(%rsp)
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 1024(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq 48(%r14), %rax
movq %rax, 176(%rsp)
movups (%r14), %xmm0
movups 16(%r14), %xmm1
movups 32(%r14), %xmm2
movaps %xmm2, 160(%rsp)
movaps %xmm1, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rax
movq 80(%rsp), %rdi
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movq %rdi, 8(%rsp)
movq %rax, (%rsp)
leaq 64(%rsp), %r9
movl $_Z16mandelbrotCalcSP14RenderSettings, %edi
callq hipLaunchKernel
.LBB5_2:
callq hipDeviceSynchronize
movq deviceBuffer(%rip), %rsi
movl 8(%r14), %eax
imull 12(%r14), %eax
shll $2, %eax
movslq %eax, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size mandelbrotCUDAsp, .Lfunc_end5-mandelbrotCUDAsp
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14mandelbrotCalc14RenderSettings, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16mandelbrotCalcSP14RenderSettings, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type deviceBuffer,@object # @deviceBuffer
.bss
.globl deviceBuffer
.p2align 3, 0x0
deviceBuffer:
.quad 0
.size deviceBuffer, 8
.type cudaInitialized,@object # @cudaInitialized
.globl cudaInitialized
cudaInitialized:
.byte 0 # 0x0
.size cudaInitialized, 1
.type _Z14mandelbrotCalc14RenderSettings,@object # @_Z14mandelbrotCalc14RenderSettings
.section .rodata,"a",@progbits
.globl _Z14mandelbrotCalc14RenderSettings
.p2align 3, 0x0
_Z14mandelbrotCalc14RenderSettings:
.quad _Z29__device_stub__mandelbrotCalc14RenderSettings
.size _Z14mandelbrotCalc14RenderSettings, 8
.type _Z16mandelbrotCalcSP14RenderSettings,@object # @_Z16mandelbrotCalcSP14RenderSettings
.globl _Z16mandelbrotCalcSP14RenderSettings
.p2align 3, 0x0
_Z16mandelbrotCalcSP14RenderSettings:
.quad _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.size _Z16mandelbrotCalcSP14RenderSettings, 8
.type _ZZ8initCUDAE5width,@object # @_ZZ8initCUDAE5width
.local _ZZ8initCUDAE5width
.comm _ZZ8initCUDAE5width,4,4
.type _ZZ8initCUDAE6height,@object # @_ZZ8initCUDAE6height
.local _ZZ8initCUDAE6height
.comm _ZZ8initCUDAE6height,4,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14mandelbrotCalc14RenderSettings"
.size .L__unnamed_1, 35
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16mandelbrotCalcSP14RenderSettings"
.size .L__unnamed_2, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__mandelbrotCalc14RenderSettings
.addrsig_sym _Z31__device_stub__mandelbrotCalcSP14RenderSettings
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceBuffer
.addrsig_sym _Z14mandelbrotCalc14RenderSettings
.addrsig_sym _Z16mandelbrotCalcSP14RenderSettings
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
cudaSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **)&d_a, memSize);
cudaMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
checkCUDAError("cudaMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
cudaMemcpy(h_a, d_scratch, sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
cudaFree(d_a);
cudaFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} | code for sm_80
Function : _Z20compute_final_kernelPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0030*/ @!P0 BRA 0x290 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0050*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0080*/ IMAD.SHL.U32 R0, R9, 0x4, RZ ; /* 0x0000000409007824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD.IADD R3, R9, 0x1, R4 ; /* 0x0000000109037824 */
/* 0x001fe200078e0204 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ BSSY B0, 0x130 ; /* 0x0000005000007945 */
/* 0x000ff60003800000 */
/*00e0*/ @P0 BRA 0x120 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0002 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000164000c1e1900 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0203e20000004800 */
/*0150*/ IADD3 R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a10 */
/* 0x000fc60007ffe0ff */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fce0003f06070 */
/*0180*/ @!P1 BRA 0x240 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x003fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26070 */
/*01b0*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*01c0*/ @!P1 LDS R6, [R9.X4] ; /* 0x0000000009069984 */
/* 0x000fe20000004800 */
/*01d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01e0*/ @!P1 LDS R7, [R2] ; /* 0x0000000002079984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 IADD3 R6, R6, R7, RZ ; /* 0x0000000706069210 */
/* 0x001fca0007ffe0ff */
/*0200*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0240*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x002fda0003f25270 */
/*0250*/ @!P1 LDS R2, [RZ] ; /* 0x00000000ff029984 */
/* 0x000e640000000800 */
/*0260*/ @!P1 IMAD.IADD R5, R5, 0x1, R2 ; /* 0x0000000105059824 */
/* 0x002fe200078e0202 */
/*0270*/ @!P0 BRA 0x90 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0280*/ BRA 0x2a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*02a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e640000002100 */
/*02b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x002fda0003f05270 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x001fca00078e00ff */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19compute_sums_kerneljPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fca00078e0203 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0190*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
cudaSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **)&d_a, memSize);
cudaMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
checkCUDAError("cudaMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
cudaMemcpy(h_a, d_scratch, sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
cudaFree(d_a);
cudaFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} | .file "tmpxft_000d1b87_00000000-6_CUDA-example-reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
.type _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_, @function
_Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19compute_sums_kerneljPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_, .-_Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
.globl _Z19compute_sums_kerneljPiS_
.type _Z19compute_sums_kerneljPiS_, @function
_Z19compute_sums_kerneljPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19compute_sums_kerneljPiS_, .-_Z19compute_sums_kerneljPiS_
.globl _Z41__device_stub__Z20compute_final_kernelPijPij
.type _Z41__device_stub__Z20compute_final_kernelPijPij, @function
_Z41__device_stub__Z20compute_final_kernelPijPij:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20compute_final_kernelPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z20compute_final_kernelPijPij, .-_Z41__device_stub__Z20compute_final_kernelPijPij
.globl _Z20compute_final_kernelPij
.type _Z20compute_final_kernelPij, @function
_Z20compute_final_kernelPij:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z20compute_final_kernelPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z20compute_final_kernelPij, .-_Z20compute_final_kernelPij
.section .rodata.str1.1
.LC1:
.string "cudaMemcpy"
.LC2:
.string "kernel execution 1"
.LC3:
.string "kernel execution 2"
.LC4:
.string "Failed!!! %d %d\n"
.LC5:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $628, %esi
call cudaMalloc@PLT
movq %r13, %rbx
leaq 40000(%r13), %r12
movl $0, %ebp
.L24:
call rand@PLT
movl %eax, (%rbx)
addl %eax, %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L24
movl $1, %ecx
movl $40000, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $157, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $256, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, 16(%rsp)
movl $512, 28(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $2048, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 0(%r13), %ecx
cmpl %ebp, %ecx
jne .L33
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $10000, %edi
call _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
jmp .L25
.L32:
movl $157, %esi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z20compute_final_kernelPijPij
jmp .L26
.L33:
movl %ebp, %r8d
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z20compute_final_kernelPij"
.LC7:
.string "_Z19compute_sums_kerneljPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compute_final_kernelPij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19compute_sums_kerneljPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <cuda_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
cudaSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
cudaMalloc((void **)&d_a, memSize);
cudaMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
cudaMemcpy(d_a, h_a, memSize, cudaMemcpyHostToDevice);
checkCUDAError("cudaMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
cudaMemcpy(h_a, d_scratch, sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("cudaMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
cudaFree(d_a);
cudaFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
hipSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **)&d_a, memSize);
hipMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
checkCUDAError("hipMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
hipMemcpy(h_a, d_scratch, sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
hipFree(d_a);
hipFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
hipSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **)&d_a, memSize);
hipMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
checkCUDAError("hipMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
hipMemcpy(h_a, d_scratch, sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
hipFree(d_a);
hipFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19compute_sums_kerneljPiS_
.globl _Z19compute_sums_kerneljPiS_
.p2align 8
.type _Z19compute_sums_kerneljPiS_,@function
_Z19compute_sums_kerneljPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19compute_sums_kerneljPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19compute_sums_kerneljPiS_, .Lfunc_end0-_Z19compute_sums_kerneljPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20compute_final_kernelPij
.globl _Z20compute_final_kernelPij
.p2align 8
.type _Z20compute_final_kernelPij,@function
_Z20compute_final_kernelPij:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB1_13
s_load_b32 s1, s[0:1], 0x1c
v_lshl_add_u32 v4, v0, 2, 0
v_cmp_eq_u32_e64 s0, 0, v0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s1, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s1, 1
s_cselect_b32 s6, -1, 0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s5, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s5, s4
s_cbranch_scc1 .LBB1_13
.LBB1_3:
v_add_nc_u32_e32 v1, s5, v0
s_mov_b32 s7, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_le_u32_e64 s4, v1
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_5
ds_store_b32 v4, v2
.LBB1_5:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s6
s_mov_b32 s7, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_11
.LBB1_8:
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v1, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
s_branch .LBB1_2
.p2align 6
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_gt_u32 s7, 3
s_mov_b32 s7, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_8
.LBB1_11:
s_lshr_b32 s8, s7, 1
s_mov_b32 s9, exec_lo
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v1, s8, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
ds_store_b32 v4, v1
s_branch .LBB1_10
.LBB1_13:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_15
v_mov_b32_e32 v0, 0
global_store_b32 v0, v3, s[2:3]
.LBB1_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20compute_final_kernelPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20compute_final_kernelPij, .Lfunc_end1-_Z20compute_final_kernelPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19compute_sums_kerneljPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19compute_sums_kerneljPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20compute_final_kernelPij
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z20compute_final_kernelPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Molecular dynamics simulation linear code for binary Lennard-Jones liquid
under NVE ensemble; Author: You-Liang Zhu, Email: youliangzhu@ciac.ac.cn
Copyright: You-Liang Zhu
This code is free: you can redistribute it and/or modify it under the terms
of the GNU General Public License.*/
#include <ctype.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/time.h>
// check CUDA error
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if (hipSuccess != err) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString(err));
exit(-1);
}
}
// parallel reduction
extern __shared__ int sdata[];
__global__ void compute_sums_kernel(unsigned int N, int *d_a, int *d_scratch) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int data = 0;
if (i < N)
data = d_a[i];
sdata[threadIdx.x] = data;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs)
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
d_scratch[blockIdx.x] = sdata[0];
}
// final parallel reduction
__global__ void compute_final_kernel(int *d_scratch,
unsigned int num_partial_sums) {
int final_sum = 0;
for (int start = 0; start < num_partial_sums; start += blockDim.x) {
__syncthreads();
if (start + threadIdx.x < num_partial_sums)
sdata[threadIdx.x] = d_scratch[start + threadIdx.x];
else
sdata[threadIdx.x] = 0;
__syncthreads();
int offs = blockDim.x >> 1;
while (offs > 0) {
if (threadIdx.x < offs) {
sdata[threadIdx.x] += sdata[threadIdx.x + offs];
}
offs >>= 1;
__syncthreads();
}
if (threadIdx.x == 0)
final_sum += sdata[0];
}
if (threadIdx.x == 0)
d_scratch[0] = final_sum;
}
int main(int argc, char **argv) {
int N = 10000; // the number of integers for reduction
int *h_a; // pointer for host memory
int *d_a, *d_scratch; // pointer for device memory
hipSetDevice(0); // set GPU ID for computation
int block_size = 64; // define block size
int n_blocks = (int)ceil((float)N / (float)block_size); // define grid size
// Part 1 of 5: allocate host and device memory
size_t memSize = N * sizeof(int);
h_a = (int *)malloc(memSize);
hipMalloc((void **)&d_a, memSize);
hipMalloc((void **)&d_scratch, n_blocks * sizeof(int));
// Part 2 of 5: initiate array
int sum = 0;
for (unsigned int i = 0; i < N; i++) {
int ran = rand();
h_a[i] = ran;
sum += ran;
}
// Part 3 of 5: copy data from host to device memory
hipMemcpy(d_a, h_a, memSize, hipMemcpyHostToDevice);
checkCUDAError("hipMemcpy");
// Part 4 of 5: launch kernel
dim3 grid(n_blocks, 1, 1);
dim3 threads(block_size, 1, 1);
unsigned int shared_bytes = sizeof(int) * block_size;
compute_sums_kernel<<<grid, threads, shared_bytes>>>(N, d_a, d_scratch);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 1");
int final_block_size = 512;
grid = dim3(1, 1, 1);
threads = dim3(final_block_size, 1, 1);
shared_bytes = sizeof(int) * final_block_size;
compute_final_kernel<<<grid, threads, shared_bytes>>>(d_scratch, n_blocks);
// block until the device has completed
/* cudaThreadSynchronize(); */
// check if kernel execution generated an error
checkCUDAError("kernel execution 2");
// Part 5 of 5: device to host copy
hipMemcpy(h_a, d_scratch, sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("hipMemcpy");
// check result from device
if (h_a[0] - sum != 0) {
fprintf(stderr, "Failed!!! %d %d\n", h_a[0], sum);
exit(-1);
}
// free device memory
hipFree(d_a);
hipFree(d_scratch);
// free host memory
free(h_a);
// If the program makes it this far, then the results are correct and
// there are no run-time errors. Good work!
printf("Success!\n");
return 0;
} | .text
.file "CUDA-example-reduction.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z34__device_stub__compute_sums_kerneljPiS_ # -- Begin function _Z34__device_stub__compute_sums_kerneljPiS_
.p2align 4, 0x90
.type _Z34__device_stub__compute_sums_kerneljPiS_,@function
_Z34__device_stub__compute_sums_kerneljPiS_: # @_Z34__device_stub__compute_sums_kerneljPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19compute_sums_kerneljPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__compute_sums_kerneljPiS_, .Lfunc_end1-_Z34__device_stub__compute_sums_kerneljPiS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__compute_final_kernelPij # -- Begin function _Z35__device_stub__compute_final_kernelPij
.p2align 4, 0x90
.type _Z35__device_stub__compute_final_kernelPij,@function
_Z35__device_stub__compute_final_kernelPij: # @_Z35__device_stub__compute_final_kernelPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20compute_final_kernelPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__compute_final_kernelPij, .Lfunc_end2-_Z35__device_stub__compute_final_kernelPij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $628, %esi # imm = 0x274
callq hipMalloc
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
addl %eax, %ebp
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB3_1
# %bb.2:
movq 16(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_Z14checkCUDAErrorPKc.exit
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 63(%r14), %rdx
leaq 156(%r14), %rdi
movl $256, %r8d # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $10000, 92(%rsp) # imm = 0x2710
movq %rax, 80(%rsp)
movq %rcx, 40(%rsp)
leaq 92(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19compute_sums_kerneljPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z14checkCUDAErrorPKc.exit48
leaq 511(%r14), %rdx
movl $2048, %r8d # imm = 0x800
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $157, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20compute_final_kernelPij, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_Z14checkCUDAErrorPKc.exit56
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.14: # %_Z14checkCUDAErrorPKc.exit58
movl (%rbx), %edx
cmpl %ebp, %edx
jne .LBB3_16
# %bb.15:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.2, %edx
jmp .LBB3_4
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.3, %edx
.LBB3_4:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %ebp, %ecx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19compute_sums_kerneljPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20compute_final_kernelPij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type _Z19compute_sums_kerneljPiS_,@object # @_Z19compute_sums_kerneljPiS_
.section .rodata,"a",@progbits
.globl _Z19compute_sums_kerneljPiS_
.p2align 3, 0x0
_Z19compute_sums_kerneljPiS_:
.quad _Z34__device_stub__compute_sums_kerneljPiS_
.size _Z19compute_sums_kerneljPiS_, 8
.type _Z20compute_final_kernelPij,@object # @_Z20compute_final_kernelPij
.globl _Z20compute_final_kernelPij
.p2align 3, 0x0
_Z20compute_final_kernelPij:
.quad _Z35__device_stub__compute_final_kernelPij
.size _Z20compute_final_kernelPij, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "hipMemcpy"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel execution 1"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel execution 2"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed!!! %d %d\n"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19compute_sums_kerneljPiS_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20compute_final_kernelPij"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__compute_sums_kerneljPiS_
.addrsig_sym _Z35__device_stub__compute_final_kernelPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19compute_sums_kerneljPiS_
.addrsig_sym _Z20compute_final_kernelPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20compute_final_kernelPij
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0030*/ @!P0 BRA 0x290 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0050*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0060*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0070*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011604 */
/*0080*/ IMAD.SHL.U32 R0, R9, 0x4, RZ ; /* 0x0000000409007824 */
/* 0x001fe400078e00ff */
/*0090*/ IMAD.IADD R3, R9, 0x1, R4 ; /* 0x0000000109037824 */
/* 0x001fe200078e0204 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe40003f06070 */
/*00d0*/ BSSY B0, 0x130 ; /* 0x0000005000007945 */
/* 0x000ff60003800000 */
/*00e0*/ @P0 BRA 0x120 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fd400000001ff */
/*0100*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0002 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000164000c1e1900 */
/*0120*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*0140*/ STS [R9.X4], R2 ; /* 0x0000000209007388 */
/* 0x0203e20000004800 */
/*0150*/ IADD3 R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a10 */
/* 0x000fc60007ffe0ff */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fce0003f06070 */
/*0180*/ @!P1 BRA 0x240 ; /* 0x000000b000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x003fca000f8e00ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R9, R3, PT ; /* 0x000000030900720c */
/* 0x000fda0003f26070 */
/*01b0*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*01c0*/ @!P1 LDS R6, [R9.X4] ; /* 0x0000000009069984 */
/* 0x000fe20000004800 */
/*01d0*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*01e0*/ @!P1 LDS R7, [R2] ; /* 0x0000000002079984 */
/* 0x000e240000000800 */
/*01f0*/ @!P1 IADD3 R6, R6, R7, RZ ; /* 0x0000000706069210 */
/* 0x001fca0007ffe0ff */
/*0200*/ @!P1 STS [R9.X4], R6 ; /* 0x0000000609009388 */
/* 0x0001e80000004800 */
/*0210*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0220*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0230*/ @P1 BRA 0x1a0 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*0240*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x002fda0003f25270 */
/*0250*/ @!P1 LDS R2, [RZ] ; /* 0x00000000ff029984 */
/* 0x000e640000000800 */
/*0260*/ @!P1 IMAD.IADD R5, R5, 0x1, R2 ; /* 0x0000000105059824 */
/* 0x002fe200078e0202 */
/*0270*/ @!P0 BRA 0x90 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0280*/ BRA 0x2a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0290*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*02a0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e640000002100 */
/*02b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x002fda0003f05270 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x001fca00078e00ff */
/*02f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z19compute_sums_kerneljPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 0 ; /* 0x00000000ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0070*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff038424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002028625 */
/* 0x000fca00078e0203 */
/*0090*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00c0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00d0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0100*/ @!P1 BRA 0x1d0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0140*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0150*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0160*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0170*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0180*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0190*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01c0*/ @P1 BRA 0x130 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01e0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fca00078e0003 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19compute_sums_kerneljPiS_
.globl _Z19compute_sums_kerneljPiS_
.p2align 8
.type _Z19compute_sums_kerneljPiS_,@function
_Z19compute_sums_kerneljPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_7:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_6
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19compute_sums_kerneljPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19compute_sums_kerneljPiS_, .Lfunc_end0-_Z19compute_sums_kerneljPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20compute_final_kernelPij
.globl _Z20compute_final_kernelPij
.p2align 8
.type _Z20compute_final_kernelPij,@function
_Z20compute_final_kernelPij:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s4, 0
s_cbranch_scc1 .LBB1_13
s_load_b32 s1, s[0:1], 0x1c
v_lshl_add_u32 v4, v0, 2, 0
v_cmp_eq_u32_e64 s0, 0, v0
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s1, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s1, 1
s_cselect_b32 s6, -1, 0
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
s_add_i32 s5, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s5, s4
s_cbranch_scc1 .LBB1_13
.LBB1_3:
v_add_nc_u32_e32 v1, s5, v0
s_mov_b32 s7, exec_lo
s_barrier
buffer_gl0_inv
v_cmpx_le_u32_e64 s4, v1
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB1_5
ds_store_b32 v4, v2
.LBB1_5:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB1_7
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v1, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s6
s_mov_b32 s7, s1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB1_11
.LBB1_8:
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB1_2
v_mov_b32_e32 v1, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v1, v3
s_branch .LBB1_2
.p2align 6
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_gt_u32 s7, 3
s_mov_b32 s7, s8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_8
.LBB1_11:
s_lshr_b32 s8, s7, 1
s_mov_b32 s9, exec_lo
v_cmpx_gt_u32_e64 s8, v0
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v1, s8, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v1, v1, 2, 0
ds_load_b32 v1, v1
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, v5, v1
ds_store_b32 v4, v1
s_branch .LBB1_10
.LBB1_13:
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_15
v_mov_b32_e32 v0, 0
global_store_b32 v0, v3, s[2:3]
.LBB1_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20compute_final_kernelPij
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20compute_final_kernelPij, .Lfunc_end1-_Z20compute_final_kernelPij
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19compute_sums_kerneljPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19compute_sums_kerneljPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20compute_final_kernelPij
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z20compute_final_kernelPij.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d1b87_00000000-6_CUDA-example-reduction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.globl _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
.type _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_, @function
_Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19compute_sums_kerneljPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_, .-_Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
.globl _Z19compute_sums_kerneljPiS_
.type _Z19compute_sums_kerneljPiS_, @function
_Z19compute_sums_kerneljPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z19compute_sums_kerneljPiS_, .-_Z19compute_sums_kerneljPiS_
.globl _Z41__device_stub__Z20compute_final_kernelPijPij
.type _Z41__device_stub__Z20compute_final_kernelPijPij, @function
_Z41__device_stub__Z20compute_final_kernelPijPij:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20compute_final_kernelPij(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z41__device_stub__Z20compute_final_kernelPijPij, .-_Z41__device_stub__Z20compute_final_kernelPijPij
.globl _Z20compute_final_kernelPij
.type _Z20compute_final_kernelPij, @function
_Z20compute_final_kernelPij:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z20compute_final_kernelPijPij
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z20compute_final_kernelPij, .-_Z20compute_final_kernelPij
.section .rodata.str1.1
.LC1:
.string "cudaMemcpy"
.LC2:
.string "kernel execution 1"
.LC3:
.string "kernel execution 2"
.LC4:
.string "Failed!!! %d %d\n"
.LC5:
.string "Success!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $628, %esi
call cudaMalloc@PLT
movq %r13, %rbx
leaq 40000(%r13), %r12
movl $0, %ebp
.L24:
call rand@PLT
movl %eax, (%rbx)
addl %eax, %ebp
addq $4, %rbx
cmpq %r12, %rbx
jne .L24
movl $1, %ecx
movl $40000, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $157, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $256, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L25:
leaq .LC2(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $1, 16(%rsp)
movl $512, 28(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $2048, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L26:
leaq .LC3(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl 0(%r13), %ecx
cmpl %ebp, %ecx
jne .L33
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl $10000, %edi
call _Z42__device_stub__Z19compute_sums_kerneljPiS_jPiS_
jmp .L25
.L32:
movl $157, %esi
movq 8(%rsp), %rdi
call _Z41__device_stub__Z20compute_final_kernelPijPij
jmp .L26
.L33:
movl %ebp, %r8d
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z20compute_final_kernelPij"
.LC7:
.string "_Z19compute_sums_kerneljPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compute_final_kernelPij(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z19compute_sums_kerneljPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA-example-reduction.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl _Z34__device_stub__compute_sums_kerneljPiS_ # -- Begin function _Z34__device_stub__compute_sums_kerneljPiS_
.p2align 4, 0x90
.type _Z34__device_stub__compute_sums_kerneljPiS_,@function
_Z34__device_stub__compute_sums_kerneljPiS_: # @_Z34__device_stub__compute_sums_kerneljPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19compute_sums_kerneljPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z34__device_stub__compute_sums_kerneljPiS_, .Lfunc_end1-_Z34__device_stub__compute_sums_kerneljPiS_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__compute_final_kernelPij # -- Begin function _Z35__device_stub__compute_final_kernelPij
.p2align 4, 0x90
.type _Z35__device_stub__compute_final_kernelPij,@function
_Z35__device_stub__compute_final_kernelPij: # @_Z35__device_stub__compute_final_kernelPij
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20compute_final_kernelPij, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z35__device_stub__compute_final_kernelPij, .Lfunc_end2-_Z35__device_stub__compute_final_kernelPij
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
leaq 8(%rsp), %rdi
movl $628, %esi # imm = 0x274
callq hipMalloc
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%rbx,%r14,4)
addl %eax, %ebp
incq %r14
cmpq $10000, %r14 # imm = 0x2710
jne .LBB3_1
# %bb.2:
movq 16(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.5: # %_Z14checkCUDAErrorPKc.exit
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 63(%r14), %rdx
leaq 156(%r14), %rdi
movl $256, %r8d # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $10000, 92(%rsp) # imm = 0x2710
movq %rax, 80(%rsp)
movq %rcx, 40(%rsp)
leaq 92(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19compute_sums_kerneljPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_8
# %bb.9: # %_Z14checkCUDAErrorPKc.exit48
leaq 511(%r14), %rdx
movl $2048, %r8d # imm = 0x800
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $157, 24(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20compute_final_kernelPij, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_11:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_12
# %bb.13: # %_Z14checkCUDAErrorPKc.exit56
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB3_3
# %bb.14: # %_Z14checkCUDAErrorPKc.exit58
movl (%rbx), %edx
cmpl %ebp, %edx
jne .LBB3_16
# %bb.15:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
jmp .LBB3_4
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.2, %edx
jmp .LBB3_4
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.3, %edx
.LBB3_4:
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB3_16:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
movl %ebp, %ecx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19compute_sums_kerneljPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20compute_final_kernelPij, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type _Z19compute_sums_kerneljPiS_,@object # @_Z19compute_sums_kerneljPiS_
.section .rodata,"a",@progbits
.globl _Z19compute_sums_kerneljPiS_
.p2align 3, 0x0
_Z19compute_sums_kerneljPiS_:
.quad _Z34__device_stub__compute_sums_kerneljPiS_
.size _Z19compute_sums_kerneljPiS_, 8
.type _Z20compute_final_kernelPij,@object # @_Z20compute_final_kernelPij
.globl _Z20compute_final_kernelPij
.p2align 3, 0x0
_Z20compute_final_kernelPij:
.quad _Z35__device_stub__compute_final_kernelPij
.size _Z20compute_final_kernelPij, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "hipMemcpy"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "kernel execution 1"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel execution 2"
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed!!! %d %d\n"
.size .L.str.4, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19compute_sums_kerneljPiS_"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20compute_final_kernelPij"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Success!"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__compute_sums_kerneljPiS_
.addrsig_sym _Z35__device_stub__compute_final_kernelPij
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19compute_sums_kerneljPiS_
.addrsig_sym _Z20compute_final_kernelPij
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
cudaMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
cudaFree(gpuFloats);
return 0;
} | code for sm_80
Function : _Z8mykernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, 0x42f60000 ; /* 0x42f60000ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R10, c[0x0][0x180] ; /* 0x00006000000a7a02 */
/* 0x000fe20000000f00 */
/*00f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0100*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fc60000000f00 */
/*0110*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
cudaMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
cudaFree(gpuFloats);
return 0;
} | .file "tmpxft_00114892_00000000-6_test_buffers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.type _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_, @function
_Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mykernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_, .-_Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.globl _Z8mykernelPfS_S_S_S_
.type _Z8mykernelPfS_S_S_S_, @function
_Z8mykernelPfS_S_S_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8mykernelPfS_S_S_S_, .-_Z8mykernelPfS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i="
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L20
.L25:
movl $2, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L28
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
.L23:
movq 8(%rsp), %rdi
movq %rdi, %r8
movq %rdi, %rcx
movq %rdi, %rdx
movq %rdi, %rsi
call _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.L18:
addl $1, %ebx
cmpl $1000, %ebx
je .L29
.L20:
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %ebx
je .L25
cmpl $999, %ebx
je .L25
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
addl $1, %ebx
jmp .L20
.L28:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelPfS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPfS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
cudaMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
cudaFree(gpuFloats);
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
hipMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
hipFree(gpuFloats);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
hipMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
hipFree(gpuFloats);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelPfS_S_S_S_
.globl _Z8mykernelPfS_S_S_S_
.p2align 8
.type _Z8mykernelPfS_S_S_S_,@function
_Z8mykernelPfS_S_S_S_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x42f60000
s_waitcnt lgkmcnt(0)
s_clause 0x4
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
global_store_b32 v0, v1, s[8:9]
global_store_b32 v0, v1, s[10:11]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelPfS_S_S_S_, .Lfunc_end0-_Z8mykernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z8mykernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
__global__ void mykernel(float *d1, float *d2, float *d3, float *d4, float *d5) {
if(threadIdx.x == 0) {
d1[0] = 123.0f;
d2[0] = 123.0f;
d3[0] = 123.0f;
d4[0] = 123.0f;
d5[0] = 123.0f;
}
}
int main(int argc, char *argv[]) {
const int bufferSizeMegs = 512;
const int bufferSize = bufferSizeMegs * 1024 * 1024;
float *gpuFloats;
hipMalloc((void**)(&gpuFloats), bufferSize);
for(int i = 0; i < 1000; i++) {
if(i % 100 == 0 || i == 999) {
std::cout << "i=" << i << std::endl;
}
mykernel<<<dim3(1024, 1, 1), dim3(256, 1, 1)>>>(gpuFloats, gpuFloats, gpuFloats, gpuFloats, gpuFloats);
}
hipFree(gpuFloats);
return 0;
} | .text
.file "test_buffers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__mykernelPfS_S_S_S_ # -- Begin function _Z23__device_stub__mykernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPfS_S_S_S_,@function
_Z23__device_stub__mykernelPfS_S_S_S_: # @_Z23__device_stub__mykernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mykernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelPfS_S_S_S_, .Lfunc_end0-_Z23__device_stub__mykernelPfS_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967552, %rbx # imm = 0x100000100
movq %rsp, %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
xorl %r14d, %r14d
leaq 768(%rbx), %r15
leaq 96(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_1 Depth=1
incl %r14d
cmpl $1000, %r14d # imm = 0x3E8
je .LBB1_11
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $999, %r14d # imm = 0x3E7
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %r14d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $100, %eax, %eax
cmpl %r14d, %eax
jne .LBB1_8
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .LBB1_12
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r12)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_7
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax
movq %rax, 88(%rsp)
movq %rax, 80(%rsp)
movq %rax, 72(%rsp)
movq %rax, 64(%rsp)
movq %rax, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z8mykernelPfS_S_S_S_, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_10
.LBB1_11:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPfS_S_S_S_,@object # @_Z8mykernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8mykernelPfS_S_S_S_
.p2align 3, 0x0
_Z8mykernelPfS_S_S_S_:
.quad _Z23__device_stub__mykernelPfS_S_S_S_
.size _Z8mykernelPfS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i="
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8mykernelPfS_S_S_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPfS_S_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fda0003f05270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, 0x42f60000 ; /* 0x42f60000ff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ MOV R8, c[0x0][0x178] ; /* 0x00005e0000087a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R10, c[0x0][0x180] ; /* 0x00006000000a7a02 */
/* 0x000fe20000000f00 */
/*00f0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0100*/ MOV R11, c[0x0][0x184] ; /* 0x00006100000b7a02 */
/* 0x000fc60000000f00 */
/*0110*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe8000c101904 */
/*0120*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe8000c101904 */
/*0130*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x000fe8000c101904 */
/*0140*/ STG.E [R10.64], R13 ; /* 0x0000000d0a007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelPfS_S_S_S_
.globl _Z8mykernelPfS_S_S_S_
.p2align 8
.type _Z8mykernelPfS_S_S_S_,@function
_Z8mykernelPfS_S_S_S_:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x42f60000
s_waitcnt lgkmcnt(0)
s_clause 0x4
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v1, s[6:7]
global_store_b32 v0, v1, s[8:9]
global_store_b32 v0, v1, s[10:11]
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelPfS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 12
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelPfS_S_S_S_, .Lfunc_end0-_Z8mykernelPfS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelPfS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z8mykernelPfS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114892_00000000-6_test_buffers.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.type _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_, @function
_Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8mykernelPfS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_, .-_Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.globl _Z8mykernelPfS_S_S_S_
.type _Z8mykernelPfS_S_S_S_, @function
_Z8mykernelPfS_S_S_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8mykernelPfS_S_S_S_, .-_Z8mykernelPfS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "i="
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
movl $0, %ebx
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbp
jmp .L20
.L25:
movl $2, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %r13
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %r14
testq %r14, %r14
je .L28
cmpb $0, 56(%r14)
je .L16
movzbl 67(%r14), %esi
.L17:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
.L23:
movq 8(%rsp), %rdi
movq %rdi, %r8
movq %rdi, %rcx
movq %rdi, %rdx
movq %rdi, %rsi
call _Z35__device_stub__Z8mykernelPfS_S_S_S_PfS_S_S_S_
.L18:
addl $1, %ebx
cmpl $1000, %ebx
je .L29
.L20:
movslq %ebx, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %ebx
je .L25
cmpl $999, %ebx
je .L25
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
addl $1, %ebx
jmp .L20
.L28:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
call _ZSt16__throw_bad_castv@PLT
.L30:
call __stack_chk_fail@PLT
.L16:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L17
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z8mykernelPfS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPfS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_buffers.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__mykernelPfS_S_S_S_ # -- Begin function _Z23__device_stub__mykernelPfS_S_S_S_
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPfS_S_S_S_,@function
_Z23__device_stub__mykernelPfS_S_S_S_: # @_Z23__device_stub__mykernelPfS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mykernelPfS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelPfS_S_S_S_, .Lfunc_end0-_Z23__device_stub__mykernelPfS_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967552, %rbx # imm = 0x100000100
movq %rsp, %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
xorl %r14d, %r14d
leaq 768(%rbx), %r15
leaq 96(%rsp), %r13
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_10: # in Loop: Header=BB1_1 Depth=1
incl %r14d
cmpl $1000, %r14d # imm = 0x3E8
je .LBB1_11
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $999, %r14d # imm = 0x3E7
je .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl %r14d, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $37, %rax
imull $100, %eax, %eax
cmpl %r14d, %eax
jne .LBB1_8
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $2, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .LBB1_12
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
cmpb $0, 56(%r12)
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_1 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_7
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_1 Depth=1
movsbl %al, %esi
movq %rbp, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_8: # in Loop: Header=BB1_1 Depth=1
movq %r15, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9: # in Loop: Header=BB1_1 Depth=1
movq (%rsp), %rax
movq %rax, 88(%rsp)
movq %rax, 80(%rsp)
movq %rax, 72(%rsp)
movq %rax, 64(%rsp)
movq %rax, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z8mykernelPfS_S_S_S_, %edi
movq %r13, %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_10
.LBB1_11:
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPfS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPfS_S_S_S_,@object # @_Z8mykernelPfS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z8mykernelPfS_S_S_S_
.p2align 3, 0x0
_Z8mykernelPfS_S_S_S_:
.quad _Z23__device_stub__mykernelPfS_S_S_S_
.size _Z8mykernelPfS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i="
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8mykernelPfS_S_S_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPfS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPfS_S_S_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | code for sm_80
Function : _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x194], PT ; /* 0x0000650003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x190], P0 ; /* 0x0000640000007a0c */
/* 0x000fe20000706670 */
/*0090*/ IMAD R0, R3, c[0x0][0x190], R0 ; /* 0x0000640003007a24 */
/* 0x000fd800078e0200 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0100*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE R8, R0, R6, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fca00078e0206 */
/*0140*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R8.64+0x4] ; /* 0x0000040408077981 */
/* 0x000ee2000c1e1900 */
/*0160*/ BSSY B0, 0xf50 ; /* 0x00000de000007945 */
/* 0x000fe20003800000 */
/*0170*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0180*/ IADD3 R10, R11, 0xb, RZ ; /* 0x0000000b0b0a7810 */
/* 0x004fc80007ffe0ff */
/*0190*/ IMNMX R10, R10, R7, PT ; /* 0x000000070a0a7217 */
/* 0x008fc80003800200 */
/*01a0*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f06270 */
/*01b0*/ @P0 BRA 0xf40 ; /* 0x00000d8000000947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fe200078e33ff */
/*01d0*/ BSSY B1, 0x400 ; /* 0x0000022000017945 */
/* 0x000fe20003800000 */
/*01e0*/ IADD3 R3, -R11, -0xc, RZ ; /* 0xfffffff40b037810 */
/* 0x000fe40007ffe1ff */
/*01f0*/ LOP3.LUT R2, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff027212 */
/* 0x000fe400078e33ff */
/*0200*/ IMNMX R3, R3, R4, !PT ; /* 0x0000000403037217 */
/* 0x000fc80007800200 */
/*0210*/ IADD3 R2, R2, -R3, RZ ; /* 0x8000000302027210 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R3, -R3, -0x2, -R11 ; /* 0xfffffffe03037810 */
/* 0x000fe40007ffe90b */
/*0230*/ LOP3.LUT P1, R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe4000782c0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd2000001ff00 */
/*0260*/ @!P1 BRA 0x3f0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R16, RZ, RZ, 0x8 ; /* 0x00000008ff107424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.WIDE R8, R11, R6, c[0x0][0x170] ; /* 0x00005c000b087625 */
/* 0x000fc800078e0206 */
/*0290*/ IMAD.WIDE R2, R11, R16, c[0x0][0x180] ; /* 0x000060000b027625 */
/* 0x000fe200078e0210 */
/*02a0*/ MOV R7, R8 ; /* 0x0000000800077202 */
/* 0x000fc60000000f00 */
/*02b0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0003 */
/*02c0*/ MOV R14, R2 ; /* 0x00000002000e7202 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*02e0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*02f0*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fca0000000f00 */
/*0300*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea4000c1e1900 */
/*0310*/ IMAD.WIDE R8, R8, R16, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x004fcc00078e0210 */
/*0320*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R7, P3, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f7e0ff */
/*0350*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0360*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200018e060d */
/*0380*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x0040640000000002 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x001fe200078e000e */
/*03a0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fc40000000f00 */
/*03b0*/ IADD3 R14, P2, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc60007f5e0ff */
/*03c0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0021e2000c101b04 */
/*03d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*03e0*/ @P1 BRA 0x2f0 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 BRA 0xf40 ; /* 0x00000b3000008947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R9, R10, -R11, RZ ; /* 0x8000000b0a097210 */
/* 0x001fe20007ffe0ff */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0430*/ BSSY B1, 0xa90 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0440*/ IMAD.WIDE R6, R11, R6, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fe200078e0206 */
/*0450*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fc60003f24270 */
/*0460*/ IMAD.WIDE R12, R11, R4, c[0x0][0x180] ; /* 0x000060000b0c7625 */
/* 0x000fe200078e0204 */
/*0470*/ IADD3 R8, P0, R6, 0x8, RZ ; /* 0x0000000806087810 */
/* 0x000fc80007f1e0ff */
/*0480*/ IADD3 R6, P2, R12, 0x10, RZ ; /* 0x000000100c067810 */
/* 0x000fe20007f5e0ff */
/*0490*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0607 */
/*04a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*04b0*/ IADD3.X R7, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff077210 */
/* 0x000fe200017fe4ff */
/*04c0*/ @!P1 BRA 0xa80 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04e0*/ IADD3 R12, R10, -0xc, RZ ; /* 0xfffffff40a0c7810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ LDG.E R15, [R8.64+-0x8] ; /* 0xfffff804080f7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0510*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0520*/ DADD R2, R14, R2 ; /* 0x000000000e027229 */
/* 0x004e0e0000000002 */
/*0530*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0540*/ LDG.E R17, [R8.64+-0x4] ; /* 0xfffffc0408117981 */
/* 0x000ea4000c1e1900 */
/*0550*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0560*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0570*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x004e4e0000000010 */
/*0580*/ STG.E.64 [R6.64+-0x8], R18 ; /* 0xfffff81206007986 */
/* 0x0023e8000c101b04 */
/*0590*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x004fcc00078e0204 */
/*05b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1b00 */
/*05c0*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x004e8e0000000014 */
/*05d0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0045e8000c101b04 */
/*05e0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */
/* 0x001ee4000c1e1900 */
/*05f0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0600*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0610*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x008e0e0000000002 */
/*0620*/ STG.E.64 [R6.64+0x8], R16 ; /* 0x0000081006007986 */
/* 0x0011e8000c101b04 */
/*0630*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080408137981 */
/* 0x002ee4000c1e1900 */
/*0640*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x008fcc00078e0204 */
/*0650*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*0660*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x008e4e0000000012 */
/*0670*/ STG.E.64 [R6.64+0x10], R20 ; /* 0x0000101406007986 */
/* 0x0023e8000c101b04 */
/*0680*/ LDG.E R15, [R8.64+0xc] ; /* 0x00000c04080f7981 */
/* 0x004ea4000c1e1900 */
/*0690*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*06a0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*06b0*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x004e8e000000000e */
/*06c0*/ STG.E.64 [R6.64+0x18], R2 ; /* 0x0000180206007986 */
/* 0x0045e8000c101b04 */
/*06d0*/ LDG.E R17, [R8.64+0x10] ; /* 0x0000100408117981 */
/* 0x001ee4000c1e1900 */
/*06e0*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x008fcc00078e0204 */
/*06f0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1b00 */
/*0700*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x008e0e0000000010 */
/*0710*/ STG.E.64 [R6.64+0x20], R18 ; /* 0x0000201206007986 */
/* 0x0011e8000c101b04 */
/*0720*/ LDG.E R21, [R8.64+0x14] ; /* 0x0000140408157981 */
/* 0x002ee4000c1e1900 */
/*0730*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x008fcc00078e0204 */
/*0740*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee4000c1e1b00 */
/*0750*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x008e4e0000000014 */
/*0760*/ STG.E.64 [R6.64+0x28], R14 ; /* 0x0000280e06007986 */
/* 0x0023e8000c101b04 */
/*0770*/ LDG.E R3, [R8.64+0x18] ; /* 0x0000180408037981 */
/* 0x004ea4000c1e1900 */
/*0780*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x004fcc00078e0204 */
/*0790*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*07a0*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x004e8e0000000002 */
/*07b0*/ STG.E.64 [R6.64+0x30], R16 ; /* 0x0000301006007986 */
/* 0x0045e8000c101b04 */
/*07c0*/ LDG.E R19, [R8.64+0x1c] ; /* 0x00001c0408137981 */
/* 0x001ee4000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x008fcc00078e0204 */
/*07e0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*07f0*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x008e0e0000000012 */
/*0800*/ STG.E.64 [R6.64+0x38], R20 ; /* 0x0000381406007986 */
/* 0x0011e8000c101b04 */
/*0810*/ LDG.E R15, [R8.64+0x20] ; /* 0x00002004080f7981 */
/* 0x002ee4000c1e1900 */
/*0820*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x008fcc00078e0204 */
/*0830*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1b00 */
/*0840*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x008e4e000000000e */
/*0850*/ STG.E.64 [R6.64+0x40], R2 ; /* 0x0000400206007986 */
/* 0x0023e8000c101b04 */
/*0860*/ LDG.E R17, [R8.64+0x24] ; /* 0x0000240408117981 */
/* 0x004ea4000c1e1900 */
/*0870*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0880*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0890*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x004e8e0000000010 */
/*08a0*/ STG.E.64 [R6.64+0x48], R18 ; /* 0x0000481206007986 */
/* 0x0045e8000c101b04 */
/*08b0*/ LDG.E R21, [R8.64+0x28] ; /* 0x0000280408157981 */
/* 0x001ee4000c1e1900 */
/*08c0*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x008fcc00078e0204 */
/*08d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee4000c1e1b00 */
/*08e0*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x008e0e0000000014 */
/*08f0*/ STG.E.64 [R6.64+0x50], R14 ; /* 0x0000500e06007986 */
/* 0x0011e8000c101b04 */
/*0900*/ LDG.E R3, [R8.64+0x2c] ; /* 0x00002c0408037981 */
/* 0x002ee4000c1e1900 */
/*0910*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0920*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0930*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x008e4e0000000002 */
/*0940*/ STG.E.64 [R6.64+0x58], R16 ; /* 0x0000581006007986 */
/* 0x0023e8000c101b04 */
/*0950*/ LDG.E R19, [R8.64+0x30] ; /* 0x0000300408137981 */
/* 0x004ea4000c1e1900 */
/*0960*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0970*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*0980*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x004e8e0000000012 */
/*0990*/ STG.E.64 [R6.64+0x60], R20 ; /* 0x0000601406007986 */
/* 0x004fe8000c101b04 */
/*09a0*/ LDG.E R15, [R8.64+0x34] ; /* 0x00003404080f7981 */
/* 0x001ea2000c1e1900 */
/*09b0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*09c0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*09d0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1b00 */
/*09e0*/ ISETP.GE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f26270 */
/*09f0*/ IADD3 R13, P3, R6, 0x80, RZ ; /* 0x00000080060d7810 */
/* 0x000fe40007f7e0ff */
/*0a00*/ IADD3 R8, P2, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x000fe40007f5e0ff */
/*0a10*/ IADD3.X R16, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff107210 */
/* 0x002fc60001ffe4ff */
/*0a20*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0a30*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x004e0e000000000e */
/*0a40*/ STG.E.64 [R6.64+0x68], R2 ; /* 0x0000680206007986 */
/* 0x0011e4000c101b04 */
/*0a50*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000d */
/*0a60*/ MOV R7, R16 ; /* 0x0000001000077202 */
/* 0x000fe20000000f00 */
/*0a70*/ @!P1 BRA 0x4f0 ; /* 0xfffffa7000009947 */
/* 0x000fea000383ffff */
/*0a80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a90*/ IMAD.IADD R12, R10, 0x1, -R11 ; /* 0x000000010a0c7824 */
/* 0x000fe200078e0a0b */
/*0aa0*/ BSSY B1, 0xde0 ; /* 0x0000033000017945 */
/* 0x000fe80003800000 */
/*0ab0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0ac0*/ @!P1 BRA 0xdd0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R13, [R8.64+-0x8] ; /* 0xfffff804080d7981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0af0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0b00*/ DADD R2, R2, R12 ; /* 0x0000000002027229 */
/* 0x004e0e000000000c */
/*0b10*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0b20*/ LDG.E R15, [R8.64+-0x4] ; /* 0xfffffc04080f7981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0b40*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ DADD R16, R2, R14 ; /* 0x0000000002107229 */
/* 0x004e4e000000000e */
/*0b60*/ STG.E.64 [R6.64+-0x8], R16 ; /* 0xfffff81006007986 */
/* 0x0023e8000c101b04 */
/*0b70*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0b90*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*0ba0*/ DADD R12, R16, R18 ; /* 0x00000000100c7229 */
/* 0x004e8e0000000012 */
/*0bb0*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0045e8000c101b04 */
/*0bc0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */
/* 0x001ee4000c1e1900 */
/*0bd0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0be0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0bf0*/ DADD R14, R12, R2 ; /* 0x000000000c0e7229 */
/* 0x008e0e0000000002 */
/*0c00*/ STG.E.64 [R6.64+0x8], R14 ; /* 0x0000080e06007986 */
/* 0x0011e8000c101b04 */
/*0c10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x002ee4000c1e1900 */
/*0c20*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x008fcc00078e0204 */
/*0c30*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1b00 */
/*0c40*/ DADD R18, R14, R16 ; /* 0x000000000e127229 */
/* 0x008e4e0000000010 */
/*0c50*/ STG.E.64 [R6.64+0x10], R18 ; /* 0x0000101206007986 */
/* 0x0023e8000c101b04 */
/*0c60*/ LDG.E R13, [R8.64+0xc] ; /* 0x00000c04080d7981 */
/* 0x004ea4000c1e1900 */
/*0c70*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0c80*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0c90*/ DADD R20, R18, R12 ; /* 0x0000000012147229 */
/* 0x004e8e000000000c */
/*0ca0*/ STG.E.64 [R6.64+0x18], R20 ; /* 0x0000181406007986 */
/* 0x004fe8000c101b04 */
/*0cb0*/ LDG.E R15, [R8.64+0x10] ; /* 0x00001004080f7981 */
/* 0x001ea4000c1e1900 */
/*0cc0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0cd0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0ce0*/ DADD R16, R20, R14 ; /* 0x0000000014107229 */
/* 0x004e0e000000000e */
/*0cf0*/ STG.E.64 [R6.64+0x20], R16 ; /* 0x0000201006007986 */
/* 0x001fe8000c101b04 */
/*0d00*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x002ea4000c1e1900 */
/*0d10*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0d20*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*0d30*/ IADD3 R12, P2, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x000fe40007f5e0ff */
/*0d40*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe40007f3e0ff */
/*0d50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0d60*/ IMAD.X R13, RZ, RZ, R7, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0607 */
/*0d70*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*0d80*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007ffe0ff */
/*0d90*/ DADD R2, R16, R18 ; /* 0x0000000010027229 */
/* 0x004e0e0000000012 */
/*0da0*/ STG.E.64 [R6.64+0x28], R2 ; /* 0x0000280206007986 */
/* 0x0011e4000c101b04 */
/*0db0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*0dc0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.LT.OR P0, PT, R11, R10, P0 ; /* 0x0000000a0b00720c */
/* 0x000fda0000701670 */
/*0df0*/ @!P0 BRA 0xf40 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0e00*/ LDG.E R11, [R8.64+-0x8] ; /* 0xfffff804080b7981 */
/* 0x000ea4000c1e1900 */
/*0e10*/ IMAD.WIDE R10, R11, R4, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x004fcc00078e0204 */
/*0e20*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*0e30*/ DADD R2, R2, R10 ; /* 0x0000000002027229 */
/* 0x004e0e000000000a */
/*0e40*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0e50*/ LDG.E R13, [R8.64+-0x4] ; /* 0xfffffc04080d7981 */
/* 0x000ea4000c1e1900 */
/*0e60*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0e70*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0e80*/ DADD R14, R2, R12 ; /* 0x00000000020e7229 */
/* 0x004e4e000000000c */
/*0e90*/ STG.E.64 [R6.64+-0x8], R14 ; /* 0xfffff80e06007986 */
/* 0x0023e8000c101b04 */
/*0ea0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea4000c1e1900 */
/*0eb0*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0ec0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0ed0*/ DADD R10, R14, R16 ; /* 0x000000000e0a7229 */
/* 0x004e8e0000000010 */
/*0ee0*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0043e8000c101b04 */
/*0ef0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x000ea4000c1e1900 */
/*0f00*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0f10*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e24000c1e1b00 */
/*0f20*/ DADD R2, R10, R18 ; /* 0x000000000a027229 */
/* 0x001e0e0000000012 */
/*0f30*/ STG.E.64 [R6.64+0x8], R2 ; /* 0x0000080206007986 */
/* 0x0013e8000c101b04 */
/*0f40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f50*/ LEA R4, P0, R0, c[0x0][0x188], 0x3 ; /* 0x0000620000047a11 */
/* 0x000fc800078018ff */
/*0f60*/ LEA.HI.X R5, R0, c[0x0][0x18c], R5, 0x3, P0 ; /* 0x0000630000057a11 */
/* 0x000fca00000f1c05 */
/*0f70*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0f80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f90*/ BRA 0xf90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .file "tmpxft_0018c9de_00000000-6_find_all_sums_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
.type _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii, @function
_Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii, .-_Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, @function
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, .-_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 8
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii,@function
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x30
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x20
v_add_nc_u32_e32 v4, 11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, v3, v4
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_4:
global_load_b32 v11, v[6:7], off
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
global_load_b64 v[11:12], v[11:12], off
v_cmp_ge_i32_e32 vcc_lo, v2, v10
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[11:12]
global_store_b64 v[8:9], v[4:5], off
v_add_co_u32 v8, s2, v8, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, .Lfunc_end0-_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void find_all_sums_kernel(bool *mask, double *node_weight, int *neighbor, int *neighbor_start, double *neighbor_accum_weight_result, double *sum_weight_result, int width, int height){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
int nid = y * width + x; // thread_index is node id
if (x < width && y < height && mask[nid]){
double sum = 0.0;
int end = min(neighbor_start[nid+1], neighbor_start[nid]+HUB_THREASHOLD+1); //+1 because HUB_THREASHOLD is out degree
for (int eid = neighbor_start[nid]; eid < end; eid++) { // this eid is just index of the neighbor in the neighbor array
sum += node_weight[neighbor[eid]];
neighbor_accum_weight_result[eid] = sum;
}
sum_weight_result[nid] = sum;
}
} | .text
.file "find_all_sums_kernel.hip"
.globl _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii # -- Begin function _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 4, 0x90
.type _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii,@function
_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii: # @_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii, .Lfunc_end0-_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii,@object # @_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .rodata,"a",@progbits
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 3, 0x0
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
.quad _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x194], PT ; /* 0x0000650003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x190], P0 ; /* 0x0000640000007a0c */
/* 0x000fe20000706670 */
/*0090*/ IMAD R0, R3, c[0x0][0x190], R0 ; /* 0x0000640003007a24 */
/* 0x000fd800078e0200 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe20000011400 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R5, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590005037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1100 */
/*0100*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0110*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE R8, R0, R6, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fca00078e0206 */
/*0140*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R7, [R8.64+0x4] ; /* 0x0000040408077981 */
/* 0x000ee2000c1e1900 */
/*0160*/ BSSY B0, 0xf50 ; /* 0x00000de000007945 */
/* 0x000fe20003800000 */
/*0170*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0180*/ IADD3 R10, R11, 0xb, RZ ; /* 0x0000000b0b0a7810 */
/* 0x004fc80007ffe0ff */
/*0190*/ IMNMX R10, R10, R7, PT ; /* 0x000000070a0a7217 */
/* 0x008fc80003800200 */
/*01a0*/ ISETP.GE.AND P0, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f06270 */
/*01b0*/ @P0 BRA 0xf40 ; /* 0x00000d8000000947 */
/* 0x000fea0003800000 */
/*01c0*/ LOP3.LUT R4, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff047212 */
/* 0x000fe200078e33ff */
/*01d0*/ BSSY B1, 0x400 ; /* 0x0000022000017945 */
/* 0x000fe20003800000 */
/*01e0*/ IADD3 R3, -R11, -0xc, RZ ; /* 0xfffffff40b037810 */
/* 0x000fe40007ffe1ff */
/*01f0*/ LOP3.LUT R2, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff027212 */
/* 0x000fe400078e33ff */
/*0200*/ IMNMX R3, R3, R4, !PT ; /* 0x0000000403037217 */
/* 0x000fc80007800200 */
/*0210*/ IADD3 R2, R2, -R3, RZ ; /* 0x8000000302027210 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R3, -R3, -0x2, -R11 ; /* 0xfffffffe03037810 */
/* 0x000fe40007ffe90b */
/*0230*/ LOP3.LUT P1, R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe4000782c0ff */
/*0240*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0250*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd2000001ff00 */
/*0260*/ @!P1 BRA 0x3f0 ; /* 0x0000018000009947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.MOV.U32 R16, RZ, RZ, 0x8 ; /* 0x00000008ff107424 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.WIDE R8, R11, R6, c[0x0][0x170] ; /* 0x00005c000b087625 */
/* 0x000fc800078e0206 */
/*0290*/ IMAD.WIDE R2, R11, R16, c[0x0][0x180] ; /* 0x000060000b027625 */
/* 0x000fe200078e0210 */
/*02a0*/ MOV R7, R8 ; /* 0x0000000800077202 */
/* 0x000fc60000000f00 */
/*02b0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0003 */
/*02c0*/ MOV R14, R2 ; /* 0x00000002000e7202 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0009 */
/*02e0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe4000001ff00 */
/*02f0*/ MOV R12, R7 ; /* 0x00000007000c7202 */
/* 0x000fca0000000f00 */
/*0300*/ LDG.E R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea4000c1e1900 */
/*0310*/ IMAD.WIDE R8, R8, R16, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x004fcc00078e0210 */
/*0320*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0340*/ IADD3 R7, P3, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007f7e0ff */
/*0350*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f25270 */
/*0360*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe20007ffe0ff */
/*0370*/ IMAD.X R13, RZ, RZ, R13, P3 ; /* 0x000000ffff0d7224 */
/* 0x000fe200018e060d */
/*0380*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x0040640000000002 */
/*0390*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x001fe200078e000e */
/*03a0*/ MOV R9, R15 ; /* 0x0000000f00097202 */
/* 0x000fc40000000f00 */
/*03b0*/ IADD3 R14, P2, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fc60007f5e0ff */
/*03c0*/ STG.E.64 [R8.64], R2 ; /* 0x0000000208007986 */
/* 0x0021e2000c101b04 */
/*03d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*03e0*/ @P1 BRA 0x2f0 ; /* 0xffffff0000001947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 BRA 0xf40 ; /* 0x00000b3000008947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R9, R10, -R11, RZ ; /* 0x8000000b0a097210 */
/* 0x001fe20007ffe0ff */
/*0420*/ IMAD.MOV.U32 R4, RZ, RZ, 0x8 ; /* 0x00000008ff047424 */
/* 0x000fe200078e00ff */
/*0430*/ BSSY B1, 0xa90 ; /* 0x0000065000017945 */
/* 0x000fe20003800000 */
/*0440*/ IMAD.WIDE R6, R11, R6, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fe200078e0206 */
/*0450*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fc60003f24270 */
/*0460*/ IMAD.WIDE R12, R11, R4, c[0x0][0x180] ; /* 0x000060000b0c7625 */
/* 0x000fe200078e0204 */
/*0470*/ IADD3 R8, P0, R6, 0x8, RZ ; /* 0x0000000806087810 */
/* 0x000fc80007f1e0ff */
/*0480*/ IADD3 R6, P2, R12, 0x10, RZ ; /* 0x000000100c067810 */
/* 0x000fe20007f5e0ff */
/*0490*/ IMAD.X R9, RZ, RZ, R7, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0607 */
/*04a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*04b0*/ IADD3.X R7, RZ, R13, RZ, P2, !PT ; /* 0x0000000dff077210 */
/* 0x000fe200017fe4ff */
/*04c0*/ @!P1 BRA 0xa80 ; /* 0x000005b000009947 */
/* 0x000fea0003800000 */
/*04d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04e0*/ IADD3 R12, R10, -0xc, RZ ; /* 0xfffffff40a0c7810 */
/* 0x000fc60007ffe0ff */
/*04f0*/ LDG.E R15, [R8.64+-0x8] ; /* 0xfffff804080f7981 */
/* 0x000ea4000c1e1900 */
/*0500*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0510*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0520*/ DADD R2, R14, R2 ; /* 0x000000000e027229 */
/* 0x004e0e0000000002 */
/*0530*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0540*/ LDG.E R17, [R8.64+-0x4] ; /* 0xfffffc0408117981 */
/* 0x000ea4000c1e1900 */
/*0550*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0560*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0570*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x004e4e0000000010 */
/*0580*/ STG.E.64 [R6.64+-0x8], R18 ; /* 0xfffff81206007986 */
/* 0x0023e8000c101b04 */
/*0590*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x004fcc00078e0204 */
/*05b0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea4000c1e1b00 */
/*05c0*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x004e8e0000000014 */
/*05d0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0045e8000c101b04 */
/*05e0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */
/* 0x001ee4000c1e1900 */
/*05f0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0600*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0610*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x008e0e0000000002 */
/*0620*/ STG.E.64 [R6.64+0x8], R16 ; /* 0x0000081006007986 */
/* 0x0011e8000c101b04 */
/*0630*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080408137981 */
/* 0x002ee4000c1e1900 */
/*0640*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x008fcc00078e0204 */
/*0650*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*0660*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x008e4e0000000012 */
/*0670*/ STG.E.64 [R6.64+0x10], R20 ; /* 0x0000101406007986 */
/* 0x0023e8000c101b04 */
/*0680*/ LDG.E R15, [R8.64+0xc] ; /* 0x00000c04080f7981 */
/* 0x004ea4000c1e1900 */
/*0690*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*06a0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*06b0*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x004e8e000000000e */
/*06c0*/ STG.E.64 [R6.64+0x18], R2 ; /* 0x0000180206007986 */
/* 0x0045e8000c101b04 */
/*06d0*/ LDG.E R17, [R8.64+0x10] ; /* 0x0000100408117981 */
/* 0x001ee4000c1e1900 */
/*06e0*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x008fcc00078e0204 */
/*06f0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1b00 */
/*0700*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x008e0e0000000010 */
/*0710*/ STG.E.64 [R6.64+0x20], R18 ; /* 0x0000201206007986 */
/* 0x0011e8000c101b04 */
/*0720*/ LDG.E R21, [R8.64+0x14] ; /* 0x0000140408157981 */
/* 0x002ee4000c1e1900 */
/*0730*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x008fcc00078e0204 */
/*0740*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee4000c1e1b00 */
/*0750*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x008e4e0000000014 */
/*0760*/ STG.E.64 [R6.64+0x28], R14 ; /* 0x0000280e06007986 */
/* 0x0023e8000c101b04 */
/*0770*/ LDG.E R3, [R8.64+0x18] ; /* 0x0000180408037981 */
/* 0x004ea4000c1e1900 */
/*0780*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x004fcc00078e0204 */
/*0790*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1b00 */
/*07a0*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x004e8e0000000002 */
/*07b0*/ STG.E.64 [R6.64+0x30], R16 ; /* 0x0000301006007986 */
/* 0x0045e8000c101b04 */
/*07c0*/ LDG.E R19, [R8.64+0x1c] ; /* 0x00001c0408137981 */
/* 0x001ee4000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x008fcc00078e0204 */
/*07e0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee4000c1e1b00 */
/*07f0*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x008e0e0000000012 */
/*0800*/ STG.E.64 [R6.64+0x38], R20 ; /* 0x0000381406007986 */
/* 0x0011e8000c101b04 */
/*0810*/ LDG.E R15, [R8.64+0x20] ; /* 0x00002004080f7981 */
/* 0x002ee4000c1e1900 */
/*0820*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x008fcc00078e0204 */
/*0830*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee4000c1e1b00 */
/*0840*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x008e4e000000000e */
/*0850*/ STG.E.64 [R6.64+0x40], R2 ; /* 0x0000400206007986 */
/* 0x0023e8000c101b04 */
/*0860*/ LDG.E R17, [R8.64+0x24] ; /* 0x0000240408117981 */
/* 0x004ea4000c1e1900 */
/*0870*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0880*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0890*/ DADD R18, R2, R16 ; /* 0x0000000002127229 */
/* 0x004e8e0000000010 */
/*08a0*/ STG.E.64 [R6.64+0x48], R18 ; /* 0x0000481206007986 */
/* 0x0045e8000c101b04 */
/*08b0*/ LDG.E R21, [R8.64+0x28] ; /* 0x0000280408157981 */
/* 0x001ee4000c1e1900 */
/*08c0*/ IMAD.WIDE R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x008fcc00078e0204 */
/*08d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ee4000c1e1b00 */
/*08e0*/ DADD R14, R18, R20 ; /* 0x00000000120e7229 */
/* 0x008e0e0000000014 */
/*08f0*/ STG.E.64 [R6.64+0x50], R14 ; /* 0x0000500e06007986 */
/* 0x0011e8000c101b04 */
/*0900*/ LDG.E R3, [R8.64+0x2c] ; /* 0x00002c0408037981 */
/* 0x002ee4000c1e1900 */
/*0910*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0920*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0930*/ DADD R16, R14, R2 ; /* 0x000000000e107229 */
/* 0x008e4e0000000002 */
/*0940*/ STG.E.64 [R6.64+0x58], R16 ; /* 0x0000581006007986 */
/* 0x0023e8000c101b04 */
/*0950*/ LDG.E R19, [R8.64+0x30] ; /* 0x0000300408137981 */
/* 0x004ea4000c1e1900 */
/*0960*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0970*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*0980*/ DADD R20, R16, R18 ; /* 0x0000000010147229 */
/* 0x004e8e0000000012 */
/*0990*/ STG.E.64 [R6.64+0x60], R20 ; /* 0x0000601406007986 */
/* 0x004fe8000c101b04 */
/*09a0*/ LDG.E R15, [R8.64+0x34] ; /* 0x00003404080f7981 */
/* 0x001ea2000c1e1900 */
/*09b0*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*09c0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*09d0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1b00 */
/*09e0*/ ISETP.GE.AND P1, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fe40003f26270 */
/*09f0*/ IADD3 R13, P3, R6, 0x80, RZ ; /* 0x00000080060d7810 */
/* 0x000fe40007f7e0ff */
/*0a00*/ IADD3 R8, P2, R8, 0x40, RZ ; /* 0x0000004008087810 */
/* 0x000fe40007f5e0ff */
/*0a10*/ IADD3.X R16, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff107210 */
/* 0x002fc60001ffe4ff */
/*0a20*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*0a30*/ DADD R2, R20, R14 ; /* 0x0000000014027229 */
/* 0x004e0e000000000e */
/*0a40*/ STG.E.64 [R6.64+0x68], R2 ; /* 0x0000680206007986 */
/* 0x0011e4000c101b04 */
/*0a50*/ IMAD.MOV.U32 R6, RZ, RZ, R13 ; /* 0x000000ffff067224 */
/* 0x001fe200078e000d */
/*0a60*/ MOV R7, R16 ; /* 0x0000001000077202 */
/* 0x000fe20000000f00 */
/*0a70*/ @!P1 BRA 0x4f0 ; /* 0xfffffa7000009947 */
/* 0x000fea000383ffff */
/*0a80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a90*/ IMAD.IADD R12, R10, 0x1, -R11 ; /* 0x000000010a0c7824 */
/* 0x000fe200078e0a0b */
/*0aa0*/ BSSY B1, 0xde0 ; /* 0x0000033000017945 */
/* 0x000fe80003800000 */
/*0ab0*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0ac0*/ @!P1 BRA 0xdd0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*0ad0*/ LDG.E R13, [R8.64+-0x8] ; /* 0xfffff804080d7981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0af0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0b00*/ DADD R2, R2, R12 ; /* 0x0000000002027229 */
/* 0x004e0e000000000c */
/*0b10*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0b20*/ LDG.E R15, [R8.64+-0x4] ; /* 0xfffffc04080f7981 */
/* 0x000ea4000c1e1900 */
/*0b30*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0b40*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ DADD R16, R2, R14 ; /* 0x0000000002107229 */
/* 0x004e4e000000000e */
/*0b60*/ STG.E.64 [R6.64+-0x8], R16 ; /* 0xfffff81006007986 */
/* 0x0023e8000c101b04 */
/*0b70*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0b90*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*0ba0*/ DADD R12, R16, R18 ; /* 0x00000000100c7229 */
/* 0x004e8e0000000012 */
/*0bb0*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0045e8000c101b04 */
/*0bc0*/ LDG.E R3, [R8.64+0x4] ; /* 0x0000040408037981 */
/* 0x001ee4000c1e1900 */
/*0bd0*/ IMAD.WIDE R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x008fcc00078e0204 */
/*0be0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee4000c1e1b00 */
/*0bf0*/ DADD R14, R12, R2 ; /* 0x000000000c0e7229 */
/* 0x008e0e0000000002 */
/*0c00*/ STG.E.64 [R6.64+0x8], R14 ; /* 0x0000080e06007986 */
/* 0x0011e8000c101b04 */
/*0c10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x002ee4000c1e1900 */
/*0c20*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x008fcc00078e0204 */
/*0c30*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee4000c1e1b00 */
/*0c40*/ DADD R18, R14, R16 ; /* 0x000000000e127229 */
/* 0x008e4e0000000010 */
/*0c50*/ STG.E.64 [R6.64+0x10], R18 ; /* 0x0000101206007986 */
/* 0x0023e8000c101b04 */
/*0c60*/ LDG.E R13, [R8.64+0xc] ; /* 0x00000c04080d7981 */
/* 0x004ea4000c1e1900 */
/*0c70*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0c80*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0c90*/ DADD R20, R18, R12 ; /* 0x0000000012147229 */
/* 0x004e8e000000000c */
/*0ca0*/ STG.E.64 [R6.64+0x18], R20 ; /* 0x0000181406007986 */
/* 0x004fe8000c101b04 */
/*0cb0*/ LDG.E R15, [R8.64+0x10] ; /* 0x00001004080f7981 */
/* 0x001ea4000c1e1900 */
/*0cc0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x004fcc00078e0204 */
/*0cd0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*0ce0*/ DADD R16, R20, R14 ; /* 0x0000000014107229 */
/* 0x004e0e000000000e */
/*0cf0*/ STG.E.64 [R6.64+0x20], R16 ; /* 0x0000201006007986 */
/* 0x001fe8000c101b04 */
/*0d00*/ LDG.E R19, [R8.64+0x14] ; /* 0x0000140408137981 */
/* 0x002ea4000c1e1900 */
/*0d10*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0d20*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1b00 */
/*0d30*/ IADD3 R12, P2, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x000fe40007f5e0ff */
/*0d40*/ IADD3 R8, P1, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x000fe40007f3e0ff */
/*0d50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0d60*/ IMAD.X R13, RZ, RZ, R7, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0607 */
/*0d70*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe40000ffe4ff */
/*0d80*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe20007ffe0ff */
/*0d90*/ DADD R2, R16, R18 ; /* 0x0000000010027229 */
/* 0x004e0e0000000012 */
/*0da0*/ STG.E.64 [R6.64+0x28], R2 ; /* 0x0000280206007986 */
/* 0x0011e4000c101b04 */
/*0db0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*0dc0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0dd0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0de0*/ ISETP.LT.OR P0, PT, R11, R10, P0 ; /* 0x0000000a0b00720c */
/* 0x000fda0000701670 */
/*0df0*/ @!P0 BRA 0xf40 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0e00*/ LDG.E R11, [R8.64+-0x8] ; /* 0xfffff804080b7981 */
/* 0x000ea4000c1e1900 */
/*0e10*/ IMAD.WIDE R10, R11, R4, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x004fcc00078e0204 */
/*0e20*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e1b00 */
/*0e30*/ DADD R2, R2, R10 ; /* 0x0000000002027229 */
/* 0x004e0e000000000a */
/*0e40*/ STG.E.64 [R6.64+-0x10], R2 ; /* 0xfffff00206007986 */
/* 0x0011e8000c101b04 */
/*0e50*/ LDG.E R13, [R8.64+-0x4] ; /* 0xfffffc04080d7981 */
/* 0x000ea4000c1e1900 */
/*0e60*/ IMAD.WIDE R12, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x004fcc00078e0204 */
/*0e70*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1b00 */
/*0e80*/ DADD R14, R2, R12 ; /* 0x00000000020e7229 */
/* 0x004e4e000000000c */
/*0e90*/ STG.E.64 [R6.64+-0x8], R14 ; /* 0xfffff80e06007986 */
/* 0x0023e8000c101b04 */
/*0ea0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea4000c1e1900 */
/*0eb0*/ IMAD.WIDE R16, R17, R4, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x004fcc00078e0204 */
/*0ec0*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea4000c1e1b00 */
/*0ed0*/ DADD R10, R14, R16 ; /* 0x000000000e0a7229 */
/* 0x004e8e0000000010 */
/*0ee0*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0043e8000c101b04 */
/*0ef0*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040408137981 */
/* 0x000ea4000c1e1900 */
/*0f00*/ IMAD.WIDE R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x004fcc00078e0204 */
/*0f10*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000e24000c1e1b00 */
/*0f20*/ DADD R2, R10, R18 ; /* 0x000000000a027229 */
/* 0x001e0e0000000012 */
/*0f30*/ STG.E.64 [R6.64+0x8], R2 ; /* 0x0000080206007986 */
/* 0x0013e8000c101b04 */
/*0f40*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f50*/ LEA R4, P0, R0, c[0x0][0x188], 0x3 ; /* 0x0000620000047a11 */
/* 0x000fc800078018ff */
/*0f60*/ LEA.HI.X R5, R0, c[0x0][0x18c], R5, 0x3, P0 ; /* 0x0000630000057a11 */
/* 0x000fca00000f1c05 */
/*0f70*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0f80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f90*/ BRA 0xf90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 8
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii,@function
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b64 s[4:5], s[0:1], 0x30
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[2:3], s[0:1], 0x18
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v3, v2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x20
v_add_nc_u32_e32 v4, 11, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_min_i32_e32 v10, v3, v4
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_mov_b32 s6, 0
.p2align 6
.LBB0_4:
global_load_b32 v11, v[6:7], off
v_add_nc_u32_e32 v2, 1, v2
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v11, vcc_lo, s4, v11
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 4
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
global_load_b64 v[11:12], v[11:12], off
v_cmp_ge_i32_e32 vcc_lo, v2, v10
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[11:12]
global_store_b64 v[8:9], v[4:5], off
v_add_co_u32 v8, s2, v8, 8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, 0, v9, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x28
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[4:5], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, .Lfunc_end0-_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018c9de_00000000-6_find_all_sums_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
.type _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii, @function
_Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii, .-_Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, @function
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z20find_all_sums_kernelPbPdPiS1_S0_S0_iiPbPdPiS1_S0_S0_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, .-_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "find_all_sums_kernel.hip"
.globl _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii # -- Begin function _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 4, 0x90
.type _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii,@function
_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii: # @_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii, .Lfunc_end0-_Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii,@object # @_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.section .rodata,"a",@progbits
.globl _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.p2align 3, 0x0
_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii:
.quad _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.size _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__find_all_sums_kernelPbPdPiS1_S0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20find_all_sums_kernelPbPdPiS1_S0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; | .file "tmpxft_000c152d_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3758:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3758:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "basic_string::append"
.LC1:
.string "0"
.text
.globl _Z14zeropad_numberB5cxx11i
.type _Z14zeropad_numberB5cxx11i, @function
_Z14zeropad_numberB5cxx11i:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $472, %rsp
.cfi_def_cfa_offset 528
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %r12
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
movq $0, 408(%rsp)
movb $0, 416(%rsp)
movb $0, 417(%rsp)
movq $0, 424(%rsp)
movq $0, 432(%rsp)
movq $0, 440(%rsp)
movq $0, 448(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq $0, 72(%rsp)
movq 64(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq 80(%rsp), %rax
movq -24(%rax), %rax
leaq 80(%rsp,%rax), %rdi
movl $0, %esi
.LEHB1:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE1:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 80(%rax), %rax
movq %rax, 192(%rsp)
leaq -40(%rax), %rax
movq %rax, 80(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movl $24, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
movq $0, 168(%rsp)
movb $0, 176(%rsp)
leaq 88(%rsp), %rsi
leaq 192(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L54
.L45:
endbr64
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp)
movq -24(%rcx), %rdx
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rdx)
movq $0, 72(%rsp)
movq %rax, %rbx
.L8:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L44:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movq 160(%rsp), %rdi
leaq 176(%rsp), %rax
cmpq %rax, %rdi
je .L10
movq 176(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L10:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rbp
leaq 144(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rbp, %rdi
call _ZNSdD2Ev@PLT
jmp .L8
.L43:
endbr64
movq %rax, %rbx
jmp .L8
.L11:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L54:
leaq 80(%rsp), %rdi
movl %ebp, %esi
.LEHB4:
call _ZNSolsEi@PLT
.LEHE4:
leaq 16(%rbx), %rax
movq %rax, 16(%rsp)
movq %rax, (%rbx)
movq $0, 8(%rbx)
movb $0, 16(%rbx)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
.LEHB5:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE5:
movl $4, %eax
subl 8(%rbx), %eax
movl %eax, 28(%rsp)
testl %eax, %eax
jle .L12
movl $0, %r14d
leaq 32(%rsp), %r13
leaq 48(%rsp), %r12
movabsq $4611686018427387903, %r15
jmp .L33
.L63:
cmpq %r15, 40(%rsp)
je .L55
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %r13, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L56
.L55:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L57
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L46:
endbr64
movq %rax, %rbp
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L19:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L35:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L57:
call __stack_chk_fail@PLT
.L56:
movq %r15, %rax
subq 40(%rsp), %rax
cmpq %rbp, %rax
jb .L58
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L59
.L58:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L60
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L60:
call __stack_chk_fail@PLT
.L59:
movq (%rbx), %rax
cmpq %rax, 16(%rsp)
je .L61
movq 32(%rsp), %rdx
cmpq %r12, %rdx
je .L62
movq 16(%rbx), %rcx
movq %rdx, (%rbx)
movq 40(%rsp), %rdx
movq %rdx, 8(%rbx)
movq 48(%rsp), %rdx
movq %rdx, 16(%rbx)
testq %rax, %rax
je .L31
movq %rax, 32(%rsp)
movq %rcx, 48(%rsp)
.L30:
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax)
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .L32
movq 48(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L32:
addl $1, %r14d
movl 28(%rsp), %eax
cmpl %eax, %r14d
je .L12
.L33:
movq 8(%rbx), %rbp
movq (%rbx), %rax
movq %rax, 8(%rsp)
movq %r12, 32(%rsp)
movq $0, 40(%rsp)
movb $0, 48(%rsp)
leaq 1(%rbp), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
.LEHE6:
jmp .L63
.L61:
movq 32(%rsp), %rdx
cmpq %r12, %rdx
je .L64
movq %rdx, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movq 48(%rsp), %rax
movq %rax, 16(%rbx)
.L31:
movq %r12, 32(%rsp)
jmp .L30
.L64:
movq 40(%rsp), %rdx
jmp .L37
.L68:
cmpq $1, %rdx
je .L65
leaq 48(%rsp), %rsi
movl %edx, %ecx
cmpl $8, %edx
jnb .L24
testb $4, %dl
jne .L66
testl %edx, %edx
je .L22
movzbl 48(%rsp), %edx
movb %dl, (%rax)
testb $2, %cl
je .L22
movl %ecx, %ecx
movzwl -2(%rsi,%rcx), %edx
movw %dx, -2(%rax,%rcx)
jmp .L22
.L65:
movzbl 48(%rsp), %edx
movb %dl, (%rax)
jmp .L22
.L66:
movl 48(%rsp), %edx
movl %edx, (%rax)
movl %ecx, %ecx
movl -4(%rsi,%rcx), %edx
movl %edx, -4(%rax,%rcx)
jmp .L22
.L24:
movq 48(%rsp), %rcx
movq %rcx, (%rax)
movl %edx, %ecx
movq -8(%rsi,%rcx), %rdi
movq %rdi, -8(%rax,%rcx)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
movq %rax, %rcx
subq %rax, %rsi
addl %edx, %ecx
andl $-8, %ecx
cmpl $8, %ecx
jb .L22
andl $-8, %ecx
movl $0, %eax
.L28:
movl %eax, %edx
movq (%rsi,%rdx), %r8
movq %r8, (%rdi,%rdx)
addl $8, %eax
cmpl %ecx, %eax
jb .L28
jmp .L22
.L12:
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 80(%rax), %rax
movq %rax, 192(%rsp)
leaq -40(%rax), %rax
movq %rax, 80(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movq 160(%rsp), %rdi
leaq 176(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 176(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq $0, 72(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L67
movq %rbx, %rax
addq $472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbp
jmp .L19
.L41:
endbr64
movq %rax, %rbp
jmp .L35
.L36:
movq %rbp, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L62:
movq 40(%rsp), %rdx
.L37:
testq %rdx, %rdx
jne .L68
.L22:
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
jmp .L30
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB3727
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 .L44-.LFB3727
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 .L41-.LFB3727
.uleb128 0
.uleb128 .LEHB5-.LFB3727
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB3727
.uleb128 0
.uleb128 .LEHB6-.LFB3727
.uleb128 .LEHE6-.LEHB6
.uleb128 .L46-.LFB3727
.uleb128 0
.uleb128 .LEHB7-.LFB3727
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.text
.size _Z14zeropad_numberB5cxx11i, .-_Z14zeropad_numberB5cxx11i
.globl main
.type main, @function
main:
.LFB3732:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3732
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %esi
.LEHB8:
call _Z14zeropad_numberB5cxx11i
.LEHE8:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB9:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE9:
movq %rsp, %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $28, %esi
movq %rbx, %rdi
.LEHB10:
call _Z14zeropad_numberB5cxx11i
.LEHE10:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB11:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE11:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L71
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.L76:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE12:
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3732:
.section .gcc_except_table
.LLSDA3732:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3732-.LLSDACSB3732
.LLSDACSB3732:
.uleb128 .LEHB8-.LFB3732
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3732
.uleb128 .LEHE9-.LEHB9
.uleb128 .L75-.LFB3732
.uleb128 0
.uleb128 .LEHB10-.LFB3732
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3732
.uleb128 .LEHE11-.LEHB11
.uleb128 .L76-.LFB3732
.uleb128 0
.uleb128 .LEHB12-.LFB3732
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE3732:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; | #include <hip/hip_runtime.h>
#include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <sstream>
#include <string>
#include <ctime>
std::string zeropad_number(int n)
{
std::stringstream ss;
ss << n;
std::string str;
ss >> str;
int len = str.length();
for (int i = 0; i < 4 - len; i++) {
str = "0" + str;
}
return str;
};
int main(){
std::cout << zeropad_number(1) << std::endl;
std::cout << zeropad_number(28) << std::endl;
return 0;
}; | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14zeropad_numberB5cxx11i # -- Begin function _Z14zeropad_numberB5cxx11i
.p2align 4, 0x90
.type _Z14zeropad_numberB5cxx11i,@function
_Z14zeropad_numberB5cxx11i: # @_Z14zeropad_numberB5cxx11i
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 48(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1Ev
leaq 64(%rsp), %rdi
.Ltmp0:
movl %ebp, %esi
callq _ZNSolsEi
.Ltmp1:
# %bb.1:
leaq 16(%rbx), %r12
movq %r12, (%rbx)
movq $0, 8(%rbx)
movb $0, 16(%rbx)
.Ltmp3:
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp4:
# %bb.2:
movl 8(%rbx), %eax
cmpl $3, %eax
jg .LBB0_20
# %bb.3: # %.lr.ph
movl $4, %ecx
subl %eax, %ecx
leaq 32(%rsp), %r13
cmpl $2, %ecx
movl $1, %ebp
cmovgel %ecx, %ebp
leaq 16(%rsp), %r14
leaq 15(%rsp), %r15
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB0_4 Depth=1
decl %ebp
je .LBB0_20
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rcx
movq 8(%rbx), %r8
.Ltmp6:
movl $.L.str, %esi
movl $1, %edx
movq %r14, %rdi
movq %r15, %r9
callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Ltmp7:
# %bb.5: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_.exit
# in Loop: Header=BB0_4 Depth=1
movq (%rbx), %rdi
movq 16(%rsp), %rsi
cmpq %r13, %rsi
je .LBB0_6
# %bb.13: # %.critedge.i
# in Loop: Header=BB0_4 Depth=1
movq 16(%rbx), %rax
movq %rsi, (%rbx)
movq 24(%rsp), %rcx
movq %rcx, 8(%rbx)
movq 32(%rsp), %rcx
movq %rcx, 16(%rbx)
cmpq %r12, %rdi
je .LBB0_16
# %bb.14: # %.critedge.i
# in Loop: Header=BB0_4 Depth=1
testq %rdi, %rdi
je .LBB0_16
# %bb.15: # in Loop: Header=BB0_4 Depth=1
movq %rdi, 16(%rsp)
movq %rax, 32(%rsp)
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_6: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i
# in Loop: Header=BB0_4 Depth=1
cmpq %rbx, %r14
je .LBB0_17
# %bb.7: # in Loop: Header=BB0_4 Depth=1
movq 24(%rsp), %rdx
testq %rdx, %rdx
je .LBB0_12
# %bb.8: # in Loop: Header=BB0_4 Depth=1
cmpq $1, %rdx
jne .LBB0_11
# %bb.9: # in Loop: Header=BB0_4 Depth=1
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_4 Depth=1
movq %r13, 16(%rsp)
jmp .LBB0_17
.LBB0_11: # in Loop: Header=BB0_4 Depth=1
callq memcpy@PLT
.LBB0_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i
# in Loop: Header=BB0_4 Depth=1
movq 24(%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
.LBB0_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit
# in Loop: Header=BB0_4 Depth=1
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax)
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_19
# %bb.18: # %.critedge.i.i
# in Loop: Header=BB0_4 Depth=1
callq _ZdlPv
jmp .LBB0_19
.LBB0_20: # %._crit_edge
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 48(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 64(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 72(%rsp)
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_22
# %bb.21: # %.critedge.i.i.i.i.i
callq _ZdlPv
.LBB0_22: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 72(%rsp)
leaq 128(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 48(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 48(%rsp,%rax)
movq $0, 56(%rsp)
leaq 176(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rax
addq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_23:
.cfi_def_cfa_offset 496
.Ltmp5:
jmp .LBB0_24
.LBB0_10:
.Ltmp2:
movq %rax, %r14
jmp .LBB0_26
.LBB0_27:
.Ltmp8:
.LBB0_24:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %r12, %rdi
je .LBB0_26
# %bb.25: # %.critedge.i.i11
callq _ZdlPv
.LBB0_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit13
leaq 48(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z14zeropad_numberB5cxx11i, .Lfunc_end0-_Z14zeropad_numberB5cxx11i
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsp, %rdi
movl $1, %esi
callq _Z14zeropad_numberB5cxx11i
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp9:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.1: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_2
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_6:
.Ltmp11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp12:
# %bb.7: # %.noexc14
movq (%r14), %rax
.Ltmp13:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp14:
.LBB1_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp15:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp16:
# %bb.9: # %.noexc16
.Ltmp17:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp18:
# %bb.10: # %_ZNSolsEPFRSoS_E.exit
movq (%rsp), %rdi
leaq 16(%rsp), %r15
cmpq %r15, %rdi
je .LBB1_12
# %bb.11: # %.critedge.i.i
callq _ZdlPv
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rsp, %rdi
movl $28, %esi
callq _Z14zeropad_numberB5cxx11i
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp19:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.13: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit3
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_14
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB1_20
.LBB1_18:
.Ltmp21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp22:
# %bb.19: # %.noexc24
movq (%r14), %rax
.Ltmp23:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp24:
.LBB1_20: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i21
.Ltmp25:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp26:
# %bb.21: # %.noexc26
.Ltmp27:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp28:
# %bb.22: # %_ZNSolsEPFRSoS_E.exit4
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB1_24
# %bb.23: # %.critedge.i.i5
callq _ZdlPv
.LBB1_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit7
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 64
.Ltmp32:
callq _ZSt16__throw_bad_castv
.Ltmp33:
# %bb.3: # %.noexc
.LBB1_14:
.Ltmp29:
callq _ZSt16__throw_bad_castv
.Ltmp30:
# %bb.15: # %.noexc23
.LBB1_26:
.Ltmp31:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
jne .LBB1_27
jmp .LBB1_28
.LBB1_25:
.Ltmp34:
movq %rax, %rbx
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_28
.LBB1_27: # %.critedge.i.i11
callq _ZdlPv
.LBB1_28:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp18-.Ltmp9 # Call between .Ltmp9 and .Ltmp18
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp28-.Ltmp19 # Call between .Ltmp19 and .Ltmp28
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"axG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.weak _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE # -- Begin function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.p2align 4, 0x90
.type _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,@function
_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE: # @_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 16(%rdi), %rbp
movq %rbp, (%rdi)
movq $0, 8(%rdi)
movb $0, 16(%rdi)
leaq (%r8,%rdx), %rsi
.Ltmp35:
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp36:
# %bb.1:
movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
movq 8(%rbx), %rsi
movq %r15, %rax
subq %rsi, %rax
cmpq %r12, %rax
jb .LBB2_11
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
leaq (%rsi,%r12), %r13
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB2_4
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq (%rbp), %rax
.LBB2_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
cmpq %rax, %r13
jbe .LBB2_5
# %bb.9:
.Ltmp37:
movq %rbx, %rdi
xorl %edx, %edx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r12, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp38:
jmp .LBB2_10
.LBB2_5:
testq %r12, %r12
je .LBB2_10
# %bb.6:
addq %rsi, %rdi
cmpq $1, %r12
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB2_10
.LBB2_8:
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq memcpy@PLT
.LBB2_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit
movq %r13, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r13)
movq 8(%rbx), %rsi
subq %rsi, %r15
cmpq %r14, %r15
jb .LBB2_11
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
leaq (%rsi,%r14), %r15
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB2_15
# %bb.14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
movq (%rbp), %rax
.LBB2_15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
cmpq %rax, %r15
jbe .LBB2_16
# %bb.20:
.Ltmp39:
movq %rbx, %rdi
xorl %edx, %edx
movq 8(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp40:
jmp .LBB2_21
.LBB2_16:
testq %r14, %r14
je .LBB2_21
# %bb.17:
addq %rsi, %rdi
cmpq $1, %r14
jne .LBB2_19
# %bb.18:
movq 8(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB2_21
.LBB2_19:
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit17
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11: # %.invoke
.cfi_def_cfa_offset 80
.Ltmp41:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp42:
# %bb.12: # %.cont
.LBB2_22:
.Ltmp43:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %rbp, %rdi
je .LBB2_24
# %bb.23: # %.critedge.i.i
callq _ZdlPv
.LBB2_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE, .Lfunc_end2-_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.cfi_endproc
.section .gcc_except_table._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"aG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.p2align 2, 0x0
GCC_except_table2:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp35-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp38-.Ltmp35 # Call between .Ltmp35 and .Ltmp38
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp42 # Call between .Ltmp42 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq (%rdi), %r14
leaq 16(%rdi), %r12
movl $15, %eax
cmpq %r12, %r14
je .LBB3_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB3_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
cmpq %rsi, %rax
jae .LBB3_12
# %bb.3:
testq %rsi, %rsi
js .LBB3_13
# %bb.4:
addq %rax, %rax
movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF
cmpq %r13, %rax
cmovbq %rax, %r13
cmpq %rsi, %rax
cmovbeq %rsi, %r13
movq %r13, %rdi
incq %rdi
js .LBB3_14
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
callq _Znwm
movq %rax, %r15
movq 8(%rbx), %rdx
cmpq $-1, %rdx
je .LBB3_9
# %bb.6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
testq %rdx, %rdx
jne .LBB3_8
# %bb.7:
movzbl (%r14), %eax
movb %al, (%r15)
.LBB3_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
cmpq %r12, %r14
je .LBB3_11
.LBB3_10: # %.critedge.i
movq %r14, %rdi
callq _ZdlPv
.LBB3_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r15, (%rbx)
movq %r13, 16(%rbx)
.LBB3_12:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_8:
.cfi_def_cfa_offset 48
incq %rdx
movq %r15, %rdi
movq %r14, %rsi
callq memcpy@PLT
cmpq %r12, %r14
jne .LBB3_10
jmp .LBB3_11
.LBB3_14:
callq _ZSt17__throw_bad_allocv
.LBB3_13:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB4_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB4_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB4_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB4_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB4_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB4_6:
movq %rbp, %rdi
incq %rdi
js .LBB4_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB4_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB4_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB4_11
.LBB4_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB4_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB4_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB4_18
# %bb.13:
je .LBB4_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB4_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB4_17
.LBB4_16:
callq memcpy@PLT
.LBB4_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB4_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB4_23
# %bb.19:
subq %r14, %r12
je .LBB4_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB4_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB4_23
.LBB4_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB4_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB4_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB4_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB4_26:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "0"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "basic_string::_M_create"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::append"
.size .L.str.2, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c152d_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3758:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3758:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "basic_string::append"
.LC1:
.string "0"
.text
.globl _Z14zeropad_numberB5cxx11i
.type _Z14zeropad_numberB5cxx11i, @function
_Z14zeropad_numberB5cxx11i:
.LFB3727:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3727
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $472, %rsp
.cfi_def_cfa_offset 528
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 456(%rsp)
xorl %eax, %eax
leaq 64(%rsp), %r12
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
movq $0, 408(%rsp)
movb $0, 416(%rsp)
movb $0, 417(%rsp)
movq $0, 424(%rsp)
movq $0, 432(%rsp)
movq $0, 440(%rsp)
movq $0, 448(%rsp)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq $0, 72(%rsp)
movq 64(%rsp), %rax
movq %r12, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq 80(%rsp), %rax
movq -24(%rax), %rax
leaq 80(%rsp,%rax), %rdi
movl $0, %esi
.LEHB1:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE1:
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 80(%rax), %rax
movq %rax, 192(%rsp)
leaq -40(%rax), %rax
movq %rax, 80(%rsp)
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt6localeC1Ev@PLT
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movl $24, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
movq $0, 168(%rsp)
movb $0, 176(%rsp)
leaq 88(%rsp), %rsi
leaq 192(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L54
.L45:
endbr64
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp)
movq -24(%rcx), %rdx
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rdx)
movq $0, 72(%rsp)
movq %rax, %rbx
.L8:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L11
call __stack_chk_fail@PLT
.L44:
endbr64
movq %rax, %rbx
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movq 160(%rsp), %rdi
leaq 176(%rsp), %rax
cmpq %rax, %rdi
je .L10
movq 176(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L10:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rbp
leaq 144(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
leaq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rsi
movq %rbp, %rdi
call _ZNSdD2Ev@PLT
jmp .L8
.L43:
endbr64
movq %rax, %rbx
jmp .L8
.L11:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L54:
leaq 80(%rsp), %rdi
movl %ebp, %esi
.LEHB4:
call _ZNSolsEi@PLT
.LEHE4:
leaq 16(%rbx), %rax
movq %rax, 16(%rsp)
movq %rax, (%rbx)
movq $0, 8(%rbx)
movb $0, 16(%rbx)
leaq 64(%rsp), %rdi
movq %rbx, %rsi
.LEHB5:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
.LEHE5:
movl $4, %eax
subl 8(%rbx), %eax
movl %eax, 28(%rsp)
testl %eax, %eax
jle .L12
movl $0, %r14d
leaq 32(%rsp), %r13
leaq 48(%rsp), %r12
movabsq $4611686018427387903, %r15
jmp .L33
.L63:
cmpq %r15, 40(%rsp)
je .L55
movl $1, %edx
leaq .LC1(%rip), %rsi
movq %r13, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L56
.L55:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L57
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L46:
endbr64
movq %rax, %rbp
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L19:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L35:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L57:
call __stack_chk_fail@PLT
.L56:
movq %r15, %rax
subq 40(%rsp), %rax
cmpq %rbp, %rax
jb .L58
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L59
.L58:
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L60
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L60:
call __stack_chk_fail@PLT
.L59:
movq (%rbx), %rax
cmpq %rax, 16(%rsp)
je .L61
movq 32(%rsp), %rdx
cmpq %r12, %rdx
je .L62
movq 16(%rbx), %rcx
movq %rdx, (%rbx)
movq 40(%rsp), %rdx
movq %rdx, 8(%rbx)
movq 48(%rsp), %rdx
movq %rdx, 16(%rbx)
testq %rax, %rax
je .L31
movq %rax, 32(%rsp)
movq %rcx, 48(%rsp)
.L30:
movq $0, 40(%rsp)
movq 32(%rsp), %rax
movb $0, (%rax)
movq 32(%rsp), %rdi
cmpq %r12, %rdi
je .L32
movq 48(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L32:
addl $1, %r14d
movl 28(%rsp), %eax
cmpl %eax, %r14d
je .L12
.L33:
movq 8(%rbx), %rbp
movq (%rbx), %rax
movq %rax, 8(%rsp)
movq %r12, 32(%rsp)
movq $0, 40(%rsp)
movb $0, 48(%rsp)
leaq 1(%rbp), %rsi
movq %r13, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
.LEHE6:
jmp .L63
.L61:
movq 32(%rsp), %rdx
cmpq %r12, %rdx
je .L64
movq %rdx, (%rbx)
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movq 48(%rsp), %rax
movq %rax, 16(%rbx)
.L31:
movq %r12, 32(%rsp)
jmp .L30
.L64:
movq 40(%rsp), %rdx
jmp .L37
.L68:
cmpq $1, %rdx
je .L65
leaq 48(%rsp), %rsi
movl %edx, %ecx
cmpl $8, %edx
jnb .L24
testb $4, %dl
jne .L66
testl %edx, %edx
je .L22
movzbl 48(%rsp), %edx
movb %dl, (%rax)
testb $2, %cl
je .L22
movl %ecx, %ecx
movzwl -2(%rsi,%rcx), %edx
movw %dx, -2(%rax,%rcx)
jmp .L22
.L65:
movzbl 48(%rsp), %edx
movb %dl, (%rax)
jmp .L22
.L66:
movl 48(%rsp), %edx
movl %edx, (%rax)
movl %ecx, %ecx
movl -4(%rsi,%rcx), %edx
movl %edx, -4(%rax,%rcx)
jmp .L22
.L24:
movq 48(%rsp), %rcx
movq %rcx, (%rax)
movl %edx, %ecx
movq -8(%rsi,%rcx), %rdi
movq %rdi, -8(%rax,%rcx)
leaq 8(%rax), %rdi
andq $-8, %rdi
subq %rdi, %rax
movq %rax, %rcx
subq %rax, %rsi
addl %edx, %ecx
andl $-8, %ecx
cmpl $8, %ecx
jb .L22
andl $-8, %ecx
movl $0, %eax
.L28:
movl %eax, %edx
movq (%rsi,%rdx), %r8
movq %r8, (%rdi,%rdx)
addl $8, %eax
cmpl %ecx, %eax
jb .L28
jmp .L22
.L12:
leaq 24+_ZTVNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
leaq 80(%rax), %rax
movq %rax, 192(%rsp)
leaq -40(%rax), %rax
movq %rax, 80(%rsp)
leaq 16+_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 88(%rsp)
movq 160(%rsp), %rdi
leaq 176(%rsp), %rax
cmpq %rax, %rdi
je .L34
movq 176(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L34:
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 88(%rsp)
leaq 144(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq 8+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 48+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq 32+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 80(%rsp)
movq -24(%rax), %rax
movq 40+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 80(%rsp,%rax)
movq 16+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 64(%rsp)
movq -24(%rax), %rax
movq 24+_ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rcx
movq %rcx, 64(%rsp,%rax)
movq $0, 72(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 192(%rsp)
leaq 192(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 456(%rsp), %rax
subq %fs:40, %rax
jne .L67
movq %rbx, %rax
addq $472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
endbr64
movq %rax, %rbp
jmp .L19
.L41:
endbr64
movq %rax, %rbp
jmp .L35
.L36:
movq %rbp, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L62:
movq 40(%rsp), %rdx
.L37:
testq %rdx, %rdx
jne .L68
.L22:
movq 40(%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
jmp .L30
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3727:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3727:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3727-.LLSDACSB3727
.LLSDACSB3727:
.uleb128 .LEHB0-.LFB3727
.uleb128 .LEHE0-.LEHB0
.uleb128 .L43-.LFB3727
.uleb128 0
.uleb128 .LEHB1-.LFB3727
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3727
.uleb128 0
.uleb128 .LEHB2-.LFB3727
.uleb128 .LEHE2-.LEHB2
.uleb128 .L44-.LFB3727
.uleb128 0
.uleb128 .LEHB3-.LFB3727
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB3727
.uleb128 .LEHE4-.LEHB4
.uleb128 .L41-.LFB3727
.uleb128 0
.uleb128 .LEHB5-.LFB3727
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB3727
.uleb128 0
.uleb128 .LEHB6-.LFB3727
.uleb128 .LEHE6-.LEHB6
.uleb128 .L46-.LFB3727
.uleb128 0
.uleb128 .LEHB7-.LFB3727
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE3727:
.text
.size _Z14zeropad_numberB5cxx11i, .-_Z14zeropad_numberB5cxx11i
.globl main
.type main, @function
main:
.LFB3732:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3732
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %esi
.LEHB8:
call _Z14zeropad_numberB5cxx11i
.LEHE8:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB9:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE9:
movq %rsp, %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $28, %esi
movq %rbx, %rdi
.LEHB10:
call _Z14zeropad_numberB5cxx11i
.LEHE10:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB11:
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE11:
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L71
call __stack_chk_fail@PLT
.L71:
movq %rbx, %rdi
.LEHB12:
call _Unwind_Resume@PLT
.L76:
endbr64
movq %rax, %rbx
movq %rsp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L73
call __stack_chk_fail@PLT
.L73:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE12:
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3732:
.section .gcc_except_table
.LLSDA3732:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3732-.LLSDACSB3732
.LLSDACSB3732:
.uleb128 .LEHB8-.LFB3732
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.uleb128 .LEHB9-.LFB3732
.uleb128 .LEHE9-.LEHB9
.uleb128 .L75-.LFB3732
.uleb128 0
.uleb128 .LEHB10-.LFB3732
.uleb128 .LEHE10-.LEHB10
.uleb128 0
.uleb128 0
.uleb128 .LEHB11-.LFB3732
.uleb128 .LEHE11-.LEHB11
.uleb128 .L76-.LFB3732
.uleb128 0
.uleb128 .LEHB12-.LFB3732
.uleb128 .LEHE12-.LEHB12
.uleb128 0
.uleb128 0
.LLSDACSE3732:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14zeropad_numberB5cxx11i # -- Begin function _Z14zeropad_numberB5cxx11i
.p2align 4, 0x90
.type _Z14zeropad_numberB5cxx11i,@function
_Z14zeropad_numberB5cxx11i: # @_Z14zeropad_numberB5cxx11i
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
leaq 48(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEC1Ev
leaq 64(%rsp), %rdi
.Ltmp0:
movl %ebp, %esi
callq _ZNSolsEi
.Ltmp1:
# %bb.1:
leaq 16(%rbx), %r12
movq %r12, (%rbx)
movq $0, 8(%rbx)
movb $0, 16(%rbx)
.Ltmp3:
leaq 48(%rsp), %rdi
movq %rbx, %rsi
callq _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE
.Ltmp4:
# %bb.2:
movl 8(%rbx), %eax
cmpl $3, %eax
jg .LBB0_20
# %bb.3: # %.lr.ph
movl $4, %ecx
subl %eax, %ecx
leaq 32(%rsp), %r13
cmpl $2, %ecx
movl $1, %ebp
cmovgel %ecx, %ebp
leaq 16(%rsp), %r14
leaq 15(%rsp), %r15
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_19: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
# in Loop: Header=BB0_4 Depth=1
decl %ebp
je .LBB0_20
.LBB0_4: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rcx
movq 8(%rbx), %r8
.Ltmp6:
movl $.L.str, %esi
movl $1, %edx
movq %r14, %rdi
movq %r15, %r9
callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Ltmp7:
# %bb.5: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_.exit
# in Loop: Header=BB0_4 Depth=1
movq (%rbx), %rdi
movq 16(%rsp), %rsi
cmpq %r13, %rsi
je .LBB0_6
# %bb.13: # %.critedge.i
# in Loop: Header=BB0_4 Depth=1
movq 16(%rbx), %rax
movq %rsi, (%rbx)
movq 24(%rsp), %rcx
movq %rcx, 8(%rbx)
movq 32(%rsp), %rcx
movq %rcx, 16(%rbx)
cmpq %r12, %rdi
je .LBB0_16
# %bb.14: # %.critedge.i
# in Loop: Header=BB0_4 Depth=1
testq %rdi, %rdi
je .LBB0_16
# %bb.15: # in Loop: Header=BB0_4 Depth=1
movq %rdi, 16(%rsp)
movq %rax, 32(%rsp)
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_6: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i
# in Loop: Header=BB0_4 Depth=1
cmpq %rbx, %r14
je .LBB0_17
# %bb.7: # in Loop: Header=BB0_4 Depth=1
movq 24(%rsp), %rdx
testq %rdx, %rdx
je .LBB0_12
# %bb.8: # in Loop: Header=BB0_4 Depth=1
cmpq $1, %rdx
jne .LBB0_11
# %bb.9: # in Loop: Header=BB0_4 Depth=1
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB0_12
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_4 Depth=1
movq %r13, 16(%rsp)
jmp .LBB0_17
.LBB0_11: # in Loop: Header=BB0_4 Depth=1
callq memcpy@PLT
.LBB0_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i
# in Loop: Header=BB0_4 Depth=1
movq 24(%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rcx
movb $0, (%rcx,%rax)
.LBB0_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit
# in Loop: Header=BB0_4 Depth=1
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movb $0, (%rax)
movq 16(%rsp), %rdi
cmpq %r13, %rdi
je .LBB0_19
# %bb.18: # %.critedge.i.i
# in Loop: Header=BB0_4 Depth=1
callq _ZdlPv
jmp .LBB0_19
.LBB0_20: # %._crit_edge
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE(%rip), %rax
movq %rax, 48(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+64(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 48(%rsp,%rax)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+72(%rip), %rax
movq %rax, 64(%rsp)
movq $_ZTVNSt7__cxx1115basic_stringbufIcSt11char_traitsIcESaIcEEE+16, 72(%rsp)
movq 144(%rsp), %rdi
leaq 160(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_22
# %bb.21: # %.critedge.i.i.i.i.i
callq _ZdlPv
.LBB0_22: # %_ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev.exit
movq $_ZTVSt15basic_streambufIcSt11char_traitsIcEE+16, 72(%rsp)
leaq 128(%rsp), %rdi
callq _ZNSt6localeD1Ev
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+16(%rip), %rax
movq %rax, 48(%rsp)
movq _ZTTNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEEE+24(%rip), %rcx
movq -24(%rax), %rax
movq %rcx, 48(%rsp,%rax)
movq $0, 56(%rsp)
leaq 176(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rax
addq $440, %rsp # imm = 0x1B8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_23:
.cfi_def_cfa_offset 496
.Ltmp5:
jmp .LBB0_24
.LBB0_10:
.Ltmp2:
movq %rax, %r14
jmp .LBB0_26
.LBB0_27:
.Ltmp8:
.LBB0_24:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %r12, %rdi
je .LBB0_26
# %bb.25: # %.critedge.i.i11
callq _ZdlPv
.LBB0_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit13
leaq 48(%rsp), %rdi
callq _ZNSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEED1Ev
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size _Z14zeropad_numberB5cxx11i, .Lfunc_end0-_Z14zeropad_numberB5cxx11i
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsp, %rdi
movl $1, %esi
callq _Z14zeropad_numberB5cxx11i
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp9:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.1: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_2
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB1_8
.LBB1_6:
.Ltmp11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp12:
# %bb.7: # %.noexc14
movq (%r14), %rax
.Ltmp13:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp14:
.LBB1_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp15:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp16:
# %bb.9: # %.noexc16
.Ltmp17:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp18:
# %bb.10: # %_ZNSolsEPFRSoS_E.exit
movq (%rsp), %rdi
leaq 16(%rsp), %r15
cmpq %r15, %rdi
je .LBB1_12
# %bb.11: # %.critedge.i.i
callq _ZdlPv
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %rsp, %rdi
movl $28, %esi
callq _Z14zeropad_numberB5cxx11i
movq (%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp19:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp20:
# %bb.13: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit3
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_14
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%r14)
je .LBB1_18
# %bb.17:
movzbl 67(%r14), %eax
jmp .LBB1_20
.LBB1_18:
.Ltmp21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp22:
# %bb.19: # %.noexc24
movq (%r14), %rax
.Ltmp23:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp24:
.LBB1_20: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i21
.Ltmp25:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp26:
# %bb.21: # %.noexc26
.Ltmp27:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp28:
# %bb.22: # %_ZNSolsEPFRSoS_E.exit4
movq (%rsp), %rdi
cmpq %r15, %rdi
je .LBB1_24
# %bb.23: # %.critedge.i.i5
callq _ZdlPv
.LBB1_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit7
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_2:
.cfi_def_cfa_offset 64
.Ltmp32:
callq _ZSt16__throw_bad_castv
.Ltmp33:
# %bb.3: # %.noexc
.LBB1_14:
.Ltmp29:
callq _ZSt16__throw_bad_castv
.Ltmp30:
# %bb.15: # %.noexc23
.LBB1_26:
.Ltmp31:
movq %rax, %rbx
movq (%rsp), %rdi
cmpq %r15, %rdi
jne .LBB1_27
jmp .LBB1_28
.LBB1_25:
.Ltmp34:
movq %rax, %rbx
movq (%rsp), %rdi
leaq 16(%rsp), %rax
cmpq %rax, %rdi
je .LBB1_28
.LBB1_27: # %.critedge.i.i11
callq _ZdlPv
.LBB1_28:
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp9-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp18-.Ltmp9 # Call between .Ltmp9 and .Ltmp18
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp28-.Ltmp19 # Call between .Ltmp19 and .Ltmp28
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp33-.Ltmp32 # Call between .Ltmp32 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin1 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Ltmp30-.Ltmp29 # Call between .Ltmp29 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin1 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin1 # >> Call Site 7 <<
.uleb128 .Lfunc_end1-.Ltmp30 # Call between .Ltmp30 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"axG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.weak _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE # -- Begin function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.p2align 4, 0x90
.type _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,@function
_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE: # @_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 16(%rdi), %rbp
movq %rbp, (%rdi)
movq $0, 8(%rdi)
movb $0, 16(%rdi)
leaq (%r8,%rdx), %rsi
.Ltmp35:
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp36:
# %bb.1:
movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
movq 8(%rbx), %rsi
movq %r15, %rax
subq %rsi, %rax
cmpq %r12, %rax
jb .LBB2_11
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
leaq (%rsi,%r12), %r13
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB2_4
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq (%rbp), %rax
.LBB2_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
cmpq %rax, %r13
jbe .LBB2_5
# %bb.9:
.Ltmp37:
movq %rbx, %rdi
xorl %edx, %edx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r12, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp38:
jmp .LBB2_10
.LBB2_5:
testq %r12, %r12
je .LBB2_10
# %bb.6:
addq %rsi, %rdi
cmpq $1, %r12
jne .LBB2_8
# %bb.7:
movq 16(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB2_10
.LBB2_8:
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq memcpy@PLT
.LBB2_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit
movq %r13, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r13)
movq 8(%rbx), %rsi
subq %rsi, %r15
cmpq %r14, %r15
jb .LBB2_11
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
leaq (%rsi,%r14), %r15
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB2_15
# %bb.14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
movq (%rbp), %rax
.LBB2_15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
cmpq %rax, %r15
jbe .LBB2_16
# %bb.20:
.Ltmp39:
movq %rbx, %rdi
xorl %edx, %edx
movq 8(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp40:
jmp .LBB2_21
.LBB2_16:
testq %r14, %r14
je .LBB2_21
# %bb.17:
addq %rsi, %rdi
cmpq $1, %r14
jne .LBB2_19
# %bb.18:
movq 8(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB2_21
.LBB2_19:
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
.LBB2_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit17
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_11: # %.invoke
.cfi_def_cfa_offset 80
.Ltmp41:
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp42:
# %bb.12: # %.cont
.LBB2_22:
.Ltmp43:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %rbp, %rdi
je .LBB2_24
# %bb.23: # %.critedge.i.i
callq _ZdlPv
.LBB2_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE, .Lfunc_end2-_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.cfi_endproc
.section .gcc_except_table._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"aG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.p2align 2, 0x0
GCC_except_table2:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp35-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp38-.Ltmp35 # Call between .Ltmp35 and .Ltmp38
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin2 # >> Call Site 2 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin2 # >> Call Site 3 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin2 # >> Call Site 4 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin2 # >> Call Site 5 <<
.uleb128 .Ltmp42-.Ltmp41 # Call between .Ltmp41 and .Ltmp42
.uleb128 .Ltmp43-.Lfunc_begin2 # jumps to .Ltmp43
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin2 # >> Call Site 6 <<
.uleb128 .Lfunc_end2-.Ltmp42 # Call between .Ltmp42 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end2:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq (%rdi), %r14
leaq 16(%rdi), %r12
movl $15, %eax
cmpq %r12, %r14
je .LBB3_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB3_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
cmpq %rsi, %rax
jae .LBB3_12
# %bb.3:
testq %rsi, %rsi
js .LBB3_13
# %bb.4:
addq %rax, %rax
movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF
cmpq %r13, %rax
cmovbq %rax, %r13
cmpq %rsi, %rax
cmovbeq %rsi, %r13
movq %r13, %rdi
incq %rdi
js .LBB3_14
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
callq _Znwm
movq %rax, %r15
movq 8(%rbx), %rdx
cmpq $-1, %rdx
je .LBB3_9
# %bb.6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
testq %rdx, %rdx
jne .LBB3_8
# %bb.7:
movzbl (%r14), %eax
movb %al, (%r15)
.LBB3_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
cmpq %r12, %r14
je .LBB3_11
.LBB3_10: # %.critedge.i
movq %r14, %rdi
callq _ZdlPv
.LBB3_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r15, (%rbx)
movq %r13, 16(%rbx)
.LBB3_12:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_8:
.cfi_def_cfa_offset 48
incq %rdx
movq %r15, %rdi
movq %r14, %rsi
callq memcpy@PLT
cmpq %r12, %r14
jne .LBB3_10
jmp .LBB3_11
.LBB3_14:
callq _ZSt17__throw_bad_allocv
.LBB3_13:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end3:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm, .Lfunc_end3-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB4_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB4_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB4_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB4_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB4_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB4_6:
movq %rbp, %rdi
incq %rdi
js .LBB4_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB4_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB4_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB4_11
.LBB4_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB4_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB4_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB4_18
# %bb.13:
je .LBB4_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB4_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB4_17
.LBB4_16:
callq memcpy@PLT
.LBB4_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB4_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB4_23
# %bb.19:
subq %r14, %r12
je .LBB4_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB4_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB4_23
.LBB4_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB4_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB4_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB4_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB4_26:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "0"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "basic_string::_M_create"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "basic_string::append"
.size .L.str.2, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} | .file "tmpxft_001529ac_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cuda_atomicAddPdd
.type _Z14cuda_atomicAddPdd, @function
_Z14cuda_atomicAddPdd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14cuda_atomicAddPdd, .-_Z14cuda_atomicAddPdd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} | #include <hip/hip_runtime.h>
__device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ double cuda_atomicAdd(double *address, double val)
{
double assumed,old=*address;
do {
assumed=old;
old=
__longlong_as_double
(
atomicCAS(
(unsigned long long int*)
address,
__double_as_longlong(assumed),
__double_as_longlong(val+assumed)));
}while (assumed!=old);
//printf("NEW ATOMIC ADD\n");
return old;
} | .text
.file "add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001529ac_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cuda_atomicAddPdd
.type _Z14cuda_atomicAddPdd, @function
_Z14cuda_atomicAddPdd:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z14cuda_atomicAddPdd, .-_Z14cuda_atomicAddPdd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
cudaStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} | code for sm_80
Function : ipv4lookup
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0000 */
/*00b0*/ LEA R4, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R5, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008057a11 */
/* 0x000fca00000f1409 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x2 ; /* 0x00000002ff037424 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008067a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ SHF.R.U32.HI R2, RZ, 0x8, R4 ; /* 0x00000008ff027819 */
/* 0x004fca0000011604 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0003 */
/*0120*/ LDG.E.U16 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1500 */
/*0130*/ IADD3.X R7, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009077a10 */
/* 0x000fe200007fe4ff */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R8, R9, c[0x0][0xc], R0 ; /* 0x0000030009087a24 */
/* 0x000fc800078e0200 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, R8.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0008 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fe40003f06070 */
/*0180*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0190*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x16c], PT, P0 ; /* 0x00005b0009007a0c */
/* 0x000fe20003f06100 */
/*01a0*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0041d8000c101104 */
/*01b0*/ @!P0 BRA 0xb0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
cudaStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} | .file "tmpxft_0009ca42_00000000-6_ipv4lookup.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
.type _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt, @function
_Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq ipv4lookup(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt, .-_Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
.globl ipv4lookup
.type ipv4lookup, @function
ipv4lookup:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size ipv4lookup, .-ipv4lookup
.globl IPv4_Lookup
.type IPv4_Lookup, @function
IPv4_Lookup:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r13
movl %r9d, %eax
movq 80(%rsp), %r9
testq %r9, %r9
je .L17
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movl %ebx, %esi
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rdi
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
jmp .L11
.L18:
movl %ebx, %esi
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rdi
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
jmp .L11
.cfi_endproc
.LFE2057:
.size IPv4_Lookup, .-IPv4_Lookup
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ipv4lookup"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ipv4lookup(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
cudaStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
hipStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
hipStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected ipv4lookup
.globl ipv4lookup
.p2align 8
.type ipv4lookup,@function
ipv4lookup:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
s_ashr_i32 s10, s1, 31
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s1
v_subrev_co_ci_u32_e32 v4, vcc_lo, s10, v0, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s1
v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo
global_load_b32 v0, v[5:6], off
v_add_co_u32 v5, vcc_lo, s4, v1
v_cmp_le_u64_e64 s0, s[2:3], v[3:4]
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v3
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s11, s0, s11
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v0, 7, v0
v_and_b32_e32 v0, 0x1fffffe, v0
global_load_u16 v0, v0, s[6:7]
s_waitcnt vmcnt(0)
global_store_b8 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ipv4lookup
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size ipv4lookup, .Lfunc_end0-ipv4lookup
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ipv4lookup
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: ipv4lookup.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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