system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} | code for sm_80
Function : _Z13floyd2DKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea20000002200 */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fe20007ffe0ff */
/*00a0*/ IMAD R5, R6, c[0x0][0x4], R7 ; /* 0x0000010006057a24 */
/* 0x004fca00078e0207 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*00c0*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fca00078e0a03 */
/*0100*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD R5, R6, R9, RZ ; /* 0x0000000906057224 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0150*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0170*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0180*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fe400078e3cff */
/*01b0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0003 */
/*01f0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff05aa12 */
/* 0x000fca00078e33ff */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0220*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fc80003f06270 */
/*0240*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R5, R3, PT ; /* 0x000000030500720c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.EQ.OR P0, PT, R5, c[0x0][0x16c], !P0 ; /* 0x00005b0005007a0c */
/* 0x000fc80004702670 */
/*0280*/ ISETP.EQ.OR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0000702670 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ IMAD R2, R5, R4, c[0x0][0x16c] ; /* 0x00005b0005027624 */
/* 0x000fe400078e0204 */
/*02e0*/ IMAD R4, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004047a24 */
/* 0x000fe400078e0203 */
/*02f0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0207 */
/*0300*/ IMAD.WIDE R4, R4, R7.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e0207 */
/*0310*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe400078e0207 */
/*0330*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fc80007ffe0ff */
/*0360*/ IMNMX R9, R0, R9, PT ; /* 0x0000000900097217 */
/* 0x008fca0003800200 */
/*0370*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} | .file "tmpxft_00002f7c_00000000-6_floyd2DKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13floyd2DKernelPiiiPiii
.type _Z35__device_stub__Z13floyd2DKernelPiiiPiii, @function
_Z35__device_stub__Z13floyd2DKernelPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13floyd2DKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13floyd2DKernelPiiiPiii, .-_Z35__device_stub__Z13floyd2DKernelPiiiPiii
.globl _Z13floyd2DKernelPiii
.type _Z13floyd2DKernelPiii, @function
_Z13floyd2DKernelPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13floyd2DKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13floyd2DKernelPiii, .-_Z13floyd2DKernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13floyd2DKernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13floyd2DKernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13floyd2DKernelPiii
.globl _Z13floyd2DKernelPiii
.p2align 8
.type _Z13floyd2DKernelPiii,@function
_Z13floyd2DKernelPiii:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s6, 31
s_lshr_b32 s5, s2, 16
s_add_i32 s4, s6, s3
s_and_b32 s2, s2, 0xffff
s_xor_b32 s4, s4, s3
s_mul_i32 s14, s14, s2
v_cvt_f32_u32_e32 v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v2
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_sub_i32 s5, 0, s4
v_mul_lo_u32 v2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v2
v_ashrrev_i32_e32 v2, 31, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v4 :: v_dual_add_nc_u32 v4, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s5, v1
v_xor_b32_e32 v2, s3, v2
v_mul_hi_u32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v3
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_sub_nc_u32_e32 v3, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v3, s6
v_cmp_ne_u32_e64 s2, s7, v3
v_sub_nc_u32_e32 v1, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_max_i32_e32 v4, v3, v1
v_cmp_ne_u32_e32 vcc_lo, v3, v1
v_cmp_ne_u32_e64 s4, s7, v1
v_cmp_gt_i32_e64 s3, s6, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s7, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s7, s6, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13floyd2DKernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13floyd2DKernelPiii, .Lfunc_end0-_Z13floyd2DKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13floyd2DKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13floyd2DKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void floyd2DKernel(int * M, const int nverts, const int k){
int jj = blockIdx.x * blockDim.x + threadIdx.x; // indice filas
int ii = blockIdx.y * blockDim.y + threadIdx.y; // indice columnas
int tid = (ii * nverts) + jj;
int i = tid/nverts;
int j = tid - i * nverts;
//printf ("Fila %u, Columna %u => Thread id %d.\n", i, j, tid);
if(i < nverts && j < nverts){
if (i!=j && i!=k && j!=k) {
int ik = (i*nverts) + k;
int kj = (k*nverts) + j;
int ij = (i*nverts) + j;
int aux = M[ik]+M[kj];
int vikj = min(aux, M[ij]);
M[ij] = vikj;
}
}
} | .text
.file "floyd2DKernel.hip"
.globl _Z28__device_stub__floyd2DKernelPiii # -- Begin function _Z28__device_stub__floyd2DKernelPiii
.p2align 4, 0x90
.type _Z28__device_stub__floyd2DKernelPiii,@function
_Z28__device_stub__floyd2DKernelPiii: # @_Z28__device_stub__floyd2DKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13floyd2DKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__floyd2DKernelPiii, .Lfunc_end0-_Z28__device_stub__floyd2DKernelPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13floyd2DKernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13floyd2DKernelPiii,@object # @_Z13floyd2DKernelPiii
.section .rodata,"a",@progbits
.globl _Z13floyd2DKernelPiii
.p2align 3, 0x0
_Z13floyd2DKernelPiii:
.quad _Z28__device_stub__floyd2DKernelPiii
.size _Z13floyd2DKernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13floyd2DKernelPiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__floyd2DKernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13floyd2DKernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13floyd2DKernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R9, c[0x0][0x168] ; /* 0x00005a0000097a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R9 ; /* 0x0000000900047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ea80000002600 */
/*0060*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000ea20000002200 */
/*0070*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fe20007ffe0ff */
/*00a0*/ IMAD R5, R6, c[0x0][0x4], R7 ; /* 0x0000010006057a24 */
/* 0x004fca00078e0207 */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000062000021f000 */
/*00c0*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fca00078e0200 */
/*00d0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe20000000000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.MOV R8, RZ, RZ, -R3 ; /* 0x000000ffff087224 */
/* 0x002fca00078e0a03 */
/*0100*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fca0000000f00 */
/*0110*/ IMAD R5, R6, R9, RZ ; /* 0x0000000906057224 */
/* 0x000fc800078e02ff */
/*0120*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0130*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0150*/ IMAD R2, R9, R2, R4 ; /* 0x0000000209027224 */
/* 0x000fca00078e0204 */
/*0160*/ ISETP.GT.U32.AND P2, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fda0003f44070 */
/*0170*/ @!P2 IADD3 R2, R2, -R9.reuse, RZ ; /* 0x800000090202a210 */
/* 0x080fe40007ffe0ff */
/*0180*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f06070 */
/*01a0*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fe400078e3cff */
/*01b0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f45270 */
/*01c0*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*01d0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01e0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0003 */
/*01f0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff05aa12 */
/* 0x000fca00078e33ff */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0220*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fc80003f06270 */
/*0240*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x168], P0 ; /* 0x00005a0005007a0c */
/* 0x000fda0000706670 */
/*0250*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0260*/ ISETP.NE.AND P0, PT, R5, R3, PT ; /* 0x000000030500720c */
/* 0x000fc80003f05270 */
/*0270*/ ISETP.EQ.OR P0, PT, R5, c[0x0][0x16c], !P0 ; /* 0x00005b0005007a0c */
/* 0x000fc80004702670 */
/*0280*/ ISETP.EQ.OR P0, PT, R3, c[0x0][0x16c], P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0000702670 */
/*0290*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02a0*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*02b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*02c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*02d0*/ IMAD R2, R5, R4, c[0x0][0x16c] ; /* 0x00005b0005027624 */
/* 0x000fe400078e0204 */
/*02e0*/ IMAD R4, R4, c[0x0][0x16c], R3 ; /* 0x00005b0004047a24 */
/* 0x000fe400078e0203 */
/*02f0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0207 */
/*0300*/ IMAD.WIDE R4, R4, R7.reuse, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x080fe400078e0207 */
/*0310*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe400078e0207 */
/*0330*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0340*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x004fc80007ffe0ff */
/*0360*/ IMNMX R9, R0, R9, PT ; /* 0x0000000900097217 */
/* 0x008fca0003800200 */
/*0370*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13floyd2DKernelPiii
.globl _Z13floyd2DKernelPiii
.p2align 8
.type _Z13floyd2DKernelPiii,@function
_Z13floyd2DKernelPiii:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s6, 31
s_lshr_b32 s5, s2, 16
s_add_i32 s4, s6, s3
s_and_b32 s2, s2, 0xffff
s_xor_b32 s4, s4, s3
s_mul_i32 s14, s14, s2
v_cvt_f32_u32_e32 v2, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v4, v2
v_mad_u64_u32 v[2:3], null, s15, s5, v[1:2]
s_sub_i32 s5, 0, s4
v_mul_lo_u32 v2, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v2
v_ashrrev_i32_e32 v2, 31, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v4 :: v_dual_add_nc_u32 v4, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_xor_b32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s5, v1
v_xor_b32_e32 v2, s3, v2
v_mul_hi_u32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v3
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v1, s4
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v3
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v3
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v1, v1, v2
v_sub_nc_u32_e32 v3, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v3, s6
v_cmp_ne_u32_e64 s2, s7, v3
v_sub_nc_u32_e32 v1, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_max_i32_e32 v4, v3, v1
v_cmp_ne_u32_e32 vcc_lo, v3, v1
v_cmp_ne_u32_e64 s4, s7, v1
v_cmp_gt_i32_e64 s3, s6, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v2, s7, v2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s7, s6, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13floyd2DKernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13floyd2DKernelPiii, .Lfunc_end0-_Z13floyd2DKernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13floyd2DKernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13floyd2DKernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00002f7c_00000000-6_floyd2DKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z13floyd2DKernelPiiiPiii
.type _Z35__device_stub__Z13floyd2DKernelPiiiPiii, @function
_Z35__device_stub__Z13floyd2DKernelPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13floyd2DKernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z13floyd2DKernelPiiiPiii, .-_Z35__device_stub__Z13floyd2DKernelPiiiPiii
.globl _Z13floyd2DKernelPiii
.type _Z13floyd2DKernelPiii, @function
_Z13floyd2DKernelPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13floyd2DKernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13floyd2DKernelPiii, .-_Z13floyd2DKernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13floyd2DKernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13floyd2DKernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "floyd2DKernel.hip"
.globl _Z28__device_stub__floyd2DKernelPiii # -- Begin function _Z28__device_stub__floyd2DKernelPiii
.p2align 4, 0x90
.type _Z28__device_stub__floyd2DKernelPiii,@function
_Z28__device_stub__floyd2DKernelPiii: # @_Z28__device_stub__floyd2DKernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13floyd2DKernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__floyd2DKernelPiii, .Lfunc_end0-_Z28__device_stub__floyd2DKernelPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13floyd2DKernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13floyd2DKernelPiii,@object # @_Z13floyd2DKernelPiii
.section .rodata,"a",@progbits
.globl _Z13floyd2DKernelPiii
.p2align 3, 0x0
_Z13floyd2DKernelPiii:
.quad _Z28__device_stub__floyd2DKernelPiii
.size _Z13floyd2DKernelPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13floyd2DKernelPiii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__floyd2DKernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13floyd2DKernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} | code for sm_80
Function : _Z9vecmabitePiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R4, 0x1, RZ ; /* 0x0000000104027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0005 */
/*0060*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} | .file "tmpxft_00092676_00000000-6_vecmabite.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9vecmabitePiS_mPiS_m
.type _Z31__device_stub__Z9vecmabitePiS_mPiS_m, @function
_Z31__device_stub__Z9vecmabitePiS_mPiS_m:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vecmabitePiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9vecmabitePiS_mPiS_m, .-_Z31__device_stub__Z9vecmabitePiS_mPiS_m
.globl _Z9vecmabitePiS_m
.type _Z9vecmabitePiS_m, @function
_Z9vecmabitePiS_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9vecmabitePiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vecmabitePiS_m, .-_Z9vecmabitePiS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vecmabitePiS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vecmabitePiS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vecmabitePiS_m
.globl _Z9vecmabitePiS_m
.p2align 8
.type _Z9vecmabitePiS_m,@function
_Z9vecmabitePiS_m:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vecmabitePiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vecmabitePiS_m, .Lfunc_end0-_Z9vecmabitePiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vecmabitePiS_m
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9vecmabitePiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void vecmabite( int *out, int *in, std::size_t size )
{
auto tid = threadIdx.x;
out[ tid ] = in[ 2 * tid ];
} | .text
.file "vecmabite.hip"
.globl _Z24__device_stub__vecmabitePiS_m # -- Begin function _Z24__device_stub__vecmabitePiS_m
.p2align 4, 0x90
.type _Z24__device_stub__vecmabitePiS_m,@function
_Z24__device_stub__vecmabitePiS_m: # @_Z24__device_stub__vecmabitePiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vecmabitePiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__vecmabitePiS_m, .Lfunc_end0-_Z24__device_stub__vecmabitePiS_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vecmabitePiS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vecmabitePiS_m,@object # @_Z9vecmabitePiS_m
.section .rodata,"a",@progbits
.globl _Z9vecmabitePiS_m
.p2align 3, 0x0
_Z9vecmabitePiS_m:
.quad _Z24__device_stub__vecmabitePiS_m
.size _Z9vecmabitePiS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vecmabitePiS_m"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vecmabitePiS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vecmabitePiS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9vecmabitePiS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ SHF.L.U32 R2, R4, 0x1, RZ ; /* 0x0000000104027819 */
/* 0x001fd000000006ff */
/*0050*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0005 */
/*0060*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0005 */
/*0080*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vecmabitePiS_m
.globl _Z9vecmabitePiS_m
.p2align 8
.type _Z9vecmabitePiS_m,@function
_Z9vecmabitePiS_m:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 3, v0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v1, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vecmabitePiS_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vecmabitePiS_m, .Lfunc_end0-_Z9vecmabitePiS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vecmabitePiS_m
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9vecmabitePiS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00092676_00000000-6_vecmabite.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9vecmabitePiS_mPiS_m
.type _Z31__device_stub__Z9vecmabitePiS_mPiS_m, @function
_Z31__device_stub__Z9vecmabitePiS_mPiS_m:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vecmabitePiS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z9vecmabitePiS_mPiS_m, .-_Z31__device_stub__Z9vecmabitePiS_mPiS_m
.globl _Z9vecmabitePiS_m
.type _Z9vecmabitePiS_m, @function
_Z9vecmabitePiS_m:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9vecmabitePiS_mPiS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9vecmabitePiS_m, .-_Z9vecmabitePiS_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9vecmabitePiS_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vecmabitePiS_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecmabite.hip"
.globl _Z24__device_stub__vecmabitePiS_m # -- Begin function _Z24__device_stub__vecmabitePiS_m
.p2align 4, 0x90
.type _Z24__device_stub__vecmabitePiS_m,@function
_Z24__device_stub__vecmabitePiS_m: # @_Z24__device_stub__vecmabitePiS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9vecmabitePiS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__vecmabitePiS_m, .Lfunc_end0-_Z24__device_stub__vecmabitePiS_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vecmabitePiS_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vecmabitePiS_m,@object # @_Z9vecmabitePiS_m
.section .rodata,"a",@progbits
.globl _Z9vecmabitePiS_m
.p2align 3, 0x0
_Z9vecmabitePiS_m:
.quad _Z24__device_stub__vecmabitePiS_m
.size _Z9vecmabitePiS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9vecmabitePiS_m"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vecmabitePiS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vecmabitePiS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by root on 2020/11/11.
//
#include "cuda_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
cudaMalloc(&h_a, size);
cudaMalloc(&h_b, size);
cudaMalloc(&h_c, size);
cudaMemcpy(h_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(h_b, b, size, cudaMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
cudaMemcpy(c, h_c, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
free(a);
free(b);
free(c);
return 0;
} | code for sm_80
Function : _Z9addMatrixPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fd600078ec0ff */
/*00c0*/ @!P0 BRA 0xec0 ; /* 0x00000df000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe40007ffe1ff */
/*00e0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*00f0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f04270 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R10, R0, R5, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R8, R0, R5, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe400078e0205 */
/*0140*/ @!P0 BRA 0xcc0 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x8d0 ; /* 0x0000075000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*01c0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*01d0*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x005fca0007ffe0ff */
/*01e0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0220*/ IMAD.WIDE R20, R5, c[0x0][0x178], R16 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0210 */
/*0230*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*0240*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*0250*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e8000c101904 */
/*0260*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*0290*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fc800078e0214 */
/*02a0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*02b0*/ IADD3 R23, R10, R11, RZ ; /* 0x0000000b0a177210 */
/* 0x004fca0007ffe0ff */
/*02c0*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000e68000c1e1900 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e62000c1e1900 */
/*02f0*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0300*/ IMAD.WIDE R14, R5, c[0x0][0x178], R8 ; /* 0x00005e00050e7a25 */
/* 0x000fe200078e0208 */
/*0310*/ IADD3 R25, R18, R19, RZ ; /* 0x0000001312197210 */
/* 0x002fc60007ffe0ff */
/*0320*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x040fe400078e0210 */
/*0330*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0340*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000e22000c1e1900 */
/*0360*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e020a */
/*0370*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0380*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0390*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e0212 */
/*03a0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000e68000c1e1900 */
/*03c0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000e62000c1e1900 */
/*03d0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*03f0*/ IADD3 R25, R8, R9, RZ ; /* 0x0000000908197210 */
/* 0x002fc60007ffe0ff */
/*0400*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x040fe400078e0214 */
/*0410*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R12, R5, c[0x0][0x178], R18 ; /* 0x00005e00050c7a25 */
/* 0x001fc800078e0212 */
/*0460*/ IMAD.WIDE R20, R5, c[0x0][0x178], R8 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0208 */
/*0470*/ IADD3 R27, R14, R15, RZ ; /* 0x0000000f0e1b7210 */
/* 0x004fca0007ffe0ff */
/*0480*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.WIDE R14, R5, c[0x0][0x178], R10 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e020a */
/*04c0*/ IMAD.WIDE R22, R5, c[0x0][0x178], R20 ; /* 0x00005e0005167a25 */
/* 0x000fe200078e0214 */
/*04d0*/ IADD3 R29, R16, R17, RZ ; /* 0x00000011101d7210 */
/* 0x004fc60007ffe0ff */
/*04e0*/ IMAD.WIDE R16, R5.reuse, c[0x0][0x178], R12 ; /* 0x00005e0005107a25 */
/* 0x040fe400078e020c */
/*04f0*/ STG.E [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000e28000c1e1900 */
/*0510*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000e22000c1e1900 */
/*0520*/ IMAD.WIDE R6, R5, c[0x0][0x178], R14 ; /* 0x00005e0005067a25 */
/* 0x002fc800078e020e */
/*0530*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x000fc800078e0216 */
/*0540*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*0550*/ IADD3 R27, R8, R9, RZ ; /* 0x00000009081b7210 */
/* 0x001fca0007ffe0ff */
/*0560*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ee8000c1e1900 */
/*0580*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IMAD.WIDE R8, R5, c[0x0][0x178], R6 ; /* 0x00005e0005087a25 */
/* 0x000fc800078e0206 */
/*05a0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R18 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0212 */
/*05b0*/ IADD3 R21, R10, R11, RZ ; /* 0x0000000b0a157210 */
/* 0x008fc60007ffe0ff */
/*05c0*/ IMAD.WIDE R10, R5.reuse, c[0x0][0x178], R24 ; /* 0x00005e00050a7a25 */
/* 0x040fe400078e0218 */
/*05d0*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x004ea8000c1e1900 */
/*05f0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0610*/ IMAD.WIDE R6, R5, c[0x0][0x178], R16 ; /* 0x00005e0005067a25 */
/* 0x001fc800078e0210 */
/*0620*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020a */
/*0630*/ IADD3 R23, R14, R15, RZ ; /* 0x0000000f0e177210 */
/* 0x004fca0007ffe0ff */
/*0640*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R25, [R6.64] ; /* 0x0000000406197981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE R14, R5, c[0x0][0x178], R12 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e020c */
/*0680*/ IMAD.WIDE R10, R5, c[0x0][0x178], R18 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0212 */
/*0690*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*06a0*/ IADD3 R25, R20, R25, RZ ; /* 0x0000001914197210 */
/* 0x004fca0007ffe0ff */
/*06b0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*06c0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000e28000c1e1900 */
/*06d0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002e22000c1e1900 */
/*06e0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R14 ; /* 0x00005e0005087a25 */
/* 0x000fc800078e020e */
/*06f0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*0700*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0710*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R10 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e020a */
/*0720*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0730*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IMAD.WIDE R6, R5, c[0x0][0x178], R8 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e0208 */
/*0760*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0214 */
/*0770*/ IMAD.WIDE R16, R5, c[0x0][0x178], R18 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0212 */
/*0780*/ IADD3 R25, R12, R13, RZ ; /* 0x0000000d0c197210 */
/* 0x004fca0007ffe0ff */
/*0790*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*07a0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000e28000c1e1900 */
/*07b0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000e22000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R6 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020a */
/*07e0*/ IADD3 R9, R14, R15, RZ ; /* 0x0000000f0e097210 */
/* 0x001fc60007ffe0ff */
/*07f0*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0210 */
/*0800*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x000ea2000c1e1900 */
/*0830*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.WIDE R20, R5, c[0x0][0x178], R12 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e020c */
/*0850*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc40007ffe0ff */
/*0860*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0870*/ IMAD.WIDE R10, R5, c[0x0][0x178], R18 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0212 */
/*0880*/ IMAD.WIDE R6, R5, c[0x0][0x178], R14 ; /* 0x00005e0005067a25 */
/* 0x002fe200078e020e */
/*0890*/ IADD3 R23, R8, R23, RZ ; /* 0x0000001708177210 */
/* 0x004fc60007ffe0ff */
/*08a0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fe400078e0214 */
/*08b0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0001e4000c101904 */
/*08c0*/ @P1 BRA 0x190 ; /* 0xfffff8c000001947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*08e0*/ @!P1 BRA 0xca0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*0920*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*0930*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x005fca0007ffe0ff */
/*0940*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R20, R5, c[0x0][0x178], R16 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0210 */
/*0990*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*09a0*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*09b0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e8000c101904 */
/*09c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*09f0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fc800078e0214 */
/*0a00*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0a10*/ IADD3 R23, R10, R11, RZ ; /* 0x0000000b0a177210 */
/* 0x004fca0007ffe0ff */
/*0a20*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e8000c101904 */
/*0a30*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000e68000c1e1900 */
/*0a40*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e62000c1e1900 */
/*0a50*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0a60*/ IMAD.WIDE R14, R5, c[0x0][0x178], R8 ; /* 0x00005e00050e7a25 */
/* 0x000fe200078e0208 */
/*0a70*/ IADD3 R25, R18, R19, RZ ; /* 0x0000001312197210 */
/* 0x002fc60007ffe0ff */
/*0a80*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x040fe400078e0210 */
/*0a90*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0aa0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e28000c1e1900 */
/*0ab0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000e22000c1e1900 */
/*0ac0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e020a */
/*0ad0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0ae0*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0af0*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e0212 */
/*0b00*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*0b40*/ IMAD.WIDE R10, R5, c[0x0][0x178], R16 ; /* 0x00005e00050a7a25 */
/* 0x002fe200078e0210 */
/*0b50*/ IADD3 R25, R8, R9, RZ ; /* 0x0000000908197210 */
/* 0x004fc60007ffe0ff */
/*0b60*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x040fe400078e0214 */
/*0b70*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*0b80*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ IMAD.WIDE R14, R5, c[0x0][0x178], R6 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e0206 */
/*0bb0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x001fc800078e020a */
/*0bc0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R8 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0208 */
/*0bd0*/ IADD3 R23, R18, R19, RZ ; /* 0x0000001312177210 */
/* 0x004fca0007ffe0ff */
/*0be0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0001e8000c101904 */
/*0bf0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.WIDE R18, R5, c[0x0][0x178], R14 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020e */
/*0c20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0c30*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ IMAD.WIDE R10, R5, c[0x0][0x178], R16 ; /* 0x00005e00050a7a25 */
/* 0x000fe200078e0210 */
/*0c50*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x002fc800078e020c */
/*0c70*/ IMAD.WIDE R8, R5, c[0x0][0x178], R18 ; /* 0x00005e0005087a25 */
/* 0x000fe200078e0212 */
/*0c80*/ IADD3 R21, R20, R21, RZ ; /* 0x0000001514157210 */
/* 0x004fca0007ffe0ff */
/*0c90*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0cb0*/ @!P0 BRA 0xec0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0cd0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*0ce0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x001fc800078e020a */
/*0cf0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R6 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0206 */
/*0d00*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x004fca0007ffe0ff */
/*0d10*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0d20*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0d30*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000ea2000c1e1900 */
/*0d40*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0d50*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fe200078e0214 */
/*0d60*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*0d70*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*0d80*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x000fe8000c101904 */
/*0d90*/ LDG.E R6, [R14.64] ; /* 0x000000040e067981 */
/* 0x000e28000c1e1900 */
/*0da0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x000e22000c1e1900 */
/*0db0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R12 ; /* 0x00005e0005107a25 */
/* 0x000fc800078e020c */
/*0dc0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*0dd0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R14 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e020e */
/*0de0*/ IADD3 R9, R6, R7, RZ ; /* 0x0000000706097210 */
/* 0x001fca0007ffe0ff */
/*0df0*/ STG.E [R16.64], R9 ; /* 0x0000000910007986 */
/* 0x0001e8000c101904 */
/*0e00*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000ea8000c1e1900 */
/*0e10*/ LDG.E R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ IMAD.WIDE R22, R5, c[0x0][0x178], R16 ; /* 0x00005e0005167a25 */
/* 0x000fe200078e0210 */
/*0e40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0e50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0e60*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0214 */
/*0e70*/ IMAD.WIDE R8, R5, c[0x0][0x178], R22 ; /* 0x00005e0005087a25 */
/* 0x001fe200078e0216 */
/*0e80*/ IADD3 R13, R6, R7, RZ ; /* 0x00000007060d7210 */
/* 0x004fc60007ffe0ff */
/*0e90*/ IMAD.WIDE R6, R5, c[0x0][0x178], R18 ; /* 0x00005e0005067a25 */
/* 0x000fe400078e0212 */
/*0ea0*/ STG.E [R22.64], R13 ; /* 0x0000000d16007986 */
/* 0x0001e4000c101904 */
/*0eb0*/ @P0 BRA 0xcc0 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0ec0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ed0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ee0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0ef0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fd200078e0200 */
/*0f00*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0f10*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0f20*/ IMAD.WIDE R8, R0, R11, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020b */
/*0f30*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x0002a8000c1e1900 */
/*0f40*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0006a2000c1e1900 */
/*0f50*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0f60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0f70*/ IMAD.WIDE R6, R11, c[0x0][0x178], R6 ; /* 0x00005e000b067a25 */
/* 0x002fc800078e0206 */
/*0f80*/ IMAD.WIDE R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a25 */
/* 0x008fe200078e0208 */
/*0f90*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x004fca0007ffe0ff */
/*0fa0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0003e4000c101904 */
/*0fb0*/ IMAD.WIDE R4, R11, c[0x0][0x178], R4 ; /* 0x00005e000b047a25 */
/* 0x002fe200078e0204 */
/*0fc0*/ @P0 BRA 0xf30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0fd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0xfe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by root on 2020/11/11.
//
#include "cuda_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
cudaMalloc(&h_a, size);
cudaMalloc(&h_b, size);
cudaMalloc(&h_c, size);
cudaMemcpy(h_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(h_b, b, size, cudaMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
cudaMemcpy(c, h_c, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_000854f7_00000000-6_SumMatrix.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
.type _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii, @function
_Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addMatrixPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii, .-_Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
.globl _Z9addMatrixPiS_S_ii
.type _Z9addMatrixPiS_S_ii, @function
_Z9addMatrixPiS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9addMatrixPiS_S_ii, .-_Z9addMatrixPiS_S_ii
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $0, %eax
.L12:
leal (%rax,%rax), %edx
movl %edx, (%r14,%rax,4)
leal 1(%rax), %edx
movl %edx, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $40, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %r12
leaq 40(%rbx), %r15
jmp .L18
.L23:
movl $2, %r8d
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
jmp .L13
.L26:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r15, %r12
je .L25
.L18:
movl (%r12), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L26
cmpb $0, 56(%rbp)
je .L16
movzbl 67(%rbp), %esi
jmp .L17
.L25:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addMatrixPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by root on 2020/11/11.
//
#include "cuda_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
cudaMalloc(&h_a, size);
cudaMalloc(&h_b, size);
cudaMalloc(&h_c, size);
cudaMemcpy(h_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(h_b, b, size, cudaMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
cudaMemcpy(c, h_c, size, cudaMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
cudaFree(h_a);
cudaFree(h_b);
cudaFree(h_c);
free(a);
free(b);
free(c);
return 0;
} | //
// Created by root on 2020/11/11.
//
#include "hip/hip_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
hipMalloc(&h_a, size);
hipMalloc(&h_b, size);
hipMalloc(&h_c, size);
hipMemcpy(h_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(h_b, b, size, hipMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
hipMemcpy(c, h_c, size, hipMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by root on 2020/11/11.
//
#include "hip/hip_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
hipMalloc(&h_a, size);
hipMalloc(&h_b, size);
hipMalloc(&h_c, size);
hipMemcpy(h_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(h_b, b, size, hipMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
hipMemcpy(c, h_c, size, hipMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPiS_S_ii
.globl _Z9addMatrixPiS_S_ii
.p2align 8
.type _Z9addMatrixPiS_S_ii,@function
_Z9addMatrixPiS_S_ii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x3
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPiS_S_ii, .Lfunc_end0-_Z9addMatrixPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by root on 2020/11/11.
//
#include "hip/hip_runtime.h"
#include "iostream"
__global__ void addMatrix(int* a, int* b, int* c, int nx, int ny) {
int idx = threadIdx.x + blockIdx.x * blockDim.x;
int idy = 0;
for (; idy < ny; idy++) {
int index = idy * nx + idx;
c[index] = a[index] + b[index];
}
}
int main() {
int x = 5, y = 2;
int size = x * y * sizeof(int);
int *a = (int*) malloc(size);
int *b = (int*) malloc(size);
int *c = (int*) malloc(size);
for (int i = 0; i < x * y; i++) {
a[i] = i * 2;
b[i] = i + 1;
}
int* h_a;
int* h_b;
int* h_c;
hipMalloc(&h_a, size);
hipMalloc(&h_b, size);
hipMalloc(&h_c, size);
hipMemcpy(h_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(h_b, b, size, hipMemcpyHostToDevice);
dim3 block(32, 32);
dim3 grid((x + block.x - 1) / block.x, (y + block.y - 1) / block.y);
addMatrix<<<grid, block>>>(h_a, h_b, h_c, x, y);
hipMemcpy(c, h_c, size, hipMemcpyDeviceToHost);
for (int i = 0; i < x * y; i++) {
std::cout << c[i] << std::endl;
}
hipFree(h_a);
hipFree(h_b);
hipFree(h_c);
free(a);
free(b);
free(c);
return 0;
} | .text
.file "SumMatrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addMatrixPiS_S_ii # -- Begin function _Z24__device_stub__addMatrixPiS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPiS_S_ii,@function
_Z24__device_stub__addMatrixPiS_S_ii: # @_Z24__device_stub__addMatrixPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addMatrixPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPiS_S_ii, .Lfunc_end0-_Z24__device_stub__addMatrixPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,2)
movl %eax, (%r14,%rcx,2)
addq $2, %rcx
incl %eax
cmpq $20, %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
movl $2, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addMatrixPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $10, %r13
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r12)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addMatrixPiS_S_ii,@object # @_Z9addMatrixPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z9addMatrixPiS_S_ii
.p2align 3, 0x0
_Z9addMatrixPiS_S_ii:
.quad _Z24__device_stub__addMatrixPiS_S_ii
.size _Z9addMatrixPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addMatrixPiS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addMatrixPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addMatrixPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0050*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x003fe200078e0203 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00b0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fd600078ec0ff */
/*00c0*/ @!P0 BRA 0xec0 ; /* 0x00000df000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, -R2, c[0x0][0x17c], RZ ; /* 0x00005f0002047a10 */
/* 0x000fe40007ffe1ff */
/*00e0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*00f0*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f04270 */
/*0100*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD.WIDE R6, R0, R5, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0205 */
/*0120*/ IMAD.WIDE R10, R0, R5, c[0x0][0x168] ; /* 0x00005a00000a7625 */
/* 0x000fc800078e0205 */
/*0130*/ IMAD.WIDE R8, R0, R5, c[0x0][0x170] ; /* 0x00005c0000087625 */
/* 0x000fe400078e0205 */
/*0140*/ @!P0 BRA 0xcc0 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0x8d0 ; /* 0x0000075000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*01c0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*01d0*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x005fca0007ffe0ff */
/*01e0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*01f0*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0220*/ IMAD.WIDE R20, R5, c[0x0][0x178], R16 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0210 */
/*0230*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*0240*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*0250*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e8000c101904 */
/*0260*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*0290*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fc800078e0214 */
/*02a0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*02b0*/ IADD3 R23, R10, R11, RZ ; /* 0x0000000b0a177210 */
/* 0x004fca0007ffe0ff */
/*02c0*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e8000c101904 */
/*02d0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000e68000c1e1900 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e62000c1e1900 */
/*02f0*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0300*/ IMAD.WIDE R14, R5, c[0x0][0x178], R8 ; /* 0x00005e00050e7a25 */
/* 0x000fe200078e0208 */
/*0310*/ IADD3 R25, R18, R19, RZ ; /* 0x0000001312197210 */
/* 0x002fc60007ffe0ff */
/*0320*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x040fe400078e0210 */
/*0330*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0340*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e28000c1e1900 */
/*0350*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000e22000c1e1900 */
/*0360*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e020a */
/*0370*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0380*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0390*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e0212 */
/*03a0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000e68000c1e1900 */
/*03c0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000e62000c1e1900 */
/*03d0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*03e0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*03f0*/ IADD3 R25, R8, R9, RZ ; /* 0x0000000908197210 */
/* 0x002fc60007ffe0ff */
/*0400*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x040fe400078e0214 */
/*0410*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*0420*/ LDG.E R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ea8000c1e1900 */
/*0430*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x000ea2000c1e1900 */
/*0440*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0450*/ IMAD.WIDE R12, R5, c[0x0][0x178], R18 ; /* 0x00005e00050c7a25 */
/* 0x001fc800078e0212 */
/*0460*/ IMAD.WIDE R20, R5, c[0x0][0x178], R8 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0208 */
/*0470*/ IADD3 R27, R14, R15, RZ ; /* 0x0000000f0e1b7210 */
/* 0x004fca0007ffe0ff */
/*0480*/ STG.E [R10.64], R27 ; /* 0x0000001b0a007986 */
/* 0x0001e8000c101904 */
/*0490*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea8000c1e1900 */
/*04a0*/ LDG.E R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x000ea2000c1e1900 */
/*04b0*/ IMAD.WIDE R14, R5, c[0x0][0x178], R10 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e020a */
/*04c0*/ IMAD.WIDE R22, R5, c[0x0][0x178], R20 ; /* 0x00005e0005167a25 */
/* 0x000fe200078e0214 */
/*04d0*/ IADD3 R29, R16, R17, RZ ; /* 0x00000011101d7210 */
/* 0x004fc60007ffe0ff */
/*04e0*/ IMAD.WIDE R16, R5.reuse, c[0x0][0x178], R12 ; /* 0x00005e0005107a25 */
/* 0x040fe400078e020c */
/*04f0*/ STG.E [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000e28000c1e1900 */
/*0510*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000e22000c1e1900 */
/*0520*/ IMAD.WIDE R6, R5, c[0x0][0x178], R14 ; /* 0x00005e0005067a25 */
/* 0x002fc800078e020e */
/*0530*/ IMAD.WIDE R24, R5, c[0x0][0x178], R22 ; /* 0x00005e0005187a25 */
/* 0x000fc800078e0216 */
/*0540*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*0550*/ IADD3 R27, R8, R9, RZ ; /* 0x00000009081b7210 */
/* 0x001fca0007ffe0ff */
/*0560*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0001e8000c101904 */
/*0570*/ LDG.E R10, [R24.64] ; /* 0x00000004180a7981 */
/* 0x000ee8000c1e1900 */
/*0580*/ LDG.E R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IMAD.WIDE R8, R5, c[0x0][0x178], R6 ; /* 0x00005e0005087a25 */
/* 0x000fc800078e0206 */
/*05a0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R18 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0212 */
/*05b0*/ IADD3 R21, R10, R11, RZ ; /* 0x0000000b0a157210 */
/* 0x008fc60007ffe0ff */
/*05c0*/ IMAD.WIDE R10, R5.reuse, c[0x0][0x178], R24 ; /* 0x00005e00050a7a25 */
/* 0x040fe400078e0218 */
/*05d0*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x004ea8000c1e1900 */
/*05f0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0600*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0610*/ IMAD.WIDE R6, R5, c[0x0][0x178], R16 ; /* 0x00005e0005067a25 */
/* 0x001fc800078e0210 */
/*0620*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020a */
/*0630*/ IADD3 R23, R14, R15, RZ ; /* 0x0000000f0e177210 */
/* 0x004fca0007ffe0ff */
/*0640*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R25, [R6.64] ; /* 0x0000000406197981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE R14, R5, c[0x0][0x178], R12 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e020c */
/*0680*/ IMAD.WIDE R10, R5, c[0x0][0x178], R18 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0212 */
/*0690*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*06a0*/ IADD3 R25, R20, R25, RZ ; /* 0x0000001914197210 */
/* 0x004fca0007ffe0ff */
/*06b0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0005e8000c101904 */
/*06c0*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000e28000c1e1900 */
/*06d0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002e22000c1e1900 */
/*06e0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R14 ; /* 0x00005e0005087a25 */
/* 0x000fc800078e020e */
/*06f0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e0210 */
/*0700*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0710*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R10 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e020a */
/*0720*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0730*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IMAD.WIDE R6, R5, c[0x0][0x178], R8 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e0208 */
/*0760*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0214 */
/*0770*/ IMAD.WIDE R16, R5, c[0x0][0x178], R18 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0212 */
/*0780*/ IADD3 R25, R12, R13, RZ ; /* 0x0000000d0c197210 */
/* 0x004fca0007ffe0ff */
/*0790*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*07a0*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000e28000c1e1900 */
/*07b0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000e22000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R6 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020a */
/*07e0*/ IADD3 R9, R14, R15, RZ ; /* 0x0000000f0e097210 */
/* 0x001fc60007ffe0ff */
/*07f0*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0210 */
/*0800*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*0810*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R8, [R18.64] ; /* 0x0000000412087981 */
/* 0x000ea2000c1e1900 */
/*0830*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0840*/ IMAD.WIDE R20, R5, c[0x0][0x178], R12 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e020c */
/*0850*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc40007ffe0ff */
/*0860*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*0870*/ IMAD.WIDE R10, R5, c[0x0][0x178], R18 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0212 */
/*0880*/ IMAD.WIDE R6, R5, c[0x0][0x178], R14 ; /* 0x00005e0005067a25 */
/* 0x002fe200078e020e */
/*0890*/ IADD3 R23, R8, R23, RZ ; /* 0x0000001708177210 */
/* 0x004fc60007ffe0ff */
/*08a0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fe400078e0214 */
/*08b0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0001e4000c101904 */
/*08c0*/ @P1 BRA 0x190 ; /* 0xfffff8c000001947 */
/* 0x000fea000383ffff */
/*08d0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*08e0*/ @!P1 BRA 0xca0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*0920*/ IMAD.WIDE R16, R5, c[0x0][0x178], R6 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0206 */
/*0930*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x005fca0007ffe0ff */
/*0940*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R20, R5, c[0x0][0x178], R16 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0210 */
/*0990*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*09a0*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*09b0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0003e8000c101904 */
/*09c0*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R11, [R20.64] ; /* 0x00000004140b7981 */
/* 0x000ea2000c1e1900 */
/*09e0*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*09f0*/ IMAD.WIDE R8, R5, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x001fc800078e0214 */
/*0a00*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0a10*/ IADD3 R23, R10, R11, RZ ; /* 0x0000000b0a177210 */
/* 0x004fca0007ffe0ff */
/*0a20*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e8000c101904 */
/*0a30*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000e68000c1e1900 */
/*0a40*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e62000c1e1900 */
/*0a50*/ IMAD.WIDE R10, R5, c[0x0][0x178], R6 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0206 */
/*0a60*/ IMAD.WIDE R14, R5, c[0x0][0x178], R8 ; /* 0x00005e00050e7a25 */
/* 0x000fe200078e0208 */
/*0a70*/ IADD3 R25, R18, R19, RZ ; /* 0x0000001312197210 */
/* 0x002fc60007ffe0ff */
/*0a80*/ IMAD.WIDE R18, R5.reuse, c[0x0][0x178], R16 ; /* 0x00005e0005127a25 */
/* 0x040fe400078e0210 */
/*0a90*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0003e8000c101904 */
/*0aa0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e28000c1e1900 */
/*0ab0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000e22000c1e1900 */
/*0ac0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e020a */
/*0ad0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R14 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e020e */
/*0ae0*/ IADD3 R23, R20, R21, RZ ; /* 0x0000001514177210 */
/* 0x001fc60007ffe0ff */
/*0af0*/ IMAD.WIDE R20, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e0005147a25 */
/* 0x040fe400078e0212 */
/*0b00*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x000fc800078e020c */
/*0b40*/ IMAD.WIDE R10, R5, c[0x0][0x178], R16 ; /* 0x00005e00050a7a25 */
/* 0x002fe200078e0210 */
/*0b50*/ IADD3 R25, R8, R9, RZ ; /* 0x0000000908197210 */
/* 0x004fc60007ffe0ff */
/*0b60*/ IMAD.WIDE R8, R5.reuse, c[0x0][0x178], R20 ; /* 0x00005e0005087a25 */
/* 0x040fe400078e0214 */
/*0b70*/ STG.E [R6.64], R25 ; /* 0x0000001906007986 */
/* 0x0003e8000c101904 */
/*0b80*/ LDG.E R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1900 */
/*0b90*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea2000c1e1900 */
/*0ba0*/ IMAD.WIDE R14, R5, c[0x0][0x178], R6 ; /* 0x00005e00050e7a25 */
/* 0x000fc800078e0206 */
/*0bb0*/ IMAD.WIDE R12, R5, c[0x0][0x178], R10 ; /* 0x00005e00050c7a25 */
/* 0x001fc800078e020a */
/*0bc0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R8 ; /* 0x00005e0005107a25 */
/* 0x000fe200078e0208 */
/*0bd0*/ IADD3 R23, R18, R19, RZ ; /* 0x0000001312177210 */
/* 0x004fca0007ffe0ff */
/*0be0*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0001e8000c101904 */
/*0bf0*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000ea8000c1e1900 */
/*0c00*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*0c10*/ IMAD.WIDE R18, R5, c[0x0][0x178], R14 ; /* 0x00005e0005127a25 */
/* 0x000fe200078e020e */
/*0c20*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0c30*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ IMAD.WIDE R10, R5, c[0x0][0x178], R16 ; /* 0x00005e00050a7a25 */
/* 0x000fe200078e0210 */
/*0c50*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ IMAD.WIDE R6, R5, c[0x0][0x178], R12 ; /* 0x00005e0005067a25 */
/* 0x002fc800078e020c */
/*0c70*/ IMAD.WIDE R8, R5, c[0x0][0x178], R18 ; /* 0x00005e0005087a25 */
/* 0x000fe200078e0212 */
/*0c80*/ IADD3 R21, R20, R21, RZ ; /* 0x0000001514157210 */
/* 0x004fca0007ffe0ff */
/*0c90*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0cb0*/ @!P0 BRA 0xec0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0cc0*/ LDG.E R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1900 */
/*0cd0*/ LDG.E R13, [R6.64] ; /* 0x00000004060d7981 */
/* 0x000ea2000c1e1900 */
/*0ce0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x001fc800078e020a */
/*0cf0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R6 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e0206 */
/*0d00*/ IADD3 R23, R12, R13, RZ ; /* 0x0000000d0c177210 */
/* 0x004fca0007ffe0ff */
/*0d10*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0001e8000c101904 */
/*0d20*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea8000c1e1900 */
/*0d30*/ LDG.E R15, [R20.64] ; /* 0x00000004140f7981 */
/* 0x000ea2000c1e1900 */
/*0d40*/ IMAD.WIDE R12, R5, c[0x0][0x178], R8 ; /* 0x00005e00050c7a25 */
/* 0x000fc800078e0208 */
/*0d50*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fe200078e0214 */
/*0d60*/ IADD3 R25, R14, R15, RZ ; /* 0x0000000f0e197210 */
/* 0x004fc60007ffe0ff */
/*0d70*/ IMAD.WIDE R14, R5.reuse, c[0x0][0x178], R18 ; /* 0x00005e00050e7a25 */
/* 0x040fe400078e0212 */
/*0d80*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x000fe8000c101904 */
/*0d90*/ LDG.E R6, [R14.64] ; /* 0x000000040e067981 */
/* 0x000e28000c1e1900 */
/*0da0*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x000e22000c1e1900 */
/*0db0*/ IMAD.WIDE R16, R5, c[0x0][0x178], R12 ; /* 0x00005e0005107a25 */
/* 0x000fc800078e020c */
/*0dc0*/ IMAD.WIDE R18, R5, c[0x0][0x178], R10 ; /* 0x00005e0005127a25 */
/* 0x000fc800078e020a */
/*0dd0*/ IMAD.WIDE R20, R5, c[0x0][0x178], R14 ; /* 0x00005e0005147a25 */
/* 0x000fe200078e020e */
/*0de0*/ IADD3 R9, R6, R7, RZ ; /* 0x0000000706097210 */
/* 0x001fca0007ffe0ff */
/*0df0*/ STG.E [R16.64], R9 ; /* 0x0000000910007986 */
/* 0x0001e8000c101904 */
/*0e00*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x000ea8000c1e1900 */
/*0e10*/ LDG.E R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x000ea2000c1e1900 */
/*0e20*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ IMAD.WIDE R22, R5, c[0x0][0x178], R16 ; /* 0x00005e0005167a25 */
/* 0x000fe200078e0210 */
/*0e40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc40007ffe0ff */
/*0e50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0e60*/ IMAD.WIDE R10, R5, c[0x0][0x178], R20 ; /* 0x00005e00050a7a25 */
/* 0x000fc800078e0214 */
/*0e70*/ IMAD.WIDE R8, R5, c[0x0][0x178], R22 ; /* 0x00005e0005087a25 */
/* 0x001fe200078e0216 */
/*0e80*/ IADD3 R13, R6, R7, RZ ; /* 0x00000007060d7210 */
/* 0x004fc60007ffe0ff */
/*0e90*/ IMAD.WIDE R6, R5, c[0x0][0x178], R18 ; /* 0x00005e0005067a25 */
/* 0x000fe400078e0212 */
/*0ea0*/ STG.E [R22.64], R13 ; /* 0x0000000d16007986 */
/* 0x0001e4000c101904 */
/*0eb0*/ @P0 BRA 0xcc0 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0ec0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0ed0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ee0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*0ef0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fd200078e0200 */
/*0f00*/ IMAD.WIDE R4, R0, R11, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e020b */
/*0f10*/ IMAD.WIDE R6, R0, R11, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x000fc800078e020b */
/*0f20*/ IMAD.WIDE R8, R0, R11, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020b */
/*0f30*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x0002a8000c1e1900 */
/*0f40*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0006a2000c1e1900 */
/*0f50*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0f60*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0f70*/ IMAD.WIDE R6, R11, c[0x0][0x178], R6 ; /* 0x00005e000b067a25 */
/* 0x002fc800078e0206 */
/*0f80*/ IMAD.WIDE R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a25 */
/* 0x008fe200078e0208 */
/*0f90*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x004fca0007ffe0ff */
/*0fa0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0003e4000c101904 */
/*0fb0*/ IMAD.WIDE R4, R11, c[0x0][0x178], R4 ; /* 0x00005e000b047a25 */
/* 0x002fe200078e0204 */
/*0fc0*/ @P0 BRA 0xf30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0fd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0xfe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addMatrixPiS_S_ii
.globl _Z9addMatrixPiS_S_ii
.p2align 8
.type _Z9addMatrixPiS_S_ii,@function
_Z9addMatrixPiS_S_ii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x3
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, -1
s_cmp_lg_u32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addMatrixPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addMatrixPiS_S_ii, .Lfunc_end0-_Z9addMatrixPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addMatrixPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addMatrixPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000854f7_00000000-6_SumMatrix.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
.type _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii, @function
_Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addMatrixPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii, .-_Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
.globl _Z9addMatrixPiS_S_ii
.type _Z9addMatrixPiS_S_ii, @function
_Z9addMatrixPiS_S_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9addMatrixPiS_S_ii, .-_Z9addMatrixPiS_S_ii
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $0, %eax
.L12:
leal (%rax,%rax), %edx
movl %edx, (%r14,%rax,4)
leal 1(%rax), %edx
movl %edx, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L13:
movl $2, %ecx
movl $40, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %r12
leaq 40(%rbx), %r15
jmp .L18
.L23:
movl $2, %r8d
movl $5, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addMatrixPiS_S_iiPiS_S_ii
jmp .L13
.L26:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
call _ZSt16__throw_bad_castv@PLT
.L24:
call __stack_chk_fail@PLT
.L16:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L17:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r15, %r12
je .L25
.L18:
movl (%r12), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L26
cmpb $0, 56(%rbp)
je .L16
movzbl 67(%rbp), %esi
jmp .L17
.L25:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addMatrixPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addMatrixPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "SumMatrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addMatrixPiS_S_ii # -- Begin function _Z24__device_stub__addMatrixPiS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__addMatrixPiS_S_ii,@function
_Z24__device_stub__addMatrixPiS_S_ii: # @_Z24__device_stub__addMatrixPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addMatrixPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addMatrixPiS_S_ii, .Lfunc_end0-_Z24__device_stub__addMatrixPiS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
movl $1, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, (%rbx,%rcx,2)
movl %eax, (%r14,%rcx,2)
addq $2, %rcx
incl %eax
cmpq $20, %rcx
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
movl $2, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addMatrixPiS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_5 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_5 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $10, %r13
je .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_5 Depth=1
cmpb $0, 56(%r12)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_5 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addMatrixPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addMatrixPiS_S_ii,@object # @_Z9addMatrixPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z9addMatrixPiS_S_ii
.p2align 3, 0x0
_Z9addMatrixPiS_S_ii:
.quad _Z24__device_stub__addMatrixPiS_S_ii
.size _Z9addMatrixPiS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addMatrixPiS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addMatrixPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addMatrixPiS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_00024da8_00000000-6_01.HelloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void cuda_hello()
{
printf("Hello World from GPU!\n");
}
int main()
{
printf("Hello World from CPU!\n");
cuda_hello<<<2,3>>>();
hipDeviceReset();
return 0;
} | .text
.file "01.HelloWorld.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10cuda_hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10cuda_hellov
.globl _Z10cuda_hellov
.p2align 8
.type _Z10cuda_hellov,@function
_Z10cuda_hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10cuda_hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10cuda_hellov, .Lfunc_end0-_Z10cuda_hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10cuda_hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10cuda_hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00024da8_00000000-6_01.HelloWorld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10cuda_hellovv
.type _Z29__device_stub__Z10cuda_hellovv, @function
_Z29__device_stub__Z10cuda_hellovv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10cuda_hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10cuda_hellovv, .-_Z29__device_stub__Z10cuda_hellovv
.globl _Z10cuda_hellov
.type _Z10cuda_hellov, @function
_Z10cuda_hellov:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10cuda_hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10cuda_hellov, .-_Z10cuda_hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 20(%rsp)
movl $1, 24(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10cuda_hellovv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z10cuda_hellov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z10cuda_hellov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01.HelloWorld.hip"
.globl _Z25__device_stub__cuda_hellov # -- Begin function _Z25__device_stub__cuda_hellov
.p2align 4, 0x90
.type _Z25__device_stub__cuda_hellov,@function
_Z25__device_stub__cuda_hellov: # @_Z25__device_stub__cuda_hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__cuda_hellov, .Lfunc_end0-_Z25__device_stub__cuda_hellov
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10cuda_hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10cuda_hellov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10cuda_hellov,@object # @_Z10cuda_hellov
.section .rodata,"a",@progbits
.globl _Z10cuda_hellov
.p2align 3, 0x0
_Z10cuda_hellov:
.quad _Z25__device_stub__cuda_hellov
.size _Z10cuda_hellov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10cuda_hellov"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__cuda_hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10cuda_hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP | .file "tmpxft_0006aa83_00000000-6_warn-device-init-fun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP | #include <hip/hip_runtime.h>
// REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// REQUIRES: nvptx-registered-target
// RUN: %clang_cc1 -triple nvptx -fcuda-is-device \
// RUN: -fgpu-allow-device-init \
// RUN: %s 2>&1 | FileCheck %s
// CHECK: warning: '-fgpu-allow-device-init' is ignored since it is only supported for HIP | .text
.file "warn-device-init-fun.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006aa83_00000000-6_warn-device-init-fun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "warn-device-init-fun.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
int main()
{
int count;
cudaGetDeviceCount(&count);
cudaDeviceProp prop;
for (int i = 0; i < count; ++i)
{
cudaGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
int main()
{
int count;
cudaGetDeviceCount(&count);
cudaDeviceProp prop;
for (int i = 0; i < count; ++i)
{
cudaGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} | .file "tmpxft_00107114_00000000-6_info_gpu2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device "
.LC1:
.string ": "
.LC2:
.string "Compute Capability: "
.LC3:
.string "."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L13
.L19:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
call _ZSt16__throw_bad_castv@PLT
.L17:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L20:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L11:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L13:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L19
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L20
cmpb $0, 56(%r15)
je .L11
movzbl 67(%r15), %esi
jmp .L12
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
using namespace std;
int main()
{
int count;
cudaGetDeviceCount(&count);
cudaDeviceProp prop;
for (int i = 0; i < count; ++i)
{
cudaGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} | #include "hip/hip_runtime.h"
#include <iostream>
using namespace std;
int main()
{
int count;
hipGetDeviceCount(&count);
hipDeviceProp_t prop;
for (int i = 0; i < count; ++i)
{
hipGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
using namespace std;
int main()
{
int count;
hipGetDeviceCount(&count);
hipDeviceProp_t prop;
for (int i = 0; i < count; ++i)
{
hipGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
using namespace std;
int main()
{
int count;
hipGetDeviceCount(&count);
hipDeviceProp_t prop;
for (int i = 0; i < count; ++i)
{
hipGetDeviceProperties(&prop, i);
cout << "Device " << i << ": " << prop.name << endl;
cout << "Compute Capability: " << prop.major << "." << prop.minor << endl;
}
return 0;
} | .text
.file "info_gpu2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_11
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit8
# in Loop: Header=BB0_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_11
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_12
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r12)
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_2 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i5
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r15)
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_10
.LBB0_11: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute Capability: "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "."
.size .L.str.3, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00107114_00000000-6_info_gpu2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device "
.LC1:
.string ": "
.LC2:
.string "Compute Capability: "
.LC3:
.string "."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L13
.L19:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L17
call _ZSt16__throw_bad_castv@PLT
.L17:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L20:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L11:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L13:
leaq 16(%rsp), %r15
movl %ebp, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r15, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r15, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L19
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L20
cmpb $0, 56(%r15)
je .L11
movzbl 67(%r15), %esi
jmp .L12
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "info_gpu2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_11
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit8
# in Loop: Header=BB0_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_11
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
callq strlen
movq %r15, %rdi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r15), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_12
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r12)
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_2 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i5
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r15)
je .LBB0_9
# %bb.8: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_10
.LBB0_11: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_12:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute Capability: "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "."
.size .L.str.3, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" __global__
void divElements(float * x, float * y, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] /= y[tid];
}
}
extern "C" __global__
void elemMax(float * dst, float * src, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
dst[tid] = max(dst[tid], src[tid]);
}
}
extern "C" __global__
void expElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = expf(x[tid]);
}
}
extern "C" __global__
void logElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = logf(x[tid]);
}
}
extern "C" __global__
void tanhElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = tanhf(x[tid]);
}
}
extern "C" __global__
void sinElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = sinf(x[tid]);
}
}
extern "C" __global__
void sigmoidElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = (1 + tanhf(x[tid] / 2)) / 2;
}
}
extern "C" __global__
void clipPositive(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = fmaxf(0, x[tid]);
}
}
extern "C" __global__
void shiftRandUniform(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] == 1.0f) {
x[tid] = 0;
}
}
}
extern "C" __global__
void uniformToBernoulli(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] > 0.5) {
x[tid] = 1;
} else {
x[tid] = 0;
}
}
}
extern "C" __global__
void addRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid % sourceLen];
}
}
extern "C" __global__
void addRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid & srcMask];
}
}
extern "C" __global__
void scaleRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid % sourceLen];
}
}
extern "C" __global__
void scaleRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid & srcMask];
}
}
extern "C" __global__
void addScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += s;
}
}
extern "C" __global__
void setScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = s;
}
}
extern "C" __global__
void addChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid / chunkSize];
}
}
extern "C" __global__
void subChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] -= source[tid / chunkSize];
}
}
extern "C" __global__
void lessThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] < s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void greaterThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] > s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void equalTo(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] == s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __device__
float addLogPair(float x, float y) {
float m = max(x, y);
return logf(expf(x-m) + expf(y-m)) + m;
}
extern "C" __global__
void addLogs(float * dst, float * src, int rowSize) {
extern __shared__ float chunk[];
int rowIdx = blockIdx.y * blockDim.x + threadIdx.x;
if (rowIdx < rowSize) {
chunk[threadIdx.x] = src[rowIdx+rowSize*blockIdx.x];
}
__syncthreads();
for (int stride = (blockDim.x>>1); stride >= 1; stride >>= 1) {
if (threadIdx.x < stride && rowIdx+stride < rowSize) {
chunk[threadIdx.x] = addLogPair(chunk[threadIdx.x],
chunk[threadIdx.x+stride]);
}
__syncthreads();
}
if (threadIdx.x == 0) {
dst[blockIdx.y + blockIdx.x*gridDim.y] = chunk[0];
}
}
extern "C" __global__
void powScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = powf(dest[tid], s);
}
}
extern "C" __global__
void mapForward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
dst[tid] = src[table[tid]];
}
}
extern "C" __global__
void mapBackward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
atomicAdd(&dst[table[tid]], src[tid]);
}
}
extern "C" __global__
void mapMax(int * table, float * data, int rows, int cols) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < rows) {
int base = tid * cols;
float * row = &data[base];
int maxIdx = 0;
float maxVal = row[0];
for (int i = 1; i < cols; ++i) {
if (row[i] > maxVal) {
maxVal = row[i];
maxIdx = i;
}
}
table[tid] = maxIdx + base;
}
} | #include <hip/hip_runtime.h>
extern "C" __global__
void divElements(float * x, float * y, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] /= y[tid];
}
}
extern "C" __global__
void elemMax(float * dst, float * src, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
dst[tid] = max(dst[tid], src[tid]);
}
}
extern "C" __global__
void expElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = expf(x[tid]);
}
}
extern "C" __global__
void logElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = logf(x[tid]);
}
}
extern "C" __global__
void tanhElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = tanhf(x[tid]);
}
}
extern "C" __global__
void sinElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = sinf(x[tid]);
}
}
extern "C" __global__
void sigmoidElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = (1 + tanhf(x[tid] / 2)) / 2;
}
}
extern "C" __global__
void clipPositive(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = fmaxf(0, x[tid]);
}
}
extern "C" __global__
void shiftRandUniform(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] == 1.0f) {
x[tid] = 0;
}
}
}
extern "C" __global__
void uniformToBernoulli(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] > 0.5) {
x[tid] = 1;
} else {
x[tid] = 0;
}
}
}
extern "C" __global__
void addRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid % sourceLen];
}
}
extern "C" __global__
void addRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid & srcMask];
}
}
extern "C" __global__
void scaleRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid % sourceLen];
}
}
extern "C" __global__
void scaleRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid & srcMask];
}
}
extern "C" __global__
void addScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += s;
}
}
extern "C" __global__
void setScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = s;
}
}
extern "C" __global__
void addChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid / chunkSize];
}
}
extern "C" __global__
void subChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] -= source[tid / chunkSize];
}
}
extern "C" __global__
void lessThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] < s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void greaterThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] > s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void equalTo(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] == s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __device__
float addLogPair(float x, float y) {
float m = max(x, y);
return logf(expf(x-m) + expf(y-m)) + m;
}
extern "C" __global__
void addLogs(float * dst, float * src, int rowSize) {
extern __shared__ float chunk[];
int rowIdx = blockIdx.y * blockDim.x + threadIdx.x;
if (rowIdx < rowSize) {
chunk[threadIdx.x] = src[rowIdx+rowSize*blockIdx.x];
}
__syncthreads();
for (int stride = (blockDim.x>>1); stride >= 1; stride >>= 1) {
if (threadIdx.x < stride && rowIdx+stride < rowSize) {
chunk[threadIdx.x] = addLogPair(chunk[threadIdx.x],
chunk[threadIdx.x+stride]);
}
__syncthreads();
}
if (threadIdx.x == 0) {
dst[blockIdx.y + blockIdx.x*gridDim.y] = chunk[0];
}
}
extern "C" __global__
void powScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = powf(dest[tid], s);
}
}
extern "C" __global__
void mapForward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
dst[tid] = src[table[tid]];
}
}
extern "C" __global__
void mapBackward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
atomicAdd(&dst[table[tid]], src[tid]);
}
}
extern "C" __global__
void mapMax(int * table, float * data, int rows, int cols) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < rows) {
int base = tid * cols;
float * row = &data[base];
int maxIdx = 0;
float maxVal = row[0];
for (int i = 1; i < cols; ++i) {
if (row[i] > maxVal) {
maxVal = row[i];
maxIdx = i;
}
}
table[tid] = maxIdx + base;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" __global__
void divElements(float * x, float * y, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] /= y[tid];
}
}
extern "C" __global__
void elemMax(float * dst, float * src, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
dst[tid] = max(dst[tid], src[tid]);
}
}
extern "C" __global__
void expElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = expf(x[tid]);
}
}
extern "C" __global__
void logElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = logf(x[tid]);
}
}
extern "C" __global__
void tanhElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = tanhf(x[tid]);
}
}
extern "C" __global__
void sinElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = sinf(x[tid]);
}
}
extern "C" __global__
void sigmoidElements(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = (1 + tanhf(x[tid] / 2)) / 2;
}
}
extern "C" __global__
void clipPositive(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
x[tid] = fmaxf(0, x[tid]);
}
}
extern "C" __global__
void shiftRandUniform(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] == 1.0f) {
x[tid] = 0;
}
}
}
extern "C" __global__
void uniformToBernoulli(float * x, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (x[tid] > 0.5) {
x[tid] = 1;
} else {
x[tid] = 0;
}
}
}
extern "C" __global__
void addRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid % sourceLen];
}
}
extern "C" __global__
void addRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid & srcMask];
}
}
extern "C" __global__
void scaleRepeated(float * dest, float * source, int destLen, int sourceLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid % sourceLen];
}
}
extern "C" __global__
void scaleRepeatedPow2(float * dest, float * source, int destLen, int srcMask) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] *= source[tid & srcMask];
}
}
extern "C" __global__
void addScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += s;
}
}
extern "C" __global__
void setScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = s;
}
}
extern "C" __global__
void addChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] += source[tid / chunkSize];
}
}
extern "C" __global__
void subChunks(float * dest, float * source, int destLen, int chunkSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] -= source[tid / chunkSize];
}
}
extern "C" __global__
void lessThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] < s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void greaterThan(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] > s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __global__
void equalTo(float s, float * v, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < n) {
if (v[tid] == s) {
v[tid] = 1;
} else {
v[tid] = 0;
}
}
}
extern "C" __device__
float addLogPair(float x, float y) {
float m = max(x, y);
return logf(expf(x-m) + expf(y-m)) + m;
}
extern "C" __global__
void addLogs(float * dst, float * src, int rowSize) {
extern __shared__ float chunk[];
int rowIdx = blockIdx.y * blockDim.x + threadIdx.x;
if (rowIdx < rowSize) {
chunk[threadIdx.x] = src[rowIdx+rowSize*blockIdx.x];
}
__syncthreads();
for (int stride = (blockDim.x>>1); stride >= 1; stride >>= 1) {
if (threadIdx.x < stride && rowIdx+stride < rowSize) {
chunk[threadIdx.x] = addLogPair(chunk[threadIdx.x],
chunk[threadIdx.x+stride]);
}
__syncthreads();
}
if (threadIdx.x == 0) {
dst[blockIdx.y + blockIdx.x*gridDim.y] = chunk[0];
}
}
extern "C" __global__
void powScaler(float s, float * dest, int destLen) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < destLen) {
dest[tid] = powf(dest[tid], s);
}
}
extern "C" __global__
void mapForward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
dst[tid] = src[table[tid]];
}
}
extern "C" __global__
void mapBackward(float * dst, float * src, int * table, int tableSize) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < tableSize) {
atomicAdd(&dst[table[tid]], src[tid]);
}
}
extern "C" __global__
void mapMax(int * table, float * data, int rows, int cols) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < rows) {
int base = tid * cols;
float * row = &data[base];
int maxIdx = 0;
float maxVal = row[0];
for (int i = 1; i < cols; ++i) {
if (row[i] > maxVal) {
maxVal = row[i];
maxIdx = i;
}
}
table[tid] = maxIdx + base;
}
} | .text
.file "kernels32.hip"
.globl __device_stub__divElements # -- Begin function __device_stub__divElements
.p2align 4, 0x90
.type __device_stub__divElements,@function
__device_stub__divElements: # @__device_stub__divElements
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $divElements, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size __device_stub__divElements, .Lfunc_end0-__device_stub__divElements
.cfi_endproc
# -- End function
.globl __device_stub__elemMax # -- Begin function __device_stub__elemMax
.p2align 4, 0x90
.type __device_stub__elemMax,@function
__device_stub__elemMax: # @__device_stub__elemMax
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $elemMax, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size __device_stub__elemMax, .Lfunc_end1-__device_stub__elemMax
.cfi_endproc
# -- End function
.globl __device_stub__expElements # -- Begin function __device_stub__expElements
.p2align 4, 0x90
.type __device_stub__expElements,@function
__device_stub__expElements: # @__device_stub__expElements
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $expElements, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__expElements, .Lfunc_end2-__device_stub__expElements
.cfi_endproc
# -- End function
.globl __device_stub__logElements # -- Begin function __device_stub__logElements
.p2align 4, 0x90
.type __device_stub__logElements,@function
__device_stub__logElements: # @__device_stub__logElements
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $logElements, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size __device_stub__logElements, .Lfunc_end3-__device_stub__logElements
.cfi_endproc
# -- End function
.globl __device_stub__tanhElements # -- Begin function __device_stub__tanhElements
.p2align 4, 0x90
.type __device_stub__tanhElements,@function
__device_stub__tanhElements: # @__device_stub__tanhElements
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $tanhElements, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size __device_stub__tanhElements, .Lfunc_end4-__device_stub__tanhElements
.cfi_endproc
# -- End function
.globl __device_stub__sinElements # -- Begin function __device_stub__sinElements
.p2align 4, 0x90
.type __device_stub__sinElements,@function
__device_stub__sinElements: # @__device_stub__sinElements
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $sinElements, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size __device_stub__sinElements, .Lfunc_end5-__device_stub__sinElements
.cfi_endproc
# -- End function
.globl __device_stub__sigmoidElements # -- Begin function __device_stub__sigmoidElements
.p2align 4, 0x90
.type __device_stub__sigmoidElements,@function
__device_stub__sigmoidElements: # @__device_stub__sigmoidElements
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $sigmoidElements, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end6:
.size __device_stub__sigmoidElements, .Lfunc_end6-__device_stub__sigmoidElements
.cfi_endproc
# -- End function
.globl __device_stub__clipPositive # -- Begin function __device_stub__clipPositive
.p2align 4, 0x90
.type __device_stub__clipPositive,@function
__device_stub__clipPositive: # @__device_stub__clipPositive
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $clipPositive, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end7:
.size __device_stub__clipPositive, .Lfunc_end7-__device_stub__clipPositive
.cfi_endproc
# -- End function
.globl __device_stub__shiftRandUniform # -- Begin function __device_stub__shiftRandUniform
.p2align 4, 0x90
.type __device_stub__shiftRandUniform,@function
__device_stub__shiftRandUniform: # @__device_stub__shiftRandUniform
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $shiftRandUniform, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end8:
.size __device_stub__shiftRandUniform, .Lfunc_end8-__device_stub__shiftRandUniform
.cfi_endproc
# -- End function
.globl __device_stub__uniformToBernoulli # -- Begin function __device_stub__uniformToBernoulli
.p2align 4, 0x90
.type __device_stub__uniformToBernoulli,@function
__device_stub__uniformToBernoulli: # @__device_stub__uniformToBernoulli
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $uniformToBernoulli, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end9:
.size __device_stub__uniformToBernoulli, .Lfunc_end9-__device_stub__uniformToBernoulli
.cfi_endproc
# -- End function
.globl __device_stub__addRepeated # -- Begin function __device_stub__addRepeated
.p2align 4, 0x90
.type __device_stub__addRepeated,@function
__device_stub__addRepeated: # @__device_stub__addRepeated
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $addRepeated, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end10:
.size __device_stub__addRepeated, .Lfunc_end10-__device_stub__addRepeated
.cfi_endproc
# -- End function
.globl __device_stub__addRepeatedPow2 # -- Begin function __device_stub__addRepeatedPow2
.p2align 4, 0x90
.type __device_stub__addRepeatedPow2,@function
__device_stub__addRepeatedPow2: # @__device_stub__addRepeatedPow2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $addRepeatedPow2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size __device_stub__addRepeatedPow2, .Lfunc_end11-__device_stub__addRepeatedPow2
.cfi_endproc
# -- End function
.globl __device_stub__scaleRepeated # -- Begin function __device_stub__scaleRepeated
.p2align 4, 0x90
.type __device_stub__scaleRepeated,@function
__device_stub__scaleRepeated: # @__device_stub__scaleRepeated
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $scaleRepeated, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end12:
.size __device_stub__scaleRepeated, .Lfunc_end12-__device_stub__scaleRepeated
.cfi_endproc
# -- End function
.globl __device_stub__scaleRepeatedPow2 # -- Begin function __device_stub__scaleRepeatedPow2
.p2align 4, 0x90
.type __device_stub__scaleRepeatedPow2,@function
__device_stub__scaleRepeatedPow2: # @__device_stub__scaleRepeatedPow2
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $scaleRepeatedPow2, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end13:
.size __device_stub__scaleRepeatedPow2, .Lfunc_end13-__device_stub__scaleRepeatedPow2
.cfi_endproc
# -- End function
.globl __device_stub__addScaler # -- Begin function __device_stub__addScaler
.p2align 4, 0x90
.type __device_stub__addScaler,@function
__device_stub__addScaler: # @__device_stub__addScaler
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $addScaler, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end14:
.size __device_stub__addScaler, .Lfunc_end14-__device_stub__addScaler
.cfi_endproc
# -- End function
.globl __device_stub__setScaler # -- Begin function __device_stub__setScaler
.p2align 4, 0x90
.type __device_stub__setScaler,@function
__device_stub__setScaler: # @__device_stub__setScaler
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $setScaler, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end15:
.size __device_stub__setScaler, .Lfunc_end15-__device_stub__setScaler
.cfi_endproc
# -- End function
.globl __device_stub__addChunks # -- Begin function __device_stub__addChunks
.p2align 4, 0x90
.type __device_stub__addChunks,@function
__device_stub__addChunks: # @__device_stub__addChunks
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $addChunks, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end16:
.size __device_stub__addChunks, .Lfunc_end16-__device_stub__addChunks
.cfi_endproc
# -- End function
.globl __device_stub__subChunks # -- Begin function __device_stub__subChunks
.p2align 4, 0x90
.type __device_stub__subChunks,@function
__device_stub__subChunks: # @__device_stub__subChunks
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $subChunks, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end17:
.size __device_stub__subChunks, .Lfunc_end17-__device_stub__subChunks
.cfi_endproc
# -- End function
.globl __device_stub__lessThan # -- Begin function __device_stub__lessThan
.p2align 4, 0x90
.type __device_stub__lessThan,@function
__device_stub__lessThan: # @__device_stub__lessThan
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $lessThan, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end18:
.size __device_stub__lessThan, .Lfunc_end18-__device_stub__lessThan
.cfi_endproc
# -- End function
.globl __device_stub__greaterThan # -- Begin function __device_stub__greaterThan
.p2align 4, 0x90
.type __device_stub__greaterThan,@function
__device_stub__greaterThan: # @__device_stub__greaterThan
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $greaterThan, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end19:
.size __device_stub__greaterThan, .Lfunc_end19-__device_stub__greaterThan
.cfi_endproc
# -- End function
.globl __device_stub__equalTo # -- Begin function __device_stub__equalTo
.p2align 4, 0x90
.type __device_stub__equalTo,@function
__device_stub__equalTo: # @__device_stub__equalTo
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $equalTo, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end20:
.size __device_stub__equalTo, .Lfunc_end20-__device_stub__equalTo
.cfi_endproc
# -- End function
.globl __device_stub__addLogs # -- Begin function __device_stub__addLogs
.p2align 4, 0x90
.type __device_stub__addLogs,@function
__device_stub__addLogs: # @__device_stub__addLogs
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $addLogs, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end21:
.size __device_stub__addLogs, .Lfunc_end21-__device_stub__addLogs
.cfi_endproc
# -- End function
.globl __device_stub__powScaler # -- Begin function __device_stub__powScaler
.p2align 4, 0x90
.type __device_stub__powScaler,@function
__device_stub__powScaler: # @__device_stub__powScaler
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movss %xmm0, 4(%rsp)
movq %rdi, 56(%rsp)
movl %esi, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $powScaler, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end22:
.size __device_stub__powScaler, .Lfunc_end22-__device_stub__powScaler
.cfi_endproc
# -- End function
.globl __device_stub__mapForward # -- Begin function __device_stub__mapForward
.p2align 4, 0x90
.type __device_stub__mapForward,@function
__device_stub__mapForward: # @__device_stub__mapForward
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mapForward, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end23:
.size __device_stub__mapForward, .Lfunc_end23-__device_stub__mapForward
.cfi_endproc
# -- End function
.globl __device_stub__mapBackward # -- Begin function __device_stub__mapBackward
.p2align 4, 0x90
.type __device_stub__mapBackward,@function
__device_stub__mapBackward: # @__device_stub__mapBackward
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mapBackward, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end24:
.size __device_stub__mapBackward, .Lfunc_end24-__device_stub__mapBackward
.cfi_endproc
# -- End function
.globl __device_stub__mapMax # -- Begin function __device_stub__mapMax
.p2align 4, 0x90
.type __device_stub__mapMax,@function
__device_stub__mapMax: # @__device_stub__mapMax
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mapMax, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end25:
.size __device_stub__mapMax, .Lfunc_end25-__device_stub__mapMax
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB26_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB26_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $divElements, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $elemMax, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $expElements, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $logElements, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $tanhElements, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sinElements, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sigmoidElements, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $clipPositive, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $shiftRandUniform, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $uniformToBernoulli, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addRepeated, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addRepeatedPow2, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $scaleRepeated, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $scaleRepeatedPow2, %esi
movl $.L__unnamed_14, %edx
movl $.L__unnamed_14, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addScaler, %esi
movl $.L__unnamed_15, %edx
movl $.L__unnamed_15, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $setScaler, %esi
movl $.L__unnamed_16, %edx
movl $.L__unnamed_16, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addChunks, %esi
movl $.L__unnamed_17, %edx
movl $.L__unnamed_17, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $subChunks, %esi
movl $.L__unnamed_18, %edx
movl $.L__unnamed_18, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $lessThan, %esi
movl $.L__unnamed_19, %edx
movl $.L__unnamed_19, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $greaterThan, %esi
movl $.L__unnamed_20, %edx
movl $.L__unnamed_20, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $equalTo, %esi
movl $.L__unnamed_21, %edx
movl $.L__unnamed_21, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $addLogs, %esi
movl $.L__unnamed_22, %edx
movl $.L__unnamed_22, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $powScaler, %esi
movl $.L__unnamed_23, %edx
movl $.L__unnamed_23, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mapForward, %esi
movl $.L__unnamed_24, %edx
movl $.L__unnamed_24, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mapBackward, %esi
movl $.L__unnamed_25, %edx
movl $.L__unnamed_25, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mapMax, %esi
movl $.L__unnamed_26, %edx
movl $.L__unnamed_26, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end26:
.size __hip_module_ctor, .Lfunc_end26-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB27_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB27_2:
retq
.Lfunc_end27:
.size __hip_module_dtor, .Lfunc_end27-__hip_module_dtor
.cfi_endproc
# -- End function
.type divElements,@object # @divElements
.section .rodata,"a",@progbits
.globl divElements
.p2align 3, 0x0
divElements:
.quad __device_stub__divElements
.size divElements, 8
.type elemMax,@object # @elemMax
.globl elemMax
.p2align 3, 0x0
elemMax:
.quad __device_stub__elemMax
.size elemMax, 8
.type expElements,@object # @expElements
.globl expElements
.p2align 3, 0x0
expElements:
.quad __device_stub__expElements
.size expElements, 8
.type logElements,@object # @logElements
.globl logElements
.p2align 3, 0x0
logElements:
.quad __device_stub__logElements
.size logElements, 8
.type tanhElements,@object # @tanhElements
.globl tanhElements
.p2align 3, 0x0
tanhElements:
.quad __device_stub__tanhElements
.size tanhElements, 8
.type sinElements,@object # @sinElements
.globl sinElements
.p2align 3, 0x0
sinElements:
.quad __device_stub__sinElements
.size sinElements, 8
.type sigmoidElements,@object # @sigmoidElements
.globl sigmoidElements
.p2align 3, 0x0
sigmoidElements:
.quad __device_stub__sigmoidElements
.size sigmoidElements, 8
.type clipPositive,@object # @clipPositive
.globl clipPositive
.p2align 3, 0x0
clipPositive:
.quad __device_stub__clipPositive
.size clipPositive, 8
.type shiftRandUniform,@object # @shiftRandUniform
.globl shiftRandUniform
.p2align 3, 0x0
shiftRandUniform:
.quad __device_stub__shiftRandUniform
.size shiftRandUniform, 8
.type uniformToBernoulli,@object # @uniformToBernoulli
.globl uniformToBernoulli
.p2align 3, 0x0
uniformToBernoulli:
.quad __device_stub__uniformToBernoulli
.size uniformToBernoulli, 8
.type addRepeated,@object # @addRepeated
.globl addRepeated
.p2align 3, 0x0
addRepeated:
.quad __device_stub__addRepeated
.size addRepeated, 8
.type addRepeatedPow2,@object # @addRepeatedPow2
.globl addRepeatedPow2
.p2align 3, 0x0
addRepeatedPow2:
.quad __device_stub__addRepeatedPow2
.size addRepeatedPow2, 8
.type scaleRepeated,@object # @scaleRepeated
.globl scaleRepeated
.p2align 3, 0x0
scaleRepeated:
.quad __device_stub__scaleRepeated
.size scaleRepeated, 8
.type scaleRepeatedPow2,@object # @scaleRepeatedPow2
.globl scaleRepeatedPow2
.p2align 3, 0x0
scaleRepeatedPow2:
.quad __device_stub__scaleRepeatedPow2
.size scaleRepeatedPow2, 8
.type addScaler,@object # @addScaler
.globl addScaler
.p2align 3, 0x0
addScaler:
.quad __device_stub__addScaler
.size addScaler, 8
.type setScaler,@object # @setScaler
.globl setScaler
.p2align 3, 0x0
setScaler:
.quad __device_stub__setScaler
.size setScaler, 8
.type addChunks,@object # @addChunks
.globl addChunks
.p2align 3, 0x0
addChunks:
.quad __device_stub__addChunks
.size addChunks, 8
.type subChunks,@object # @subChunks
.globl subChunks
.p2align 3, 0x0
subChunks:
.quad __device_stub__subChunks
.size subChunks, 8
.type lessThan,@object # @lessThan
.globl lessThan
.p2align 3, 0x0
lessThan:
.quad __device_stub__lessThan
.size lessThan, 8
.type greaterThan,@object # @greaterThan
.globl greaterThan
.p2align 3, 0x0
greaterThan:
.quad __device_stub__greaterThan
.size greaterThan, 8
.type equalTo,@object # @equalTo
.globl equalTo
.p2align 3, 0x0
equalTo:
.quad __device_stub__equalTo
.size equalTo, 8
.type addLogs,@object # @addLogs
.globl addLogs
.p2align 3, 0x0
addLogs:
.quad __device_stub__addLogs
.size addLogs, 8
.type powScaler,@object # @powScaler
.globl powScaler
.p2align 3, 0x0
powScaler:
.quad __device_stub__powScaler
.size powScaler, 8
.type mapForward,@object # @mapForward
.globl mapForward
.p2align 3, 0x0
mapForward:
.quad __device_stub__mapForward
.size mapForward, 8
.type mapBackward,@object # @mapBackward
.globl mapBackward
.p2align 3, 0x0
mapBackward:
.quad __device_stub__mapBackward
.size mapBackward, 8
.type mapMax,@object # @mapMax
.globl mapMax
.p2align 3, 0x0
mapMax:
.quad __device_stub__mapMax
.size mapMax, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "divElements"
.size .L__unnamed_1, 12
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "elemMax"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "expElements"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "logElements"
.size .L__unnamed_4, 12
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "tanhElements"
.size .L__unnamed_5, 13
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "sinElements"
.size .L__unnamed_6, 12
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "sigmoidElements"
.size .L__unnamed_7, 16
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "clipPositive"
.size .L__unnamed_8, 13
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "shiftRandUniform"
.size .L__unnamed_9, 17
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "uniformToBernoulli"
.size .L__unnamed_10, 19
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "addRepeated"
.size .L__unnamed_11, 12
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "addRepeatedPow2"
.size .L__unnamed_12, 16
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "scaleRepeated"
.size .L__unnamed_13, 14
.type .L__unnamed_14,@object # @13
.L__unnamed_14:
.asciz "scaleRepeatedPow2"
.size .L__unnamed_14, 18
.type .L__unnamed_15,@object # @14
.L__unnamed_15:
.asciz "addScaler"
.size .L__unnamed_15, 10
.type .L__unnamed_16,@object # @15
.L__unnamed_16:
.asciz "setScaler"
.size .L__unnamed_16, 10
.type .L__unnamed_17,@object # @16
.L__unnamed_17:
.asciz "addChunks"
.size .L__unnamed_17, 10
.type .L__unnamed_18,@object # @17
.L__unnamed_18:
.asciz "subChunks"
.size .L__unnamed_18, 10
.type .L__unnamed_19,@object # @18
.L__unnamed_19:
.asciz "lessThan"
.size .L__unnamed_19, 9
.type .L__unnamed_20,@object # @19
.L__unnamed_20:
.asciz "greaterThan"
.size .L__unnamed_20, 12
.type .L__unnamed_21,@object # @20
.L__unnamed_21:
.asciz "equalTo"
.size .L__unnamed_21, 8
.type .L__unnamed_22,@object # @21
.L__unnamed_22:
.asciz "addLogs"
.size .L__unnamed_22, 8
.type .L__unnamed_23,@object # @22
.L__unnamed_23:
.asciz "powScaler"
.size .L__unnamed_23, 10
.type .L__unnamed_24,@object # @23
.L__unnamed_24:
.asciz "mapForward"
.size .L__unnamed_24, 11
.type .L__unnamed_25,@object # @24
.L__unnamed_25:
.asciz "mapBackward"
.size .L__unnamed_25, 12
.type .L__unnamed_26,@object # @25
.L__unnamed_26:
.asciz "mapMax"
.size .L__unnamed_26, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__divElements
.addrsig_sym __device_stub__elemMax
.addrsig_sym __device_stub__expElements
.addrsig_sym __device_stub__logElements
.addrsig_sym __device_stub__tanhElements
.addrsig_sym __device_stub__sinElements
.addrsig_sym __device_stub__sigmoidElements
.addrsig_sym __device_stub__clipPositive
.addrsig_sym __device_stub__shiftRandUniform
.addrsig_sym __device_stub__uniformToBernoulli
.addrsig_sym __device_stub__addRepeated
.addrsig_sym __device_stub__addRepeatedPow2
.addrsig_sym __device_stub__scaleRepeated
.addrsig_sym __device_stub__scaleRepeatedPow2
.addrsig_sym __device_stub__addScaler
.addrsig_sym __device_stub__setScaler
.addrsig_sym __device_stub__addChunks
.addrsig_sym __device_stub__subChunks
.addrsig_sym __device_stub__lessThan
.addrsig_sym __device_stub__greaterThan
.addrsig_sym __device_stub__equalTo
.addrsig_sym __device_stub__addLogs
.addrsig_sym __device_stub__powScaler
.addrsig_sym __device_stub__mapForward
.addrsig_sym __device_stub__mapBackward
.addrsig_sym __device_stub__mapMax
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym divElements
.addrsig_sym elemMax
.addrsig_sym expElements
.addrsig_sym logElements
.addrsig_sym tanhElements
.addrsig_sym sinElements
.addrsig_sym sigmoidElements
.addrsig_sym clipPositive
.addrsig_sym shiftRandUniform
.addrsig_sym uniformToBernoulli
.addrsig_sym addRepeated
.addrsig_sym addRepeatedPow2
.addrsig_sym scaleRepeated
.addrsig_sym scaleRepeatedPow2
.addrsig_sym addScaler
.addrsig_sym setScaler
.addrsig_sym addChunks
.addrsig_sym subChunks
.addrsig_sym lessThan
.addrsig_sym greaterThan
.addrsig_sym equalTo
.addrsig_sym addLogs
.addrsig_sym powScaler
.addrsig_sym mapForward
.addrsig_sym mapBackward
.addrsig_sym mapMax
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
cudaError_t cudaStatus;
cudaSetDevice(0);
cudaMalloc((void**)&dev_input, 100 * sizeof(int));
cudaMalloc((void**)&dev_output, 100 * sizeof(int));
cudaMemcpy(dev_input, input, 100 * sizeof(int), cudaMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
cudaDeviceSynchronize();
cudaMemcpy(output, dev_output, 100 * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_input);
cudaFree(dev_output);
} | code for sm_80
Function : _Z9addKernelPiPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.HI R0, R2, 0x55555556, RZ ; /* 0x5555555602007827 */
/* 0x004fca00078e02ff */
/*00a0*/ LEA.HI R0, R0, R0, RZ, 0x1 ; /* 0x0000000000007211 */
/* 0x000fc800078f08ff */
/*00b0*/ IADD3 R7, R0, -0x2, RZ ; /* 0xfffffffe00077810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
cudaError_t cudaStatus;
cudaSetDevice(0);
cudaMalloc((void**)&dev_input, 100 * sizeof(int));
cudaMalloc((void**)&dev_output, 100 * sizeof(int));
cudaMemcpy(dev_input, input, 100 * sizeof(int), cudaMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
cudaDeviceSynchronize();
cudaMemcpy(output, dev_output, 100 * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_input);
cudaFree(dev_output);
} | .file "tmpxft_0013f199_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4045:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20doComputationOutput2i
.type _Z20doComputationOutput2i, @function
_Z20doComputationOutput2i:
.LFB4040:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
cmpl $8, %edi
jg .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movslq %edi, %rdi
imulq $1431655766, %rdi, %rdi
shrq $32, %rdi
movl %ebx, %eax
sarl $31, %eax
subl %eax, %edi
subl $2, %edi
call _Z20doComputationOutput2i
addl %eax, %ebx
jmp .L4
.cfi_endproc
.LFE4040:
.size _Z20doComputationOutput2i, .-_Z20doComputationOutput2i
.globl _Z31__device_stub__Z9addKernelPiPKiPiPKi
.type _Z31__device_stub__Z9addKernelPiPKiPiPKi, @function
_Z31__device_stub__Z9addKernelPiPKiPiPKi:
.LFB4067:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z31__device_stub__Z9addKernelPiPKiPiPKi, .-_Z31__device_stub__Z9addKernelPiPKiPiPKi
.globl _Z9addKernelPiPKi
.type _Z9addKernelPiPKi, @function
_Z9addKernelPiPKi:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z9addKernelPiPKi, .-_Z9addKernelPiPKi
.globl _Z17doCudaComputationPiS_
.type _Z17doCudaComputationPiS_, @function
_Z17doCudaComputationPiS_:
.LFB4042:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4042:
.size _Z17doCudaComputationPiS_, .-_Z17doCudaComputationPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "input.txt"
.text
.globl _Z8readFilePi
.type _Z8readFilePi, @function
_Z8readFilePi:
.LFB4041:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4041
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $552, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 16(%rsp), %rbp
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
movq $0, 488(%rsp)
movb $0, 496(%rsp)
movb $0, 497(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, 16(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r13
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 32(%rsp), %rsi
leaq 272(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L46
.L41:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L26:
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
.L27:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L40:
endbr64
movq %rax, %rbx
jmp .L26
.L39:
endbr64
movq %rax, %rbx
jmp .L27
.L28:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L46:
leaq 32(%rsp), %rdi
movl $8, %edx
leaq .LC1(%rip), %rsi
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L47
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L31
.L47:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L31:
leaq 12(%rsp), %rbp
jmp .L30
.L49:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L48
movl 12(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
.L30:
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call _ZNSirsERi@PLT
.LEHE4:
jmp .L49
.L48:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L34
.L42:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L34:
leaq 136(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4041:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4041:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4041-.LLSDATTD4041
.LLSDATTD4041:
.byte 0x1
.uleb128 .LLSDACSE4041-.LLSDACSB4041
.LLSDACSB4041:
.uleb128 .LEHB0-.LFB4041
.uleb128 .LEHE0-.LEHB0
.uleb128 .L39-.LFB4041
.uleb128 0
.uleb128 .LEHB1-.LFB4041
.uleb128 .LEHE1-.LEHB1
.uleb128 .L40-.LFB4041
.uleb128 0
.uleb128 .LEHB2-.LFB4041
.uleb128 .LEHE2-.LEHB2
.uleb128 .L41-.LFB4041
.uleb128 0
.uleb128 .LEHB3-.LFB4041
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4041
.uleb128 .LEHE4-.LEHB4
.uleb128 .L38-.LFB4041
.uleb128 0
.uleb128 .LEHB5-.LFB4041
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB4041
.uleb128 0x1
.uleb128 .LEHB6-.LFB4041
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4041:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4041:
.text
.size _Z8readFilePi, .-_Z8readFilePi
.section .rodata.str1.1
.LC2:
.string "Sum: %d\n"
.LC3:
.string "Sum2: %d\n"
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $400, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z8readFilePi
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17doCudaComputationPiS_
movq %rbx, %rbp
leaq 400(%rbx), %r13
movq %rbx, %rax
movl $0, %edx
.L52:
addl (%rax), %edx
movl %edx, %r12d
addq $4, %rax
cmpq %r13, %rax
jne .L52
movl $0, %ebx
.L53:
movl 0(%rbp), %edi
call _Z20doComputationOutput2i
addl %eax, %ebx
addq $4, %rbp
cmpq %r13, %rbp
jne .L53
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
cudaError_t cudaStatus;
cudaSetDevice(0);
cudaMalloc((void**)&dev_input, 100 * sizeof(int));
cudaMalloc((void**)&dev_output, 100 * sizeof(int));
cudaMemcpy(dev_input, input, 100 * sizeof(int), cudaMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
cudaDeviceSynchronize();
cudaMemcpy(output, dev_output, 100 * sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_input);
cudaFree(dev_output);
} | #include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
hipError_t cudaStatus;
hipSetDevice(0);
hipMalloc((void**)&dev_input, 100 * sizeof(int));
hipMalloc((void**)&dev_output, 100 * sizeof(int));
hipMemcpy(dev_input, input, 100 * sizeof(int), hipMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
hipDeviceSynchronize();
hipMemcpy(output, dev_output, 100 * sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_input);
hipFree(dev_output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
hipError_t cudaStatus;
hipSetDevice(0);
hipMalloc((void**)&dev_input, 100 * sizeof(int));
hipMalloc((void**)&dev_output, 100 * sizeof(int));
hipMemcpy(dev_input, input, 100 * sizeof(int), hipMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
hipDeviceSynchronize();
hipMemcpy(output, dev_output, 100 * sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_input);
hipFree(dev_output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKi
.globl _Z9addKernelPiPKi
.p2align 8
.type _Z9addKernelPiPKi,@function
_Z9addKernelPiPKi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v2, v2, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v2
v_add3_u32 v2, v2, v3, -2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKi, .Lfunc_end0-_Z9addKernelPiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
#include <iomanip>
#include <fstream>
#include <stdio.h>
hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
void doCudaComputation(int* input, int* output);
int doComputationOutput2(int input);
void readFile(int* input);
__global__ void addKernel(int *output, const int *input)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int x = input[i] / 3;
output[i] = x - 2;
}
int main()
{
int* input = new int[100];
int* output = new int[100];
readFile(input);
doCudaComputation(input, output);
int sum = 0;
for (int i = 0; i < 100; ++i) {
sum += output[i];
}
int sum2 = 0;
for (int i = 0; i < 100; ++i) {
sum2 += doComputationOutput2(output[i]);
}
printf("Sum: %d\n", sum);
printf("Sum2: %d\n", sum2);
return 0;
}
int doComputationOutput2(int input) {
int x = input / 3;
if (x != 0 && x - 2 > 0) {
return input + doComputationOutput2(x - 2);
}
else {
return input;
}
}
void readFile(int* input) {
int mass = 0;
int compt = 0;
std::ifstream inFile;
inFile.open("input.txt");
while (inFile >> mass) {
input[compt] = mass;
compt++;
}
}
void doCudaComputation(int *input, int *output) {
int *dev_input = nullptr;
int *dev_output = nullptr;
hipError_t cudaStatus;
hipSetDevice(0);
hipMalloc((void**)&dev_input, 100 * sizeof(int));
hipMalloc((void**)&dev_output, 100 * sizeof(int));
hipMemcpy(dev_input, input, 100 * sizeof(int), hipMemcpyHostToDevice);
addKernel<<<1, 100>>>(dev_output, dev_input);
hipDeviceSynchronize();
hipMemcpy(output, dev_output, 100 * sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_input);
hipFree(dev_output);
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKi # -- Begin function _Z24__device_stub__addKernelPiPKi
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKi,@function
_Z24__device_stub__addKernelPiPKi: # @_Z24__device_stub__addKernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKi, .Lfunc_end0-_Z24__device_stub__addKernelPiPKi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
movq %r14, %rdi
callq _Z8readFilePi
movq %r14, %rdi
movq %rbx, %rsi
callq _Z17doCudaComputationPiS_
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edi
callq _Z20doComputationOutput2i
addl %eax, %r14d
incq %r15
cmpq $100, %r15
jne .LBB1_3
# %bb.4:
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z8readFilePi # -- Begin function _Z8readFilePi
.p2align 4, 0x90
.type _Z8readFilePi,@function
_Z8readFilePi: # @_Z8readFilePi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $0, 4(%rsp)
leaq 8(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 24(%rsp), %rdi
.Ltmp0:
movl $.L.str.2, %esi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 8(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%r14), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp2:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit.preheader
leaq 8(%rsp), %r14
leaq 4(%rsp), %r15
.p2align 4, 0x90
.LBB2_5: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
# =>This Inner Loop Header: Depth=1
.Ltmp5:
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_11
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl 4(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
jmp .LBB2_5
.LBB2_11:
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9: # %.loopexit.split-lp
.cfi_def_cfa_offset 560
.Ltmp4:
jmp .LBB2_10
.LBB2_8: # %.loopexit
.Ltmp7:
.LBB2_10:
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z8readFilePi, .Lfunc_end2-_Z8readFilePi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z17doCudaComputationPiS_ # -- Begin function _Z17doCudaComputationPiS_
.p2align 4, 0x90
.type _Z17doCudaComputationPiS_,@function
_Z17doCudaComputationPiS_: # @_Z17doCudaComputationPiS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17doCudaComputationPiS_, .Lfunc_end3-_Z17doCudaComputationPiS_
.cfi_endproc
# -- End function
.globl _Z20doComputationOutput2i # -- Begin function _Z20doComputationOutput2i
.p2align 4, 0x90
.type _Z20doComputationOutput2i,@function
_Z20doComputationOutput2i: # @_Z20doComputationOutput2i
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
cmpl $9, %edi
jl .LBB4_3
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
addl %edi, %eax
movl %edi, %edx
imulq %rcx, %rdx
shrq $33, %rdx
addl $-2, %edx
movl %edx, %edi
cmpl $9, %edi
jge .LBB4_2
.LBB4_3:
addl %edi, %eax
retq
.Lfunc_end4:
.size _Z20doComputationOutput2i, .Lfunc_end4-_Z20doComputationOutput2i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKi,@object # @_Z9addKernelPiPKi
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKi
.p2align 3, 0x0
_Z9addKernelPiPKi:
.quad _Z24__device_stub__addKernelPiPKi
.size _Z9addKernelPiPKi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum: %d\n"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sum2: %d\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "input.txt"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9addKernelPiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.HI R0, R2, 0x55555556, RZ ; /* 0x5555555602007827 */
/* 0x004fca00078e02ff */
/*00a0*/ LEA.HI R0, R0, R0, RZ, 0x1 ; /* 0x0000000000007211 */
/* 0x000fc800078f08ff */
/*00b0*/ IADD3 R7, R0, -0x2, RZ ; /* 0xfffffffe00077810 */
/* 0x000fca0007ffe0ff */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKi
.globl _Z9addKernelPiPKi
.p2align 8
.type _Z9addKernelPiPKi,@function
_Z9addKernelPiPKi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_hi_i32 v2, v2, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v2
v_add3_u32 v2, v2, v3, -2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKi, .Lfunc_end0-_Z9addKernelPiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f199_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4045:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20doComputationOutput2i
.type _Z20doComputationOutput2i, @function
_Z20doComputationOutput2i:
.LFB4040:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
cmpl $8, %edi
jg .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movslq %edi, %rdi
imulq $1431655766, %rdi, %rdi
shrq $32, %rdi
movl %ebx, %eax
sarl $31, %eax
subl %eax, %edi
subl $2, %edi
call _Z20doComputationOutput2i
addl %eax, %ebx
jmp .L4
.cfi_endproc
.LFE4040:
.size _Z20doComputationOutput2i, .-_Z20doComputationOutput2i
.globl _Z31__device_stub__Z9addKernelPiPKiPiPKi
.type _Z31__device_stub__Z9addKernelPiPKiPiPKi, @function
_Z31__device_stub__Z9addKernelPiPKiPiPKi:
.LFB4067:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z31__device_stub__Z9addKernelPiPKiPiPKi, .-_Z31__device_stub__Z9addKernelPiPKiPiPKi
.globl _Z9addKernelPiPKi
.type _Z9addKernelPiPKi, @function
_Z9addKernelPiPKi:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z9addKernelPiPKi, .-_Z9addKernelPiPKi
.globl _Z17doCudaComputationPiS_
.type _Z17doCudaComputationPiS_, @function
_Z17doCudaComputationPiS_:
.LFB4042:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $400, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9addKernelPiPKiPiPKi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4042:
.size _Z17doCudaComputationPiS_, .-_Z17doCudaComputationPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addKernelPiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC1:
.string "input.txt"
.text
.globl _Z8readFilePi
.type _Z8readFilePi, @function
_Z8readFilePi:
.LFB4041:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4041
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $552, %rsp
.cfi_def_cfa_offset 592
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 16(%rsp), %rbp
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseC2Ev@PLT
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
movq $0, 488(%rsp)
movb $0, 496(%rsp)
movb $0, 497(%rsp)
movq $0, 504(%rsp)
movq $0, 512(%rsp)
movq $0, 520(%rsp)
movq $0, 528(%rsp)
movq 8+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r12
movq %r12, 16(%rsp)
movq 16+_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %r13
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
movq 16(%rsp), %rax
movq %rbp, %rdi
addq -24(%rax), %rdi
movl $0, %esi
.LEHB0:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE0:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 32(%rsp), %rdi
.LEHB1:
call _ZNSt13basic_filebufIcSt11char_traitsIcEEC1Ev@PLT
.LEHE1:
leaq 32(%rsp), %rsi
leaq 272(%rsp), %rdi
.LEHB2:
call _ZNSt9basic_iosIcSt11char_traitsIcEE4initEPSt15basic_streambufIcS1_E@PLT
.LEHE2:
jmp .L46
.L41:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13basic_filebufIcSt11char_traitsIcEED1Ev@PLT
.L26:
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
.L27:
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L40:
endbr64
movq %rax, %rbx
jmp .L26
.L39:
endbr64
movq %rax, %rbx
jmp .L27
.L28:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L46:
leaq 32(%rsp), %rdi
movl $8, %edx
leaq .LC1(%rip), %rsi
.LEHB4:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
testq %rax, %rax
je .L47
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl $0, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L31
.L47:
movq 16(%rsp), %rax
movq -24(%rax), %rax
leaq 16(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $4, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
.L31:
leaq 12(%rsp), %rbp
jmp .L30
.L49:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L48
movl 12(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
.L30:
leaq 16(%rsp), %rdi
movq %rbp, %rsi
call _ZNSirsERi@PLT
.LEHE4:
jmp .L49
.L48:
leaq 24+_ZTVSt14basic_ifstreamIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 16(%rsp)
leaq 40(%rax), %rax
movq %rax, 272(%rsp)
leaq 16+_ZTVSt13basic_filebufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rdi
.LEHB5:
call _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv@PLT
.LEHE5:
jmp .L34
.L42:
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
call __cxa_end_catch@PLT
.L34:
leaq 136(%rsp), %rdi
call _ZNSt12__basic_fileIcED1Ev@PLT
leaq 16+_ZTVSt15basic_streambufIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
call _ZNSt6localeD1Ev@PLT
movq %r12, 16(%rsp)
movq -24(%r12), %rax
movq %r13, 16(%rsp,%rax)
movq $0, 24(%rsp)
leaq 16+_ZTVSt9basic_iosIcSt11char_traitsIcEE(%rip), %rax
movq %rax, 272(%rsp)
leaq 272(%rsp), %rdi
call _ZNSt8ios_baseD2Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L36
call __stack_chk_fail@PLT
.L36:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4041:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA4041:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4041-.LLSDATTD4041
.LLSDATTD4041:
.byte 0x1
.uleb128 .LLSDACSE4041-.LLSDACSB4041
.LLSDACSB4041:
.uleb128 .LEHB0-.LFB4041
.uleb128 .LEHE0-.LEHB0
.uleb128 .L39-.LFB4041
.uleb128 0
.uleb128 .LEHB1-.LFB4041
.uleb128 .LEHE1-.LEHB1
.uleb128 .L40-.LFB4041
.uleb128 0
.uleb128 .LEHB2-.LFB4041
.uleb128 .LEHE2-.LEHB2
.uleb128 .L41-.LFB4041
.uleb128 0
.uleb128 .LEHB3-.LFB4041
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.uleb128 .LEHB4-.LFB4041
.uleb128 .LEHE4-.LEHB4
.uleb128 .L38-.LFB4041
.uleb128 0
.uleb128 .LEHB5-.LFB4041
.uleb128 .LEHE5-.LEHB5
.uleb128 .L42-.LFB4041
.uleb128 0x1
.uleb128 .LEHB6-.LFB4041
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4041:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4041:
.text
.size _Z8readFilePi, .-_Z8readFilePi
.section .rodata.str1.1
.LC2:
.string "Sum: %d\n"
.LC3:
.string "Sum2: %d\n"
.text
.globl main
.type main, @function
main:
.LFB4039:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $400, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %rbx
movq %rbp, %rdi
call _Z8readFilePi
movq %rbx, %rsi
movq %rbp, %rdi
call _Z17doCudaComputationPiS_
movq %rbx, %rbp
leaq 400(%rbx), %r13
movq %rbx, %rax
movl $0, %edx
.L52:
addl (%rax), %edx
movl %edx, %r12d
addq $4, %rax
cmpq %r13, %rax
jne .L52
movl $0, %ebx
.L53:
movl 0(%rbp), %edi
call _Z20doComputationOutput2i
addl %eax, %ebx
addq $4, %rbp
cmpq %r13, %rbp
jne .L53
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKi # -- Begin function _Z24__device_stub__addKernelPiPKi
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKi,@function
_Z24__device_stub__addKernelPiPKi: # @_Z24__device_stub__addKernelPiPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKi, .Lfunc_end0-_Z24__device_stub__addKernelPiPKi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %rbx
movq %r14, %rdi
callq _Z8readFilePi
movq %r14, %rdi
movq %rbx, %rsi
callq _Z17doCudaComputationPiS_
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
addl (%rbx,%rax,4), %ebp
incq %rax
cmpq $100, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %r15d, %r15d
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %edi
callq _Z20doComputationOutput2i
addl %eax, %r14d
incq %r15
cmpq $100, %r15
jne .LBB1_3
# %bb.4:
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z8readFilePi # -- Begin function _Z8readFilePi
.p2align 4, 0x90
.type _Z8readFilePi,@function
_Z8readFilePi: # @_Z8readFilePi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $0, 4(%rsp)
leaq 8(%rsp), %r14
movq %r14, %rdi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1Ev
leaq 24(%rsp), %rdi
.Ltmp0:
movl $.L.str.2, %esi
movl $8, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp1:
# %bb.1: # %.noexc
movq 8(%rsp), %rcx
addq -24(%rcx), %r14
xorl %esi, %esi
testq %rax, %rax
jne .LBB2_3
# %bb.2:
movl 32(%r14), %esi
orl $4, %esi
.LBB2_3: # %.invoke
.Ltmp2:
movq %r14, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp3:
# %bb.4: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit.preheader
leaq 8(%rsp), %r14
leaq 4(%rsp), %r15
.p2align 4, 0x90
.LBB2_5: # %_ZNSt14basic_ifstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
# =>This Inner Loop Header: Depth=1
.Ltmp5:
movq %r14, %rdi
movq %r15, %rsi
callq _ZNSirsERi
.Ltmp6:
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movq (%rax), %rcx
movq -24(%rcx), %rcx
testb $5, 32(%rax,%rcx)
jne .LBB2_11
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl 4(%rsp), %eax
movl %eax, (%rbx)
addq $4, %rbx
jmp .LBB2_5
.LBB2_11:
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
addq $528, %rsp # imm = 0x210
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9: # %.loopexit.split-lp
.cfi_def_cfa_offset 560
.Ltmp4:
jmp .LBB2_10
.LBB2_8: # %.loopexit
.Ltmp7:
.LBB2_10:
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $_ZTTSt14basic_ifstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt14basic_ifstreamIcSt11char_traitsIcEED2Ev
leaq 264(%rsp), %rdi
callq _ZNSt8ios_baseD2Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _Z8readFilePi, .Lfunc_end2-_Z8readFilePi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp6 # Call between .Ltmp6 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z17doCudaComputationPiS_ # -- Begin function _Z17doCudaComputationPiS_
.p2align 4, 0x90
.type _Z17doCudaComputationPiS_,@function
_Z17doCudaComputationPiS_: # @_Z17doCudaComputationPiS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 99(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17doCudaComputationPiS_, .Lfunc_end3-_Z17doCudaComputationPiS_
.cfi_endproc
# -- End function
.globl _Z20doComputationOutput2i # -- Begin function _Z20doComputationOutput2i
.p2align 4, 0x90
.type _Z20doComputationOutput2i,@function
_Z20doComputationOutput2i: # @_Z20doComputationOutput2i
.cfi_startproc
# %bb.0:
xorl %eax, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
cmpl $9, %edi
jl .LBB4_3
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
addl %edi, %eax
movl %edi, %edx
imulq %rcx, %rdx
shrq $33, %rdx
addl $-2, %edx
movl %edx, %edi
cmpl $9, %edi
jge .LBB4_2
.LBB4_3:
addl %edi, %eax
retq
.Lfunc_end4:
.size _Z20doComputationOutput2i, .Lfunc_end4-_Z20doComputationOutput2i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKi,@object # @_Z9addKernelPiPKi
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKi
.p2align 3, 0x0
_Z9addKernelPiPKi:
.quad _Z24__device_stub__addKernelPiPKi
.size _Z9addKernelPiPKi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Sum: %d\n"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Sum2: %d\n"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "input.txt"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9addKernelPiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} | .file "tmpxft_0002ec17_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int *a, int *b, int *c)
{
//blockDim is num threads/block, multiplied by block number to index to one of them, then select thread inside block via thread Id
int threadID = threadIdx.x + blockIdx.x * blockDim.x;
//Max 65 535 blocks, with 512 threads each ~ 8 million elements, if vector exceeds that amount require a soln
//Run arbitrary number of blocks and threads
//Done at each parallel process, allows a single launch of threads to iteratively cycle through all available indices of vector
//As long as each thread begins at a unique index-val, all will iterate arr without affecting one another
while (threadID < N)
{
c[threadID] = a[threadID] + b[threadID];
//Add
threadID += blockDim.x * gridDim.x;
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002ec17_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
cudaError_t err = cudaMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(A_gpu.data, A.data, A_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", cudaGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = cudaMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(B_gpu.data, B.data, B_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", cudaGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
cudaMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(C_gpu.data, C.data, C_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", cudaGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = cudaThreadSynchronize();
printf("Run Cuda Code: %s\n", cudaGetErrorString(err));
//Get Result
err = cudaMemcpy(C.data, C_gpu.data, C_size, cudaMemcpyDeviceToHost);
printf("Get Result: %s\n", cudaGetErrorString(err));
cudaFree(A_gpu.data);
cudaFree(B_gpu.data);
cudaFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} | code for sm_80
Function : _Z8MatMul_k6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0020*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ S2UR UR7, SR_CTAID.Y ; /* 0x00000000000779c3 */
/* 0x000e620000002600 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x10, PT ; /* 0x000000100400780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc800000001ff */
/*0080*/ S2UR UR8, SR_CTAID.X ; /* 0x00000000000879c3 */
/* 0x000ef00000002500 */
/*0090*/ @!P0 BRA 0x510 ; /* 0x0000047000008947 */
/* 0x00afea0003800000 */
/*00a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*00b0*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.SHL.U32 R2, R0, 0x40, RZ ; /* 0x0000004000027824 */
/* 0x004fe200078e00ff */
/*00d0*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe2000f8e023f */
/*00e0*/ LEA.HI R4, R4, c[0x0][0x164], RZ, 0x4 ; /* 0x0000590004047a11 */
/* 0x000fe200078f20ff */
/*00f0*/ IMAD R24, R0.reuse, c[0x0][0x164], R3.reuse ; /* 0x0000590000187a24 */
/* 0x141fe200078e0203 */
/*0100*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R25, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000197a24 */
/* 0x000fe200078e0203 */
/*0120*/ SHF.R.S32.HI R17, RZ, 0x4, R4 ; /* 0x00000004ff117819 */
/* 0x000fe20000011404 */
/*0130*/ IMAD R16, R3, 0x4, R2 ; /* 0x0000000403107824 */
/* 0x000fe200078e0202 */
/*0140*/ USHF.L.U32 UR5, UR4, 0x4, URZ ; /* 0x0000000404057899 */
/* 0x000fc4000800063f */
/*0150*/ USHF.L.U32 UR6, UR8, 0x4, URZ ; /* 0x0000000408067899 */
/* 0x000fe4000800063f */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0170*/ USHF.R.S32.HI UR12, URZ, 0x1f, UR6 ; /* 0x0000001f3f0c7899 */
/* 0x000fe20008011406 */
/*0180*/ IADD3 R6, P0, R25, UR6, RZ ; /* 0x0000000619067c10 */
/* 0x000fe2000ff1e0ff */
/*0190*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR5 ; /* 0x0000001f3f097899 */
/* 0x000fe20008011405 */
/*01a0*/ IADD3 R5, P1, R24, UR5, RZ ; /* 0x0000000518057c10 */
/* 0x000fc6000ff3e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R25, UR12, 0x1, P0 ; /* 0x0000000c19077c11 */
/* 0x000fe400080f0eff */
/*01c0*/ LEA.HI.X.SX32 R8, R24, UR9, 0x1, P1 ; /* 0x0000000918087c11 */
/* 0x000fe400088f0eff */
/*01d0*/ LEA R10, P0, R6.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c00060a7a11 */
/* 0x040fe400078010ff */
/*01e0*/ LEA R4, P1, R5.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0005047a11 */
/* 0x040fe400078210ff */
/*01f0*/ LEA.HI.X R11, R6, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d00060b7a11 */
/* 0x000fe400000f1407 */
/*0200*/ LEA.HI.X R5, R5, c[0x0][0x174], R8, 0x2, P1 ; /* 0x00005d0005057a11 */
/* 0x000fc800008f1408 */
/*0210*/ LDG.E R11, [R10.64] ; /* 0x0000000a0a0b7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R19, [R4.64] ; /* 0x0000000a04137981 */
/* 0x000ee2000c1e1900 */
/*0230*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0240*/ ISETP.LE.AND P0, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe2000bf03270 */
/*0250*/ ULDC UR9, c[0x0][0x17c] ; /* 0x00005f0000097ab9 */
/* 0x000fe40000000800 */
/*0260*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0270*/ ULEA UR6, UR9, UR6, 0x4 ; /* 0x0000000609067291 */
/* 0x000fe2000f8e203f */
/*0280*/ STS [R16+0x400], R11 ; /* 0x0004000b10007388 */
/* 0x004fe80000000800 */
/*0290*/ STS [R16], R19 ; /* 0x0000001310007388 */
/* 0x008fe80000000800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS R8, [R3.X4+0x400] ; /* 0x0004000003087984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS.128 R12, [R2] ; /* 0x00000000020c7984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS R21, [R3.X4+0x440] ; /* 0x0004400003157984 */
/* 0x000e680000004800 */
/*02e0*/ LDS R23, [R3.X4+0x480] ; /* 0x0004800003177984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R26, [R3.X4+0x4c0] ; /* 0x0004c000031a7984 */
/* 0x000ee80000004800 */
/*0300*/ LDS R27, [R3.X4+0x500] ; /* 0x00050000031b7984 */
/* 0x000fe80000004800 */
/*0310*/ LDS.128 R4, [R2+0x10] ; /* 0x0000100002047984 */
/* 0x000f280000000c00 */
/*0320*/ LDS R20, [R3.X4+0x540] ; /* 0x0005400003147984 */
/* 0x000f680000004800 */
/*0330*/ LDS R19, [R3.X4+0x580] ; /* 0x0005800003137984 */
/* 0x000f680000004800 */
/*0340*/ LDS R18, [R3.X4+0x5c0] ; /* 0x0005c00003127984 */
/* 0x000f680000004800 */
/*0350*/ LDS R22, [R3.X4+0x640] ; /* 0x0006400003167984 */
/* 0x000fe20000004800 */
/*0360*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*0370*/ FFMA R13, R21, R13, R8 ; /* 0x0000000d150d7223 */
/* 0x002fe40000000008 */
/*0380*/ LDS R21, [R3.X4+0x600] ; /* 0x0006000003157984 */
/* 0x000fe40000004800 */
/*0390*/ FFMA R13, R23, R14, R13 ; /* 0x0000000e170d7223 */
/* 0x004fe4000000000d */
/*03a0*/ LDS.128 R8, [R2+0x20] ; /* 0x0000200002087984 */
/* 0x000e240000000c00 */
/*03b0*/ FFMA R13, R26, R15, R13 ; /* 0x0000000f1a0d7223 */
/* 0x008fe4000000000d */
/*03c0*/ LDS R23, [R3.X4+0x680] ; /* 0x0006800003177984 */
/* 0x000e640000004800 */
/*03d0*/ FFMA R13, R27, R4, R13 ; /* 0x000000041b0d7223 */
/* 0x010fc4000000000d */
/*03e0*/ LDS R4, [R3.X4+0x6c0] ; /* 0x0006c00003047984 */
/* 0x000ea40000004800 */
/*03f0*/ FFMA R20, R20, R5, R13 ; /* 0x0000000514147223 */
/* 0x020fe4000000000d */
/*0400*/ LDS R5, [R3.X4+0x700] ; /* 0x0007000003057984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R12, [R2+0x30] ; /* 0x00003000020c7984 */
/* 0x000ee20000000c00 */
/*0420*/ FFMA R26, R19, R6, R20 ; /* 0x00000006131a7223 */
/* 0x000fc60000000014 */
/*0430*/ LDS R20, [R3.X4+0x740] ; /* 0x0007400003147984 */
/* 0x000f280000004800 */
/*0440*/ LDS R19, [R3.X4+0x780] ; /* 0x0007800003137984 */
/* 0x000f680000004800 */
/*0450*/ LDS R6, [R3.X4+0x7c0] ; /* 0x0007c00003067984 */
/* 0x000f620000004800 */
/*0460*/ FFMA R7, R18, R7, R26 ; /* 0x0000000712077223 */
/* 0x000fc8000000001a */
/*0470*/ FFMA R7, R21, R8, R7 ; /* 0x0000000815077223 */
/* 0x001fc80000000007 */
/*0480*/ FFMA R7, R22, R9, R7 ; /* 0x0000000916077223 */
/* 0x000fc80000000007 */
/*0490*/ FFMA R7, R23, R10, R7 ; /* 0x0000000a17077223 */
/* 0x002fc80000000007 */
/*04a0*/ FFMA R4, R4, R11, R7 ; /* 0x0000000b04047223 */
/* 0x004fc80000000007 */
/*04b0*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x008fc80000000004 */
/*04c0*/ FFMA R4, R20, R13, R4 ; /* 0x0000000d14047223 */
/* 0x010fc80000000004 */
/*04d0*/ FFMA R4, R19, R14, R4 ; /* 0x0000000e13047223 */
/* 0x020fc80000000004 */
/*04e0*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @!P0 BRA 0x170 ; /* 0xfffffc6000008947 */
/* 0x000fea000383ffff */
/*0510*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0520*/ IMAD R0, R0, c[0x0][0x194], R3 ; /* 0x0000650000007a24 */
/* 0x005fe200078e0203 */
/*0530*/ UIMAD UR4, UR7, UR4, UR8 ; /* 0x00000004070472a4 */
/* 0x000fc8000f8e0208 */
/*0540*/ USHF.L.U32 UR4, UR4, 0x4, URZ ; /* 0x0000000404047899 */
/* 0x000fc8000800063f */
/*0550*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0560*/ IADD3 R3, P0, R0, UR4, RZ ; /* 0x0000000400037c10 */
/* 0x000fc8000ff1e0ff */
/*0570*/ LEA.HI.X.SX32 R0, R0, UR5, 0x1, P0 ; /* 0x0000000500007c11 */
/* 0x000fe400080f0eff */
/*0580*/ LEA R2, P0, R3, c[0x0][0x1a0], 0x2 ; /* 0x0000680003027a11 */
/* 0x000fc800078010ff */
/*0590*/ LEA.HI.X R3, R3, c[0x0][0x1a4], R0, 0x2, P0 ; /* 0x0000690003037a11 */
/* 0x000fca00000f1400 */
/*05a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c10190a */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
cudaError_t err = cudaMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(A_gpu.data, A.data, A_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", cudaGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = cudaMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(B_gpu.data, B.data, B_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", cudaGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
cudaMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(C_gpu.data, C.data, C_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", cudaGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = cudaThreadSynchronize();
printf("Run Cuda Code: %s\n", cudaGetErrorString(err));
//Get Result
err = cudaMemcpy(C.data, C_gpu.data, C_size, cudaMemcpyDeviceToHost);
printf("Get Result: %s\n", cudaGetErrorString(err));
cudaFree(A_gpu.data);
cudaFree(B_gpu.data);
cudaFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} | .file "tmpxft_00167447_00000000-6_matMulLocal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9CopyShape6Matrix
.type _Z9CopyShape6Matrix, @function
_Z9CopyShape6Matrix:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rax
movl 8(%rsp), %edx
movl %edx, (%rdi)
movl 12(%rsp), %edx
movl %edx, 4(%rdi)
ret
.cfi_endproc
.LFE2057:
.size _Z9CopyShape6Matrix, .-_Z9CopyShape6Matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Reading past end of array\n"
.text
.globl _Z6SetVal6Matrixiif
.type _Z6SetVal6Matrixiif, @function
_Z6SetVal6Matrixiif:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movd %xmm0, %ebp
movl 36(%rsp), %eax
imull %eax, %esi
leal (%rsi,%rdi), %ebx
imull 32(%rsp), %eax
cmpl %eax, %ebx
jg .L7
.L5:
movslq %ebx, %rbx
movq 48(%rsp), %rax
movl %ebp, (%rax,%rbx,4)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2059:
.size _Z6SetVal6Matrixiif, .-_Z6SetVal6Matrixiif
.globl _Z6GetVal6Matrixii
.type _Z6GetVal6Matrixii, @function
_Z6GetVal6Matrixii:
.LFB2060:
.cfi_startproc
endbr64
imull 12(%rsp), %esi
addl %edi, %esi
movslq %esi, %rsi
movq 24(%rsp), %rax
movss (%rax,%rsi,4), %xmm0
ret
.cfi_endproc
.LFE2060:
.size _Z6GetVal6Matrixii, .-_Z6GetVal6Matrixii
.globl _Z10InitMatrix6Matrix
.type _Z10InitMatrix6Matrix, @function
_Z10InitMatrix6Matrix:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl 48(%rsp), %r13d
movl 52(%rsp), %ebp
movl $0, %r12d
testl %r13d, %r13d
jg .L10
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call rand@PLT
movl %r13d, 48(%rsp)
movl %ebp, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
subq $32, %rsp
.cfi_def_cfa_offset 80
movdqu 80(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl %r12d, %esi
movl %ebx, %edi
call _Z6SetVal6Matrixiif
addl $1, %ebx
addq $32, %rsp
.cfi_def_cfa_offset 48
cmpl %ebx, %ebp
jne .L12
.L13:
addl $1, %r12d
cmpl %r13d, %r12d
je .L9
.L10:
movl $0, %ebx
testl %ebp, %ebp
jg .L12
jmp .L13
.cfi_endproc
.LFE2061:
.size _Z10InitMatrix6Matrix, .-_Z10InitMatrix6Matrix
.globl _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
.type _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_, @function
_Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MatMul_k6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_, .-_Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
.globl _Z8MatMul_k6MatrixS_S_
.type _Z8MatMul_k6MatrixS_S_, @function
_Z8MatMul_k6MatrixS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8MatMul_k6MatrixS_S_, .-_Z8MatMul_k6MatrixS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Inner matrix dimensions must be equal!"
.section .rodata.str1.1
.LC4:
.string "Cuda Error: malloc A: %s\n"
.LC5:
.string "Cuda Error: cpy A: %s\n"
.LC6:
.string "Cuda Error: malloc B: %s\n"
.LC7:
.string "Cuda Error: cpy B: %s\n"
.LC8:
.string "Cuda Error: malloc C: %s\n"
.LC9:
.string "Cuda Error: cpy C: %s\n"
.LC10:
.string "Run Cuda Code: %s\n"
.LC11:
.string "Get Result: %s\n"
.text
.globl _Z6MatMul6MatrixS_
.type _Z6MatMul6MatrixS_, @function
_Z6MatMul6MatrixS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movl 304(%rsp), %r14d
movl 308(%rsp), %r13d
movl %r14d, 4(%rdi)
movl 332(%rsp), %r15d
movl %r15d, (%rdi)
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, 16(%rbx)
movl 328(%rsp), %r12d
cmpl %r13d, %r12d
je .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 16(%rbx)
.L28:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L34
movq %rbx, %rax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %r14d, 48(%rsp)
movl %r13d, 52(%rsp)
imull %r14d, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r13, %rdx
movq 320(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 80(%rsp)
movl %r15d, 84(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r12, %rdx
movq 344(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 112(%rsp)
movl %r14d, 116(%rsp)
leaq 128(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 116(%rsp), %edx
shrl $4, %edx
movl 112(%rsp), %eax
shrl $4, %eax
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 128(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
jmp .L28
.L35:
movdqa 48(%rsp), %xmm0
movaps %xmm0, 144(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 176(%rsp)
movq 96(%rsp), %rax
movq %rax, 192(%rsp)
movdqa 112(%rsp), %xmm2
movaps %xmm2, 208(%rsp)
movq 128(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 144(%rsp), %rdi
call _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
jmp .L31
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6MatMul6MatrixS_, .-_Z6MatMul6MatrixS_
.section .rodata.str1.8
.align 8
.LC12:
.string "********Entering Matrix Mul*****\n"
.section .rodata.str1.1
.LC14:
.string "Time %d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5000, %r14d
movl $1, %ebx
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
.L37:
imull $3500, %ebx, %r13d
movl %r14d, %edi
imull %r13d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, 16(%rsp)
movl %r13d, 20(%rsp)
movq %rax, 32(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 208
movdqa 48(%rsp), %xmm1
movups %xmm1, (%rsp)
movq %rax, 16(%rsp)
call _Z10InitMatrix6Matrix
imull $7500, %ebx, %r15d
addq $32, %rsp
.cfi_def_cfa_offset 176
movl %r13d, %edi
imull %r15d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r13d, 48(%rsp)
movl %r15d, 52(%rsp)
movq %rax, 64(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 208
movdqa 80(%rsp), %xmm2
movups %xmm2, (%rsp)
movq %rax, 16(%rsp)
call _Z10InitMatrix6Matrix
addq $32, %rsp
.cfi_def_cfa_offset 176
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r13
subq $48, %rsp
.cfi_def_cfa_offset 224
movdqa 96(%rsp), %xmm3
movups %xmm3, 24(%rsp)
movq 112(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 64(%rsp), %xmm4
movups %xmm4, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
movq 56(%rsp), %rdi
call _Z6MatMul6MatrixS_
addq $48, %rsp
.cfi_def_cfa_offset 176
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 96(%rsp), %rdi
call free@PLT
addl $1, %ebx
addl $5000, %r14d
cmpl $4, %ebx
jne .L37
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z8MatMul_k6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MatMul_k6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1101004800
.align 4
.LC2:
.long 805306368
.align 4
.LC13:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
cudaError_t err = cudaMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(A_gpu.data, A.data, A_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", cudaGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = cudaMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(B_gpu.data, B.data, B_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", cudaGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
cudaMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", cudaGetErrorString(err));
err = cudaMemcpy(C_gpu.data, C.data, C_size, cudaMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", cudaGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = cudaThreadSynchronize();
printf("Run Cuda Code: %s\n", cudaGetErrorString(err));
//Get Result
err = cudaMemcpy(C.data, C_gpu.data, C_size, cudaMemcpyDeviceToHost);
printf("Get Result: %s\n", cudaGetErrorString(err));
cudaFree(A_gpu.data);
cudaFree(B_gpu.data);
cudaFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
hipError_t err = hipMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", hipGetErrorString(err));
err = hipMemcpy(A_gpu.data, A.data, A_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", hipGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = hipMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", hipGetErrorString(err));
err = hipMemcpy(B_gpu.data, B.data, B_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", hipGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
hipMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", hipGetErrorString(err));
err = hipMemcpy(C_gpu.data, C.data, C_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", hipGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = hipDeviceSynchronize();
printf("Run Cuda Code: %s\n", hipGetErrorString(err));
//Get Result
err = hipMemcpy(C.data, C_gpu.data, C_size, hipMemcpyDeviceToHost);
printf("Get Result: %s\n", hipGetErrorString(err));
hipFree(A_gpu.data);
hipFree(B_gpu.data);
hipFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
hipError_t err = hipMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", hipGetErrorString(err));
err = hipMemcpy(A_gpu.data, A.data, A_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", hipGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = hipMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", hipGetErrorString(err));
err = hipMemcpy(B_gpu.data, B.data, B_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", hipGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
hipMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", hipGetErrorString(err));
err = hipMemcpy(C_gpu.data, C.data, C_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", hipGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = hipDeviceSynchronize();
printf("Run Cuda Code: %s\n", hipGetErrorString(err));
//Get Result
err = hipMemcpy(C.data, C_gpu.data, C_size, hipMemcpyDeviceToHost);
printf("Get Result: %s\n", hipGetErrorString(err));
hipFree(A_gpu.data);
hipFree(B_gpu.data);
hipFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MatMul_k6MatrixS_S_
.globl _Z8MatMul_k6MatrixS_S_
.p2align 8
.type _Z8MatMul_k6MatrixS_S_,@function
_Z8MatMul_k6MatrixS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 16
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b32_e32 v5, 2, v1
s_ashr_i32 s5, s6, 31
s_mov_b32 s7, 0
s_lshr_b32 s5, s5, 28
v_lshlrev_b32_e32 v4, 6, v0
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s5, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, s4, v0, v[1:2]
v_mad_u64_u32 v[2:3], null, s6, v0, v[1:2]
v_mov_b32_e32 v3, 0
s_mul_i32 s6, s6, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, v4, v5
v_add_nc_u32_e32 v5, 0x400, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v11, vcc_lo
v_add_nc_u32_e32 v10, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 4
s_lshl_b32 s10, s10, 4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
s_clause 0x1
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v2, v12
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v4
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, s0, v0, v[1:2]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MatMul_k6MatrixS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MatMul_k6MatrixS_S_, .Lfunc_end0-_Z8MatMul_k6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MatMul_k6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MatMul_k6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
//use 16 for portability
#define BLOCK_SIZE 16
struct Matrix
{
int height;
int width;
int pWidth; //width of parent matrix
float* data;
};
void InitMatrix(Matrix M);
Matrix CopyShape(const Matrix M){
struct Matrix M_copy;
M_copy.height = M.height;
M_copy.width = M.width;
return M_copy;
}
//A and B are input, C is output
//Naive matrix multiplication algorithm
__global__ void MatMul_k(const struct Matrix A, const struct Matrix B, Matrix C){
//row of A determines C row, Col of B determines C col
//Block determines which submatrix of C we work on
//Create sub matrix of C to calculate with shared memory
struct Matrix C_sub;
C_sub.width = BLOCK_SIZE;
C_sub.height = BLOCK_SIZE;
//int C_stride = C.width;
int C_y = C.width * BLOCK_SIZE * blockIdx.y;
int C_x = BLOCK_SIZE * blockIdx.x;
C_sub.data = &C.data[C_y + C_x];
//Thread determines where in C block we are
float C_val = 0.0;
int x = threadIdx.y;
int y = threadIdx.x;
//loop over A and B submatrices to compute C submatrix
for(int m = 0; m < (A.width / BLOCK_SIZE); m++){
struct Matrix A_sub;
A_sub.width = BLOCK_SIZE;
A_sub.height = BLOCK_SIZE;
int A_y = A.width * blockIdx.y * BLOCK_SIZE;
int A_x = m * BLOCK_SIZE;
A_sub.data = &A.data[A_y + A_x];
struct Matrix B_sub;
B_sub.width = BLOCK_SIZE;
B_sub.height = BLOCK_SIZE;
int B_y = B.width * m * BLOCK_SIZE;
int B_x = blockIdx.x * BLOCK_SIZE;
B_sub.data = &A.data[B_y + B_x];
//this memory is shared between threads
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
//each thread loads an element
//note we use parent widths
As[y][x] = A_sub.data[A.width * y + x];
Bs[y][x] = B_sub.data[B.width * y + x];
//make sure all memory is loaded
__syncthreads();
//Compute Asub and Bsub product to accumulate Csub element
for(int c = 0; c < BLOCK_SIZE; c++){
C_val += As[y][c] * Bs[c][x];
}
//wait for computation to finish before loading new memory
__syncthreads();
}
//write C sub element, again note parent width
C_sub.data[C.width * y + x] = C_val;
}
Matrix MatMul(const Matrix A, const Matrix B){
Matrix C;
C.width = A.height;
C.height = B.width;
C.data = (float*)malloc(C.width * C.height * sizeof(float));
if(A.width != B.height){
printf("Inner matrix dimensions must be equal!");
C.data = NULL;
return C;
}
//Copy A and B over to GPU
struct Matrix A_gpu;// = CopyShape(A);
A_gpu.height = A.height;
A_gpu.width = A.width;
size_t A_size = A_gpu.height * A_gpu.width * sizeof(float);
hipError_t err = hipMalloc(&A_gpu.data, A_size);
printf("Cuda Error: malloc A: %s\n", hipGetErrorString(err));
err = hipMemcpy(A_gpu.data, A.data, A_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy A: %s\n", hipGetErrorString(err));
struct Matrix B_gpu = CopyShape(B);
size_t B_size = B_gpu.height * B_gpu.width * sizeof(float);
err = hipMalloc(&B_gpu.data, B_size);
printf("Cuda Error: malloc B: %s\n", hipGetErrorString(err));
err = hipMemcpy(B_gpu.data, B.data, B_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy B: %s\n", hipGetErrorString(err));
//Make space for resul matrix
struct Matrix C_gpu = CopyShape(C);
size_t C_size = C_gpu.width * C_gpu.height * sizeof(float);
//C_gpu.data = (float*)malloc(C_gpu.width * C_gpu.height * sizeof(float));
//InitMatrix(C_gpu);
hipMalloc(&C_gpu.data, C_size);
printf("Cuda Error: malloc C: %s\n", hipGetErrorString(err));
err = hipMemcpy(C_gpu.data, C.data, C_size, hipMemcpyHostToDevice);
printf("Cuda Error: cpy C: %s\n", hipGetErrorString(err));
//Run Cuda Code
dim3 block_dim(BLOCK_SIZE, BLOCK_SIZE); //z dim = 1
int grid_x = ceil(C_gpu.width/block_dim.x);
int grid_y = ceil(C_gpu.height/block_dim.y);
dim3 grid_dim(grid_x, grid_y);
MatMul_k<<<grid_dim, block_dim>>>(A_gpu, B_gpu, C_gpu);
err = hipDeviceSynchronize();
printf("Run Cuda Code: %s\n", hipGetErrorString(err));
//Get Result
err = hipMemcpy(C.data, C_gpu.data, C_size, hipMemcpyDeviceToHost);
printf("Get Result: %s\n", hipGetErrorString(err));
hipFree(A_gpu.data);
hipFree(B_gpu.data);
hipFree(C_gpu.data);
return C;
}
void SetVal(Matrix M, int x, int y, float val){
if(y*M.width + x > M.width*M.height)
printf("Reading past end of array\n");
M.data[y*M.width + x] = val;
}
float GetVal(Matrix M, int x, int y){
return M.data[y*M.width + x];
}
void InitMatrix(Matrix M){
for(int y = 0; y<M.height; y++){
for(int x = 0; x<M.width; x++){
float val = 20*(float)rand()/(float)RAND_MAX;
SetVal(M, x, y, val);
}
}
}
int main(){
int NUM_ARRAYS = 3;
//struct Matrix As[NUM_ARRAYS];
//struct Matrix Bs[NUM_ARRAYS];
for(int i=1; i<NUM_ARRAYS+1; i++){
struct Matrix A, B;
//Initialize Array
A.height = i*5000;
A.width = i*3500;
A.data = (float*)malloc(A.width * A.height * sizeof(float));
InitMatrix(A);
B.height = i*3500;
B.width = i*7500;
B.data = (float*)malloc(B.width * B.height * sizeof(float));
InitMatrix(B);
//Get Matrix Product of Array
printf("********Entering Matrix Mul*****\n");
clock_t start = clock();
struct Matrix C = MatMul(A, B);
clock_t time = clock() - start;
float sec = (float)time/(float)CLOCKS_PER_SEC;
printf("Time %d: %f\n", i, sec);
free(A.data);
free(B.data);
free(C.data);
}
} | .text
.file "matMulLocal.hip"
.globl _Z9CopyShape6Matrix # -- Begin function _Z9CopyShape6Matrix
.p2align 4, 0x90
.type _Z9CopyShape6Matrix,@function
_Z9CopyShape6Matrix: # @_Z9CopyShape6Matrix
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movl 8(%rsp), %ecx
movl %ecx, (%rdi)
movl 12(%rsp), %ecx
movl %ecx, 4(%rdi)
retq
.Lfunc_end0:
.size _Z9CopyShape6Matrix, .Lfunc_end0-_Z9CopyShape6Matrix
.cfi_endproc
# -- End function
.globl _Z23__device_stub__MatMul_k6MatrixS_S_ # -- Begin function _Z23__device_stub__MatMul_k6MatrixS_S_
.p2align 4, 0x90
.type _Z23__device_stub__MatMul_k6MatrixS_S_,@function
_Z23__device_stub__MatMul_k6MatrixS_S_: # @_Z23__device_stub__MatMul_k6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MatMul_k6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__MatMul_k6MatrixS_S_, .Lfunc_end1-_Z23__device_stub__MatMul_k6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_ # -- Begin function _Z6MatMul6MatrixS_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_,@function
_Z6MatMul6MatrixS_: # @_Z6MatMul6MatrixS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl 304(%rsp), %r13d
movl %r13d, 4(%rdi)
movl 332(%rsp), %r15d
movl %r15d, (%rdi)
movl %r15d, %eax
imull %r13d, %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rbx)
movl 308(%rsp), %ecx
movl 328(%rsp), %ebp
cmpl %ebp, %ecx
jne .LBB2_1
# %bb.2:
movl %r13d, 48(%rsp)
movl %ecx, 52(%rsp)
imull %r13d, %ecx
movslq %ecx, %r12
shlq $2, %r12
leaq 64(%rsp), %rdi
movq %rax, 72(%rsp) # 8-byte Spill
movq %r12, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rdi
leaq 304(%rsp), %rax
movq 16(%rax), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %ebp, 24(%rsp)
movl %r15d, 28(%rsp)
imull %r15d, %ebp
movslq %ebp, %r12
shlq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
leaq 328(%rsp), %rax
movq 16(%rax), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %r15d, (%rsp)
movl %r13d, 4(%rsp)
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl (%rsp), %edi
movl 4(%rsp), %eax
shrl $4, %eax
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movups 48(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 40(%rsp), %rax
movq %rax, 208(%rsp)
movups 24(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 16(%rsp), %rax
movq %rax, 240(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8MatMul_k6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rbx), %rdi
movq 16(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
jmp .LBB2_5
.LBB2_1:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq $0, 16(%rbx)
.LBB2_5:
movq %rbx, %rax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6MatMul6MatrixS_, .Lfunc_end2-_Z6MatMul6MatrixS_
.cfi_endproc
# -- End function
.globl _Z6SetVal6Matrixiif # -- Begin function _Z6SetVal6Matrixiif
.p2align 4, 0x90
.type _Z6SetVal6Matrixiif,@function
_Z6SetVal6Matrixiif: # @_Z6SetVal6Matrixiif
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
leaq 32(%rsp), %r14
movl 36(%rsp), %eax
imull %eax, %ebx
addl %edi, %ebx
imull 32(%rsp), %eax
cmpl %eax, %ebx
jle .LBB3_2
# %bb.1:
movl $.Lstr, %edi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
.LBB3_2:
movq 16(%r14), %rax
movslq %ebx, %rcx
movss %xmm0, (%rax,%rcx,4)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z6SetVal6Matrixiif, .Lfunc_end3-_Z6SetVal6Matrixiif
.cfi_endproc
# -- End function
.globl _Z6GetVal6Matrixii # -- Begin function _Z6GetVal6Matrixii
.p2align 4, 0x90
.type _Z6GetVal6Matrixii,@function
_Z6GetVal6Matrixii: # @_Z6GetVal6Matrixii
.cfi_startproc
# %bb.0:
movq 24(%rsp), %rax
imull 12(%rsp), %esi
addl %edi, %esi
movslq %esi, %rcx
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
retq
.Lfunc_end4:
.size _Z6GetVal6Matrixii, .Lfunc_end4-_Z6GetVal6Matrixii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10InitMatrix6Matrix
.LCPI5_0:
.long 0x41a00000 # float 20
.LCPI5_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10InitMatrix6Matrix
.p2align 4, 0x90
.type _Z10InitMatrix6Matrix,@function
_Z10InitMatrix6Matrix: # @_Z10InitMatrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 80(%rsp), %eax
movq %rax, 8(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
leaq 80(%rsp), %rax
movl 4(%rax), %r14d
movq 16(%rax), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl %r14d, %ebp
imull 8(%rsp), %ebp # 4-byte Folded Reload
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r13
addq %r14, %r12
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_8
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %r14d, %r14d
jle .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebx, %ebx
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_6: # %_Z6SetVal6Matrixiif.exit
# in Loop: Header=BB5_4 Depth=2
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq %rbx, %r14
je .LBB5_7
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
leal (%r12,%rbx), %eax
cmpl %eax, %ebp
jge .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
movl $.Lstr, %edi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB5_6
.LBB5_8: # %._crit_edge12
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z10InitMatrix6Matrix, .Lfunc_end5-_Z10InitMatrix6Matrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x41a00000 # float 20
.LCPI6_1:
.long 0x30000000 # float 4.65661287E-10
.LCPI6_2:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
movl $3500, %r14d # imm = 0xDAC
movl $7500, %eax # imm = 0x1D4C
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_13: # %_Z10InitMatrix6Matrix.exit46
# in Loop: Header=BB6_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, 112(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 116(%rsp)
movq %r15, 128(%rsp)
movl %eax, 136(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 140(%rsp)
movq %r12, 152(%rsp)
movq %r12, 40(%rsp)
movups 136(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
movups 112(%rsp), %xmm0
movups %xmm0, (%rsp)
leaq 160(%rsp), %rdi
callq _Z6MatMul6MatrixS_
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI6_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movq 72(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 176(%rsp), %rdi
callq free
movq 64(%rsp), %rax # 8-byte Reload
incq %rbx
movq 88(%rsp), %r14 # 8-byte Reload
addq $3500, %r14 # imm = 0xDAC
addq $7500, %rax # imm = 0x1D4C
cmpq $4, %rbx
je .LBB6_14
.LBB6_1: # %.preheader.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
# Child Loop BB6_8 Depth 2
# Child Loop BB6_9 Depth 3
movq %rax, 64(%rsp) # 8-byte Spill
imulq $5000, %rbx, %rcx # imm = 0x1388
movq %rbx, 72(%rsp) # 8-byte Spill
imulq $3500, %rbx, %rbx # imm = 0xDAC
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rcx, 80(%rsp) # 8-byte Spill
imulq %rcx, %rbx
leal (,%rbx,4), %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
xorl %r13d, %r13d
movq %r14, 88(%rsp) # 8-byte Spill
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_2 Depth=2
incq %r13
movq 88(%rsp), %r14 # 8-byte Reload
addq %r14, %r12
cmpq 80(%rsp), %r13 # 8-byte Folded Reload
je .LBB6_7
.LBB6_2: # %.preheader.i
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
movq %r12, %rbp
andq $-4, %rbp
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_5: # %_Z6SetVal6Matrixiif.exit.i
# in Loop: Header=BB6_3 Depth=3
movss %xmm0, (%r15,%rbp,4)
incq %rbp
decq %r14
je .LBB6_6
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI6_0(%rip), %xmm0
mulss .LCPI6_1(%rip), %xmm0
cmpq %rbx, %rbp
jbe .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=3
movl $.Lstr, %edi
movss %xmm0, 52(%rsp) # 4-byte Spill
callq puts@PLT
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # %_Z10InitMatrix6Matrix.exit
# in Loop: Header=BB6_1 Depth=1
imulq $7500, 72(%rsp), %rbx # 8-byte Folded Reload
# imm = 0x1D4C
movq %rbx, 96(%rsp) # 8-byte Spill
imulq 56(%rsp), %rbx # 8-byte Folded Reload
leal (,%rbx,4), %edi
andl $-64, %edi
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
xorl %ebp, %ebp
movq 64(%rsp), %r14 # 8-byte Reload
jmp .LBB6_8
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i36
# in Loop: Header=BB6_8 Depth=2
incq %rbp
movq 64(%rsp), %r14 # 8-byte Reload
movq 104(%rsp), %r13 # 8-byte Reload
addq %r14, %r13
cmpq 56(%rsp), %rbp # 8-byte Folded Reload
je .LBB6_13
.LBB6_8: # %.preheader.i34
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_9 Depth 3
movq %r13, 104(%rsp) # 8-byte Spill
andq $-4, %r13
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_11: # %_Z6SetVal6Matrixiif.exit.i42
# in Loop: Header=BB6_9 Depth=3
movss %xmm0, (%r12,%r13,4)
incq %r13
decq %r14
je .LBB6_12
.LBB6_9: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_8 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI6_0(%rip), %xmm0
mulss .LCPI6_1(%rip), %xmm0
cmpq %rbx, %r13
jbe .LBB6_11
# %bb.10: # in Loop: Header=BB6_9 Depth=3
movl $.Lstr, %edi
movss %xmm0, 52(%rsp) # 4-byte Spill
callq puts@PLT
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB6_11
.LBB6_14:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MatMul_k6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MatMul_k6MatrixS_S_,@object # @_Z8MatMul_k6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z8MatMul_k6MatrixS_S_
.p2align 3, 0x0
_Z8MatMul_k6MatrixS_S_:
.quad _Z23__device_stub__MatMul_k6MatrixS_S_
.size _Z8MatMul_k6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Inner matrix dimensions must be equal!"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda Error: malloc A: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda Error: cpy A: %s\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda Error: malloc B: %s\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda Error: cpy B: %s\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda Error: malloc C: %s\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda Error: cpy C: %s\n"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Run Cuda Code: %s\n"
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Get Result: %s\n"
.size .L.str.8, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time %d: %f\n"
.size .L.str.11, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MatMul_k6MatrixS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Reading past end of array"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "********Entering Matrix Mul*****"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MatMul_k6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MatMul_k6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8MatMul_k6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002200 */
/*0020*/ MOV R4, c[0x0][0x164] ; /* 0x0000590000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ S2UR UR7, SR_CTAID.Y ; /* 0x00000000000779c3 */
/* 0x000e620000002600 */
/*0040*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x10, PT ; /* 0x000000100400780c */
/* 0x000fe20003f06270 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc800000001ff */
/*0080*/ S2UR UR8, SR_CTAID.X ; /* 0x00000000000879c3 */
/* 0x000ef00000002500 */
/*0090*/ @!P0 BRA 0x510 ; /* 0x0000047000008947 */
/* 0x00afea0003800000 */
/*00a0*/ SHF.R.S32.HI R4, RZ, 0x1f, R4 ; /* 0x0000001fff047819 */
/* 0x000fe20000011404 */
/*00b0*/ ULDC UR4, c[0x0][0x164] ; /* 0x0000590000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ IMAD.SHL.U32 R2, R0, 0x40, RZ ; /* 0x0000004000027824 */
/* 0x004fe200078e00ff */
/*00d0*/ UIMAD UR4, UR7, UR4, URZ ; /* 0x00000004070472a4 */
/* 0x000fe2000f8e023f */
/*00e0*/ LEA.HI R4, R4, c[0x0][0x164], RZ, 0x4 ; /* 0x0000590004047a11 */
/* 0x000fe200078f20ff */
/*00f0*/ IMAD R24, R0.reuse, c[0x0][0x164], R3.reuse ; /* 0x0000590000187a24 */
/* 0x141fe200078e0203 */
/*0100*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R25, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000197a24 */
/* 0x000fe200078e0203 */
/*0120*/ SHF.R.S32.HI R17, RZ, 0x4, R4 ; /* 0x00000004ff117819 */
/* 0x000fe20000011404 */
/*0130*/ IMAD R16, R3, 0x4, R2 ; /* 0x0000000403107824 */
/* 0x000fe200078e0202 */
/*0140*/ USHF.L.U32 UR5, UR4, 0x4, URZ ; /* 0x0000000404057899 */
/* 0x000fc4000800063f */
/*0150*/ USHF.L.U32 UR6, UR8, 0x4, URZ ; /* 0x0000000408067899 */
/* 0x000fe4000800063f */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*0170*/ USHF.R.S32.HI UR12, URZ, 0x1f, UR6 ; /* 0x0000001f3f0c7899 */
/* 0x000fe20008011406 */
/*0180*/ IADD3 R6, P0, R25, UR6, RZ ; /* 0x0000000619067c10 */
/* 0x000fe2000ff1e0ff */
/*0190*/ USHF.R.S32.HI UR9, URZ, 0x1f, UR5 ; /* 0x0000001f3f097899 */
/* 0x000fe20008011405 */
/*01a0*/ IADD3 R5, P1, R24, UR5, RZ ; /* 0x0000000518057c10 */
/* 0x000fc6000ff3e0ff */
/*01b0*/ LEA.HI.X.SX32 R7, R25, UR12, 0x1, P0 ; /* 0x0000000c19077c11 */
/* 0x000fe400080f0eff */
/*01c0*/ LEA.HI.X.SX32 R8, R24, UR9, 0x1, P1 ; /* 0x0000000918087c11 */
/* 0x000fe400088f0eff */
/*01d0*/ LEA R10, P0, R6.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c00060a7a11 */
/* 0x040fe400078010ff */
/*01e0*/ LEA R4, P1, R5.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0005047a11 */
/* 0x040fe400078210ff */
/*01f0*/ LEA.HI.X R11, R6, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d00060b7a11 */
/* 0x000fe400000f1407 */
/*0200*/ LEA.HI.X R5, R5, c[0x0][0x174], R8, 0x2, P1 ; /* 0x00005d0005057a11 */
/* 0x000fc800008f1408 */
/*0210*/ LDG.E R11, [R10.64] ; /* 0x0000000a0a0b7981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R19, [R4.64] ; /* 0x0000000a04137981 */
/* 0x000ee2000c1e1900 */
/*0230*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0240*/ ISETP.LE.AND P0, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe2000bf03270 */
/*0250*/ ULDC UR9, c[0x0][0x17c] ; /* 0x00005f0000097ab9 */
/* 0x000fe40000000800 */
/*0260*/ UIADD3 UR5, UR5, 0x10, URZ ; /* 0x0000001005057890 */
/* 0x000fe4000fffe03f */
/*0270*/ ULEA UR6, UR9, UR6, 0x4 ; /* 0x0000000609067291 */
/* 0x000fe2000f8e203f */
/*0280*/ STS [R16+0x400], R11 ; /* 0x0004000b10007388 */
/* 0x004fe80000000800 */
/*0290*/ STS [R16], R19 ; /* 0x0000001310007388 */
/* 0x008fe80000000800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS R8, [R3.X4+0x400] ; /* 0x0004000003087984 */
/* 0x000fe80000004800 */
/*02c0*/ LDS.128 R12, [R2] ; /* 0x00000000020c7984 */
/* 0x000e280000000c00 */
/*02d0*/ LDS R21, [R3.X4+0x440] ; /* 0x0004400003157984 */
/* 0x000e680000004800 */
/*02e0*/ LDS R23, [R3.X4+0x480] ; /* 0x0004800003177984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R26, [R3.X4+0x4c0] ; /* 0x0004c000031a7984 */
/* 0x000ee80000004800 */
/*0300*/ LDS R27, [R3.X4+0x500] ; /* 0x00050000031b7984 */
/* 0x000fe80000004800 */
/*0310*/ LDS.128 R4, [R2+0x10] ; /* 0x0000100002047984 */
/* 0x000f280000000c00 */
/*0320*/ LDS R20, [R3.X4+0x540] ; /* 0x0005400003147984 */
/* 0x000f680000004800 */
/*0330*/ LDS R19, [R3.X4+0x580] ; /* 0x0005800003137984 */
/* 0x000f680000004800 */
/*0340*/ LDS R18, [R3.X4+0x5c0] ; /* 0x0005c00003127984 */
/* 0x000f680000004800 */
/*0350*/ LDS R22, [R3.X4+0x640] ; /* 0x0006400003167984 */
/* 0x000fe20000004800 */
/*0360*/ FFMA R8, R8, R12, R9 ; /* 0x0000000c08087223 */
/* 0x001fc80000000009 */
/*0370*/ FFMA R13, R21, R13, R8 ; /* 0x0000000d150d7223 */
/* 0x002fe40000000008 */
/*0380*/ LDS R21, [R3.X4+0x600] ; /* 0x0006000003157984 */
/* 0x000fe40000004800 */
/*0390*/ FFMA R13, R23, R14, R13 ; /* 0x0000000e170d7223 */
/* 0x004fe4000000000d */
/*03a0*/ LDS.128 R8, [R2+0x20] ; /* 0x0000200002087984 */
/* 0x000e240000000c00 */
/*03b0*/ FFMA R13, R26, R15, R13 ; /* 0x0000000f1a0d7223 */
/* 0x008fe4000000000d */
/*03c0*/ LDS R23, [R3.X4+0x680] ; /* 0x0006800003177984 */
/* 0x000e640000004800 */
/*03d0*/ FFMA R13, R27, R4, R13 ; /* 0x000000041b0d7223 */
/* 0x010fc4000000000d */
/*03e0*/ LDS R4, [R3.X4+0x6c0] ; /* 0x0006c00003047984 */
/* 0x000ea40000004800 */
/*03f0*/ FFMA R20, R20, R5, R13 ; /* 0x0000000514147223 */
/* 0x020fe4000000000d */
/*0400*/ LDS R5, [R3.X4+0x700] ; /* 0x0007000003057984 */
/* 0x000fe80000004800 */
/*0410*/ LDS.128 R12, [R2+0x30] ; /* 0x00003000020c7984 */
/* 0x000ee20000000c00 */
/*0420*/ FFMA R26, R19, R6, R20 ; /* 0x00000006131a7223 */
/* 0x000fc60000000014 */
/*0430*/ LDS R20, [R3.X4+0x740] ; /* 0x0007400003147984 */
/* 0x000f280000004800 */
/*0440*/ LDS R19, [R3.X4+0x780] ; /* 0x0007800003137984 */
/* 0x000f680000004800 */
/*0450*/ LDS R6, [R3.X4+0x7c0] ; /* 0x0007c00003067984 */
/* 0x000f620000004800 */
/*0460*/ FFMA R7, R18, R7, R26 ; /* 0x0000000712077223 */
/* 0x000fc8000000001a */
/*0470*/ FFMA R7, R21, R8, R7 ; /* 0x0000000815077223 */
/* 0x001fc80000000007 */
/*0480*/ FFMA R7, R22, R9, R7 ; /* 0x0000000916077223 */
/* 0x000fc80000000007 */
/*0490*/ FFMA R7, R23, R10, R7 ; /* 0x0000000a17077223 */
/* 0x002fc80000000007 */
/*04a0*/ FFMA R4, R4, R11, R7 ; /* 0x0000000b04047223 */
/* 0x004fc80000000007 */
/*04b0*/ FFMA R4, R5, R12, R4 ; /* 0x0000000c05047223 */
/* 0x008fc80000000004 */
/*04c0*/ FFMA R4, R20, R13, R4 ; /* 0x0000000d14047223 */
/* 0x010fc80000000004 */
/*04d0*/ FFMA R4, R19, R14, R4 ; /* 0x0000000e13047223 */
/* 0x020fc80000000004 */
/*04e0*/ FFMA R9, R6, R15, R4 ; /* 0x0000000f06097223 */
/* 0x000fe20000000004 */
/*04f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0500*/ @!P0 BRA 0x170 ; /* 0xfffffc6000008947 */
/* 0x000fea000383ffff */
/*0510*/ ULDC UR4, c[0x0][0x194] ; /* 0x0000650000047ab9 */
/* 0x000fe20000000800 */
/*0520*/ IMAD R0, R0, c[0x0][0x194], R3 ; /* 0x0000650000007a24 */
/* 0x005fe200078e0203 */
/*0530*/ UIMAD UR4, UR7, UR4, UR8 ; /* 0x00000004070472a4 */
/* 0x000fc8000f8e0208 */
/*0540*/ USHF.L.U32 UR4, UR4, 0x4, URZ ; /* 0x0000000404047899 */
/* 0x000fc8000800063f */
/*0550*/ USHF.R.S32.HI UR5, URZ, 0x1f, UR4 ; /* 0x0000001f3f057899 */
/* 0x000fe40008011404 */
/*0560*/ IADD3 R3, P0, R0, UR4, RZ ; /* 0x0000000400037c10 */
/* 0x000fc8000ff1e0ff */
/*0570*/ LEA.HI.X.SX32 R0, R0, UR5, 0x1, P0 ; /* 0x0000000500007c11 */
/* 0x000fe400080f0eff */
/*0580*/ LEA R2, P0, R3, c[0x0][0x1a0], 0x2 ; /* 0x0000680003027a11 */
/* 0x000fc800078010ff */
/*0590*/ LEA.HI.X R3, R3, c[0x0][0x1a4], R0, 0x2, P0 ; /* 0x0000690003037a11 */
/* 0x000fca00000f1400 */
/*05a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c10190a */
/*05b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05c0*/ BRA 0x5c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8MatMul_k6MatrixS_S_
.globl _Z8MatMul_k6MatrixS_S_
.p2align 8
.type _Z8MatMul_k6MatrixS_S_,@function
_Z8MatMul_k6MatrixS_S_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x4
s_load_b64 s[2:3], s[0:1], 0x40
v_bfe_u32 v1, v0, 10, 10
v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s6, 16
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x10
v_lshlrev_b32_e32 v5, 2, v1
s_ashr_i32 s5, s6, 31
s_mov_b32 s7, 0
s_lshr_b32 s5, s5, 28
v_lshlrev_b32_e32 v4, 6, v0
s_add_i32 s5, s6, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s5, s5, 4
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, s4, v0, v[1:2]
v_mad_u64_u32 v[2:3], null, s6, v0, v[1:2]
v_mov_b32_e32 v3, 0
s_mul_i32 s6, s6, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, v4, v5
v_add_nc_u32_e32 v5, 0x400, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v11, vcc_lo
v_add_nc_u32_e32 v10, v5, v4
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
s_mul_i32 s8, s7, s4
s_add_i32 s9, s7, s6
s_add_i32 s10, s8, s14
s_lshl_b32 s8, s9, 4
s_lshl_b32 s10, s10, 4
s_ashr_i32 s9, s8, 31
s_ashr_i32 s11, s10, 31
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v11, vcc_lo, v6, s8
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v7, vcc_lo
s_lshl_b64 s[8:9], s[10:11], 2
v_add_co_u32 v13, vcc_lo, v8, s8
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v9, vcc_lo
s_clause 0x1
global_load_b32 v12, v[11:12], off
global_load_b32 v13, v[13:14], off
v_mov_b32_e32 v11, v5
s_mov_b32 s8, 0
s_waitcnt vmcnt(1)
ds_store_b32 v2, v12
s_waitcnt vmcnt(0)
ds_store_b32 v10, v13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v12, s8, v4
s_add_i32 s8, s8, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 64, v11
s_cmp_eq_u32 s8, 64
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v12, v13
s_cbranch_scc0 .LBB0_3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b32 s0, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[4:5], null, s0, v0, v[1:2]
s_mul_i32 s0, s0, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s0, s0, s14
s_lshl_b32 s0, s0, 4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_ashrrev_i32_e32 v5, 31, v4
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8MatMul_k6MatrixS_S_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 72
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8MatMul_k6MatrixS_S_, .Lfunc_end0-_Z8MatMul_k6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 24
.value_kind: by_value
- .offset: 24
.size: 24
.value_kind: by_value
- .offset: 48
.size: 24
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 72
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8MatMul_k6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8MatMul_k6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167447_00000000-6_matMulLocal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9CopyShape6Matrix
.type _Z9CopyShape6Matrix, @function
_Z9CopyShape6Matrix:
.LFB2057:
.cfi_startproc
endbr64
movq %rdi, %rax
movl 8(%rsp), %edx
movl %edx, (%rdi)
movl 12(%rsp), %edx
movl %edx, 4(%rdi)
ret
.cfi_endproc
.LFE2057:
.size _Z9CopyShape6Matrix, .-_Z9CopyShape6Matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Reading past end of array\n"
.text
.globl _Z6SetVal6Matrixiif
.type _Z6SetVal6Matrixiif, @function
_Z6SetVal6Matrixiif:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movd %xmm0, %ebp
movl 36(%rsp), %eax
imull %eax, %esi
leal (%rsi,%rdi), %ebx
imull 32(%rsp), %eax
cmpl %eax, %ebx
jg .L7
.L5:
movslq %ebx, %rbx
movq 48(%rsp), %rax
movl %ebp, (%rax,%rbx,4)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.cfi_endproc
.LFE2059:
.size _Z6SetVal6Matrixiif, .-_Z6SetVal6Matrixiif
.globl _Z6GetVal6Matrixii
.type _Z6GetVal6Matrixii, @function
_Z6GetVal6Matrixii:
.LFB2060:
.cfi_startproc
endbr64
imull 12(%rsp), %esi
addl %edi, %esi
movslq %esi, %rsi
movq 24(%rsp), %rax
movss (%rax,%rsi,4), %xmm0
ret
.cfi_endproc
.LFE2060:
.size _Z6GetVal6Matrixii, .-_Z6GetVal6Matrixii
.globl _Z10InitMatrix6Matrix
.type _Z10InitMatrix6Matrix, @function
_Z10InitMatrix6Matrix:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl 48(%rsp), %r13d
movl 52(%rsp), %ebp
movl $0, %r12d
testl %r13d, %r13d
jg .L10
.L9:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call rand@PLT
movl %r13d, 48(%rsp)
movl %ebp, 52(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
subq $32, %rsp
.cfi_def_cfa_offset 80
movdqu 80(%rsp), %xmm1
movups %xmm1, (%rsp)
movq 96(%rsp), %rax
movq %rax, 16(%rsp)
movl %r12d, %esi
movl %ebx, %edi
call _Z6SetVal6Matrixiif
addl $1, %ebx
addq $32, %rsp
.cfi_def_cfa_offset 48
cmpl %ebx, %ebp
jne .L12
.L13:
addl $1, %r12d
cmpl %r13d, %r12d
je .L9
.L10:
movl $0, %ebx
testl %ebp, %ebp
jg .L12
jmp .L13
.cfi_endproc
.LFE2061:
.size _Z10InitMatrix6Matrix, .-_Z10InitMatrix6Matrix
.globl _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
.type _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_, @function
_Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_:
.LFB2087:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8MatMul_k6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_, .-_Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
.globl _Z8MatMul_k6MatrixS_S_
.type _Z8MatMul_k6MatrixS_S_, @function
_Z8MatMul_k6MatrixS_S_:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rsi
leaq 16(%rsp), %rdi
call _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z8MatMul_k6MatrixS_S_, .-_Z8MatMul_k6MatrixS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Inner matrix dimensions must be equal!"
.section .rodata.str1.1
.LC4:
.string "Cuda Error: malloc A: %s\n"
.LC5:
.string "Cuda Error: cpy A: %s\n"
.LC6:
.string "Cuda Error: malloc B: %s\n"
.LC7:
.string "Cuda Error: cpy B: %s\n"
.LC8:
.string "Cuda Error: malloc C: %s\n"
.LC9:
.string "Cuda Error: cpy C: %s\n"
.LC10:
.string "Run Cuda Code: %s\n"
.LC11:
.string "Get Result: %s\n"
.text
.globl _Z6MatMul6MatrixS_
.type _Z6MatMul6MatrixS_, @function
_Z6MatMul6MatrixS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $248, %rsp
.cfi_def_cfa_offset 304
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
movl 304(%rsp), %r14d
movl 308(%rsp), %r13d
movl %r14d, 4(%rdi)
movl 332(%rsp), %r15d
movl %r15d, (%rdi)
movl %r15d, %ebp
imull %r14d, %ebp
movslq %ebp, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, 16(%rbx)
movl 328(%rsp), %r12d
cmpl %r13d, %r12d
je .L29
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $0, 16(%rbx)
.L28:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L34
movq %rbx, %rax
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %r14d, 48(%rsp)
movl %r13d, 52(%rsp)
imull %r14d, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r13, %rdx
movq 320(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 80(%rsp)
movl %r15d, 84(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 96(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %r12, %rdx
movq 344(%rsp), %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, 112(%rsp)
movl %r14d, 116(%rsp)
leaq 128(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq 128(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 116(%rsp), %edx
shrl $4, %edx
movl 112(%rsp), %eax
shrl $4, %eax
movl %edx, 36(%rsp)
movl %eax, 40(%rsp)
movl $16, 24(%rsp)
movl $16, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L31:
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbp, %rdx
movq 128(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 128(%rsp), %rdi
call cudaFree@PLT
jmp .L28
.L35:
movdqa 48(%rsp), %xmm0
movaps %xmm0, 144(%rsp)
movq 64(%rsp), %rax
movq %rax, 160(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 176(%rsp)
movq 96(%rsp), %rax
movq %rax, 192(%rsp)
movdqa 112(%rsp), %xmm2
movaps %xmm2, 208(%rsp)
movq 128(%rsp), %rax
movq %rax, 224(%rsp)
leaq 208(%rsp), %rdx
leaq 176(%rsp), %rsi
leaq 144(%rsp), %rdi
call _Z36__device_stub__Z8MatMul_k6MatrixS_S_RK6MatrixS1_RS_
jmp .L31
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6MatMul6MatrixS_, .-_Z6MatMul6MatrixS_
.section .rodata.str1.8
.align 8
.LC12:
.string "********Entering Matrix Mul*****\n"
.section .rodata.str1.1
.LC14:
.string "Time %d: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $5000, %r14d
movl $1, %ebx
leaq 80(%rsp), %rax
movq %rax, 8(%rsp)
.L37:
imull $3500, %ebx, %r13d
movl %r14d, %edi
imull %r13d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, 16(%rsp)
movl %r13d, 20(%rsp)
movq %rax, 32(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 208
movdqa 48(%rsp), %xmm1
movups %xmm1, (%rsp)
movq %rax, 16(%rsp)
call _Z10InitMatrix6Matrix
imull $7500, %ebx, %r15d
addq $32, %rsp
.cfi_def_cfa_offset 176
movl %r13d, %edi
imull %r15d, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
movl %r13d, 48(%rsp)
movl %r15d, 52(%rsp)
movq %rax, 64(%rsp)
subq $32, %rsp
.cfi_def_cfa_offset 208
movdqa 80(%rsp), %xmm2
movups %xmm2, (%rsp)
movq %rax, 16(%rsp)
call _Z10InitMatrix6Matrix
addq $32, %rsp
.cfi_def_cfa_offset 176
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r13
subq $48, %rsp
.cfi_def_cfa_offset 224
movdqa 96(%rsp), %xmm3
movups %xmm3, 24(%rsp)
movq 112(%rsp), %rax
movq %rax, 40(%rsp)
movdqa 64(%rsp), %xmm4
movups %xmm4, (%rsp)
movq 80(%rsp), %rax
movq %rax, 16(%rsp)
movq 56(%rsp), %rdi
call _Z6MatMul6MatrixS_
addq $48, %rsp
.cfi_def_cfa_offset 176
call clock@PLT
subq %r13, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 96(%rsp), %rdi
call free@PLT
addl $1, %ebx
addl $5000, %r14d
cmpl $4, %ebx
jne .L37
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z8MatMul_k6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8MatMul_k6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1101004800
.align 4
.LC2:
.long 805306368
.align 4
.LC13:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMulLocal.hip"
.globl _Z9CopyShape6Matrix # -- Begin function _Z9CopyShape6Matrix
.p2align 4, 0x90
.type _Z9CopyShape6Matrix,@function
_Z9CopyShape6Matrix: # @_Z9CopyShape6Matrix
.cfi_startproc
# %bb.0:
movq %rdi, %rax
movl 8(%rsp), %ecx
movl %ecx, (%rdi)
movl 12(%rsp), %ecx
movl %ecx, 4(%rdi)
retq
.Lfunc_end0:
.size _Z9CopyShape6Matrix, .Lfunc_end0-_Z9CopyShape6Matrix
.cfi_endproc
# -- End function
.globl _Z23__device_stub__MatMul_k6MatrixS_S_ # -- Begin function _Z23__device_stub__MatMul_k6MatrixS_S_
.p2align 4, 0x90
.type _Z23__device_stub__MatMul_k6MatrixS_S_,@function
_Z23__device_stub__MatMul_k6MatrixS_S_: # @_Z23__device_stub__MatMul_k6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 104(%rsp), %rax
movq %rax, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8MatMul_k6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z23__device_stub__MatMul_k6MatrixS_S_, .Lfunc_end1-_Z23__device_stub__MatMul_k6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_ # -- Begin function _Z6MatMul6MatrixS_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_,@function
_Z6MatMul6MatrixS_: # @_Z6MatMul6MatrixS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl 304(%rsp), %r13d
movl %r13d, 4(%rdi)
movl 332(%rsp), %r15d
movl %r15d, (%rdi)
movl %r15d, %eax
imull %r13d, %eax
movslq %eax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, 16(%rbx)
movl 308(%rsp), %ecx
movl 328(%rsp), %ebp
cmpl %ebp, %ecx
jne .LBB2_1
# %bb.2:
movl %r13d, 48(%rsp)
movl %ecx, 52(%rsp)
imull %r13d, %ecx
movslq %ecx, %r12
shlq $2, %r12
leaq 64(%rsp), %rdi
movq %rax, 72(%rsp) # 8-byte Spill
movq %r12, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rdi
leaq 304(%rsp), %rax
movq 16(%rax), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %ebp, 24(%rsp)
movl %r15d, 28(%rsp)
imull %r15d, %ebp
movslq %ebp, %r12
shlq $2, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
leaq 328(%rsp), %rax
movq 16(%rax), %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %ebp
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl %r15d, (%rsp)
movl %r13d, 4(%rsp)
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %ebp, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl (%rsp), %edi
movl 4(%rsp), %eax
shrl $4, %eax
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movups 48(%rsp), %xmm0
movaps %xmm0, 160(%rsp)
movq 40(%rsp), %rax
movq %rax, 208(%rsp)
movups 24(%rsp), %xmm0
movaps %xmm0, 192(%rsp)
movq 16(%rsp), %rax
movq %rax, 240(%rsp)
movups (%rsp), %xmm0
movaps %xmm0, 224(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 224(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8MatMul_k6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 16(%rbx), %rdi
movq 16(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movq 64(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
jmp .LBB2_5
.LBB2_1:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq $0, 16(%rbx)
.LBB2_5:
movq %rbx, %rax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z6MatMul6MatrixS_, .Lfunc_end2-_Z6MatMul6MatrixS_
.cfi_endproc
# -- End function
.globl _Z6SetVal6Matrixiif # -- Begin function _Z6SetVal6Matrixiif
.p2align 4, 0x90
.type _Z6SetVal6Matrixiif,@function
_Z6SetVal6Matrixiif: # @_Z6SetVal6Matrixiif
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
leaq 32(%rsp), %r14
movl 36(%rsp), %eax
imull %eax, %ebx
addl %edi, %ebx
imull 32(%rsp), %eax
cmpl %eax, %ebx
jle .LBB3_2
# %bb.1:
movl $.Lstr, %edi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
.LBB3_2:
movq 16(%r14), %rax
movslq %ebx, %rcx
movss %xmm0, (%rax,%rcx,4)
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z6SetVal6Matrixiif, .Lfunc_end3-_Z6SetVal6Matrixiif
.cfi_endproc
# -- End function
.globl _Z6GetVal6Matrixii # -- Begin function _Z6GetVal6Matrixii
.p2align 4, 0x90
.type _Z6GetVal6Matrixii,@function
_Z6GetVal6Matrixii: # @_Z6GetVal6Matrixii
.cfi_startproc
# %bb.0:
movq 24(%rsp), %rax
imull 12(%rsp), %esi
addl %edi, %esi
movslq %esi, %rcx
movss (%rax,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
retq
.Lfunc_end4:
.size _Z6GetVal6Matrixii, .Lfunc_end4-_Z6GetVal6Matrixii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10InitMatrix6Matrix
.LCPI5_0:
.long 0x41a00000 # float 20
.LCPI5_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10InitMatrix6Matrix
.p2align 4, 0x90
.type _Z10InitMatrix6Matrix,@function
_Z10InitMatrix6Matrix: # @_Z10InitMatrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl 80(%rsp), %eax
movq %rax, 8(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader.lr.ph
leaq 80(%rsp), %rax
movl 4(%rax), %r14d
movq 16(%rax), %rax
movq %rax, 16(%rsp) # 8-byte Spill
movl %r14d, %ebp
imull 8(%rsp), %ebp # 4-byte Folded Reload
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_7: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incq %r13
addq %r14, %r12
cmpq 8(%rsp), %r13 # 8-byte Folded Reload
je .LBB5_8
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %r14d, %r14d
jle .LBB5_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %r12d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %ebx, %ebx
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_6: # %_Z6SetVal6Matrixiif.exit
# in Loop: Header=BB5_4 Depth=2
movss %xmm0, (%r15,%rbx,4)
incq %rbx
cmpq %rbx, %r14
je .LBB5_7
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI5_0(%rip), %xmm0
mulss .LCPI5_1(%rip), %xmm0
leal (%r12,%rbx), %eax
cmpl %eax, %ebp
jge .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
movl $.Lstr, %edi
movss %xmm0, 4(%rsp) # 4-byte Spill
callq puts@PLT
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB5_6
.LBB5_8: # %._crit_edge12
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z10InitMatrix6Matrix, .Lfunc_end5-_Z10InitMatrix6Matrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x41a00000 # float 20
.LCPI6_1:
.long 0x30000000 # float 4.65661287E-10
.LCPI6_2:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %ebx
movl $3500, %r14d # imm = 0xDAC
movl $7500, %eax # imm = 0x1D4C
jmp .LBB6_1
.p2align 4, 0x90
.LBB6_13: # %_Z10InitMatrix6Matrix.exit46
# in Loop: Header=BB6_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
callq clock
movq %rax, %rbx
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, 112(%rsp)
movq 56(%rsp), %rax # 8-byte Reload
movl %eax, 116(%rsp)
movq %r15, 128(%rsp)
movl %eax, 136(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
movl %eax, 140(%rsp)
movq %r12, 152(%rsp)
movq %r12, 40(%rsp)
movups 136(%rsp), %xmm0
movups %xmm0, 24(%rsp)
movq 128(%rsp), %rax
movq %rax, 16(%rsp)
movups 112(%rsp), %xmm0
movups %xmm0, (%rsp)
leaq 160(%rsp), %rdi
callq _Z6MatMul6MatrixS_
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI6_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movq 72(%rsp), %rbx # 8-byte Reload
movl %ebx, %esi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 176(%rsp), %rdi
callq free
movq 64(%rsp), %rax # 8-byte Reload
incq %rbx
movq 88(%rsp), %r14 # 8-byte Reload
addq $3500, %r14 # imm = 0xDAC
addq $7500, %rax # imm = 0x1D4C
cmpq $4, %rbx
je .LBB6_14
.LBB6_1: # %.preheader.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB6_2 Depth 2
# Child Loop BB6_3 Depth 3
# Child Loop BB6_8 Depth 2
# Child Loop BB6_9 Depth 3
movq %rax, 64(%rsp) # 8-byte Spill
imulq $5000, %rbx, %rcx # imm = 0x1388
movq %rbx, 72(%rsp) # 8-byte Spill
imulq $3500, %rbx, %rbx # imm = 0xDAC
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rcx, 80(%rsp) # 8-byte Spill
imulq %rcx, %rbx
leal (,%rbx,4), %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
xorl %r13d, %r13d
movq %r14, 88(%rsp) # 8-byte Spill
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_6: # %._crit_edge.i
# in Loop: Header=BB6_2 Depth=2
incq %r13
movq 88(%rsp), %r14 # 8-byte Reload
addq %r14, %r12
cmpq 80(%rsp), %r13 # 8-byte Folded Reload
je .LBB6_7
.LBB6_2: # %.preheader.i
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_3 Depth 3
movq %r12, %rbp
andq $-4, %rbp
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_5: # %_Z6SetVal6Matrixiif.exit.i
# in Loop: Header=BB6_3 Depth=3
movss %xmm0, (%r15,%rbp,4)
incq %rbp
decq %r14
je .LBB6_6
.LBB6_3: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_2 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI6_0(%rip), %xmm0
mulss .LCPI6_1(%rip), %xmm0
cmpq %rbx, %rbp
jbe .LBB6_5
# %bb.4: # in Loop: Header=BB6_3 Depth=3
movl $.Lstr, %edi
movss %xmm0, 52(%rsp) # 4-byte Spill
callq puts@PLT
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # %_Z10InitMatrix6Matrix.exit
# in Loop: Header=BB6_1 Depth=1
imulq $7500, 72(%rsp), %rbx # 8-byte Folded Reload
# imm = 0x1D4C
movq %rbx, 96(%rsp) # 8-byte Spill
imulq 56(%rsp), %rbx # 8-byte Folded Reload
leal (,%rbx,4), %edi
andl $-64, %edi
callq malloc
movq %rax, %r12
xorl %r13d, %r13d
xorl %ebp, %ebp
movq 64(%rsp), %r14 # 8-byte Reload
jmp .LBB6_8
.p2align 4, 0x90
.LBB6_12: # %._crit_edge.i36
# in Loop: Header=BB6_8 Depth=2
incq %rbp
movq 64(%rsp), %r14 # 8-byte Reload
movq 104(%rsp), %r13 # 8-byte Reload
addq %r14, %r13
cmpq 56(%rsp), %rbp # 8-byte Folded Reload
je .LBB6_13
.LBB6_8: # %.preheader.i34
# Parent Loop BB6_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_9 Depth 3
movq %r13, 104(%rsp) # 8-byte Spill
andq $-4, %r13
jmp .LBB6_9
.p2align 4, 0x90
.LBB6_11: # %_Z6SetVal6Matrixiif.exit.i42
# in Loop: Header=BB6_9 Depth=3
movss %xmm0, (%r12,%r13,4)
incq %r13
decq %r14
je .LBB6_12
.LBB6_9: # Parent Loop BB6_1 Depth=1
# Parent Loop BB6_8 Depth=2
# => This Inner Loop Header: Depth=3
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI6_0(%rip), %xmm0
mulss .LCPI6_1(%rip), %xmm0
cmpq %rbx, %r13
jbe .LBB6_11
# %bb.10: # in Loop: Header=BB6_9 Depth=3
movl $.Lstr, %edi
movss %xmm0, 52(%rsp) # 4-byte Spill
callq puts@PLT
movss 52(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB6_11
.LBB6_14:
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8MatMul_k6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8MatMul_k6MatrixS_S_,@object # @_Z8MatMul_k6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z8MatMul_k6MatrixS_S_
.p2align 3, 0x0
_Z8MatMul_k6MatrixS_S_:
.quad _Z23__device_stub__MatMul_k6MatrixS_S_
.size _Z8MatMul_k6MatrixS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Inner matrix dimensions must be equal!"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Cuda Error: malloc A: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Cuda Error: cpy A: %s\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda Error: malloc B: %s\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Cuda Error: cpy B: %s\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Cuda Error: malloc C: %s\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Cuda Error: cpy C: %s\n"
.size .L.str.6, 23
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Run Cuda Code: %s\n"
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Get Result: %s\n"
.size .L.str.8, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Time %d: %f\n"
.size .L.str.11, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8MatMul_k6MatrixS_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Reading past end of array"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "********Entering Matrix Mul*****"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__MatMul_k6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8MatMul_k6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} | code for sm_80
Function : _Z10smoothGrayPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x10, URZ ; /* 0x0000001004047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR5, UR7, UR6, URZ ; /* 0x00000006070572a4 */
/* 0x000fe2000f8e023f */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002600 */
/*0080*/ IMAD R0, R0, 0x400, R5 ; /* 0x0000040000007824 */
/* 0x001fc800078e0205 */
/*0090*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x002fca000f8e0200 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f45070 */
/*00e0*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*00f0*/ BSSY B1, 0xf80 ; /* 0x00000e8000017945 */
/* 0x000fe20003800000 */
/*0100*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0180*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01a0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*01c0*/ IMAD R5, R5, c[0x0][0x170], R0 ; /* 0x00005c0005057a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R5, R5, -c[0x0][0x170], RZ ; /* 0x80005c0005050a10 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03aa12 */
/* 0x000fc800078e33ff */
/*0230*/ IADD3 R2, R3.reuse, 0x2, RZ ; /* 0x0000000203027810 */
/* 0x040fe20007ffe0ff */
/*0240*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a03 */
/*0250*/ IADD3 R3, R3, -0x2, RZ ; /* 0xfffffffe03037810 */
/* 0x000fe40007ffe0ff */
/*0260*/ ISETP.GE.U32.AND P0, PT, R2.reuse, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x040fe20003f06070 */
/*0270*/ IMAD R4, R5, c[0x0][0x170], R0 ; /* 0x00005c0005047a24 */
/* 0x000fe200078e0200 */
/*0280*/ IMNMX R7, RZ, R3, !PT ; /* 0x00000003ff077217 */
/* 0x000fe40007800200 */
/*0290*/ SEL R2, R2, UR4, !P0 ; /* 0x0000000402027c07 */
/* 0x000fe4000c000000 */
/*02a0*/ IADD3 R5, R4, 0x2, RZ ; /* 0x0000000204057810 */
/* 0x000fc40007ffe0ff */
/*02b0*/ ISETP.GT.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fe40003f24270 */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R5.reuse, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x040fe40003f06070 */
/*02d0*/ IADD3 R4, R4, -0x2, RZ ; /* 0xfffffffe04047810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ SEL R5, R5, UR4, !P0 ; /* 0x0000000405057c07 */
/* 0x000fe2000c000000 */
/*02f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0300*/ IMNMX R4, RZ, R4, !PT ; /* 0x00000004ff047217 */
/* 0x000fca0007800200 */
/*0310*/ @P1 BRA 0xf70 ; /* 0x00000c5000001947 */
/* 0x000fea0003800000 */
/*0320*/ IMAD.IADD R3, R5, 0x1, -R4 ; /* 0x0000000105037824 */
/* 0x000fe200078e0a04 */
/*0330*/ IADD3 R10, -R4.reuse, 0x1, R5 ; /* 0x00000001040a7810 */
/* 0x040fe20007ffe105 */
/*0340*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0350*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe20007ffe0ff */
/*0360*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0370*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f26070 */
/*0380*/ IADD3 R8, R4.reuse, 0x2, RZ ; /* 0x0000000204087810 */
/* 0x040fe40007ffe0ff */
/*0390*/ IADD3 R9, R4, 0x3, RZ ; /* 0x0000000304097810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ LOP3.LUT R10, R10, 0x3, RZ, 0xc0, !PT ; /* 0x000000030a0a7812 */
/* 0x000fc400078ec0ff */
/*03b0*/ ISETP.GE.AND P0, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fe20003f06270 */
/*03c0*/ BSSY B0, 0xf40 ; /* 0x00000b7000007945 */
/* 0x000fd80003800000 */
/*03d0*/ @!P0 BRA 0xf30 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*03f0*/ BSSY B2, 0x5c0 ; /* 0x000001c000027945 */
/* 0x000fe20003800000 */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fd600078e0004 */
/*0410*/ @!P0 BRA 0x5b0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0420*/ IMAD R12, R7, c[0x0][0x170], R4 ; /* 0x00005c00070c7a24 */
/* 0x000fca00078e0204 */
/*0430*/ IADD3 R12, P0, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fca0007f1e0ff */
/*0440*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0d7624 */
/* 0x000fca00000e06ff */
/*0450*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1100 */
/*0460*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f05270 */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, R23 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0017 */
/*0480*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0006 */
/*04a0*/ IMAD.IADD R11, R11, 0x1, R12 ; /* 0x000000010b0b7824 */
/* 0x004fd000078e020c */
/*04b0*/ @!P0 BRA 0x5b0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*04c0*/ ISETP.NE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x000fe20003f05270 */
/*04d0*/ IMAD R12, R7, c[0x0][0x170], R6 ; /* 0x00005c00070c7a24 */
/* 0x000fca00078e0206 */
/*04e0*/ IADD3 R12, P2, R12, c[0x0][0x160], RZ ; /* 0x000058000c0c7a10 */
/* 0x000fca0007f5e0ff */
/*04f0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0d7624 */
/* 0x000fe400010e06ff */
/*0500*/ @P0 IMAD R14, R7, c[0x0][0x170], R8 ; /* 0x00005c00070e0a24 */
/* 0x000fc600078e0208 */
/*0510*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea4000c1e1100 */
/*0520*/ @P0 IADD3 R14, P3, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e0a10 */
/* 0x000fca0007f7e0ff */
/*0530*/ @P0 IMAD.X R15, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff0f0624 */
/* 0x000fca00018e06ff */
/*0540*/ @P0 LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e0981 */
/* 0x000ee2000c1e1100 */
/*0550*/ IADD3 R23, R3.reuse, 0x2, RZ ; /* 0x0000000203177810 */
/* 0x040fe20007ffe0ff */
/*0560*/ IMAD.MOV.U32 R16, RZ, RZ, R8 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0008 */
/*0570*/ @P0 IADD3 R23, R3, 0x3, RZ ; /* 0x0000000303170810 */
/* 0x000fe20007ffe0ff */
/*0580*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, R9 ; /* 0x000000ffff100224 */
/* 0x000fe400078e0009 */
/*0590*/ IMAD.IADD R11, R11, 0x1, R12 ; /* 0x000000010b0b7824 */
/* 0x004fc800078e020c */
/*05a0*/ @P0 IMAD.IADD R11, R11, 0x1, R14 ; /* 0x000000010b0b0824 */
/* 0x008fe400078e020e */
/*05b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*05c0*/ @!P1 BRA 0xf30 ; /* 0x0000096000009947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R26, R16, -0x1, RZ ; /* 0xffffffff101a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ IMAD R13, R7, c[0x0][0x170], R16 ; /* 0x00005c00070d7a24 */
/* 0x000fe200078e0210 */
/*05f0*/ BSSY B2, 0xb40 ; /* 0x0000054000027945 */
/* 0x000fe20003800000 */
/*0600*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0610*/ IMAD.IADD R3, R5, 0x1, -R26 ; /* 0x0000000105037824 */
/* 0x000fca00078e0a1a */
/*0620*/ ISETP.GT.AND P2, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f44270 */
/*0630*/ IADD3 R3, R13, 0x3, RZ ; /* 0x000000030d037810 */
/* 0x000fd60007ffe0ff */
/*0640*/ @!P2 BRA 0xb30 ; /* 0x000004e00000a947 */
/* 0x000fea0003800000 */
/*0650*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0660*/ IADD3 R12, R5, -0xc, RZ ; /* 0xfffffff4050c7810 */
/* 0x000fe40007ffe0ff */
/*0670*/ IADD3 R18, R3, -0x2, RZ ; /* 0xfffffffe03127810 */
/* 0x000fe40007ffe0ff */
/*0680*/ IADD3 R20, P2, R13, c[0x0][0x160], RZ ; /* 0x000058000d147a10 */
/* 0x000fe40007f5e0ff */
/*0690*/ IADD3 R18, P3, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe40007f7e0ff */
/*06a0*/ IADD3 R28, R3.reuse, -0x1, RZ ; /* 0xffffffff031c7810 */
/* 0x040fe20007ffe0ff */
/*06b0*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff157624 */
/* 0x000fe400010e06ff */
/*06c0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff137624 */
/* 0x000fe200018e06ff */
/*06d0*/ IADD3 R16, P3, R3, c[0x0][0x160], RZ ; /* 0x0000580003107a10 */
/* 0x000fc40007f7e0ff */
/*06e0*/ IADD3 R24, R13, 0x4, RZ ; /* 0x000000040d187810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0000a2000c1e1100 */
/*0700*/ IADD3 R14, R3, 0x2, RZ ; /* 0x00000002030e7810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R28, P2, R28, c[0x0][0x160], RZ ; /* 0x000058001c1c7a10 */
/* 0x000fe20007f5e0ff */
/*0720*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff117624 */
/* 0x000fe200018e06ff */
/*0730*/ IADD3 R24, P3, R24, c[0x0][0x160], RZ ; /* 0x0000580018187a10 */
/* 0x000fe20007f7e0ff */
/*0740*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x0002a2000c1e1100 */
/*0750*/ IADD3 R14, P4, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e7a10 */
/* 0x000fe20007f9e0ff */
/*0760*/ IMAD.X R29, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff1d7624 */
/* 0x000fe400010e06ff */
/*0770*/ IMAD.X R25, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff197624 */
/* 0x000fe200018e06ff */
/*0780*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000722000c1e1100 */
/*0790*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P4 ; /* 0x00005900ff0f7624 */
/* 0x000fc600020e06ff */
/*07a0*/ LDG.E.U8 R21, [R28.64] ; /* 0x000000041c157981 */
/* 0x001128000c1e1100 */
/*07b0*/ LDG.E.U8 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000b28000c1e1100 */
/*07c0*/ LDG.E.U8 R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x008722000c1e1100 */
/*07d0*/ IADD3 R22, R3.reuse, 0x3, RZ ; /* 0x0000000303167810 */
/* 0x040fe40007ffe0ff */
/*07e0*/ IADD3 R18, R3, 0x4, RZ ; /* 0x0000000403127810 */
/* 0x002fc40007ffe0ff */
/*07f0*/ IADD3 R28, P2, R22, c[0x0][0x160], RZ ; /* 0x00005800161c7a10 */
/* 0x001fe40007f5e0ff */
/*0800*/ IADD3 R22, R13, 0x8, RZ ; /* 0x000000080d167810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R27, R3, 0x6, RZ ; /* 0x00000006031b7810 */
/* 0x000fe20007ffe0ff */
/*0820*/ IMAD.X R29, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff1d7624 */
/* 0x000fe200010e06ff */
/*0830*/ IADD3 R14, P2, R22, c[0x0][0x160], RZ ; /* 0x00005800160e7a10 */
/* 0x008fe40007f5e0ff */
/*0840*/ IADD3 R18, P3, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe40007f7e0ff */
/*0850*/ LDG.E.U8 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x0000e2000c1e1100 */
/*0860*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0f7624 */
/* 0x000fca00010e06ff */
/*0870*/ LDG.E.U8 R25, [R14.64] ; /* 0x000000040e197981 */
/* 0x020362000c1e1100 */
/*0880*/ IADD3 R28, P2, R27, c[0x0][0x160], RZ ; /* 0x000058001b1c7a10 */
/* 0x001fe40007f5e0ff */
/*0890*/ IADD3 R14, R3, 0x7, RZ ; /* 0x00000007030e7810 */
/* 0x002fc60007ffe0ff */
/*08a0*/ IMAD.X R29, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff1d7624 */
/* 0x000fe200010e06ff */
/*08b0*/ IADD3 R27, R13, 0xc, RZ ; /* 0x0000000c0d1b7810 */
/* 0x000fc80007ffe0ff */
/*08c0*/ LDG.E.U8 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000162000c1e1100 */
/*08d0*/ IADD3 R20, R19, R11, R20 ; /* 0x0000000b13147210 */
/* 0x004fe20007ffe014 */
/*08e0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff137624 */
/* 0x000fca00018e06ff */
/*08f0*/ LDG.E.U8 R11, [R18.64] ; /* 0x00000004120b7981 */
/* 0x0002e2000c1e1100 */
/*0900*/ IADD3 R20, R16, R20, R21 ; /* 0x0000001410147210 */
/* 0x010fe40007ffe015 */
/*0910*/ IADD3 R21, R3, 0x8, RZ ; /* 0x0000000803157810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R16, P3, R14, c[0x0][0x160], RZ ; /* 0x000058000e107a10 */
/* 0x000fe40007f7e0ff */
/*0930*/ IADD3 R24, R17, R20, R24 ; /* 0x0000001411187210 */
/* 0x000fe40007ffe018 */
/*0940*/ IADD3 R20, P2, R21, c[0x0][0x160], RZ ; /* 0x0000580015147a10 */
/* 0x000fe20007f5e0ff */
/*0950*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff117624 */
/* 0x000fe200018e06ff */
/*0960*/ IADD3 R14, R3, 0xa, RZ ; /* 0x0000000a030e7810 */
/* 0x000fc40007ffe0ff */
/*0970*/ IADD3 R18, P3, R27, c[0x0][0x160], RZ ; /* 0x000058001b127a10 */
/* 0x002fe20007f7e0ff */
/*0980*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff157624 */
/* 0x000fe200010e06ff */
/*0990*/ IADD3 R14, P2, R14, c[0x0][0x160], RZ ; /* 0x000058000e0e7a10 */
/* 0x000fe20007f5e0ff */
/*09a0*/ LDG.E.U8 R27, [R16.64] ; /* 0x00000004101b7981 */
/* 0x0002a8000c1e1100 */
/*09b0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0f7624 */
/* 0x000fe200010e06ff */
/*09c0*/ LDG.E.U8 R29, [R20.64] ; /* 0x00000004141d7981 */
/* 0x0010a2000c1e1100 */
/*09d0*/ IADD3 R16, R3, 0xb, RZ ; /* 0x0000000b03107810 */
/* 0x002fe20007ffe0ff */
/*09e0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff137624 */
/* 0x000fc600018e06ff */
/*09f0*/ LDG.E.U8 R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f22000c1e1100 */
/*0a00*/ IADD3 R16, P2, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe40007f5e0ff */
/*0a10*/ IADD3 R20, R3, 0xc, RZ ; /* 0x0000000c03147810 */
/* 0x001fe20007ffe0ff */
/*0a20*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f24000c1e1100 */
/*0a30*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fe200010e06ff */
/*0a40*/ IADD3 R20, P2, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fc80007f5e0ff */
/*0a50*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f22000c1e1100 */
/*0a60*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff157624 */
/* 0x000fca00010e06ff */
/*0a70*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1100 */
/*0a80*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.GE.AND P2, PT, R26, R12, PT ; /* 0x0000000c1a00720c */
/* 0x000fe40003f46270 */
/*0aa0*/ IADD3 R23, R23, 0x10, RZ ; /* 0x0000001017177810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0ac0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*0ad0*/ IADD3 R11, R11, R24, R22 ; /* 0x000000180b0b7210 */
/* 0x008fc80007ffe016 */
/*0ae0*/ IADD3 R28, R28, R11, R25 ; /* 0x0000000b1c1c7210 */
/* 0x020fc80007ffe019 */
/*0af0*/ IADD3 R27, R29, R28, R27 ; /* 0x0000001c1d1b7210 */
/* 0x004fc80007ffe01b */
/*0b00*/ IADD3 R15, R15, R27, R18 ; /* 0x0000001b0f0f7210 */
/* 0x010fc80007ffe012 */
/*0b10*/ IADD3 R11, R20, R15, R16 ; /* 0x0000000f140b7210 */
/* 0x000fe20007ffe010 */
/*0b20*/ @!P2 BRA 0x670 ; /* 0xfffffb400000a947 */
/* 0x000fea000383ffff */
/*0b30*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b40*/ IMAD.IADD R12, R5, 0x1, -R26 ; /* 0x00000001050c7824 */
/* 0x000fe200078e0a1a */
/*0b50*/ BSSY B2, 0xe00 ; /* 0x000002a000027945 */
/* 0x000fe80003800000 */
/*0b60*/ ISETP.GT.AND P2, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f44270 */
/*0b70*/ @!P2 BRA 0xdf0 ; /* 0x000002700000a947 */
/* 0x000fea0003800000 */
/*0b80*/ IADD3 R16, P0, R13, c[0x0][0x160], RZ ; /* 0x000058000d107a10 */
/* 0x000fe40007f1e0ff */
/*0b90*/ IADD3 R28, R3.reuse, -0x2, RZ ; /* 0xfffffffe031c7810 */
/* 0x040fe40007ffe0ff */
/*0ba0*/ IADD3 R14, P2, R3.reuse, c[0x0][0x160], RZ ; /* 0x00005800030e7a10 */
/* 0x040fe20007f5e0ff */
/*0bb0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff117624 */
/* 0x000fe200000e06ff */
/*0bc0*/ IADD3 R28, P0, R28, c[0x0][0x160], RZ ; /* 0x000058001c1c7a10 */
/* 0x000fe40007f1e0ff */
/*0bd0*/ IADD3 R24, R3, -0x1, RZ ; /* 0xffffffff03187810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff0f7624 */
/* 0x000fe200010e06ff */
/*0bf0*/ IADD3 R20, R13, 0x4, RZ ; /* 0x000000040d147810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ IMAD.X R29, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff1d7624 */
/* 0x000fe200000e06ff */
/*0c10*/ IADD3 R24, P0, R24, c[0x0][0x160], RZ ; /* 0x0000580018187a10 */
/* 0x000fe20007f1e0ff */
/*0c20*/ LDG.E.U8 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0000a2000c1e1100 */
/*0c30*/ IADD3 R18, R3, 0x2, RZ ; /* 0x0000000203127810 */
/* 0x000fc40007ffe0ff */
/*0c40*/ IADD3 R20, P2, R20, c[0x0][0x160], RZ ; /* 0x0000580014147a10 */
/* 0x000fe20007f5e0ff */
/*0c50*/ IMAD.X R25, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff197624 */
/* 0x000fe200000e06ff */
/*0c60*/ IADD3 R19, R3.reuse, 0x3, RZ ; /* 0x0000000303137810 */
/* 0x040fe20007ffe0ff */
/*0c70*/ LDG.E.U8 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1100 */
/*0c80*/ IADD3 R18, P0, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe40007f1e0ff */
/*0c90*/ IADD3 R17, R3, 0x4, RZ ; /* 0x0000000403117810 */
/* 0x001fe20007ffe0ff */
/*0ca0*/ LDG.E.U8 R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x0000e2000c1e1100 */
/*0cb0*/ IMAD.X R21, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff157624 */
/* 0x000fe200010e06ff */
/*0cc0*/ IADD3 R16, P2, R19, c[0x0][0x160], RZ ; /* 0x0000580013107a10 */
/* 0x000fe20007f5e0ff */
/*0cd0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x000fe200000e06ff */
/*0ce0*/ LDG.E.U8 R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ee8000c1e1100 */
/*0cf0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f22000c1e1100 */
/*0d00*/ IADD3 R14, P3, R17, c[0x0][0x160], RZ ; /* 0x00005800110e7a10 */
/* 0x001fe20007f7e0ff */
/*0d10*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fc400010e06ff */
/*0d20*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f24000c1e1100 */
/*0d30*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff0f7624 */
/* 0x000fe400018e06ff */
/*0d40*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f68000c1e1100 */
/*0d50*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f62000c1e1100 */
/*0d60*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0d70*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fc40007ffe0ff */
/*0d80*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0da0*/ IADD3 R13, R13, 0x8, RZ ; /* 0x000000080d0d7810 */
/* 0x000fe40007ffe0ff */
/*0db0*/ IADD3 R12, R28, R11, R12 ; /* 0x0000000b1c0c7210 */
/* 0x004fc80007ffe00c */
/*0dc0*/ IADD3 R25, R22, R12, R25 ; /* 0x0000000c16197210 */
/* 0x008fc80007ffe019 */
/*0dd0*/ IADD3 R25, R18, R25, R20 ; /* 0x0000001912197210 */
/* 0x010fc80007ffe014 */
/*0de0*/ IADD3 R11, R14, R25, R16 ; /* 0x000000190e0b7210 */
/* 0x020fe40007ffe010 */
/*0df0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e00*/ ISETP.LT.OR P0, PT, R26, R5, P0 ; /* 0x000000051a00720c */
/* 0x000fda0000701670 */
/*0e10*/ @!P0 BRA 0xf30 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0e20*/ IADD3 R18, R3, -0x2, RZ ; /* 0xfffffffe03127810 */
/* 0x000fe40007ffe0ff */
/*0e30*/ IADD3 R14, P0, R13, c[0x0][0x160], RZ ; /* 0x000058000d0e7a10 */
/* 0x000fe40007f1e0ff */
/*0e40*/ IADD3 R16, R3.reuse, -0x1, RZ ; /* 0xffffffff03107810 */
/* 0x040fe40007ffe0ff */
/*0e50*/ IADD3 R18, P2, R18, c[0x0][0x160], RZ ; /* 0x0000580012127a10 */
/* 0x000fe20007f5e0ff */
/*0e60*/ IMAD.X R15, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff0f7624 */
/* 0x000fe200000e06ff */
/*0e70*/ IADD3 R12, P3, R3, c[0x0][0x160], RZ ; /* 0x00005800030c7a10 */
/* 0x000fe40007f7e0ff */
/*0e80*/ IADD3 R16, P0, R16, c[0x0][0x160], RZ ; /* 0x0000580010107a10 */
/* 0x000fe20007f1e0ff */
/*0e90*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff137624 */
/* 0x000fe200010e06ff */
/*0ea0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1100 */
/*0eb0*/ IMAD.X R13, RZ, RZ, c[0x0][0x164], P3 ; /* 0x00005900ff0d7624 */
/* 0x000fc400018e06ff */
/*0ec0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff117624 */
/* 0x000fe200000e06ff */
/*0ed0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1100 */
/*0ee0*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee8000c1e1100 */
/*0ef0*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1100 */
/*0f00*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fc40007ffe0ff */
/*0f10*/ IADD3 R11, R18, R11, R14 ; /* 0x0000000b120b7210 */
/* 0x004fc80007ffe00e */
/*0f20*/ IADD3 R11, R12, R11, R16 ; /* 0x0000000b0c0b7210 */
/* 0x008fe40007ffe010 */
/*0f30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f40*/ ISETP.GE.AND P0, PT, R7.reuse, R2, PT ; /* 0x000000020700720c */
/* 0x040fe40003f06270 */
/*0f50*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fd60007ffe0ff */
/*0f60*/ @!P0 BRA 0x3b0 ; /* 0xfffff44000008947 */
/* 0x000fea000383ffff */
/*0f70*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0f80*/ IABS R5, R23 ; /* 0x0000001700057213 */
/* 0x000fe40000000000 */
/*0f90*/ IABS R8, R11 ; /* 0x0000000b00087213 */
/* 0x000fe40000000000 */
/*0fa0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e220000209400 */
/*0fb0*/ IABS R9, R23.reuse ; /* 0x0000001700097213 */
/* 0x080fe40000000000 */
/*0fc0*/ LOP3.LUT R11, R11, R23, RZ, 0x3c, !PT ; /* 0x000000170b0b7212 */
/* 0x000fc800078e3cff */
/*0fd0*/ ISETP.GE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f46270 */
/*0fe0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0ff0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*1000*/ IMAD.MOV R4, RZ, RZ, -R9 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0a09 */
/*1010*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*1020*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*1030*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*1040*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe400078e02ff */
/*1050*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*1060*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*1070*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*1080*/ IMAD R2, R3, R4, R6 ; /* 0x0000000403027224 */
/* 0x000fca00078e0206 */
/*1090*/ ISETP.GT.U32.AND P1, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fda0003f24070 */
/*10a0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R5 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a05 */
/*10b0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*10c0*/ ISETP.NE.AND P1, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe40003f25270 */
/*10d0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f06070 */
/*10e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*10f0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc60007f1e0ff */
/*1100*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0003 */
/*1110*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fe400000e06ff */
/*1120*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fe200078e0a05 */
/*1130*/ @!P1 LOP3.LUT R5, RZ, R23, RZ, 0x33, !PT ; /* 0x00000017ff059212 */
/* 0x000fca00078e33ff */
/*1140*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101104 */
/*1150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1160*/ BRA 0x1160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} | .file "tmpxft_000520d5_00000000-6_smoothGray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
.type _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj, @function
_Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10smoothGrayPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj, .-_Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
.globl _Z10smoothGrayPhS_jj
.type _Z10smoothGrayPhS_jj, @function
_Z10smoothGrayPhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10smoothGrayPhS_jj, .-_Z10smoothGrayPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10smoothGrayPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10smoothGrayPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10smoothGrayPhS_jj
.globl _Z10smoothGrayPhS_jj
.p2align 8
.type _Z10smoothGrayPhS_jj,@function
_Z10smoothGrayPhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_lshl_b32 s3, s14, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b32 s2, s15, 16
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_or_b32_e32 v0, s2, v0
s_mul_i32 s2, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s2, 0, s4
s_mov_b32 s5, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s2, v1
s_add_i32 s2, s4, -1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s4
v_add_nc_u32_e32 v3, 1, v1
v_sub_nc_u32_e32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v4, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v1, v3, vcc_lo
v_add_nc_u32_e32 v4, 2, v3
v_add_nc_u32_e32 v1, -2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s4, v4
v_max_i32_e32 v2, 0, v1
v_cndmask_b32_e32 v1, s2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 v2, v1
s_cbranch_execz .LBB0_9
v_mul_lo_u32 v3, v3, s4
s_load_b64 s[6:7], s[0:1], 0x0
v_mul_lo_u32 v7, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_add_nc_u32_e32 v4, -2, v3
v_add_nc_u32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_gt_u32_e32 vcc_lo, s4, v3
v_dual_cndmask_b32 v6, s2, v3 :: v_dual_mov_b32 v3, 0
v_max_i32_e32 v5, 0, v4
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, v5, v6
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v8, 1, v2
v_cmp_ge_i32_e64 s2, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v2, v8 :: v_dual_add_nc_u32 v7, s4, v7
s_or_b32 s5, s2, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB0_8
.LBB0_4:
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v8, v5
s_mov_b32 s9, 0
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v10, 1, v8
v_add_nc_u32_e32 v9, v7, v8
v_cmp_ge_i32_e64 s2, v8, v6
v_add_nc_u32_e32 v4, 1, v4
v_mov_b32_e32 v8, v10
s_waitcnt lgkmcnt(0)
global_load_u8 v9, v9, s[6:7]
s_or_b32 s9, s2, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v3, v9
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s9
s_branch .LBB0_3
.LBB0_8:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s5
v_ashrrev_i32_e32 v1, 31, v4
v_ashrrev_i32_e32 v6, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v4, v1
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v1
v_xor_b32_e32 v1, v6, v1
v_xor_b32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v4, v2
v_sub_nc_u32_e32 v5, 0, v2
v_rcp_iflag_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_mul_lo_u32 v5, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_sub_nc_u32_e32 v7, v3, v2
v_cmp_ge_u32_e32 vcc_lo, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v4, v4, v5 :: v_dual_cndmask_b32 v3, v3, v7
v_add_nc_u32_e32 v5, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_u32_e32 vcc_lo, v3, v2
v_cndmask_b32_e32 v2, v4, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v1
v_sub_nc_u32_e32 v4, v2, v1
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
global_store_b8 v0, v4, s[0:1]
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10smoothGrayPhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10smoothGrayPhS_jj, .Lfunc_end0-_Z10smoothGrayPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10smoothGrayPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10smoothGrayPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void smoothGray (unsigned char *imagem, unsigned char *saida, unsigned int cols, unsigned int linhas)
{
unsigned int indice = (blockIdx.y * blockDim.x * 65536) + (blockIdx.x * 1024) + threadIdx.x; // calcula o indice do vetor com base nas dimensões de bloco e indice da thread
if(indice >= cols*linhas)
return;
//indices para o campo da imagem que participará do smooth
int i_begin = (indice/(int)cols) - 2, i_end = (indice/(int)cols)+2;
int j_begin = (indice%(int)cols) - 2, j_end = (indice%(int)cols)+2;
if(i_begin<0) i_begin = 0;
if(j_begin<0) j_begin = 0;
if(i_end>=cols) i_end = cols-1;
if(j_end>=cols) j_end = cols-1;
//calcula o smooth no ponto de indice da thread
int media = 0;
int qtd = 0;
for (int i = i_begin; i<= i_end; ++i)
{
for(int j = j_begin; j<= j_end; ++j)
{
media += imagem[(i*cols)+j];
qtd++;
}
}
saida[indice] = (unsigned char)(media/qtd);
} | .text
.file "smoothGray.hip"
.globl _Z25__device_stub__smoothGrayPhS_jj # -- Begin function _Z25__device_stub__smoothGrayPhS_jj
.p2align 4, 0x90
.type _Z25__device_stub__smoothGrayPhS_jj,@function
_Z25__device_stub__smoothGrayPhS_jj: # @_Z25__device_stub__smoothGrayPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10smoothGrayPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__smoothGrayPhS_jj, .Lfunc_end0-_Z25__device_stub__smoothGrayPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10smoothGrayPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10smoothGrayPhS_jj,@object # @_Z10smoothGrayPhS_jj
.section .rodata,"a",@progbits
.globl _Z10smoothGrayPhS_jj
.p2align 3, 0x0
_Z10smoothGrayPhS_jj:
.quad _Z25__device_stub__smoothGrayPhS_jj
.size _Z10smoothGrayPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10smoothGrayPhS_jj"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__smoothGrayPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10smoothGrayPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000520d5_00000000-6_smoothGray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
.type _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj, @function
_Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10smoothGrayPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj, .-_Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
.globl _Z10smoothGrayPhS_jj
.type _Z10smoothGrayPhS_jj, @function
_Z10smoothGrayPhS_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10smoothGrayPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10smoothGrayPhS_jj, .-_Z10smoothGrayPhS_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10smoothGrayPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10smoothGrayPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smoothGray.hip"
.globl _Z25__device_stub__smoothGrayPhS_jj # -- Begin function _Z25__device_stub__smoothGrayPhS_jj
.p2align 4, 0x90
.type _Z25__device_stub__smoothGrayPhS_jj,@function
_Z25__device_stub__smoothGrayPhS_jj: # @_Z25__device_stub__smoothGrayPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10smoothGrayPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__smoothGrayPhS_jj, .Lfunc_end0-_Z25__device_stub__smoothGrayPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10smoothGrayPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10smoothGrayPhS_jj,@object # @_Z10smoothGrayPhS_jj
.section .rodata,"a",@progbits
.globl _Z10smoothGrayPhS_jj
.p2align 3, 0x0
_Z10smoothGrayPhS_jj:
.quad _Z25__device_stub__smoothGrayPhS_jj
.size _Z10smoothGrayPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10smoothGrayPhS_jj"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__smoothGrayPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10smoothGrayPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <sys/types.h>
#include <cuda_runtime_api.h>
#define sizeGrid 65535
#define sizeBlock 1024
#define sizeWarp 32
__global__ void training(int dimP, int nP, int *ps, float *ws)
{
float product;
int x;
x = blockIdx.x*blockDim.x + threadIdx.x;
if (x < dimP*dimP){
product = 0.0f;
for (int i = 0; i < nP; i++)
product += (float)((2*ps[i*dimP+(x/dimP)]-1)*(2*ps[i*dimP+(x%dimP)]-1));
product = (!((((x/dimP)*dimP)+(x/dimP)) == x)) * product;
ws[x] = product/nP;
}
}
__global__ void hopActivation(int dimP, float *ws, int *pt, int *at)
{
extern __shared__ float sdata [];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int wid = tid / sizeWarp;
int lane = tid % sizeWarp;
if (wid < dimP ){
int start_neuron = (wid*dimP);
int end_neuron = ((wid+1)*dimP);
sdata[threadIdx.x]=0;
for(int i=start_neuron+lane;i<end_neuron;i+=32)
sdata[threadIdx.x]+= ws[i] * (2*pt[i % dimP ] -1);
__syncthreads();
if (lane < 16) sdata[threadIdx.x] += sdata[threadIdx.x+16]; __syncthreads();
if (lane < 8) sdata[threadIdx.x] += sdata[threadIdx.x+ 8]; __syncthreads();
if (lane < 4) sdata[threadIdx.x] += sdata[threadIdx.x+ 4]; __syncthreads();
if (lane < 2) sdata[threadIdx.x] += sdata[threadIdx.x+ 2]; __syncthreads();
if (lane < 1) sdata[threadIdx.x] += sdata[threadIdx.x+ 1];
if (lane == 0)
at[wid] = ((sdata[threadIdx.x] > 0) - (sdata[threadIdx.x] < 0)+1)/2;
}
}
float * lState (int nPatterns, int dimPattern, int *patterns)
{
int *ps;
float *weights, *ws;
int sizeP = dimPattern*sizeof(int);
int sizeW = dimPattern*dimPattern;
if ((weights = (float*) malloc (sizeW*sizeof(float))) == NULL ) return NULL;
if ( cudaSuccess != cudaMalloc ( &ps, (sizeP*nPatterns))) return NULL;
if ( cudaSuccess != cudaMalloc ( &ws, (sizeW*sizeof(float)))) return NULL;
if ( cudaSuccess != cudaMemcpy (ps, patterns, sizeP*nPatterns, cudaMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM ((sizeW+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
training<<< GRID_DIM, BLOCK_DIM >>> (dimPattern, nPatterns, ps, ws);
if (cudaSuccess != cudaMemcpy (weights, ws, sizeW*sizeof(float), cudaMemcpyDeviceToHost)) return NULL;
cudaFree(ps);
cudaFree(ws);
return weights;
}
int * actFunc(int dimP, int *pattern, float *weight)
{
float *ws;
int *pt, *activation, *at;
if ( (activation = (int *) malloc (dimP*sizeof(int))) == NULL) return NULL;
if (cudaSuccess != cudaMalloc (&ws, dimP*dimP*sizeof(float))) return NULL;
if (cudaSuccess != cudaMalloc (&pt, dimP*sizeof(int))) return NULL;
if (cudaSuccess != cudaMalloc (&at, dimP*sizeof(int))) return NULL;
if ( cudaSuccess != cudaMemcpy (ws, weight, dimP*dimP*sizeof(float), cudaMemcpyHostToDevice)) return NULL;
if ( cudaSuccess != cudaMemcpy (pt, pattern, dimP*sizeof(int), cudaMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM (((dimP*32)+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
hopActivation<<< GRID_DIM, BLOCK_DIM, sizeBlock*sizeof(float) >>> (dimP, ws, pt, at);
if (cudaSuccess != cudaMemcpy (activation, at, dimP*sizeof(int), cudaMemcpyDeviceToHost)) return NULL;
cudaFree(ws);
cudaFree(pt);
cudaFree(at);
return activation;
} | .file "tmpxft_000d860e_00000000-6_hopfield.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8trainingiiPiPfiiPiPf
.type _Z31__device_stub__Z8trainingiiPiPfiiPiPf, @function
_Z31__device_stub__Z8trainingiiPiPfiiPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8trainingiiPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8trainingiiPiPfiiPiPf, .-_Z31__device_stub__Z8trainingiiPiPfiiPiPf
.globl _Z8trainingiiPiPf
.type _Z8trainingiiPiPf, @function
_Z8trainingiiPiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8trainingiiPiPfiiPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8trainingiiPiPf, .-_Z8trainingiiPiPf
.globl _Z6lStateiiPi
.type _Z6lStateiiPi, @function
_Z6lStateiiPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %ebp
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %ebx
movl %esi, %r15d
imull %esi, %r15d
movslq %r15d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L11
imull %r14d, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L15
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L17
leal 2046(%r15), %eax
addl $1023, %r15d
cmovns %r15d, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L18
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L20:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r14d, %esi
movl %ebp, %edi
call _Z31__device_stub__Z8trainingiiPiPfiiPiPf
jmp .L13
.L15:
movl $0, %r12d
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $0, %r12d
jmp .L11
.L17:
movl $0, %r12d
jmp .L11
.L18:
movl $0, %r12d
jmp .L11
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6lStateiiPi, .-_Z6lStateiiPi
.globl _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
.type _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_, @function
_Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13hopActivationiPfPiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_, .-_Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
.globl _Z13hopActivationiPfPiS0_
.type _Z13hopActivationiPfPiS0_, @function
_Z13hopActivationiPfPiS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13hopActivationiPfPiS0_, .-_Z13hopActivationiPfPiS0_
.globl _Z7actFunciPiPf
.type _Z7actFunciPiPf, @function
_Z7actFunciPiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movq %rsi, %r15
movq %rdx, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L30
movl %ebp, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
leal 32(%rbp), %eax
sall $5, %eax
leal 1022(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L32:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L30
.L41:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
jmp .L32
.L34:
movl $0, %r12d
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, %r12d
jmp .L30
.L36:
movl $0, %r12d
jmp .L30
.L37:
movl $0, %r12d
jmp .L30
.L38:
movl $0, %r12d
jmp .L30
.L39:
movl $0, %r12d
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7actFunciPiPf, .-_Z7actFunciPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13hopActivationiPfPiS0_"
.LC1:
.string "_Z8trainingiiPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13hopActivationiPfPiS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8trainingiiPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <sys/types.h>
#include <cuda_runtime_api.h>
#define sizeGrid 65535
#define sizeBlock 1024
#define sizeWarp 32
__global__ void training(int dimP, int nP, int *ps, float *ws)
{
float product;
int x;
x = blockIdx.x*blockDim.x + threadIdx.x;
if (x < dimP*dimP){
product = 0.0f;
for (int i = 0; i < nP; i++)
product += (float)((2*ps[i*dimP+(x/dimP)]-1)*(2*ps[i*dimP+(x%dimP)]-1));
product = (!((((x/dimP)*dimP)+(x/dimP)) == x)) * product;
ws[x] = product/nP;
}
}
__global__ void hopActivation(int dimP, float *ws, int *pt, int *at)
{
extern __shared__ float sdata [];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int wid = tid / sizeWarp;
int lane = tid % sizeWarp;
if (wid < dimP ){
int start_neuron = (wid*dimP);
int end_neuron = ((wid+1)*dimP);
sdata[threadIdx.x]=0;
for(int i=start_neuron+lane;i<end_neuron;i+=32)
sdata[threadIdx.x]+= ws[i] * (2*pt[i % dimP ] -1);
__syncthreads();
if (lane < 16) sdata[threadIdx.x] += sdata[threadIdx.x+16]; __syncthreads();
if (lane < 8) sdata[threadIdx.x] += sdata[threadIdx.x+ 8]; __syncthreads();
if (lane < 4) sdata[threadIdx.x] += sdata[threadIdx.x+ 4]; __syncthreads();
if (lane < 2) sdata[threadIdx.x] += sdata[threadIdx.x+ 2]; __syncthreads();
if (lane < 1) sdata[threadIdx.x] += sdata[threadIdx.x+ 1];
if (lane == 0)
at[wid] = ((sdata[threadIdx.x] > 0) - (sdata[threadIdx.x] < 0)+1)/2;
}
}
float * lState (int nPatterns, int dimPattern, int *patterns)
{
int *ps;
float *weights, *ws;
int sizeP = dimPattern*sizeof(int);
int sizeW = dimPattern*dimPattern;
if ((weights = (float*) malloc (sizeW*sizeof(float))) == NULL ) return NULL;
if ( cudaSuccess != cudaMalloc ( &ps, (sizeP*nPatterns))) return NULL;
if ( cudaSuccess != cudaMalloc ( &ws, (sizeW*sizeof(float)))) return NULL;
if ( cudaSuccess != cudaMemcpy (ps, patterns, sizeP*nPatterns, cudaMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM ((sizeW+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
training<<< GRID_DIM, BLOCK_DIM >>> (dimPattern, nPatterns, ps, ws);
if (cudaSuccess != cudaMemcpy (weights, ws, sizeW*sizeof(float), cudaMemcpyDeviceToHost)) return NULL;
cudaFree(ps);
cudaFree(ws);
return weights;
}
int * actFunc(int dimP, int *pattern, float *weight)
{
float *ws;
int *pt, *activation, *at;
if ( (activation = (int *) malloc (dimP*sizeof(int))) == NULL) return NULL;
if (cudaSuccess != cudaMalloc (&ws, dimP*dimP*sizeof(float))) return NULL;
if (cudaSuccess != cudaMalloc (&pt, dimP*sizeof(int))) return NULL;
if (cudaSuccess != cudaMalloc (&at, dimP*sizeof(int))) return NULL;
if ( cudaSuccess != cudaMemcpy (ws, weight, dimP*dimP*sizeof(float), cudaMemcpyHostToDevice)) return NULL;
if ( cudaSuccess != cudaMemcpy (pt, pattern, dimP*sizeof(int), cudaMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM (((dimP*32)+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
hopActivation<<< GRID_DIM, BLOCK_DIM, sizeBlock*sizeof(float) >>> (dimP, ws, pt, at);
if (cudaSuccess != cudaMemcpy (activation, at, dimP*sizeof(int), cudaMemcpyDeviceToHost)) return NULL;
cudaFree(ws);
cudaFree(pt);
cudaFree(at);
return activation;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <sys/types.h>
#include <hip/hip_runtime_api.h>
#define sizeGrid 65535
#define sizeBlock 1024
#define sizeWarp 32
__global__ void training(int dimP, int nP, int *ps, float *ws)
{
float product;
int x;
x = blockIdx.x*blockDim.x + threadIdx.x;
if (x < dimP*dimP){
product = 0.0f;
for (int i = 0; i < nP; i++)
product += (float)((2*ps[i*dimP+(x/dimP)]-1)*(2*ps[i*dimP+(x%dimP)]-1));
product = (!((((x/dimP)*dimP)+(x/dimP)) == x)) * product;
ws[x] = product/nP;
}
}
__global__ void hopActivation(int dimP, float *ws, int *pt, int *at)
{
extern __shared__ float sdata [];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int wid = tid / sizeWarp;
int lane = tid % sizeWarp;
if (wid < dimP ){
int start_neuron = (wid*dimP);
int end_neuron = ((wid+1)*dimP);
sdata[threadIdx.x]=0;
for(int i=start_neuron+lane;i<end_neuron;i+=32)
sdata[threadIdx.x]+= ws[i] * (2*pt[i % dimP ] -1);
__syncthreads();
if (lane < 16) sdata[threadIdx.x] += sdata[threadIdx.x+16]; __syncthreads();
if (lane < 8) sdata[threadIdx.x] += sdata[threadIdx.x+ 8]; __syncthreads();
if (lane < 4) sdata[threadIdx.x] += sdata[threadIdx.x+ 4]; __syncthreads();
if (lane < 2) sdata[threadIdx.x] += sdata[threadIdx.x+ 2]; __syncthreads();
if (lane < 1) sdata[threadIdx.x] += sdata[threadIdx.x+ 1];
if (lane == 0)
at[wid] = ((sdata[threadIdx.x] > 0) - (sdata[threadIdx.x] < 0)+1)/2;
}
}
float * lState (int nPatterns, int dimPattern, int *patterns)
{
int *ps;
float *weights, *ws;
int sizeP = dimPattern*sizeof(int);
int sizeW = dimPattern*dimPattern;
if ((weights = (float*) malloc (sizeW*sizeof(float))) == NULL ) return NULL;
if ( hipSuccess != hipMalloc ( &ps, (sizeP*nPatterns))) return NULL;
if ( hipSuccess != hipMalloc ( &ws, (sizeW*sizeof(float)))) return NULL;
if ( hipSuccess != hipMemcpy (ps, patterns, sizeP*nPatterns, hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM ((sizeW+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
training<<< GRID_DIM, BLOCK_DIM >>> (dimPattern, nPatterns, ps, ws);
if (hipSuccess != hipMemcpy (weights, ws, sizeW*sizeof(float), hipMemcpyDeviceToHost)) return NULL;
hipFree(ps);
hipFree(ws);
return weights;
}
int * actFunc(int dimP, int *pattern, float *weight)
{
float *ws;
int *pt, *activation, *at;
if ( (activation = (int *) malloc (dimP*sizeof(int))) == NULL) return NULL;
if (hipSuccess != hipMalloc (&ws, dimP*dimP*sizeof(float))) return NULL;
if (hipSuccess != hipMalloc (&pt, dimP*sizeof(int))) return NULL;
if (hipSuccess != hipMalloc (&at, dimP*sizeof(int))) return NULL;
if ( hipSuccess != hipMemcpy (ws, weight, dimP*dimP*sizeof(float), hipMemcpyHostToDevice)) return NULL;
if ( hipSuccess != hipMemcpy (pt, pattern, dimP*sizeof(int), hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM (((dimP*32)+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
hopActivation<<< GRID_DIM, BLOCK_DIM, sizeBlock*sizeof(float) >>> (dimP, ws, pt, at);
if (hipSuccess != hipMemcpy (activation, at, dimP*sizeof(int), hipMemcpyDeviceToHost)) return NULL;
hipFree(ws);
hipFree(pt);
hipFree(at);
return activation;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <sys/types.h>
#include <hip/hip_runtime_api.h>
#define sizeGrid 65535
#define sizeBlock 1024
#define sizeWarp 32
__global__ void training(int dimP, int nP, int *ps, float *ws)
{
float product;
int x;
x = blockIdx.x*blockDim.x + threadIdx.x;
if (x < dimP*dimP){
product = 0.0f;
for (int i = 0; i < nP; i++)
product += (float)((2*ps[i*dimP+(x/dimP)]-1)*(2*ps[i*dimP+(x%dimP)]-1));
product = (!((((x/dimP)*dimP)+(x/dimP)) == x)) * product;
ws[x] = product/nP;
}
}
__global__ void hopActivation(int dimP, float *ws, int *pt, int *at)
{
extern __shared__ float sdata [];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int wid = tid / sizeWarp;
int lane = tid % sizeWarp;
if (wid < dimP ){
int start_neuron = (wid*dimP);
int end_neuron = ((wid+1)*dimP);
sdata[threadIdx.x]=0;
for(int i=start_neuron+lane;i<end_neuron;i+=32)
sdata[threadIdx.x]+= ws[i] * (2*pt[i % dimP ] -1);
__syncthreads();
if (lane < 16) sdata[threadIdx.x] += sdata[threadIdx.x+16]; __syncthreads();
if (lane < 8) sdata[threadIdx.x] += sdata[threadIdx.x+ 8]; __syncthreads();
if (lane < 4) sdata[threadIdx.x] += sdata[threadIdx.x+ 4]; __syncthreads();
if (lane < 2) sdata[threadIdx.x] += sdata[threadIdx.x+ 2]; __syncthreads();
if (lane < 1) sdata[threadIdx.x] += sdata[threadIdx.x+ 1];
if (lane == 0)
at[wid] = ((sdata[threadIdx.x] > 0) - (sdata[threadIdx.x] < 0)+1)/2;
}
}
float * lState (int nPatterns, int dimPattern, int *patterns)
{
int *ps;
float *weights, *ws;
int sizeP = dimPattern*sizeof(int);
int sizeW = dimPattern*dimPattern;
if ((weights = (float*) malloc (sizeW*sizeof(float))) == NULL ) return NULL;
if ( hipSuccess != hipMalloc ( &ps, (sizeP*nPatterns))) return NULL;
if ( hipSuccess != hipMalloc ( &ws, (sizeW*sizeof(float)))) return NULL;
if ( hipSuccess != hipMemcpy (ps, patterns, sizeP*nPatterns, hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM ((sizeW+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
training<<< GRID_DIM, BLOCK_DIM >>> (dimPattern, nPatterns, ps, ws);
if (hipSuccess != hipMemcpy (weights, ws, sizeW*sizeof(float), hipMemcpyDeviceToHost)) return NULL;
hipFree(ps);
hipFree(ws);
return weights;
}
int * actFunc(int dimP, int *pattern, float *weight)
{
float *ws;
int *pt, *activation, *at;
if ( (activation = (int *) malloc (dimP*sizeof(int))) == NULL) return NULL;
if (hipSuccess != hipMalloc (&ws, dimP*dimP*sizeof(float))) return NULL;
if (hipSuccess != hipMalloc (&pt, dimP*sizeof(int))) return NULL;
if (hipSuccess != hipMalloc (&at, dimP*sizeof(int))) return NULL;
if ( hipSuccess != hipMemcpy (ws, weight, dimP*dimP*sizeof(float), hipMemcpyHostToDevice)) return NULL;
if ( hipSuccess != hipMemcpy (pt, pattern, dimP*sizeof(int), hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM (((dimP*32)+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
hopActivation<<< GRID_DIM, BLOCK_DIM, sizeBlock*sizeof(float) >>> (dimP, ws, pt, at);
if (hipSuccess != hipMemcpy (activation, at, dimP*sizeof(int), hipMemcpyDeviceToHost)) return NULL;
hipFree(ws);
hipFree(pt);
hipFree(at);
return activation;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8trainingiiPiPf
.globl _Z8trainingiiPiPf
.p2align 8
.type _Z8trainingiiPiPf,@function
_Z8trainingiiPiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s4, s4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
s_load_b32 s5, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s6, s4, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s2, s4, s6
s_mov_b32 s7, s5
s_xor_b32 s2, s2, s6
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s3, 0, s2
v_xor_b32_e32 v6, s6, v3
s_mov_b32 s6, 0
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v2, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_load_b64 s[2:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v6
v_xor_b32_e32 v4, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v0, v6
v_sub_nc_u32_e32 v3, v4, v3
v_mov_b32_e32 v0, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, s6, v2
v_add_nc_u32_e32 v6, s6, v3
s_add_i32 s7, s7, -1
s_add_i32 s6, s6, s4
s_cmp_eq_u32 s7, 0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_clause 0x1
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
s_waitcnt vmcnt(1)
v_lshl_add_u32 v4, v4, 1, -1
s_waitcnt vmcnt(0)
v_lshl_add_u32 v5, v5, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v5, v4
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v0, v4
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v0, 0
.LBB0_5:
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s3, s4, s2
s_load_b64 s[0:1], s[0:1], 0x10
s_xor_b32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v2, s3
s_sub_i32 s6, 0, s3
v_add_nc_u32_e32 v5, v1, v4
v_rcp_iflag_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v4
v_xor_b32_e32 v4, s2, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s6, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v2, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v2, s3
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v3
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v3
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_xor_b32_e32 v2, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v4
v_mad_u64_u32 v[3:4], null, v2, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, v3, v1
v_cvt_f32_i32_e32 v3, s5
v_cndmask_b32_e64 v2, 0, 1.0, vcc_lo
v_mul_f32_e32 v4, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v0, null, v3, v3, v4
v_rcp_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v2, v5
v_div_scale_f32 v6, vcc_lo, v4, v3, v4
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v0, v7, v6
v_fmac_f32_e32 v7, v2, v5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, -v0, v7, v6
v_div_fmas_f32 v5, v0, v5, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_div_fixup_f32 v2, v5, v3, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8trainingiiPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8trainingiiPiPf, .Lfunc_end0-_Z8trainingiiPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13hopActivationiPfPiS0_
.globl _Z13hopActivationiPfPiS0_
.p2align 8
.type _Z13hopActivationiPfPiS0_,@function
_Z13hopActivationiPfPiS0_:
s_load_b32 s2, s[0:1], 0x2c
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_load_b32 s2, s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v1, 27, v1
v_add_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 5, v1
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB1_17
v_lshlrev_b32_e32 v3, 5, v1
v_mul_lo_u32 v4, v1, s2
v_lshl_add_u32 v5, v0, 2, 0
s_mov_b32 s8, 0
s_mov_b32 s3, exec_lo
v_sub_nc_u32_e32 v6, v2, v3
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v7, s2, v4
v_add_nc_u32_e32 v2, v4, v6
ds_store_b32 v5, v3
v_cmpx_lt_i32_e64 v2, v7
s_cbranch_execz .LBB1_5
s_ashr_i32 s4, s2, 31
ds_load_b32 v8, v5
s_add_i32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_xor_b32 s9, s2, s4
s_load_b128 s[4:7], s[0:1], 0x8
v_cvt_f32_u32_e32 v3, s9
s_sub_i32 s2, 0, s9
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v9, v3
v_ashrrev_i32_e32 v3, 31, v2
v_mul_lo_u32 v10, s2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_hi_u32 v10, v9, v10
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v9, v9, v10
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v10, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, v2, v10
v_add_nc_u32_e32 v2, 32, v2
v_xor_b32_e32 v11, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_i32_e64 s2, v2, v7
v_mul_hi_u32 v12, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s8, s2, s8
v_mul_lo_u32 v12, v12, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v11, v11, v12
v_subrev_nc_u32_e32 v12, s9, v11
v_cmp_le_u32_e32 vcc_lo, s9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_subrev_nc_u32_e32 v12, s9, v11
v_cmp_le_u32_e32 vcc_lo, s9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v11, v11, v12, vcc_lo
v_xor_b32_e32 v11, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v11, v10
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v10, v[10:11], off
global_load_b32 v11, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 0x80
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(1)
v_lshl_add_u32 v10, v10, 1, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v10, v10
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, v11, v10
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB1_3
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s8
ds_store_b32 v5, v8
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 16, v6
s_cbranch_execz .LBB1_7
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:64
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v5, v2
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 8, v6
s_cbranch_execz .LBB1_9
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:32
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v5, v2
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 4, v6
s_cbranch_execz .LBB1_11
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:16
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v5, v2
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 2, v6
s_cbranch_execz .LBB1_13
v_lshl_add_u32 v2, v0, 2, 0
ds_load_b32 v2, v2 offset:8
ds_load_b32 v3, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v5, v2
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e32 1, v6
s_cbranch_execz .LBB1_15
v_lshl_add_u32 v0, v0, 2, 0
ds_load_b32 v0, v0 offset:4
ds_load_b32 v2, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v2
ds_store_b32 v5, v0
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_17
ds_load_b32 v0, v5
s_load_b64 s[0:1], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v3, 1, 2, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_lshrrev_b32_e32 v2, 1, v3
global_store_b32 v[0:1], v2, off
.LBB1_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13hopActivationiPfPiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13hopActivationiPfPiS0_, .Lfunc_end1-_Z13hopActivationiPfPiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8trainingiiPiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8trainingiiPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13hopActivationiPfPiS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13hopActivationiPfPiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#include <sys/types.h>
#include <hip/hip_runtime_api.h>
#define sizeGrid 65535
#define sizeBlock 1024
#define sizeWarp 32
__global__ void training(int dimP, int nP, int *ps, float *ws)
{
float product;
int x;
x = blockIdx.x*blockDim.x + threadIdx.x;
if (x < dimP*dimP){
product = 0.0f;
for (int i = 0; i < nP; i++)
product += (float)((2*ps[i*dimP+(x/dimP)]-1)*(2*ps[i*dimP+(x%dimP)]-1));
product = (!((((x/dimP)*dimP)+(x/dimP)) == x)) * product;
ws[x] = product/nP;
}
}
__global__ void hopActivation(int dimP, float *ws, int *pt, int *at)
{
extern __shared__ float sdata [];
int tid = blockDim.x*blockIdx.x+threadIdx.x;
int wid = tid / sizeWarp;
int lane = tid % sizeWarp;
if (wid < dimP ){
int start_neuron = (wid*dimP);
int end_neuron = ((wid+1)*dimP);
sdata[threadIdx.x]=0;
for(int i=start_neuron+lane;i<end_neuron;i+=32)
sdata[threadIdx.x]+= ws[i] * (2*pt[i % dimP ] -1);
__syncthreads();
if (lane < 16) sdata[threadIdx.x] += sdata[threadIdx.x+16]; __syncthreads();
if (lane < 8) sdata[threadIdx.x] += sdata[threadIdx.x+ 8]; __syncthreads();
if (lane < 4) sdata[threadIdx.x] += sdata[threadIdx.x+ 4]; __syncthreads();
if (lane < 2) sdata[threadIdx.x] += sdata[threadIdx.x+ 2]; __syncthreads();
if (lane < 1) sdata[threadIdx.x] += sdata[threadIdx.x+ 1];
if (lane == 0)
at[wid] = ((sdata[threadIdx.x] > 0) - (sdata[threadIdx.x] < 0)+1)/2;
}
}
float * lState (int nPatterns, int dimPattern, int *patterns)
{
int *ps;
float *weights, *ws;
int sizeP = dimPattern*sizeof(int);
int sizeW = dimPattern*dimPattern;
if ((weights = (float*) malloc (sizeW*sizeof(float))) == NULL ) return NULL;
if ( hipSuccess != hipMalloc ( &ps, (sizeP*nPatterns))) return NULL;
if ( hipSuccess != hipMalloc ( &ws, (sizeW*sizeof(float)))) return NULL;
if ( hipSuccess != hipMemcpy (ps, patterns, sizeP*nPatterns, hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM ((sizeW+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
training<<< GRID_DIM, BLOCK_DIM >>> (dimPattern, nPatterns, ps, ws);
if (hipSuccess != hipMemcpy (weights, ws, sizeW*sizeof(float), hipMemcpyDeviceToHost)) return NULL;
hipFree(ps);
hipFree(ws);
return weights;
}
int * actFunc(int dimP, int *pattern, float *weight)
{
float *ws;
int *pt, *activation, *at;
if ( (activation = (int *) malloc (dimP*sizeof(int))) == NULL) return NULL;
if (hipSuccess != hipMalloc (&ws, dimP*dimP*sizeof(float))) return NULL;
if (hipSuccess != hipMalloc (&pt, dimP*sizeof(int))) return NULL;
if (hipSuccess != hipMalloc (&at, dimP*sizeof(int))) return NULL;
if ( hipSuccess != hipMemcpy (ws, weight, dimP*dimP*sizeof(float), hipMemcpyHostToDevice)) return NULL;
if ( hipSuccess != hipMemcpy (pt, pattern, dimP*sizeof(int), hipMemcpyHostToDevice)) return NULL;
dim3 GRID_DIM (((dimP*32)+sizeBlock-1)/sizeBlock);
dim3 BLOCK_DIM (sizeBlock);
hopActivation<<< GRID_DIM, BLOCK_DIM, sizeBlock*sizeof(float) >>> (dimP, ws, pt, at);
if (hipSuccess != hipMemcpy (activation, at, dimP*sizeof(int), hipMemcpyDeviceToHost)) return NULL;
hipFree(ws);
hipFree(pt);
hipFree(at);
return activation;
} | .text
.file "hopfield.hip"
.globl _Z23__device_stub__trainingiiPiPf # -- Begin function _Z23__device_stub__trainingiiPiPf
.p2align 4, 0x90
.type _Z23__device_stub__trainingiiPiPf,@function
_Z23__device_stub__trainingiiPiPf: # @_Z23__device_stub__trainingiiPiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8trainingiiPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__trainingiiPiPf, .Lfunc_end0-_Z23__device_stub__trainingiiPiPf
.cfi_endproc
# -- End function
.globl _Z28__device_stub__hopActivationiPfPiS0_ # -- Begin function _Z28__device_stub__hopActivationiPfPiS0_
.p2align 4, 0x90
.type _Z28__device_stub__hopActivationiPfPiS0_,@function
_Z28__device_stub__hopActivationiPfPiS0_: # @_Z28__device_stub__hopActivationiPfPiS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13hopActivationiPfPiS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__hopActivationiPfPiS0_, .Lfunc_end1-_Z28__device_stub__hopActivationiPfPiS0_
.cfi_endproc
# -- End function
.globl _Z6lStateiiPi # -- Begin function _Z6lStateiiPi
.p2align 4, 0x90
.type _Z6lStateiiPi,@function
_Z6lStateiiPi: # @_Z6lStateiiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r13
movl %esi, %r15d
movl %edi, %ebp
movl %esi, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB2_3
# %bb.1:
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r15d, %eax
shll $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.4:
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.6:
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_3
# %bb.8:
addl $1023, %r12d # imm = 0x3FF
shrl $10, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1024, %rdx # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 8(%rsp), %rdx
movq (%rsp), %rcx
movl %r15d, %edi
movl %ebp, %esi
callq _Z23__device_stub__trainingiiPiPf
.LBB2_10:
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_12
.LBB2_3:
xorl %eax, %eax
.LBB2_13:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 80
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rax # 8-byte Reload
jmp .LBB2_13
.Lfunc_end2:
.size _Z6lStateiiPi, .Lfunc_end2-_Z6lStateiiPi
.cfi_endproc
# -- End function
.globl _Z7actFunciPiPf # -- Begin function _Z7actFunciPiPf
.p2align 4, 0x90
.type _Z7actFunciPiPf,@function
_Z7actFunciPiPf: # @_Z7actFunciPiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r12
movq %rsi, %r15
movl %edi, %ebp
movslq %edi, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB3_3
# %bb.1:
movq %rax, %rbx
movl %ebp, %r13d
imull %r13d, %r13d
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.4:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.6:
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.8:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_3
# %bb.10:
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_3
# %bb.12:
movl %ebp, %edi
shll $5, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq (%rsp), %rcx
movl %ebp, %edi
callq _Z28__device_stub__hopActivationiPfPiS0_
.LBB3_14:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_16
.LBB3_3:
xorl %eax, %eax
.LBB3_17:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_16:
.cfi_def_cfa_offset 80
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rax
jmp .LBB3_17
.Lfunc_end3:
.size _Z7actFunciPiPf, .Lfunc_end3-_Z7actFunciPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8trainingiiPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13hopActivationiPfPiS0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8trainingiiPiPf,@object # @_Z8trainingiiPiPf
.section .rodata,"a",@progbits
.globl _Z8trainingiiPiPf
.p2align 3, 0x0
_Z8trainingiiPiPf:
.quad _Z23__device_stub__trainingiiPiPf
.size _Z8trainingiiPiPf, 8
.type _Z13hopActivationiPfPiS0_,@object # @_Z13hopActivationiPfPiS0_
.globl _Z13hopActivationiPfPiS0_
.p2align 3, 0x0
_Z13hopActivationiPfPiS0_:
.quad _Z28__device_stub__hopActivationiPfPiS0_
.size _Z13hopActivationiPfPiS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8trainingiiPiPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13hopActivationiPfPiS0_"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__trainingiiPiPf
.addrsig_sym _Z28__device_stub__hopActivationiPfPiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8trainingiiPiPf
.addrsig_sym _Z13hopActivationiPfPiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d860e_00000000-6_hopfield.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8trainingiiPiPfiiPiPf
.type _Z31__device_stub__Z8trainingiiPiPfiiPiPf, @function
_Z31__device_stub__Z8trainingiiPiPfiiPiPf:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8trainingiiPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z8trainingiiPiPfiiPiPf, .-_Z31__device_stub__Z8trainingiiPiPfiiPiPf
.globl _Z8trainingiiPiPf
.type _Z8trainingiiPiPf, @function
_Z8trainingiiPiPf:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8trainingiiPiPfiiPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8trainingiiPiPf, .-_Z8trainingiiPiPf
.globl _Z6lStateiiPi
.type _Z6lStateiiPi, @function
_Z6lStateiiPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %r14d
movl %esi, %ebp
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rsi,4), %ebx
movl %esi, %r15d
imull %esi, %r15d
movslq %r15d, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L11
imull %r14d, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L15
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L16
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L17
leal 2046(%r15), %eax
addl $1023, %r15d
cmovns %r15d, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L18
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L11
.L20:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movl %r14d, %esi
movl %ebp, %edi
call _Z31__device_stub__Z8trainingiiPiPfiiPiPf
jmp .L13
.L15:
movl $0, %r12d
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $0, %r12d
jmp .L11
.L17:
movl $0, %r12d
jmp .L11
.L18:
movl $0, %r12d
jmp .L11
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6lStateiiPi, .-_Z6lStateiiPi
.globl _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
.type _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_, @function
_Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13hopActivationiPfPiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_, .-_Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
.globl _Z13hopActivationiPfPiS0_
.type _Z13hopActivationiPfPiS0_, @function
_Z13hopActivationiPfPiS0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13hopActivationiPfPiS0_, .-_Z13hopActivationiPfPiS0_
.globl _Z7actFunciPiPf
.type _Z7actFunciPiPf, @function
_Z7actFunciPiPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movl %edi, %ebp
movq %rsi, %r15
movq %rdx, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movslq %edi, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
testq %rax, %rax
je .L30
movl %ebp, %ebx
imull %ebp, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L34
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L37
movl $1, %ecx
movq %r13, %rdx
movq %r15, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
leal 32(%rbp), %eax
sall $5, %eax
leal 1022(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $10, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L41
.L32:
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L39
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
jmp .L30
.L41:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl %ebp, %edi
call _Z39__device_stub__Z13hopActivationiPfPiS0_iPfPiS0_
jmp .L32
.L34:
movl $0, %r12d
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L42
movq %r12, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl $0, %r12d
jmp .L30
.L36:
movl $0, %r12d
jmp .L30
.L37:
movl $0, %r12d
jmp .L30
.L38:
movl $0, %r12d
jmp .L30
.L39:
movl $0, %r12d
jmp .L30
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z7actFunciPiPf, .-_Z7actFunciPiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13hopActivationiPfPiS0_"
.LC1:
.string "_Z8trainingiiPiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13hopActivationiPfPiS0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z8trainingiiPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hopfield.hip"
.globl _Z23__device_stub__trainingiiPiPf # -- Begin function _Z23__device_stub__trainingiiPiPf
.p2align 4, 0x90
.type _Z23__device_stub__trainingiiPiPf,@function
_Z23__device_stub__trainingiiPiPf: # @_Z23__device_stub__trainingiiPiPf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8trainingiiPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__trainingiiPiPf, .Lfunc_end0-_Z23__device_stub__trainingiiPiPf
.cfi_endproc
# -- End function
.globl _Z28__device_stub__hopActivationiPfPiS0_ # -- Begin function _Z28__device_stub__hopActivationiPfPiS0_
.p2align 4, 0x90
.type _Z28__device_stub__hopActivationiPfPiS0_,@function
_Z28__device_stub__hopActivationiPfPiS0_: # @_Z28__device_stub__hopActivationiPfPiS0_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13hopActivationiPfPiS0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__hopActivationiPfPiS0_, .Lfunc_end1-_Z28__device_stub__hopActivationiPfPiS0_
.cfi_endproc
# -- End function
.globl _Z6lStateiiPi # -- Begin function _Z6lStateiiPi
.p2align 4, 0x90
.type _Z6lStateiiPi,@function
_Z6lStateiiPi: # @_Z6lStateiiPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r13
movl %esi, %r15d
movl %edi, %ebp
movl %esi, %r12d
imull %r12d, %r12d
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB2_3
# %bb.1:
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebp, %eax
imull %r15d, %eax
shll $2, %eax
movslq %eax, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.4:
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_3
# %bb.6:
movq 8(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_3
# %bb.8:
addl $1023, %r12d # imm = 0x3FF
shrl $10, %r12d
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1024, %rdx # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 8(%rsp), %rdx
movq (%rsp), %rcx
movl %r15d, %edi
movl %ebp, %esi
callq _Z23__device_stub__trainingiiPiPf
.LBB2_10:
movq (%rsp), %rsi
movq 16(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB2_12
.LBB2_3:
xorl %eax, %eax
.LBB2_13:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_12:
.cfi_def_cfa_offset 80
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rax # 8-byte Reload
jmp .LBB2_13
.Lfunc_end2:
.size _Z6lStateiiPi, .Lfunc_end2-_Z6lStateiiPi
.cfi_endproc
# -- End function
.globl _Z7actFunciPiPf # -- Begin function _Z7actFunciPiPf
.p2align 4, 0x90
.type _Z7actFunciPiPf,@function
_Z7actFunciPiPf: # @_Z7actFunciPiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r12
movq %rsi, %r15
movl %edi, %ebp
movslq %edi, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
testq %rax, %rax
je .LBB3_3
# %bb.1:
movq %rax, %rbx
movl %ebp, %r13d
imull %r13d, %r13d
shlq $2, %r13
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.4:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.6:
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB3_3
# %bb.8:
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_3
# %bb.10:
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_3
# %bb.12:
movl %ebp, %edi
shll $5, %edi
leal 1023(%rdi), %eax
addl $2046, %edi # imm = 0x7FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
movq (%rsp), %rcx
movl %ebp, %edi
callq _Z28__device_stub__hopActivationiPfPiS0_
.LBB3_14:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB3_16
.LBB3_3:
xorl %eax, %eax
.LBB3_17:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_16:
.cfi_def_cfa_offset 80
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rax
jmp .LBB3_17
.Lfunc_end3:
.size _Z7actFunciPiPf, .Lfunc_end3-_Z7actFunciPiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8trainingiiPiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13hopActivationiPfPiS0_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8trainingiiPiPf,@object # @_Z8trainingiiPiPf
.section .rodata,"a",@progbits
.globl _Z8trainingiiPiPf
.p2align 3, 0x0
_Z8trainingiiPiPf:
.quad _Z23__device_stub__trainingiiPiPf
.size _Z8trainingiiPiPf, 8
.type _Z13hopActivationiPfPiS0_,@object # @_Z13hopActivationiPfPiS0_
.globl _Z13hopActivationiPfPiS0_
.p2align 3, 0x0
_Z13hopActivationiPfPiS0_:
.quad _Z28__device_stub__hopActivationiPfPiS0_
.size _Z13hopActivationiPfPiS0_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8trainingiiPiPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13hopActivationiPfPiS0_"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__trainingiiPiPf
.addrsig_sym _Z28__device_stub__hopActivationiPfPiS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8trainingiiPiPf
.addrsig_sym _Z13hopActivationiPfPiS0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} | code for sm_80
Function : _Z7oneMovePiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x174] ; /* 0x00005d0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ BSSY B0, 0x2d0 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000ea60000002500 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x002fe40003f25270 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fca0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R5, c[0x0][0x174], RZ ; /* 0x00005d0005057a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R6, R3, R8, RZ ; /* 0x0000000803067227 */
/* 0x004fc800078e00ff */
/*00f0*/ IMAD.MOV R7, RZ, RZ, -R6 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a06 */
/*0100*/ IMAD R7, R7, c[0x0][0x174], R8 ; /* 0x00005d0007077a24 */
/* 0x000fca00078e0208 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fe20003f06070 */
/*0120*/ @P1 BRA 0x2c0 ; /* 0x0000019000001947 */
/* 0x000fee0003800000 */
/*0130*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*0140*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f65070 */
/*0150*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*01a0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01c0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*01e0*/ IMAD R5, R5, c[0x0][0x170], R8 ; /* 0x00005c0005057a24 */
/* 0x000fca00078e0208 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IADD3 R5, R5, -c[0x0][0x170], RZ ; /* 0x80005c0005051a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P2, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f46070 */
/*0230*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P3 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03ba12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD R2, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a24 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a03 */
/*0270*/ IMAD.SHL.U32 R3, R9, 0x200, RZ ; /* 0x0000020009037824 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD R4, R5, c[0x0][0x170], R8 ; /* 0x00005c0005047a24 */
/* 0x000fc800078e0208 */
/*02a0*/ IMAD R2, R3, R4, R2 ; /* 0x0000000403027224 */
/* 0x000fca00078e0202 */
/*02b0*/ STS [0x1000], R2 ; /* 0x00100002ff007388 */
/* 0x0001e40000000800 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ @P0 IADD3 R7, R7, -c[0x0][0x174], RZ ; /* 0x80005d0007070a10 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f45070 */
/*0300*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fe20003f26070 */
/*0310*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0320*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fd60007ffe0ff */
/*0330*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0340*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff06aa12 */
/* 0x000fe200078e33ff */
/*0350*/ LDS R3, [0x1000] ; /* 0x00100000ff037984 */
/* 0x000e660000000800 */
/*0360*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ec0ff */
/*0370*/ ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f05070 */
/*0380*/ @P0 BRA 0x5a0 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*03a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe200078e00ff */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fc80003f06070 */
/*03d0*/ IADD3 R2, R2, -0x200, RZ ; /* 0xfffffe0002027810 */
/* 0x000fc80007ffe0ff */
/*03e0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fc80000000000 */
/*03f0*/ IADD3 R2, R3, R2, R0 ; /* 0x0000000203027210 */
/* 0x002fe40007ffe000 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0410*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0005 */
/*0420*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f04070 */
/*0440*/ BSSY B0, 0x4e0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0450*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @P0 BRA 0x4d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x001fe80000004800 */
/*0490*/ LDS R6, [R0.X4+0x800] ; /* 0x0008000000067984 */
/* 0x000e240000004800 */
/*04a0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x001fda0003f06270 */
/*04b0*/ @!P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700008388 */
/* 0x0001e80000004800 */
/*04c0*/ @!P0 STS [R0.X4], R6 ; /* 0x0000000600008388 */
/* 0x0001e40000004800 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3 R3, R3, 0x200, RZ ; /* 0x0000020003037810 */
/* 0x000fe40007ffe0ff */
/*0510*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fe40007ffe0ff */
/*0520*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0530*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101904 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ LDS R6, [0x1000] ; /* 0x00100000ff067984 */
/* 0x000e240000000800 */
/*0560*/ IMAD R6, R9, 0x200, R6 ; /* 0x0000020009067824 */
/* 0x001fca00078e0206 */
/*0570*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0580*/ @!P0 BRA 0x400 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe200078e00ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fc80003f06070 */
/*05e0*/ IADD3 R2, R2, -0x200, RZ ; /* 0xfffffe0002027810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fc80000000000 */
/*0600*/ IADD3 R2, R3, R2, R0 ; /* 0x0000000203027210 */
/* 0x002fe40007ffe000 */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0005 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f04070 */
/*0650*/ BSSY B0, 0x6f0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0660*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ @P0 BRA 0x6e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0690*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x001fe80000004800 */
/*06a0*/ LDS R6, [R0.X4+0x800] ; /* 0x0008000000067984 */
/* 0x000e240000004800 */
/*06b0*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x001fda0003f04270 */
/*06c0*/ @P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700000388 */
/* 0x0001e80000004800 */
/*06d0*/ @P0 STS [R0.X4], R6 ; /* 0x0000000600000388 */
/* 0x0001e40000004800 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*06f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0700*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0710*/ IADD3 R3, R3, 0x200, RZ ; /* 0x0000020003037810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0740*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101904 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R6, [0x1000] ; /* 0x00100000ff067984 */
/* 0x000e240000000800 */
/*0770*/ IMAD R6, R9, 0x200, R6 ; /* 0x0000020009067824 */
/* 0x001fca00078e0206 */
/*0780*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0790*/ @!P0 BRA 0x610 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} | .file "tmpxft_001340bd_00000000-6_oneMove.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7oneMovePiiiiiPiiiii
.type _Z30__device_stub__Z7oneMovePiiiiiPiiiii, @function
_Z30__device_stub__Z7oneMovePiiiiiPiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7oneMovePiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7oneMovePiiiiiPiiiii, .-_Z30__device_stub__Z7oneMovePiiiiiPiiiii
.globl _Z7oneMovePiiiii
.type _Z7oneMovePiiiii, @function
_Z7oneMovePiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7oneMovePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7oneMovePiiiii, .-_Z7oneMovePiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7oneMovePiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7oneMovePiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7oneMovePiiiii
.globl _Z7oneMovePiiiii
.p2align 8
.type _Z7oneMovePiiiii,@function
_Z7oneMovePiiiii:
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s7, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v1
v_mov_b32_e32 v1, 0
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s15, s6
s_mul_i32 s7, s6, s3
s_add_i32 s8, s6, 1
s_sub_i32 s7, s15, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s6, s3
s_mul_i32 s6, s4, s6
s_sub_i32 s3, s15, s3
s_lshl_b32 s6, s6, 1
s_mul_i32 s3, s5, s3
s_lshl_b32 s3, s3, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s6
v_mov_b32_e32 v2, s3
ds_store_b32 v1, v2 offset:4096
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s6, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s15, s2
s_mul_i32 s2, s7, s6
s_add_i32 s9, s7, 1
s_sub_i32 s8, s15, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_sub_i32 s10, s8, s6
s_cmp_ge_u32 s8, s6
s_cselect_b32 s0, s9, s7
s_cselect_b32 s1, s10, s8
s_add_i32 s7, s0, 1
s_cmp_ge_u32 s1, s6
s_cselect_b32 s0, s7, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_bitcmp1_b32 s0, 0
s_cselect_b32 s0, -1, 0
s_lshl_b32 s1, s5, 9
s_cmp_gt_i32 s5, 0
s_cselect_b32 s5, -1, 0
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b32 s0, -1
s_cbranch_vccz .LBB0_10
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_9
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_add_nc_u32_e32 v4, s4, v0
v_cmp_gt_u32_e64 s0, 0x200, v0
ds_load_b32 v3, v2 offset:4096
v_add_nc_u32_e32 v6, 0x800, v5
v_add_nc_u32_e32 v1, 0xfffffe00, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v7, v1, v0, s0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
v_add3_u32 v1, v4, v3, 0xfffffe00
v_add_nc_u32_e32 v8, v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v10, v5
v_cndmask_b32_e64 v1, v1, v8, s0
v_add_nc_u32_e32 v3, 0x200, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[8:9], v10, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v3, v1
s_cbranch_vccz .LBB0_9
.LBB0_6:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v7, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_5
ds_load_b32 v1, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
ds_store_b32 v6, v1
ds_store_b32 v5, v8
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s0, 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_17
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_17
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_add_nc_u32_e32 v4, s4, v0
v_cmp_gt_u32_e64 s0, 0x200, v0
ds_load_b32 v3, v2 offset:4096
v_add_nc_u32_e32 v6, 0x800, v5
v_add_nc_u32_e32 v1, 0xfffffe00, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v7, v1, v0, s0
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
v_add3_u32 v1, v4, v3, 0xfffffe00
v_add_nc_u32_e32 v8, v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v10, v5
v_cndmask_b32_e64 v1, v1, v8, s0
v_add_nc_u32_e32 v3, 0x200, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[8:9], v10, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v1
s_cbranch_vccnz .LBB0_17
.LBB0_14:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v7, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_13
ds_load_b32 v1, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
ds_store_b32 v6, v1
ds_store_b32 v5, v8
s_branch .LBB0_13
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7oneMovePiiiii
.amdhsa_group_segment_fixed_size 4100
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7oneMovePiiiii, .Lfunc_end0-_Z7oneMovePiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4100
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7oneMovePiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7oneMovePiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INF 2147483647
extern "C" {
}
__global__ void oneMove(int * tab, int dist, int pow, int blocksPerTask, int period) {
__shared__ int tmp_T[1024];
__shared__ int begin;
if(threadIdx.x == 0)
begin = (blockIdx.x/blocksPerTask)*dist*2 + (blockIdx.x%blocksPerTask)*512*pow;
__syncthreads();
if((blockIdx.x / period) % 2 == 0) {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] > tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
} else {
for(int i = begin; i < begin + pow*512; i += 512) {
if(threadIdx.x < 512) tmp_T[threadIdx.x] = tab[i + threadIdx.x];
else tmp_T[threadIdx.x] = tab[i + threadIdx.x - 512 + dist];
__syncthreads();
if(threadIdx.x < 512 && tmp_T[threadIdx.x] < tmp_T[threadIdx.x + 512]) {
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
tmp_T[threadIdx.x + 512] ^= tmp_T[threadIdx.x];
tmp_T[threadIdx.x] ^= tmp_T[threadIdx.x + 512];
}
__syncthreads();
if(threadIdx.x < 512) tab[i + threadIdx.x] = tmp_T[threadIdx.x];
else tab[i + threadIdx.x - 512 + dist] = tmp_T[threadIdx.x];
__syncthreads();
}
}
} | .text
.file "oneMove.hip"
.globl _Z22__device_stub__oneMovePiiiii # -- Begin function _Z22__device_stub__oneMovePiiiii
.p2align 4, 0x90
.type _Z22__device_stub__oneMovePiiiii,@function
_Z22__device_stub__oneMovePiiiii: # @_Z22__device_stub__oneMovePiiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7oneMovePiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__oneMovePiiiii, .Lfunc_end0-_Z22__device_stub__oneMovePiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7oneMovePiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7oneMovePiiiii,@object # @_Z7oneMovePiiiii
.section .rodata,"a",@progbits
.globl _Z7oneMovePiiiii
.p2align 3, 0x0
_Z7oneMovePiiiii:
.quad _Z22__device_stub__oneMovePiiiii
.size _Z7oneMovePiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7oneMovePiiiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__oneMovePiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7oneMovePiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7oneMovePiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x174] ; /* 0x00005d0000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ BSSY B0, 0x2d0 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe400078e00ff */
/*0050*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000ea60000002500 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x002fe40003f25270 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fca0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R5, c[0x0][0x174], RZ ; /* 0x00005d0005057a24 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R6, R3, R8, RZ ; /* 0x0000000803067227 */
/* 0x004fc800078e00ff */
/*00f0*/ IMAD.MOV R7, RZ, RZ, -R6 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a06 */
/*0100*/ IMAD R7, R7, c[0x0][0x174], R8 ; /* 0x00005d0007077a24 */
/* 0x000fca00078e0208 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fe20003f06070 */
/*0120*/ @P1 BRA 0x2c0 ; /* 0x0000019000001947 */
/* 0x000fee0003800000 */
/*0130*/ I2F.U32.RP R4, c[0x0][0x170] ; /* 0x00005c0000047b06 */
/* 0x000e220000209000 */
/*0140*/ ISETP.NE.U32.AND P3, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fce0003f65070 */
/*0150*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0160*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0170*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0190*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*01a0*/ IMAD R5, R5, c[0x0][0x170], RZ ; /* 0x00005c0005057a24 */
/* 0x000fc800078e02ff */
/*01b0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*01c0*/ IMAD.HI.U32 R3, R3, R8, RZ ; /* 0x0000000803037227 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*01e0*/ IMAD R5, R5, c[0x0][0x170], R8 ; /* 0x00005c0005057a24 */
/* 0x000fca00078e0208 */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f26070 */
/*0200*/ @P1 IADD3 R5, R5, -c[0x0][0x170], RZ ; /* 0x80005c0005051a10 */
/* 0x000fe40007ffe0ff */
/*0210*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P2, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fda0003f46070 */
/*0230*/ @P2 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103032810 */
/* 0x000fe40007ffe0ff */
/*0240*/ @!P3 LOP3.LUT R3, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff03ba12 */
/* 0x000fca00078e33ff */
/*0250*/ IMAD R2, R3, c[0x0][0x168], RZ ; /* 0x00005a0003027a24 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a03 */
/*0270*/ IMAD.SHL.U32 R3, R9, 0x200, RZ ; /* 0x0000020009037824 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD R4, R5, c[0x0][0x170], R8 ; /* 0x00005c0005047a24 */
/* 0x000fc800078e0208 */
/*02a0*/ IMAD R2, R3, R4, R2 ; /* 0x0000000403027224 */
/* 0x000fca00078e0202 */
/*02b0*/ STS [0x1000], R2 ; /* 0x00100002ff007388 */
/* 0x0001e40000000800 */
/*02c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02e0*/ @P0 IADD3 R7, R7, -c[0x0][0x174], RZ ; /* 0x80005d0007070a10 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f45070 */
/*0300*/ ISETP.GE.U32.AND P1, PT, R7, c[0x0][0x174], PT ; /* 0x00005d0007007a0c */
/* 0x000fe20003f26070 */
/*0310*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0320*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fd60007ffe0ff */
/*0330*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*0340*/ @!P2 LOP3.LUT R6, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff06aa12 */
/* 0x000fe200078e33ff */
/*0350*/ LDS R3, [0x1000] ; /* 0x00100000ff037984 */
/* 0x000e660000000800 */
/*0360*/ LOP3.LUT R6, R6, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106067812 */
/* 0x000fc800078ec0ff */
/*0370*/ ISETP.NE.U32.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fda0003f05070 */
/*0380*/ @P0 BRA 0x5a0 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*03a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe200078e00ff */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fc80003f06070 */
/*03d0*/ IADD3 R2, R2, -0x200, RZ ; /* 0xfffffe0002027810 */
/* 0x000fc80007ffe0ff */
/*03e0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fc80000000000 */
/*03f0*/ IADD3 R2, R3, R2, R0 ; /* 0x0000000203027210 */
/* 0x002fe40007ffe000 */
/*0400*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0410*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0005 */
/*0420*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0430*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f04070 */
/*0440*/ BSSY B0, 0x4e0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0450*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ @P0 BRA 0x4d0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0480*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x001fe80000004800 */
/*0490*/ LDS R6, [R0.X4+0x800] ; /* 0x0008000000067984 */
/* 0x000e240000004800 */
/*04a0*/ ISETP.GE.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x001fda0003f06270 */
/*04b0*/ @!P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700008388 */
/* 0x0001e80000004800 */
/*04c0*/ @!P0 STS [R0.X4], R6 ; /* 0x0000000600008388 */
/* 0x0001e40000004800 */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0500*/ IADD3 R3, R3, 0x200, RZ ; /* 0x0000020003037810 */
/* 0x000fe40007ffe0ff */
/*0510*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fe40007ffe0ff */
/*0520*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0530*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101904 */
/*0540*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0550*/ LDS R6, [0x1000] ; /* 0x00100000ff067984 */
/* 0x000e240000000800 */
/*0560*/ IMAD R6, R9, 0x200, R6 ; /* 0x0000020009067824 */
/* 0x001fca00078e0206 */
/*0570*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0580*/ @!P0 BRA 0x400 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*0590*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*05b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*05c0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x001fe200078e00ff */
/*05d0*/ ISETP.GE.U32.AND P0, PT, R0, 0x200, PT ; /* 0x000002000000780c */
/* 0x000fc80003f06070 */
/*05e0*/ IADD3 R2, R2, -0x200, RZ ; /* 0xfffffe0002027810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ SEL R2, R2, RZ, P0 ; /* 0x000000ff02027207 */
/* 0x000fc80000000000 */
/*0600*/ IADD3 R2, R3, R2, R0 ; /* 0x0000000203027210 */
/* 0x002fe40007ffe000 */
/*0610*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0620*/ IMAD.WIDE.U32 R4, R2, R5, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e0005 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea2000c1e1900 */
/*0640*/ ISETP.GT.U32.AND P0, PT, R0, 0x1ff, PT ; /* 0x000001ff0000780c */
/* 0x000fe20003f04070 */
/*0650*/ BSSY B0, 0x6f0 ; /* 0x0000009000007945 */
/* 0x000fe40003800000 */
/*0660*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0041e80000004800 */
/*0670*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0680*/ @P0 BRA 0x6e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0690*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x001fe80000004800 */
/*06a0*/ LDS R6, [R0.X4+0x800] ; /* 0x0008000000067984 */
/* 0x000e240000004800 */
/*06b0*/ ISETP.GT.AND P0, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x001fda0003f04270 */
/*06c0*/ @P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700000388 */
/* 0x0001e80000004800 */
/*06d0*/ @P0 STS [R0.X4], R6 ; /* 0x0000000600000388 */
/* 0x0001e40000004800 */
/*06e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*06f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0700*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fe200078e00ff */
/*0710*/ IADD3 R3, R3, 0x200, RZ ; /* 0x0000020003037810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R2, R2, 0x200, RZ ; /* 0x0000020002027810 */
/* 0x000fe40007ffe0ff */
/*0730*/ LDS R7, [R0.X4] ; /* 0x0000000000077984 */
/* 0x000e280000004800 */
/*0740*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x001fe8000c101904 */
/*0750*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0760*/ LDS R6, [0x1000] ; /* 0x00100000ff067984 */
/* 0x000e240000000800 */
/*0770*/ IMAD R6, R9, 0x200, R6 ; /* 0x0000020009067824 */
/* 0x001fca00078e0206 */
/*0780*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0790*/ @!P0 BRA 0x610 ; /* 0xfffffe7000008947 */
/* 0x000fea000383ffff */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7oneMovePiiiii
.globl _Z7oneMovePiiiii
.p2align 8
.type _Z7oneMovePiiiii,@function
_Z7oneMovePiiiii:
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s7, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s6, v1
v_mov_b32_e32 v1, 0
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s15, s6
s_mul_i32 s7, s6, s3
s_add_i32 s8, s6, 1
s_sub_i32 s7, s15, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s3
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s3
s_cselect_b32 s6, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s6, s3
s_mul_i32 s6, s4, s6
s_sub_i32 s3, s15, s3
s_lshl_b32 s6, s6, 1
s_mul_i32 s3, s5, s3
s_lshl_b32 s3, s3, 9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s6
v_mov_b32_e32 v2, s3
ds_store_b32 v1, v2 offset:4096
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s6, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s15, s2
s_mul_i32 s2, s7, s6
s_add_i32 s9, s7, 1
s_sub_i32 s8, s15, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_sub_i32 s10, s8, s6
s_cmp_ge_u32 s8, s6
s_cselect_b32 s0, s9, s7
s_cselect_b32 s1, s10, s8
s_add_i32 s7, s0, 1
s_cmp_ge_u32 s1, s6
s_cselect_b32 s0, s7, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_bitcmp1_b32 s0, 0
s_cselect_b32 s0, -1, 0
s_lshl_b32 s1, s5, 9
s_cmp_gt_i32 s5, 0
s_cselect_b32 s5, -1, 0
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b32 s0, -1
s_cbranch_vccz .LBB0_10
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_9
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_add_nc_u32_e32 v4, s4, v0
v_cmp_gt_u32_e64 s0, 0x200, v0
ds_load_b32 v3, v2 offset:4096
v_add_nc_u32_e32 v6, 0x800, v5
v_add_nc_u32_e32 v1, 0xfffffe00, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v7, v1, v0, s0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s6
v_add3_u32 v1, v4, v3, 0xfffffe00
v_add_nc_u32_e32 v8, v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v10, v5
v_cndmask_b32_e64 v1, v1, v8, s0
v_add_nc_u32_e32 v3, 0x200, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[8:9], v10, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v3, v1
s_cbranch_vccz .LBB0_9
.LBB0_6:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v7, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s6, s0
s_cbranch_execz .LBB0_5
ds_load_b32 v1, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
ds_store_b32 v6, v1
ds_store_b32 v5, v8
s_branch .LBB0_5
.LBB0_9:
s_mov_b32 s0, 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_17
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_17
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
v_add_nc_u32_e32 v4, s4, v0
v_cmp_gt_u32_e64 s0, 0x200, v0
ds_load_b32 v3, v2 offset:4096
v_add_nc_u32_e32 v6, 0x800, v5
v_add_nc_u32_e32 v1, 0xfffffe00, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v7, v1, v0, s0
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s4
v_add3_u32 v1, v4, v3, 0xfffffe00
v_add_nc_u32_e32 v8, v0, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v10, v5
v_cndmask_b32_e64 v1, v1, v8, s0
v_add_nc_u32_e32 v3, 0x200, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[8:9], v10, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v3, v1
s_cbranch_vccnz .LBB0_17
.LBB0_14:
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v7, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v1, v[8:9], off
s_waitcnt vmcnt(0)
ds_store_b32 v5, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB0_13
ds_load_b32 v1, v5
ds_load_b32 v8, v6
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_13
ds_store_b32 v6, v1
ds_store_b32 v5, v8
s_branch .LBB0_13
.LBB0_17:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7oneMovePiiiii
.amdhsa_group_segment_fixed_size 4100
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7oneMovePiiiii, .Lfunc_end0-_Z7oneMovePiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 4100
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7oneMovePiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7oneMovePiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001340bd_00000000-6_oneMove.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z7oneMovePiiiiiPiiiii
.type _Z30__device_stub__Z7oneMovePiiiiiPiiiii, @function
_Z30__device_stub__Z7oneMovePiiiiiPiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7oneMovePiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z7oneMovePiiiiiPiiiii, .-_Z30__device_stub__Z7oneMovePiiiiiPiiiii
.globl _Z7oneMovePiiiii
.type _Z7oneMovePiiiii, @function
_Z7oneMovePiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7oneMovePiiiiiPiiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7oneMovePiiiii, .-_Z7oneMovePiiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7oneMovePiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7oneMovePiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "oneMove.hip"
.globl _Z22__device_stub__oneMovePiiiii # -- Begin function _Z22__device_stub__oneMovePiiiii
.p2align 4, 0x90
.type _Z22__device_stub__oneMovePiiiii,@function
_Z22__device_stub__oneMovePiiiii: # @_Z22__device_stub__oneMovePiiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7oneMovePiiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__oneMovePiiiii, .Lfunc_end0-_Z22__device_stub__oneMovePiiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7oneMovePiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7oneMovePiiiii,@object # @_Z7oneMovePiiiii
.section .rodata,"a",@progbits
.globl _Z7oneMovePiiiii
.p2align 3, 0x0
_Z7oneMovePiiiii:
.quad _Z22__device_stub__oneMovePiiiii
.size _Z7oneMovePiiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7oneMovePiiiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__oneMovePiiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7oneMovePiiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
cudaEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
cudaMalloc((void **) &A_d,size);
cudaMalloc((void **) &B_d,size);
cudaMalloc((void **) &C_d,size);
// Host to Device transfer
cudaMemcpy(A_d, A_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, size, cudaMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
cudaMemcpy(C_h, C_d, size,cudaMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | code for sm_80
Function : _Z11multiply_gmPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x170] ; /* 0x00005c0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
cudaEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
cudaMalloc((void **) &A_d,size);
cudaMalloc((void **) &B_d,size);
cudaMalloc((void **) &C_d,size);
// Host to Device transfer
cudaMemcpy(A_d, A_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, size, cudaMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
cudaMemcpy(C_h, C_d, size,cudaMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | .file "tmpxft_000082a1_00000000-6_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6div_upii
.type _Z6div_upii, @function
_Z6div_upii:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z6div_upii, .-_Z6div_upii
.globl _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
.type _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiply_gmPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
.globl _Z11multiply_gmPfS_S_ii
.type _Z11multiply_gmPfS_S_ii, @function
_Z11multiply_gmPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11multiply_gmPfS_S_ii, .-_Z11multiply_gmPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Time : %f ms\n"
.LC5:
.string "sleep 1"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
imull %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
comiss .LC1(%rip), %xmm0
jnb .L13
cvttss2siq %xmm0, %r13
.L14:
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %r12d, %r12d
jle .L15
movslq %r12d, %rdi
salq $2, %rdi
leal -1(%r12), %esi
leaq 4(,%rsi,4), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L16:
leaq (%rsi,%rdx), %rax
.L17:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L17
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %r14d
jne .L16
.L15:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
testb $15, %r12b
setne %dl
movzbl %dl, %edx
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
addl %edx, %eax
movl %eax, 60(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call system@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
subss .LC1(%rip), %xmm0
cvttss2siq %xmm0, %r13
btcq $63, %r13
jmp .L14
.L22:
movl %r12d, %r8d
movl %r14d, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11multiply_gmPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiply_gmPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1082130432
.align 4
.LC1:
.long 1593835520
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
cudaEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
cudaMalloc((void **) &A_d,size);
cudaMalloc((void **) &B_d,size);
cudaMalloc((void **) &C_d,size);
// Host to Device transfer
cudaMemcpy(A_d, A_h, size, cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, size, cudaMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
cudaMemcpy(C_h, C_d, size,cudaMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
hipEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
hipMalloc((void **) &A_d,size);
hipMalloc((void **) &B_d,size);
hipMalloc((void **) &C_d,size);
// Host to Device transfer
hipMemcpy(A_d, A_h, size, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, size, hipMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
hipMemcpy(C_h, C_d, size,hipMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
hipEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
hipMalloc((void **) &A_d,size);
hipMalloc((void **) &B_d,size);
hipMalloc((void **) &C_d,size);
// Host to Device transfer
hipMemcpy(A_d, A_h, size, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, size, hipMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
hipMemcpy(C_h, C_d, size,hipMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiply_gmPfS_S_ii
.globl _Z11multiply_gmPfS_S_ii
.p2align 8
.type _Z11multiply_gmPfS_S_ii,@function
_Z11multiply_gmPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v2, s3
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiply_gmPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiply_gmPfS_S_ii, .Lfunc_end0-_Z11multiply_gmPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiply_gmPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiply_gmPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define BLOCK_SIZE 16
// Matrixes Multiplcation (Global Memory)
__global__ void multiply_gm(float *C,float *A,float *B, int nrow,int ncol)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int index=idy*ncol+idx;
if (idy<nrow && idx<ncol){
float sum=0.0f;
for(int k=0;k<ncol;k++){
sum+=A[idy*ncol+k]*B[k*ncol+idx];
}
C[index] = sum;
}
}
int div_up(int a,int b){
return(a/b + (a%b == 0 ? 0:1));
}
int main(int argc, char* argv[]){
float *A_h,*B_h,*C_h; // Host matrixes
float *A_d,*B_d,*C_d; //Device matrixes
int nrow = atoi(argv[1]); // rows
int ncol = nrow; // cols
float N=nrow*ncol; // number of elements
//GPU Time
hipEvent_t start, stop;
float time;
size_t size=N * sizeof(float);
A_h = (float *)malloc(size);
B_h = (float *)malloc(size);
C_h = (float *)malloc(size);
//Initializing Host matrixes
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
A_h[i*ncol+j] = 1.0f;
B_h[i*ncol+j] = 2.0f;
//A_h[i*ncol+j] = rand()/100.0f;
//B_h[i*ncol+j] = rand()/100.0f;
}
}
/*
printf("\nMatrix A:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", A_h[i*ncol+j]);
}
printf("\n");
}
printf("\n\nMatrix B:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", B_h[i*ncol+j]);
}
printf("\n");
}
*/
hipMalloc((void **) &A_d,size);
hipMalloc((void **) &B_d,size);
hipMalloc((void **) &C_d,size);
// Host to Device transfer
hipMemcpy(A_d, A_h, size, hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, size, hipMemcpyHostToDevice);
//Realizamos el cálculo en el Device
dim3 block_size(BLOCK_SIZE,BLOCK_SIZE);
dim3 n_blocks(div_up(ncol,block_size.x),div_up(nrow,block_size.y)) ;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
multiply_gm<<< n_blocks, block_size >>> (C_d,A_d,B_d,nrow,ncol);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
printf("Time : %f ms\n",time);
// Result from Device to Host
hipMemcpy(C_h, C_d, size,hipMemcpyDeviceToHost);
/*
//Results
printf("\n\nMatrix C:\n");
for (int i=0; i<nrow; i++){
for(int j=0;j<ncol;j++){
printf("%.2f ", C_h[i*ncol+j]);
}
printf("\n");
}
*/
system("sleep 1");
free(A_h);
free(B_h);
free(C_h);
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.file "mult.hip"
.globl _Z26__device_stub__multiply_gmPfS_S_ii # -- Begin function _Z26__device_stub__multiply_gmPfS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__multiply_gmPfS_S_ii,@function
_Z26__device_stub__multiply_gmPfS_S_ii: # @_Z26__device_stub__multiply_gmPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiply_gmPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__multiply_gmPfS_S_ii, .Lfunc_end0-_Z26__device_stub__multiply_gmPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z6div_upii # -- Begin function _Z6div_upii
.p2align 4, 0x90
.type _Z6div_upii,@function
_Z6div_upii: # @_Z6div_upii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end1:
.size _Z6div_upii, .Lfunc_end1-_Z6div_upii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40800000 # float 4
.LCPI2_1:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
imull %eax, %eax
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
cvttss2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subss .LCPI2_1(%rip), %xmm0
cvttss2si %xmm0, %r14
andq %rcx, %r14
orq %rax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebp, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rsi,%rdi,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rdi,4) # imm = 0x40000000
incq %rdi
cmpq %rdi, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rcx
addl %r13d, %ebp
cmpq %rax, %rcx
jne .LBB2_2
.LBB2_5: # %._crit_edge50
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r13), %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movl %r13d, %ecx
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
movl %r13d, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11multiply_gmPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
callq system
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiply_gmPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiply_gmPfS_S_ii,@object # @_Z11multiply_gmPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z11multiply_gmPfS_S_ii
.p2align 3, 0x0
_Z11multiply_gmPfS_S_ii:
.quad _Z26__device_stub__multiply_gmPfS_S_ii
.size _Z11multiply_gmPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %f ms\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sleep 1"
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11multiply_gmPfS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiply_gmPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiply_gmPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11multiply_gmPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x170] ; /* 0x00005c0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x170] ; /* 0x00005c0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11multiply_gmPfS_S_ii
.globl _Z11multiply_gmPfS_S_ii
.p2align 8
.type _Z11multiply_gmPfS_S_ii,@function
_Z11multiply_gmPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s5, v[4:5]
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v1, v2, s3
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s2, s3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11multiply_gmPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11multiply_gmPfS_S_ii, .Lfunc_end0-_Z11multiply_gmPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11multiply_gmPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11multiply_gmPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000082a1_00000000-6_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6div_upii
.type _Z6div_upii, @function
_Z6div_upii:
.LFB2057:
.cfi_startproc
endbr64
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z6div_upii, .-_Z6div_upii
.globl _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
.type _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11multiply_gmPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
.globl _Z11multiply_gmPfS_S_ii
.type _Z11multiply_gmPfS_S_ii, @function
_Z11multiply_gmPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11multiply_gmPfS_S_ii, .-_Z11multiply_gmPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "Time : %f ms\n"
.LC5:
.string "sleep 1"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r14d
imull %eax, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
comiss .LC1(%rip), %xmm0
jnb .L13
cvttss2siq %xmm0, %r13
.L14:
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %r12d, %r12d
jle .L15
movslq %r12d, %rdi
salq $2, %rdi
leal -1(%r12), %esi
leaq 4(,%rsi,4), %rdx
movl $0, %ecx
notq %rsi
salq $2, %rsi
movss .LC2(%rip), %xmm1
movss .LC3(%rip), %xmm0
.L16:
leaq (%rsi,%rdx), %rax
.L17:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L17
addl $1, %ecx
addq %rdi, %rdx
cmpl %ecx, %r14d
jne .L16
.L15:
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 56(%rsp)
testb $15, %r12b
setne %dl
movzbl %dl, %edx
leal 15(%r12), %eax
testl %r12d, %r12d
cmovns %r12d, %eax
sarl $4, %eax
addl %edx, %eax
movl %eax, 60(%rsp)
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $16, 48(%rsp)
movl $16, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L18:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %r13, %rdx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rdi
call system@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
subss .LC1(%rip), %xmm0
cvttss2siq %xmm0, %r13
btcq $63, %r13
jmp .L14
.L22:
movl %r12d, %r8d
movl %r14d, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z11multiply_gmPfS_S_iiPfS_S_ii
jmp .L18
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z11multiply_gmPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11multiply_gmPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1082130432
.align 4
.LC1:
.long 1593835520
.align 4
.LC2:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mult.hip"
.globl _Z26__device_stub__multiply_gmPfS_S_ii # -- Begin function _Z26__device_stub__multiply_gmPfS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__multiply_gmPfS_S_ii,@function
_Z26__device_stub__multiply_gmPfS_S_ii: # @_Z26__device_stub__multiply_gmPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11multiply_gmPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__multiply_gmPfS_S_ii, .Lfunc_end0-_Z26__device_stub__multiply_gmPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z6div_upii # -- Begin function _Z6div_upii
.p2align 4, 0x90
.type _Z6div_upii,@function
_Z6div_upii: # @_Z6div_upii
.cfi_startproc
# %bb.0:
movl %edi, %eax
cltd
idivl %esi
cmpl $1, %edx
sbbl $-1, %eax
retq
.Lfunc_end1:
.size _Z6div_upii, .Lfunc_end1-_Z6div_upii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40800000 # float 4
.LCPI2_1:
.long 0x5f000000 # float 9.22337203E+18
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
imull %eax, %eax
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
cvttss2si %xmm0, %rax
movq %rax, %rcx
sarq $63, %rcx
subss .LCPI2_1(%rip), %xmm0
cvttss2si %xmm0, %r14
andq %rcx, %r14
orq %rax, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
testl %r13d, %r13d
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %r13d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %ebp, %esi
leaq (%r15,%rsi,4), %rdx
leaq (%rbx,%rsi,4), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rsi,%rdi,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rdi,4) # imm = 0x40000000
incq %rdi
cmpq %rdi, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rcx
addl %r13d, %ebp
cmpq %rax, %rcx
jne .LBB2_2
.LBB2_5: # %._crit_edge50
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r13), %eax
testl %r13d, %r13d
cmovnsl %r13d, %eax
sarl $4, %eax
movl %r13d, %ecx
andl $15, %ecx
cmpl $1, %ecx
sbbl $-1, %eax
movq %rax, %rbp
shlq $32, %rbp
orq %rax, %rbp
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_7
# %bb.6:
movq 16(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %r13d, 44(%rsp)
movl %r13d, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z11multiply_gmPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_7:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.1, %edi
callq system
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11multiply_gmPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11multiply_gmPfS_S_ii,@object # @_Z11multiply_gmPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z11multiply_gmPfS_S_ii
.p2align 3, 0x0
_Z11multiply_gmPfS_S_ii:
.quad _Z26__device_stub__multiply_gmPfS_S_ii
.size _Z11multiply_gmPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time : %f ms\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "sleep 1"
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11multiply_gmPfS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__multiply_gmPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11multiply_gmPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void count_newlines(char *arr, long n, int *result) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long chars_per_thread = (n+stride-1) / stride;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
if (arr[i] == '\n') {
count += 1;
}
}
result[index] = count;
} | .file "tmpxft_00014a9d_00000000-6_count_newlines.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14count_newlinesPclPiPclPi
.type _Z37__device_stub__Z14count_newlinesPclPiPclPi, @function
_Z37__device_stub__Z14count_newlinesPclPiPclPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14count_newlinesPclPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14count_newlinesPclPiPclPi, .-_Z37__device_stub__Z14count_newlinesPclPiPclPi
.globl _Z14count_newlinesPclPi
.type _Z14count_newlinesPclPi, @function
_Z14count_newlinesPclPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14count_newlinesPclPiPclPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14count_newlinesPclPi, .-_Z14count_newlinesPclPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14count_newlinesPclPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14count_newlinesPclPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void count_newlines(char *arr, long n, int *result) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long chars_per_thread = (n+stride-1) / stride;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
if (arr[i] == '\n') {
count += 1;
}
}
result[index] = count;
} | #include <hip/hip_runtime.h>
__global__ void count_newlines(char *arr, long n, int *result) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long chars_per_thread = (n+stride-1) / stride;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
if (arr[i] == '\n') {
count += 1;
}
}
result[index] = count;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void count_newlines(char *arr, long n, int *result) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long chars_per_thread = (n+stride-1) / stride;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
if (arr[i] == '\n') {
count += 1;
}
}
result[index] = count;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14count_newlinesPclPi
.globl _Z14count_newlinesPclPi
.p2align 8
.type _Z14count_newlinesPclPi,@function
_Z14count_newlinesPclPi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s3, s14
s_ashr_i32 s7, s6, 31
s_add_u32 s2, s4, s6
s_addc_u32 s3, s5, s7
s_add_u32 s8, s2, -1
s_addc_u32 s9, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b64 s[10:11], s[8:9], s[6:7]
s_mov_b32 s10, 0
s_cmp_lg_u64 s[10:11], 0
s_cbranch_scc0 .LBB0_8
s_add_u32 s2, s6, s7
s_mov_b32 s12, s7
s_mov_b32 s13, s7
s_addc_u32 s3, s7, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[2:3], s[2:3], s[12:13]
v_cvt_f32_u32_e32 v1, s2
v_cvt_f32_u32_e32 v2, s3
s_sub_u32 s16, 0, s2
s_subb_u32 s17, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v1, v2, 0x4f800000, v1
v_rcp_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x5f7ffffc, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, 0x2f800000, v1
v_trunc_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v1, v2, 0xcf800000, v1
v_cvt_u32_f32_e32 v2, v2
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s7, v2
v_readfirstlane_b32 s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s18, s16, s7
s_mul_hi_u32 s20, s16, s11
s_mul_i32 s19, s17, s11
s_add_i32 s18, s20, s18
s_mul_i32 s21, s16, s11
s_add_i32 s18, s18, s19
s_mul_hi_u32 s20, s11, s21
s_mul_hi_u32 s22, s7, s21
s_mul_i32 s19, s7, s21
s_mul_hi_u32 s21, s11, s18
s_mul_i32 s11, s11, s18
s_mul_hi_u32 s23, s7, s18
s_add_u32 s11, s20, s11
s_addc_u32 s20, 0, s21
s_add_u32 s11, s11, s19
s_mul_i32 s18, s7, s18
s_addc_u32 s11, s20, s22
s_addc_u32 s19, s23, 0
s_add_u32 s11, s11, s18
s_addc_u32 s18, 0, s19
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s7, s7, s18
v_readfirstlane_b32 s11, v1
s_mul_i32 s18, s16, s7
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s19, s16, s11
s_mul_i32 s17, s17, s11
s_add_i32 s18, s19, s18
s_mul_i32 s16, s16, s11
s_add_i32 s18, s18, s17
s_mul_hi_u32 s19, s7, s16
s_mul_i32 s20, s7, s16
s_mul_hi_u32 s16, s11, s16
s_mul_hi_u32 s21, s11, s18
s_mul_i32 s11, s11, s18
s_mul_hi_u32 s17, s7, s18
s_add_u32 s11, s16, s11
s_addc_u32 s16, 0, s21
s_add_u32 s11, s11, s20
s_mul_i32 s18, s7, s18
s_addc_u32 s11, s16, s19
s_addc_u32 s16, s17, 0
s_add_u32 s11, s11, s18
s_addc_u32 s16, 0, s16
v_add_co_u32 v1, s11, v1, s11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s11, 0
s_addc_u32 s7, s7, s16
s_ashr_i32 s16, s9, 31
s_add_u32 s18, s8, s16
s_addc_u32 s19, s9, s16
v_readfirstlane_b32 s9, v1
s_mov_b32 s17, s16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b64 s[18:19], s[18:19], s[16:17]
s_mul_i32 s20, s18, s7
s_delay_alu instid0(VALU_DEP_1)
s_mul_hi_u32 s21, s18, s9
s_mul_hi_u32 s11, s18, s7
s_mul_hi_u32 s23, s19, s9
s_mul_i32 s9, s19, s9
s_add_u32 s20, s21, s20
s_addc_u32 s11, 0, s11
s_mul_hi_u32 s22, s19, s7
s_add_u32 s9, s20, s9
s_mul_i32 s7, s19, s7
s_addc_u32 s9, s11, s23
s_addc_u32 s11, s22, 0
s_add_u32 s7, s9, s7
s_addc_u32 s9, 0, s11
s_mul_i32 s22, s2, s7
s_mul_hi_u32 s11, s2, s7
s_mul_i32 s21, s2, s9
v_sub_co_u32 v1, s18, s18, s22
s_mul_i32 s20, s3, s7
s_add_i32 s11, s11, s21
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s11, s11, s20
v_sub_co_u32 v2, s21, v1, s2
s_sub_i32 s20, s19, s11
s_cmp_lg_u32 s18, 0
s_subb_u32 s20, s20, s3
s_cmp_lg_u32 s21, 0
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_subb_u32 s20, s20, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s20, s3
v_cndmask_b32_e64 v2, 0, -1, vcc_lo
s_cselect_b32 s21, -1, 0
s_cmp_eq_u32 s20, s3
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s20, s7, 1
v_cndmask_b32_e32 v2, s21, v2, vcc_lo
s_addc_u32 s21, s9, 0
s_add_u32 s22, s7, 2
s_addc_u32 s23, s9, 0
v_mov_b32_e32 v3, s22
s_cmp_lg_u32 s18, 0
v_cmp_le_u32_e32 vcc_lo, s2, v1
s_subb_u32 s2, s19, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s2, s3
v_cndmask_b32_e64 v1, 0, -1, vcc_lo
s_cselect_b32 s11, -1, 0
s_cmp_eq_u32 s2, s3
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_cselect_b32 s2, -1, 0
v_mov_b32_e32 v2, s23
v_cndmask_b32_e64 v1, s11, v1, s2
s_xor_b64 s[2:3], s[16:17], s[12:13]
v_cndmask_b32_e32 v3, s20, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, s21, v2, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v1, s9, v2, vcc_lo
v_cndmask_b32_e32 v2, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v1, s3, v1
v_xor_b32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_co_u32 v5, vcc_lo, v2, s2
v_subrev_co_ci_u32_e32 v6, vcc_lo, s3, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_3
.LBB0_2:
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s2, v1
s_mul_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s3, s2, s3
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s2, s8, s2
s_mul_i32 s3, s2, s6
s_add_i32 s7, s2, 1
s_sub_i32 s3, s8, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s8, s3, s6
s_cmp_ge_u32 s3, s6
s_cselect_b32 s2, s7, s2
s_cselect_b32 s3, s8, s3
s_add_i32 s7, s2, 1
s_cmp_ge_u32 s3, s6
s_mov_b32 s3, 0
s_cselect_b32 s2, s7, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
.LBB0_3:
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, v6, v1
v_mad_u64_u32 v[3:4], null, v5, v1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v5, v2
v_add_co_u32 v5, vcc_lo, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v4, v4, v7, v0
v_mov_b32_e32 v0, 0
v_add_co_ci_u32_e32 v6, vcc_lo, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[5:6]
v_cndmask_b32_e32 v6, s5, v6, vcc_lo
v_cndmask_b32_e32 v5, s4, v5, vcc_lo
v_cmpx_lt_i64_e64 v[3:4], v[5:6]
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 0
.LBB0_5:
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
global_load_u8 v7, v[7:8], off
v_cmp_ge_i64_e32 vcc_lo, v[3:4], v[5:6]
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e64 s2, 10, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v0, s2, 0, v0, s2
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_8:
s_branch .LBB0_2
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14count_newlinesPclPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14count_newlinesPclPi, .Lfunc_end0-_Z14count_newlinesPclPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14count_newlinesPclPi
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z14count_newlinesPclPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void count_newlines(char *arr, long n, int *result) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
long chars_per_thread = (n+stride-1) / stride;
long start = index * chars_per_thread;
long end = start + chars_per_thread;
int count = 0;
for (long i = start; i < end && i < n; i += 1) {
if (arr[i] == '\n') {
count += 1;
}
}
result[index] = count;
} | .text
.file "count_newlines.hip"
.globl _Z29__device_stub__count_newlinesPclPi # -- Begin function _Z29__device_stub__count_newlinesPclPi
.p2align 4, 0x90
.type _Z29__device_stub__count_newlinesPclPi,@function
_Z29__device_stub__count_newlinesPclPi: # @_Z29__device_stub__count_newlinesPclPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14count_newlinesPclPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__count_newlinesPclPi, .Lfunc_end0-_Z29__device_stub__count_newlinesPclPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14count_newlinesPclPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14count_newlinesPclPi,@object # @_Z14count_newlinesPclPi
.section .rodata,"a",@progbits
.globl _Z14count_newlinesPclPi
.p2align 3, 0x0
_Z14count_newlinesPclPi:
.quad _Z29__device_stub__count_newlinesPclPi
.size _Z14count_newlinesPclPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14count_newlinesPclPi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__count_newlinesPclPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14count_newlinesPclPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00014a9d_00000000-6_count_newlines.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z14count_newlinesPclPiPclPi
.type _Z37__device_stub__Z14count_newlinesPclPiPclPi, @function
_Z37__device_stub__Z14count_newlinesPclPiPclPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14count_newlinesPclPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z14count_newlinesPclPiPclPi, .-_Z37__device_stub__Z14count_newlinesPclPiPclPi
.globl _Z14count_newlinesPclPi
.type _Z14count_newlinesPclPi, @function
_Z14count_newlinesPclPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14count_newlinesPclPiPclPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14count_newlinesPclPi, .-_Z14count_newlinesPclPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14count_newlinesPclPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14count_newlinesPclPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "count_newlines.hip"
.globl _Z29__device_stub__count_newlinesPclPi # -- Begin function _Z29__device_stub__count_newlinesPclPi
.p2align 4, 0x90
.type _Z29__device_stub__count_newlinesPclPi,@function
_Z29__device_stub__count_newlinesPclPi: # @_Z29__device_stub__count_newlinesPclPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14count_newlinesPclPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__count_newlinesPclPi, .Lfunc_end0-_Z29__device_stub__count_newlinesPclPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14count_newlinesPclPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14count_newlinesPclPi,@object # @_Z14count_newlinesPclPi
.section .rodata,"a",@progbits
.globl _Z14count_newlinesPclPi
.p2align 3, 0x0
_Z14count_newlinesPclPi:
.quad _Z29__device_stub__count_newlinesPclPi
.size _Z14count_newlinesPclPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14count_newlinesPclPi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__count_newlinesPclPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14count_newlinesPclPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} | code for sm_80
Function : _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R0, SR_CTAID.Z ; /* 0x0000000000007919 */
/* 0x000e680000002700 */
/*0060*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000ea80000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002200 */
/*0080*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0202 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x002fc8000bf06270 */
/*00a0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R2, R4, c[0x0][0x4], R5 ; /* 0x0000010004027a24 */
/* 0x004fca00078e0205 */
/*00c0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x17c], P0 ; /* 0x00005f0002007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IABS R7, c[0x0][0x184] ; /* 0x0000610000077a13 */
/* 0x000fe20000000000 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0150*/ IMAD.MOV R8, RZ, RZ, -R5 ; /* 0x000000ffff087224 */
/* 0x002fc800078e0a05 */
/*0160*/ IMAD R9, R8, R7, RZ ; /* 0x0000000708097224 */
/* 0x000fe200078e02ff */
/*0170*/ IABS R8, R0 ; /* 0x0000000000087213 */
/* 0x000fc80000000000 */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0190*/ LOP3.LUT R4, R0, c[0x0][0x184], RZ, 0x3c, !PT ; /* 0x0000610000047a12 */
/* 0x000fc800078e3cff */
/*01a0*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f26270 */
/*01b0*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*01c0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*01d0*/ IMAD R6, R7, R6, R8 ; /* 0x0000000607067224 */
/* 0x000fca00078e0208 */
/*01e0*/ ISETP.GT.U32.AND P2, PT, R7, R6, PT ; /* 0x000000060700720c */
/* 0x000fda0003f44070 */
/*01f0*/ @!P2 IADD3 R6, R6, -R7.reuse, RZ ; /* 0x800000070606a210 */
/* 0x080fe40007ffe0ff */
/*0200*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GE.U32.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x000fe40003f06070 */
/*0220*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x184], PT ; /* 0x00006100ff007a0c */
/* 0x000fe40003f45270 */
/*0230*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fd20000000f00 */
/*0240*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fca0007ffe0ff */
/*0250*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*0260*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x184], RZ, 0x33, !PT ; /* 0x00006100ff05aa12 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R7, -R5.reuse, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x040fe20007ffe1ff */
/*0280*/ IMAD R5, R5, c[0x0][0x188], R3 ; /* 0x0000620005057a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD R7, R7, c[0x0][0x184], R0 ; /* 0x0000610007077a24 */
/* 0x000fc800078e0200 */
/*02a0*/ IMAD R4, R7, c[0x0][0x18c], R2 ; /* 0x0000630007047a24 */
/* 0x000fc800078e0202 */
/*02b0*/ IMAD R4, R5, c[0x0][0x16c], R4 ; /* 0x00005b0005047a24 */
/* 0x000fc800078e0204 */
/*02c0*/ IMAD.WIDE R4, R4, R6, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0206 */
/*02d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*02e0*/ IMAD R3, R0, c[0x0][0x178], R3 ; /* 0x00005e0000037a24 */
/* 0x000fc800078e0203 */
/*02f0*/ IMAD R3, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0202 */
/*0300*/ IMAD.WIDE R2, R3, R6, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0206 */
/*0310*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101b04 */
/*0320*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0330*/ BRA 0x330; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} | .file "tmpxft_0012fd7d_00000000-6_cuArraysCopyToBatch_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
.type _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii, @function
_Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 216
pushq 40(%rsp)
.cfi_def_cfa_offset 224
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii, .-_Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
.globl _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.type _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii, @function
_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z64__device_stub__Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiiiPK6float2iiPS_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii, .-_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26cuArraysCopyToBatch_kernelPK6float2iiPS_iiiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuArraysCopyToBatch_kernel(const float2 *imageIn, const int inNX, const int inNY, float2 *imageOut, const int outNX, const int outNY, const int nImagesX, const int nImagesY, const int strideX, const int strideY)
{
int idxImage = blockIdx.z;
int outx = threadIdx.x + blockDim.x*blockIdx.x;
int outy = threadIdx.y + blockDim.y*blockIdx.y;
if(idxImage >=nImagesX*nImagesY|| outx >= outNX || outy >= outNY) return;
int idxOut = idxImage*outNX*outNY + outx*outNY + outy;
int idxImageX = idxImage/nImagesY;
int idxImageY = idxImage%nImagesY;
int idxIn = (idxImageX*strideX+outx)*inNY + idxImageY*strideY+outy;
imageOut[idxOut] = imageIn[idxIn];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.globl _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.p2align 8
.type _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii,@function
_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b128 s[4:7], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s13, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mul_i32 s2, s7, s6
s_cmp_lt_i32 s15, s2
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v0
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s3, s3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_ashr_i32 s6, s7, 31
s_ashr_i32 s9, s15, 31
s_add_i32 s2, s7, s6
s_add_i32 s10, s15, s9
s_xor_b32 s8, s2, s6
s_xor_b32 s10, s10, s9
v_cvt_f32_u32_e32 v2, s8
s_sub_i32 s3, 0, s8
s_xor_b32 s6, s9, s6
s_load_b32 s13, s[0:1], 0xc
v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_readfirstlane_b32 s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, s2
s_mul_hi_u32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s2, s3
s_load_b64 s[2:3], s[0:1], 0x28
s_mul_hi_u32 s11, s10, s11
s_mul_i32 s12, s11, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s10, s12
s_add_i32 s10, s11, 1
s_sub_i32 s12, s9, s8
s_cmp_ge_u32 s9, s8
s_cselect_b32 s10, s10, s11
s_cselect_b32 s9, s12, s9
s_add_i32 s11, s10, 1
s_cmp_ge_u32 s9, s8
s_cselect_b32 s8, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s8, s8, s6
s_sub_i32 s6, s8, s6
s_load_b64 s[8:9], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, s6, s2, v[0:1]
s_mul_i32 s6, s6, s7
s_load_b64 s[0:1], s[0:1], 0x0
s_sub_i32 s2, s15, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s3
v_mul_lo_u32 v2, v2, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, s2, v1, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v4, s5, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[5:6]
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii, .Lfunc_end0-_Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26cuArraysCopyToBatch_kernelPK15HIP_vector_typeIfLj2EEiiPS0_iiiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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